1*4882a593Smuzhiyun /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without
4*4882a593Smuzhiyun * modification, are permitted provided that the following conditions are met:
5*4882a593Smuzhiyun * * Redistributions of source code must retain the above copyright
6*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer.
7*4882a593Smuzhiyun * * Redistributions in binary form must reproduce the above copyright
8*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in the
9*4882a593Smuzhiyun * documentation and/or other materials provided with the distribution.
10*4882a593Smuzhiyun * * Neither the name of Freescale Semiconductor nor the
11*4882a593Smuzhiyun * names of its contributors may be used to endorse or promote products
12*4882a593Smuzhiyun * derived from this software without specific prior written permission.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * ALTERNATIVELY, this software may be distributed under the terms of the
15*4882a593Smuzhiyun * GNU General Public License ("GPL") as published by the Free Software
16*4882a593Smuzhiyun * Foundation, either version 2 of that License or (at your option) any
17*4882a593Smuzhiyun * later version.
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
20*4882a593Smuzhiyun * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21*4882a593Smuzhiyun * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22*4882a593Smuzhiyun * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
23*4882a593Smuzhiyun * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24*4882a593Smuzhiyun * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25*4882a593Smuzhiyun * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26*4882a593Smuzhiyun * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28*4882a593Smuzhiyun * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29*4882a593Smuzhiyun */
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #include "qman_priv.h"
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun struct qman_portal *qman_dma_portal;
34*4882a593Smuzhiyun EXPORT_SYMBOL(qman_dma_portal);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* Enable portal interupts (as opposed to polling mode) */
37*4882a593Smuzhiyun #define CONFIG_FSL_DPA_PIRQ_SLOW 1
38*4882a593Smuzhiyun #define CONFIG_FSL_DPA_PIRQ_FAST 1
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun static struct cpumask portal_cpus;
41*4882a593Smuzhiyun static int __qman_portals_probed;
42*4882a593Smuzhiyun /* protect qman global registers and global data shared among portals */
43*4882a593Smuzhiyun static DEFINE_SPINLOCK(qman_lock);
44*4882a593Smuzhiyun
portal_set_cpu(struct qm_portal_config * pcfg,int cpu)45*4882a593Smuzhiyun static void portal_set_cpu(struct qm_portal_config *pcfg, int cpu)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun #ifdef CONFIG_FSL_PAMU
48*4882a593Smuzhiyun struct device *dev = pcfg->dev;
49*4882a593Smuzhiyun int window_count = 1;
50*4882a593Smuzhiyun struct iommu_domain_geometry geom_attr;
51*4882a593Smuzhiyun struct pamu_stash_attribute stash_attr;
52*4882a593Smuzhiyun int ret;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun pcfg->iommu_domain = iommu_domain_alloc(&platform_bus_type);
55*4882a593Smuzhiyun if (!pcfg->iommu_domain) {
56*4882a593Smuzhiyun dev_err(dev, "%s(): iommu_domain_alloc() failed", __func__);
57*4882a593Smuzhiyun goto no_iommu;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun geom_attr.aperture_start = 0;
60*4882a593Smuzhiyun geom_attr.aperture_end =
61*4882a593Smuzhiyun ((dma_addr_t)1 << min(8 * sizeof(dma_addr_t), (size_t)36)) - 1;
62*4882a593Smuzhiyun geom_attr.force_aperture = true;
63*4882a593Smuzhiyun ret = iommu_domain_set_attr(pcfg->iommu_domain, DOMAIN_ATTR_GEOMETRY,
64*4882a593Smuzhiyun &geom_attr);
65*4882a593Smuzhiyun if (ret < 0) {
66*4882a593Smuzhiyun dev_err(dev, "%s(): iommu_domain_set_attr() = %d", __func__,
67*4882a593Smuzhiyun ret);
68*4882a593Smuzhiyun goto out_domain_free;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun ret = iommu_domain_set_attr(pcfg->iommu_domain, DOMAIN_ATTR_WINDOWS,
71*4882a593Smuzhiyun &window_count);
72*4882a593Smuzhiyun if (ret < 0) {
73*4882a593Smuzhiyun dev_err(dev, "%s(): iommu_domain_set_attr() = %d", __func__,
74*4882a593Smuzhiyun ret);
75*4882a593Smuzhiyun goto out_domain_free;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun stash_attr.cpu = cpu;
78*4882a593Smuzhiyun stash_attr.cache = PAMU_ATTR_CACHE_L1;
79*4882a593Smuzhiyun ret = iommu_domain_set_attr(pcfg->iommu_domain,
80*4882a593Smuzhiyun DOMAIN_ATTR_FSL_PAMU_STASH,
81*4882a593Smuzhiyun &stash_attr);
82*4882a593Smuzhiyun if (ret < 0) {
83*4882a593Smuzhiyun dev_err(dev, "%s(): iommu_domain_set_attr() = %d",
84*4882a593Smuzhiyun __func__, ret);
85*4882a593Smuzhiyun goto out_domain_free;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun ret = iommu_domain_window_enable(pcfg->iommu_domain, 0, 0, 1ULL << 36,
88*4882a593Smuzhiyun IOMMU_READ | IOMMU_WRITE);
89*4882a593Smuzhiyun if (ret < 0) {
90*4882a593Smuzhiyun dev_err(dev, "%s(): iommu_domain_window_enable() = %d",
91*4882a593Smuzhiyun __func__, ret);
92*4882a593Smuzhiyun goto out_domain_free;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun ret = iommu_attach_device(pcfg->iommu_domain, dev);
95*4882a593Smuzhiyun if (ret < 0) {
96*4882a593Smuzhiyun dev_err(dev, "%s(): iommu_device_attach() = %d", __func__,
97*4882a593Smuzhiyun ret);
98*4882a593Smuzhiyun goto out_domain_free;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun ret = iommu_domain_set_attr(pcfg->iommu_domain,
101*4882a593Smuzhiyun DOMAIN_ATTR_FSL_PAMU_ENABLE,
102*4882a593Smuzhiyun &window_count);
103*4882a593Smuzhiyun if (ret < 0) {
104*4882a593Smuzhiyun dev_err(dev, "%s(): iommu_domain_set_attr() = %d", __func__,
105*4882a593Smuzhiyun ret);
106*4882a593Smuzhiyun goto out_detach_device;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun no_iommu:
110*4882a593Smuzhiyun #endif
111*4882a593Smuzhiyun qman_set_sdest(pcfg->channel, cpu);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun return;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun #ifdef CONFIG_FSL_PAMU
116*4882a593Smuzhiyun out_detach_device:
117*4882a593Smuzhiyun iommu_detach_device(pcfg->iommu_domain, NULL);
118*4882a593Smuzhiyun out_domain_free:
119*4882a593Smuzhiyun iommu_domain_free(pcfg->iommu_domain);
120*4882a593Smuzhiyun pcfg->iommu_domain = NULL;
121*4882a593Smuzhiyun #endif
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
init_pcfg(struct qm_portal_config * pcfg)124*4882a593Smuzhiyun static struct qman_portal *init_pcfg(struct qm_portal_config *pcfg)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun struct qman_portal *p;
127*4882a593Smuzhiyun u32 irq_sources = 0;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /* We need the same LIODN offset for all portals */
130*4882a593Smuzhiyun qman_liodn_fixup(pcfg->channel);
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun pcfg->iommu_domain = NULL;
133*4882a593Smuzhiyun portal_set_cpu(pcfg, pcfg->cpu);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun p = qman_create_affine_portal(pcfg, NULL);
136*4882a593Smuzhiyun if (!p) {
137*4882a593Smuzhiyun dev_crit(pcfg->dev, "%s: Portal failure on cpu %d\n",
138*4882a593Smuzhiyun __func__, pcfg->cpu);
139*4882a593Smuzhiyun return NULL;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun /* Determine what should be interrupt-vs-poll driven */
143*4882a593Smuzhiyun #ifdef CONFIG_FSL_DPA_PIRQ_SLOW
144*4882a593Smuzhiyun irq_sources |= QM_PIRQ_EQCI | QM_PIRQ_EQRI | QM_PIRQ_MRI |
145*4882a593Smuzhiyun QM_PIRQ_CSCI;
146*4882a593Smuzhiyun #endif
147*4882a593Smuzhiyun #ifdef CONFIG_FSL_DPA_PIRQ_FAST
148*4882a593Smuzhiyun irq_sources |= QM_PIRQ_DQRI;
149*4882a593Smuzhiyun #endif
150*4882a593Smuzhiyun qman_p_irqsource_add(p, irq_sources);
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun spin_lock(&qman_lock);
153*4882a593Smuzhiyun if (cpumask_equal(&portal_cpus, cpu_possible_mask)) {
154*4882a593Smuzhiyun /* all assigned portals are initialized now */
155*4882a593Smuzhiyun qman_init_cgr_all();
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun if (!qman_dma_portal)
159*4882a593Smuzhiyun qman_dma_portal = p;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun spin_unlock(&qman_lock);
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun dev_info(pcfg->dev, "Portal initialised, cpu %d\n", pcfg->cpu);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun return p;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
qman_portal_update_sdest(const struct qm_portal_config * pcfg,unsigned int cpu)168*4882a593Smuzhiyun static void qman_portal_update_sdest(const struct qm_portal_config *pcfg,
169*4882a593Smuzhiyun unsigned int cpu)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun #ifdef CONFIG_FSL_PAMU /* TODO */
172*4882a593Smuzhiyun struct pamu_stash_attribute stash_attr;
173*4882a593Smuzhiyun int ret;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun if (pcfg->iommu_domain) {
176*4882a593Smuzhiyun stash_attr.cpu = cpu;
177*4882a593Smuzhiyun stash_attr.cache = PAMU_ATTR_CACHE_L1;
178*4882a593Smuzhiyun ret = iommu_domain_set_attr(pcfg->iommu_domain,
179*4882a593Smuzhiyun DOMAIN_ATTR_FSL_PAMU_STASH, &stash_attr);
180*4882a593Smuzhiyun if (ret < 0) {
181*4882a593Smuzhiyun dev_err(pcfg->dev,
182*4882a593Smuzhiyun "Failed to update pamu stash setting\n");
183*4882a593Smuzhiyun return;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun #endif
187*4882a593Smuzhiyun qman_set_sdest(pcfg->channel, cpu);
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
qman_offline_cpu(unsigned int cpu)190*4882a593Smuzhiyun static int qman_offline_cpu(unsigned int cpu)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun struct qman_portal *p;
193*4882a593Smuzhiyun const struct qm_portal_config *pcfg;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun p = affine_portals[cpu];
196*4882a593Smuzhiyun if (p) {
197*4882a593Smuzhiyun pcfg = qman_get_qm_portal_config(p);
198*4882a593Smuzhiyun if (pcfg) {
199*4882a593Smuzhiyun /* select any other online CPU */
200*4882a593Smuzhiyun cpu = cpumask_any_but(cpu_online_mask, cpu);
201*4882a593Smuzhiyun irq_set_affinity(pcfg->irq, cpumask_of(cpu));
202*4882a593Smuzhiyun qman_portal_update_sdest(pcfg, cpu);
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun return 0;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun
qman_online_cpu(unsigned int cpu)208*4882a593Smuzhiyun static int qman_online_cpu(unsigned int cpu)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun struct qman_portal *p;
211*4882a593Smuzhiyun const struct qm_portal_config *pcfg;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun p = affine_portals[cpu];
214*4882a593Smuzhiyun if (p) {
215*4882a593Smuzhiyun pcfg = qman_get_qm_portal_config(p);
216*4882a593Smuzhiyun if (pcfg) {
217*4882a593Smuzhiyun irq_set_affinity(pcfg->irq, cpumask_of(cpu));
218*4882a593Smuzhiyun qman_portal_update_sdest(pcfg, cpu);
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun return 0;
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun
qman_portals_probed(void)224*4882a593Smuzhiyun int qman_portals_probed(void)
225*4882a593Smuzhiyun {
226*4882a593Smuzhiyun return __qman_portals_probed;
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(qman_portals_probed);
229*4882a593Smuzhiyun
qman_portal_probe(struct platform_device * pdev)230*4882a593Smuzhiyun static int qman_portal_probe(struct platform_device *pdev)
231*4882a593Smuzhiyun {
232*4882a593Smuzhiyun struct device *dev = &pdev->dev;
233*4882a593Smuzhiyun struct device_node *node = dev->of_node;
234*4882a593Smuzhiyun struct qm_portal_config *pcfg;
235*4882a593Smuzhiyun struct resource *addr_phys[2];
236*4882a593Smuzhiyun int irq, cpu, err, i;
237*4882a593Smuzhiyun u32 val;
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun err = qman_is_probed();
240*4882a593Smuzhiyun if (!err)
241*4882a593Smuzhiyun return -EPROBE_DEFER;
242*4882a593Smuzhiyun if (err < 0) {
243*4882a593Smuzhiyun dev_err(&pdev->dev, "failing probe due to qman probe error\n");
244*4882a593Smuzhiyun return -ENODEV;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun pcfg = devm_kmalloc(dev, sizeof(*pcfg), GFP_KERNEL);
248*4882a593Smuzhiyun if (!pcfg) {
249*4882a593Smuzhiyun __qman_portals_probed = -1;
250*4882a593Smuzhiyun return -ENOMEM;
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun pcfg->dev = dev;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun addr_phys[0] = platform_get_resource(pdev, IORESOURCE_MEM,
256*4882a593Smuzhiyun DPAA_PORTAL_CE);
257*4882a593Smuzhiyun if (!addr_phys[0]) {
258*4882a593Smuzhiyun dev_err(dev, "Can't get %pOF property 'reg::CE'\n", node);
259*4882a593Smuzhiyun goto err_ioremap1;
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun addr_phys[1] = platform_get_resource(pdev, IORESOURCE_MEM,
263*4882a593Smuzhiyun DPAA_PORTAL_CI);
264*4882a593Smuzhiyun if (!addr_phys[1]) {
265*4882a593Smuzhiyun dev_err(dev, "Can't get %pOF property 'reg::CI'\n", node);
266*4882a593Smuzhiyun goto err_ioremap1;
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun err = of_property_read_u32(node, "cell-index", &val);
270*4882a593Smuzhiyun if (err) {
271*4882a593Smuzhiyun dev_err(dev, "Can't get %pOF property 'cell-index'\n", node);
272*4882a593Smuzhiyun __qman_portals_probed = -1;
273*4882a593Smuzhiyun return err;
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun pcfg->channel = val;
276*4882a593Smuzhiyun pcfg->cpu = -1;
277*4882a593Smuzhiyun irq = platform_get_irq(pdev, 0);
278*4882a593Smuzhiyun if (irq <= 0)
279*4882a593Smuzhiyun goto err_ioremap1;
280*4882a593Smuzhiyun pcfg->irq = irq;
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun pcfg->addr_virt_ce = memremap(addr_phys[0]->start,
283*4882a593Smuzhiyun resource_size(addr_phys[0]),
284*4882a593Smuzhiyun QBMAN_MEMREMAP_ATTR);
285*4882a593Smuzhiyun if (!pcfg->addr_virt_ce) {
286*4882a593Smuzhiyun dev_err(dev, "memremap::CE failed\n");
287*4882a593Smuzhiyun goto err_ioremap1;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun pcfg->addr_virt_ci = ioremap(addr_phys[1]->start,
291*4882a593Smuzhiyun resource_size(addr_phys[1]));
292*4882a593Smuzhiyun if (!pcfg->addr_virt_ci) {
293*4882a593Smuzhiyun dev_err(dev, "ioremap::CI failed\n");
294*4882a593Smuzhiyun goto err_ioremap2;
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun pcfg->pools = qm_get_pools_sdqcr();
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun spin_lock(&qman_lock);
300*4882a593Smuzhiyun cpu = cpumask_next_zero(-1, &portal_cpus);
301*4882a593Smuzhiyun if (cpu >= nr_cpu_ids) {
302*4882a593Smuzhiyun __qman_portals_probed = 1;
303*4882a593Smuzhiyun /* unassigned portal, skip init */
304*4882a593Smuzhiyun spin_unlock(&qman_lock);
305*4882a593Smuzhiyun return 0;
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun cpumask_set_cpu(cpu, &portal_cpus);
309*4882a593Smuzhiyun spin_unlock(&qman_lock);
310*4882a593Smuzhiyun pcfg->cpu = cpu;
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun if (dma_set_mask(dev, DMA_BIT_MASK(40))) {
313*4882a593Smuzhiyun dev_err(dev, "dma_set_mask() failed\n");
314*4882a593Smuzhiyun goto err_portal_init;
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun if (!init_pcfg(pcfg)) {
318*4882a593Smuzhiyun dev_err(dev, "portal init failed\n");
319*4882a593Smuzhiyun goto err_portal_init;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun /* clear irq affinity if assigned cpu is offline */
323*4882a593Smuzhiyun if (!cpu_online(cpu))
324*4882a593Smuzhiyun qman_offline_cpu(cpu);
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun if (__qman_portals_probed == 1 && qman_requires_cleanup()) {
327*4882a593Smuzhiyun /*
328*4882a593Smuzhiyun * QMan wasn't reset prior to boot (Kexec for example)
329*4882a593Smuzhiyun * Empty all the frame queues so they are in reset state
330*4882a593Smuzhiyun */
331*4882a593Smuzhiyun for (i = 0; i < qm_get_fqid_maxcnt(); i++) {
332*4882a593Smuzhiyun err = qman_shutdown_fq(i);
333*4882a593Smuzhiyun if (err) {
334*4882a593Smuzhiyun dev_err(dev, "Failed to shutdown frame queue %d\n",
335*4882a593Smuzhiyun i);
336*4882a593Smuzhiyun goto err_portal_init;
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun qman_done_cleanup();
340*4882a593Smuzhiyun }
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun return 0;
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun err_portal_init:
345*4882a593Smuzhiyun iounmap(pcfg->addr_virt_ci);
346*4882a593Smuzhiyun err_ioremap2:
347*4882a593Smuzhiyun memunmap(pcfg->addr_virt_ce);
348*4882a593Smuzhiyun err_ioremap1:
349*4882a593Smuzhiyun __qman_portals_probed = -1;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun return -ENXIO;
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun static const struct of_device_id qman_portal_ids[] = {
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun .compatible = "fsl,qman-portal",
357*4882a593Smuzhiyun },
358*4882a593Smuzhiyun {}
359*4882a593Smuzhiyun };
360*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, qman_portal_ids);
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun static struct platform_driver qman_portal_driver = {
363*4882a593Smuzhiyun .driver = {
364*4882a593Smuzhiyun .name = KBUILD_MODNAME,
365*4882a593Smuzhiyun .of_match_table = qman_portal_ids,
366*4882a593Smuzhiyun },
367*4882a593Smuzhiyun .probe = qman_portal_probe,
368*4882a593Smuzhiyun };
369*4882a593Smuzhiyun
qman_portal_driver_register(struct platform_driver * drv)370*4882a593Smuzhiyun static int __init qman_portal_driver_register(struct platform_driver *drv)
371*4882a593Smuzhiyun {
372*4882a593Smuzhiyun int ret;
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun ret = platform_driver_register(drv);
375*4882a593Smuzhiyun if (ret < 0)
376*4882a593Smuzhiyun return ret;
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
379*4882a593Smuzhiyun "soc/qman_portal:online",
380*4882a593Smuzhiyun qman_online_cpu, qman_offline_cpu);
381*4882a593Smuzhiyun if (ret < 0) {
382*4882a593Smuzhiyun pr_err("qman: failed to register hotplug callbacks.\n");
383*4882a593Smuzhiyun platform_driver_unregister(drv);
384*4882a593Smuzhiyun return ret;
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun return 0;
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun module_driver(qman_portal_driver,
390*4882a593Smuzhiyun qman_portal_driver_register, platform_driver_unregister);
391