1*4882a593Smuzhiyun // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2014-2016 Freescale Semiconductor Inc.
4*4882a593Smuzhiyun * Copyright NXP 2016
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/types.h>
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/interrupt.h>
13*4882a593Smuzhiyun #include <linux/msi.h>
14*4882a593Smuzhiyun #include <linux/dma-mapping.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/io.h>
17*4882a593Smuzhiyun #include <linux/sys_soc.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <linux/fsl/mc.h>
20*4882a593Smuzhiyun #include <soc/fsl/dpaa2-io.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include "qbman-portal.h"
23*4882a593Smuzhiyun #include "dpio.h"
24*4882a593Smuzhiyun #include "dpio-cmd.h"
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun MODULE_LICENSE("Dual BSD/GPL");
27*4882a593Smuzhiyun MODULE_AUTHOR("Freescale Semiconductor, Inc");
28*4882a593Smuzhiyun MODULE_DESCRIPTION("DPIO Driver");
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun struct dpio_priv {
31*4882a593Smuzhiyun struct dpaa2_io *io;
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun static cpumask_var_t cpus_unused_mask;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun static const struct soc_device_attribute ls1088a_soc[] = {
37*4882a593Smuzhiyun {.family = "QorIQ LS1088A"},
38*4882a593Smuzhiyun { /* sentinel */ }
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun static const struct soc_device_attribute ls2080a_soc[] = {
42*4882a593Smuzhiyun {.family = "QorIQ LS2080A"},
43*4882a593Smuzhiyun { /* sentinel */ }
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun static const struct soc_device_attribute ls2088a_soc[] = {
47*4882a593Smuzhiyun {.family = "QorIQ LS2088A"},
48*4882a593Smuzhiyun { /* sentinel */ }
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun static const struct soc_device_attribute lx2160a_soc[] = {
52*4882a593Smuzhiyun {.family = "QorIQ LX2160A"},
53*4882a593Smuzhiyun { /* sentinel */ }
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun
dpaa2_dpio_get_cluster_sdest(struct fsl_mc_device * dpio_dev,int cpu)56*4882a593Smuzhiyun static int dpaa2_dpio_get_cluster_sdest(struct fsl_mc_device *dpio_dev, int cpu)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun int cluster_base, cluster_size;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun if (soc_device_match(ls1088a_soc)) {
61*4882a593Smuzhiyun cluster_base = 2;
62*4882a593Smuzhiyun cluster_size = 4;
63*4882a593Smuzhiyun } else if (soc_device_match(ls2080a_soc) ||
64*4882a593Smuzhiyun soc_device_match(ls2088a_soc) ||
65*4882a593Smuzhiyun soc_device_match(lx2160a_soc)) {
66*4882a593Smuzhiyun cluster_base = 0;
67*4882a593Smuzhiyun cluster_size = 2;
68*4882a593Smuzhiyun } else {
69*4882a593Smuzhiyun dev_err(&dpio_dev->dev, "unknown SoC version\n");
70*4882a593Smuzhiyun return -1;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun return cluster_base + cpu / cluster_size;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
dpio_irq_handler(int irq_num,void * arg)76*4882a593Smuzhiyun static irqreturn_t dpio_irq_handler(int irq_num, void *arg)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun struct device *dev = (struct device *)arg;
79*4882a593Smuzhiyun struct dpio_priv *priv = dev_get_drvdata(dev);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun return dpaa2_io_irq(priv->io);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
unregister_dpio_irq_handlers(struct fsl_mc_device * dpio_dev)84*4882a593Smuzhiyun static void unregister_dpio_irq_handlers(struct fsl_mc_device *dpio_dev)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun struct fsl_mc_device_irq *irq;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun irq = dpio_dev->irqs[0];
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* clear the affinity hint */
91*4882a593Smuzhiyun irq_set_affinity_hint(irq->msi_desc->irq, NULL);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
register_dpio_irq_handlers(struct fsl_mc_device * dpio_dev,int cpu)94*4882a593Smuzhiyun static int register_dpio_irq_handlers(struct fsl_mc_device *dpio_dev, int cpu)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun int error;
97*4882a593Smuzhiyun struct fsl_mc_device_irq *irq;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun irq = dpio_dev->irqs[0];
100*4882a593Smuzhiyun error = devm_request_irq(&dpio_dev->dev,
101*4882a593Smuzhiyun irq->msi_desc->irq,
102*4882a593Smuzhiyun dpio_irq_handler,
103*4882a593Smuzhiyun 0,
104*4882a593Smuzhiyun dev_name(&dpio_dev->dev),
105*4882a593Smuzhiyun &dpio_dev->dev);
106*4882a593Smuzhiyun if (error < 0) {
107*4882a593Smuzhiyun dev_err(&dpio_dev->dev,
108*4882a593Smuzhiyun "devm_request_irq() failed: %d\n",
109*4882a593Smuzhiyun error);
110*4882a593Smuzhiyun return error;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* set the affinity hint */
114*4882a593Smuzhiyun if (irq_set_affinity_hint(irq->msi_desc->irq, cpumask_of(cpu)))
115*4882a593Smuzhiyun dev_err(&dpio_dev->dev,
116*4882a593Smuzhiyun "irq_set_affinity failed irq %d cpu %d\n",
117*4882a593Smuzhiyun irq->msi_desc->irq, cpu);
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun return 0;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
dpaa2_dpio_probe(struct fsl_mc_device * dpio_dev)122*4882a593Smuzhiyun static int dpaa2_dpio_probe(struct fsl_mc_device *dpio_dev)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun struct dpio_attr dpio_attrs;
125*4882a593Smuzhiyun struct dpaa2_io_desc desc;
126*4882a593Smuzhiyun struct dpio_priv *priv;
127*4882a593Smuzhiyun int err = -ENOMEM;
128*4882a593Smuzhiyun struct device *dev = &dpio_dev->dev;
129*4882a593Smuzhiyun int possible_next_cpu;
130*4882a593Smuzhiyun int sdest;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
133*4882a593Smuzhiyun if (!priv)
134*4882a593Smuzhiyun goto err_priv_alloc;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun dev_set_drvdata(dev, priv);
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun err = fsl_mc_portal_allocate(dpio_dev, 0, &dpio_dev->mc_io);
139*4882a593Smuzhiyun if (err) {
140*4882a593Smuzhiyun dev_dbg(dev, "MC portal allocation failed\n");
141*4882a593Smuzhiyun err = -EPROBE_DEFER;
142*4882a593Smuzhiyun goto err_priv_alloc;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun err = dpio_open(dpio_dev->mc_io, 0, dpio_dev->obj_desc.id,
146*4882a593Smuzhiyun &dpio_dev->mc_handle);
147*4882a593Smuzhiyun if (err) {
148*4882a593Smuzhiyun dev_err(dev, "dpio_open() failed\n");
149*4882a593Smuzhiyun goto err_open;
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun err = dpio_reset(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
153*4882a593Smuzhiyun if (err) {
154*4882a593Smuzhiyun dev_err(dev, "dpio_reset() failed\n");
155*4882a593Smuzhiyun goto err_reset;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun err = dpio_get_attributes(dpio_dev->mc_io, 0, dpio_dev->mc_handle,
159*4882a593Smuzhiyun &dpio_attrs);
160*4882a593Smuzhiyun if (err) {
161*4882a593Smuzhiyun dev_err(dev, "dpio_get_attributes() failed %d\n", err);
162*4882a593Smuzhiyun goto err_get_attr;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun desc.qman_version = dpio_attrs.qbman_version;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun err = dpio_enable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
167*4882a593Smuzhiyun if (err) {
168*4882a593Smuzhiyun dev_err(dev, "dpio_enable() failed %d\n", err);
169*4882a593Smuzhiyun goto err_get_attr;
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun /* initialize DPIO descriptor */
173*4882a593Smuzhiyun desc.receives_notifications = dpio_attrs.num_priorities ? 1 : 0;
174*4882a593Smuzhiyun desc.has_8prio = dpio_attrs.num_priorities == 8 ? 1 : 0;
175*4882a593Smuzhiyun desc.dpio_id = dpio_dev->obj_desc.id;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun /* get the cpu to use for the affinity hint */
178*4882a593Smuzhiyun possible_next_cpu = cpumask_first(cpus_unused_mask);
179*4882a593Smuzhiyun if (possible_next_cpu >= nr_cpu_ids) {
180*4882a593Smuzhiyun dev_err(dev, "probe failed. Number of DPIOs exceeds NR_CPUS.\n");
181*4882a593Smuzhiyun err = -ERANGE;
182*4882a593Smuzhiyun goto err_allocate_irqs;
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun desc.cpu = possible_next_cpu;
185*4882a593Smuzhiyun cpumask_clear_cpu(possible_next_cpu, cpus_unused_mask);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun sdest = dpaa2_dpio_get_cluster_sdest(dpio_dev, desc.cpu);
188*4882a593Smuzhiyun if (sdest >= 0) {
189*4882a593Smuzhiyun err = dpio_set_stashing_destination(dpio_dev->mc_io, 0,
190*4882a593Smuzhiyun dpio_dev->mc_handle,
191*4882a593Smuzhiyun sdest);
192*4882a593Smuzhiyun if (err)
193*4882a593Smuzhiyun dev_err(dev, "dpio_set_stashing_destination failed for cpu%d\n",
194*4882a593Smuzhiyun desc.cpu);
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun if (dpio_dev->obj_desc.region_count < 3) {
198*4882a593Smuzhiyun /* No support for DDR backed portals, use classic mapping */
199*4882a593Smuzhiyun /*
200*4882a593Smuzhiyun * Set the CENA regs to be the cache inhibited area of the
201*4882a593Smuzhiyun * portal to avoid coherency issues if a user migrates to
202*4882a593Smuzhiyun * another core.
203*4882a593Smuzhiyun */
204*4882a593Smuzhiyun desc.regs_cena = devm_memremap(dev, dpio_dev->regions[1].start,
205*4882a593Smuzhiyun resource_size(&dpio_dev->regions[1]),
206*4882a593Smuzhiyun MEMREMAP_WC);
207*4882a593Smuzhiyun } else {
208*4882a593Smuzhiyun desc.regs_cena = devm_memremap(dev, dpio_dev->regions[2].start,
209*4882a593Smuzhiyun resource_size(&dpio_dev->regions[2]),
210*4882a593Smuzhiyun MEMREMAP_WB);
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun if (IS_ERR(desc.regs_cena)) {
214*4882a593Smuzhiyun dev_err(dev, "devm_memremap failed\n");
215*4882a593Smuzhiyun err = PTR_ERR(desc.regs_cena);
216*4882a593Smuzhiyun goto err_allocate_irqs;
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun desc.regs_cinh = devm_ioremap(dev, dpio_dev->regions[1].start,
220*4882a593Smuzhiyun resource_size(&dpio_dev->regions[1]));
221*4882a593Smuzhiyun if (!desc.regs_cinh) {
222*4882a593Smuzhiyun err = -ENOMEM;
223*4882a593Smuzhiyun dev_err(dev, "devm_ioremap failed\n");
224*4882a593Smuzhiyun goto err_allocate_irqs;
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun err = fsl_mc_allocate_irqs(dpio_dev);
228*4882a593Smuzhiyun if (err) {
229*4882a593Smuzhiyun dev_err(dev, "fsl_mc_allocate_irqs failed. err=%d\n", err);
230*4882a593Smuzhiyun goto err_allocate_irqs;
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun priv->io = dpaa2_io_create(&desc, dev);
234*4882a593Smuzhiyun if (!priv->io) {
235*4882a593Smuzhiyun dev_err(dev, "dpaa2_io_create failed\n");
236*4882a593Smuzhiyun err = -ENOMEM;
237*4882a593Smuzhiyun goto err_dpaa2_io_create;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun err = register_dpio_irq_handlers(dpio_dev, desc.cpu);
241*4882a593Smuzhiyun if (err)
242*4882a593Smuzhiyun goto err_register_dpio_irq;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun dev_info(dev, "probed\n");
245*4882a593Smuzhiyun dev_dbg(dev, " receives_notifications = %d\n",
246*4882a593Smuzhiyun desc.receives_notifications);
247*4882a593Smuzhiyun dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun return 0;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun err_dpaa2_io_create:
252*4882a593Smuzhiyun unregister_dpio_irq_handlers(dpio_dev);
253*4882a593Smuzhiyun err_register_dpio_irq:
254*4882a593Smuzhiyun fsl_mc_free_irqs(dpio_dev);
255*4882a593Smuzhiyun err_allocate_irqs:
256*4882a593Smuzhiyun dpio_disable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
257*4882a593Smuzhiyun err_get_attr:
258*4882a593Smuzhiyun err_reset:
259*4882a593Smuzhiyun dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
260*4882a593Smuzhiyun err_open:
261*4882a593Smuzhiyun fsl_mc_portal_free(dpio_dev->mc_io);
262*4882a593Smuzhiyun err_priv_alloc:
263*4882a593Smuzhiyun return err;
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun /* Tear down interrupts for a given DPIO object */
dpio_teardown_irqs(struct fsl_mc_device * dpio_dev)267*4882a593Smuzhiyun static void dpio_teardown_irqs(struct fsl_mc_device *dpio_dev)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun unregister_dpio_irq_handlers(dpio_dev);
270*4882a593Smuzhiyun fsl_mc_free_irqs(dpio_dev);
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
dpaa2_dpio_remove(struct fsl_mc_device * dpio_dev)273*4882a593Smuzhiyun static int dpaa2_dpio_remove(struct fsl_mc_device *dpio_dev)
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun struct device *dev;
276*4882a593Smuzhiyun struct dpio_priv *priv;
277*4882a593Smuzhiyun int err = 0, cpu;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun dev = &dpio_dev->dev;
280*4882a593Smuzhiyun priv = dev_get_drvdata(dev);
281*4882a593Smuzhiyun cpu = dpaa2_io_get_cpu(priv->io);
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun dpaa2_io_down(priv->io);
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun dpio_teardown_irqs(dpio_dev);
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun cpumask_set_cpu(cpu, cpus_unused_mask);
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun err = dpio_open(dpio_dev->mc_io, 0, dpio_dev->obj_desc.id,
290*4882a593Smuzhiyun &dpio_dev->mc_handle);
291*4882a593Smuzhiyun if (err) {
292*4882a593Smuzhiyun dev_err(dev, "dpio_open() failed\n");
293*4882a593Smuzhiyun goto err_open;
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun dpio_disable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun fsl_mc_portal_free(dpio_dev->mc_io);
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun return 0;
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun err_open:
305*4882a593Smuzhiyun fsl_mc_portal_free(dpio_dev->mc_io);
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun return err;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun static const struct fsl_mc_device_id dpaa2_dpio_match_id_table[] = {
311*4882a593Smuzhiyun {
312*4882a593Smuzhiyun .vendor = FSL_MC_VENDOR_FREESCALE,
313*4882a593Smuzhiyun .obj_type = "dpio",
314*4882a593Smuzhiyun },
315*4882a593Smuzhiyun { .vendor = 0x0 }
316*4882a593Smuzhiyun };
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun static struct fsl_mc_driver dpaa2_dpio_driver = {
319*4882a593Smuzhiyun .driver = {
320*4882a593Smuzhiyun .name = KBUILD_MODNAME,
321*4882a593Smuzhiyun .owner = THIS_MODULE,
322*4882a593Smuzhiyun },
323*4882a593Smuzhiyun .probe = dpaa2_dpio_probe,
324*4882a593Smuzhiyun .remove = dpaa2_dpio_remove,
325*4882a593Smuzhiyun .match_id_table = dpaa2_dpio_match_id_table
326*4882a593Smuzhiyun };
327*4882a593Smuzhiyun
dpio_driver_init(void)328*4882a593Smuzhiyun static int dpio_driver_init(void)
329*4882a593Smuzhiyun {
330*4882a593Smuzhiyun if (!zalloc_cpumask_var(&cpus_unused_mask, GFP_KERNEL))
331*4882a593Smuzhiyun return -ENOMEM;
332*4882a593Smuzhiyun cpumask_copy(cpus_unused_mask, cpu_online_mask);
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun return fsl_mc_driver_register(&dpaa2_dpio_driver);
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun
dpio_driver_exit(void)337*4882a593Smuzhiyun static void dpio_driver_exit(void)
338*4882a593Smuzhiyun {
339*4882a593Smuzhiyun free_cpumask_var(cpus_unused_mask);
340*4882a593Smuzhiyun fsl_mc_driver_unregister(&dpaa2_dpio_driver);
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun module_init(dpio_driver_init);
343*4882a593Smuzhiyun module_exit(dpio_driver_exit);
344