1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright © 2014-2017 Broadcom 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include <linux/linkage.h> 7*4882a593Smuzhiyun#include <asm/assembler.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "pm.h" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun .text 12*4882a593Smuzhiyun .align 3 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun#define AON_CTRL_REG r10 15*4882a593Smuzhiyun#define DDR_PHY_STATUS_REG r11 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun/* 18*4882a593Smuzhiyun * r0: AON_CTRL base address 19*4882a593Smuzhiyun * r1: DDRY PHY PLL status register address 20*4882a593Smuzhiyun */ 21*4882a593SmuzhiyunENTRY(brcmstb_pm_do_s2) 22*4882a593Smuzhiyun stmfd sp!, {r4-r11, lr} 23*4882a593Smuzhiyun mov AON_CTRL_REG, r0 24*4882a593Smuzhiyun mov DDR_PHY_STATUS_REG, r1 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Flush memory transactions */ 27*4882a593Smuzhiyun dsb 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Cache DDR_PHY_STATUS_REG translation */ 30*4882a593Smuzhiyun ldr r0, [DDR_PHY_STATUS_REG] 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* power down request */ 33*4882a593Smuzhiyun ldr r0, =PM_S2_COMMAND 34*4882a593Smuzhiyun ldr r1, =0 35*4882a593Smuzhiyun str r1, [AON_CTRL_REG, #AON_CTRL_PM_CTRL] 36*4882a593Smuzhiyun ldr r1, [AON_CTRL_REG, #AON_CTRL_PM_CTRL] 37*4882a593Smuzhiyun str r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL] 38*4882a593Smuzhiyun ldr r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL] 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* Wait for interrupt */ 41*4882a593Smuzhiyun wfi 42*4882a593Smuzhiyun nop 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Bring MEMC back up */ 45*4882a593Smuzhiyun1: ldr r0, [DDR_PHY_STATUS_REG] 46*4882a593Smuzhiyun ands r0, #1 47*4882a593Smuzhiyun beq 1b 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Power-up handshake */ 50*4882a593Smuzhiyun ldr r0, =1 51*4882a593Smuzhiyun str r0, [AON_CTRL_REG, #AON_CTRL_HOST_MISC_CMDS] 52*4882a593Smuzhiyun ldr r0, [AON_CTRL_REG, #AON_CTRL_HOST_MISC_CMDS] 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun ldr r0, =0 55*4882a593Smuzhiyun str r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL] 56*4882a593Smuzhiyun ldr r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL] 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Return to caller */ 59*4882a593Smuzhiyun ldr r0, =0 60*4882a593Smuzhiyun ldmfd sp!, {r4-r11, pc} 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun ENDPROC(brcmstb_pm_do_s2) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Place literal pool here */ 65*4882a593Smuzhiyun .ltorg 66*4882a593Smuzhiyun 67*4882a593SmuzhiyunENTRY(brcmstb_pm_do_s2_sz) 68*4882a593Smuzhiyun .word . - brcmstb_pm_do_s2 69