1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Definitions for Broadcom STB power management / Always ON (AON) block 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright © 2016-2017 Broadcom 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __BRCMSTB_PM_H__ 9*4882a593Smuzhiyun #define __BRCMSTB_PM_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define AON_CTRL_RESET_CTRL 0x00 12*4882a593Smuzhiyun #define AON_CTRL_PM_CTRL 0x04 13*4882a593Smuzhiyun #define AON_CTRL_PM_STATUS 0x08 14*4882a593Smuzhiyun #define AON_CTRL_PM_CPU_WAIT_COUNT 0x10 15*4882a593Smuzhiyun #define AON_CTRL_PM_INITIATE 0x88 16*4882a593Smuzhiyun #define AON_CTRL_HOST_MISC_CMDS 0x8c 17*4882a593Smuzhiyun #define AON_CTRL_SYSTEM_DATA_RAM_OFS 0x200 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* MIPS PM constants */ 20*4882a593Smuzhiyun /* MEMC0 offsets */ 21*4882a593Smuzhiyun #define DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x10 22*4882a593Smuzhiyun #define DDR40_PHY_CONTROL_REGS_0_STANDBY_CTRL 0xa4 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* TIMER offsets */ 25*4882a593Smuzhiyun #define TIMER_TIMER1_CTRL 0x0c 26*4882a593Smuzhiyun #define TIMER_TIMER1_STAT 0x1c 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* TIMER defines */ 29*4882a593Smuzhiyun #define RESET_TIMER 0x0 30*4882a593Smuzhiyun #define START_TIMER 0xbfffffff 31*4882a593Smuzhiyun #define TIMER_MASK 0x3fffffff 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* PM_CTRL bitfield (Method #0) */ 34*4882a593Smuzhiyun #define PM_FAST_PWRDOWN (1 << 6) 35*4882a593Smuzhiyun #define PM_WARM_BOOT (1 << 5) 36*4882a593Smuzhiyun #define PM_DEEP_STANDBY (1 << 4) 37*4882a593Smuzhiyun #define PM_CPU_PWR (1 << 3) 38*4882a593Smuzhiyun #define PM_USE_CPU_RDY (1 << 2) 39*4882a593Smuzhiyun #define PM_PLL_PWRDOWN (1 << 1) 40*4882a593Smuzhiyun #define PM_PWR_DOWN (1 << 0) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* PM_CTRL bitfield (Method #1) */ 43*4882a593Smuzhiyun #define PM_DPHY_STANDBY_CLEAR (1 << 20) 44*4882a593Smuzhiyun #define PM_MIN_S3_WIDTH_TIMER_BYPASS (1 << 7) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define PM_S2_COMMAND (PM_PLL_PWRDOWN | PM_USE_CPU_RDY | PM_PWR_DOWN) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* Method 0 bitmasks */ 49*4882a593Smuzhiyun #define PM_COLD_CONFIG (PM_PLL_PWRDOWN | PM_DEEP_STANDBY) 50*4882a593Smuzhiyun #define PM_WARM_CONFIG (PM_COLD_CONFIG | PM_USE_CPU_RDY | PM_WARM_BOOT) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* Method 1 bitmask */ 53*4882a593Smuzhiyun #define M1_PM_WARM_CONFIG (PM_DPHY_STANDBY_CLEAR | \ 54*4882a593Smuzhiyun PM_MIN_S3_WIDTH_TIMER_BYPASS | \ 55*4882a593Smuzhiyun PM_WARM_BOOT | PM_DEEP_STANDBY | \ 56*4882a593Smuzhiyun PM_PLL_PWRDOWN | PM_PWR_DOWN) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define M1_PM_COLD_CONFIG (PM_DPHY_STANDBY_CLEAR | \ 59*4882a593Smuzhiyun PM_MIN_S3_WIDTH_TIMER_BYPASS | \ 60*4882a593Smuzhiyun PM_DEEP_STANDBY | \ 61*4882a593Smuzhiyun PM_PLL_PWRDOWN | PM_PWR_DOWN) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #ifndef CONFIG_MIPS 66*4882a593Smuzhiyun extern const unsigned long brcmstb_pm_do_s2_sz; 67*4882a593Smuzhiyun extern asmlinkage int brcmstb_pm_do_s2(void __iomem *aon_ctrl_base, 68*4882a593Smuzhiyun void __iomem *ddr_phy_pll_status); 69*4882a593Smuzhiyun #else 70*4882a593Smuzhiyun /* s2 asm */ 71*4882a593Smuzhiyun extern asmlinkage int brcm_pm_do_s2(u32 *s2_params); 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* s3 asm */ 74*4882a593Smuzhiyun extern asmlinkage int brcm_pm_do_s3(void __iomem *aon_ctrl_base, 75*4882a593Smuzhiyun int dcache_linesz); 76*4882a593Smuzhiyun extern int s3_reentry; 77*4882a593Smuzhiyun #endif /* CONFIG_MIPS */ 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #endif 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #endif /* __BRCMSTB_PM_H__ */ 82