1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * BCM63xx Power Domain Controller Driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <dt-bindings/soc/bcm6318-pm.h>
9*4882a593Smuzhiyun #include <dt-bindings/soc/bcm6328-pm.h>
10*4882a593Smuzhiyun #include <dt-bindings/soc/bcm6362-pm.h>
11*4882a593Smuzhiyun #include <dt-bindings/soc/bcm63268-pm.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/pm_domain.h>
16*4882a593Smuzhiyun #include <linux/of.h>
17*4882a593Smuzhiyun #include <linux/of_device.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun struct bcm63xx_power_dev {
20*4882a593Smuzhiyun struct generic_pm_domain genpd;
21*4882a593Smuzhiyun struct bcm63xx_power *power;
22*4882a593Smuzhiyun uint32_t mask;
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun struct bcm63xx_power {
26*4882a593Smuzhiyun void __iomem *base;
27*4882a593Smuzhiyun spinlock_t lock;
28*4882a593Smuzhiyun struct bcm63xx_power_dev *dev;
29*4882a593Smuzhiyun struct genpd_onecell_data genpd_data;
30*4882a593Smuzhiyun struct generic_pm_domain **genpd;
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun struct bcm63xx_power_data {
34*4882a593Smuzhiyun const char * const name;
35*4882a593Smuzhiyun uint8_t bit;
36*4882a593Smuzhiyun unsigned int flags;
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
bcm63xx_power_get_state(struct bcm63xx_power_dev * pmd,bool * is_on)39*4882a593Smuzhiyun static int bcm63xx_power_get_state(struct bcm63xx_power_dev *pmd, bool *is_on)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun struct bcm63xx_power *power = pmd->power;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun if (!pmd->mask) {
44*4882a593Smuzhiyun *is_on = false;
45*4882a593Smuzhiyun return -EINVAL;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun *is_on = !(__raw_readl(power->base) & pmd->mask);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun return 0;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
bcm63xx_power_set_state(struct bcm63xx_power_dev * pmd,bool on)53*4882a593Smuzhiyun static int bcm63xx_power_set_state(struct bcm63xx_power_dev *pmd, bool on)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun struct bcm63xx_power *power = pmd->power;
56*4882a593Smuzhiyun unsigned long flags;
57*4882a593Smuzhiyun uint32_t val;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun if (!pmd->mask)
60*4882a593Smuzhiyun return -EINVAL;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun spin_lock_irqsave(&power->lock, flags);
63*4882a593Smuzhiyun val = __raw_readl(power->base);
64*4882a593Smuzhiyun if (on)
65*4882a593Smuzhiyun val &= ~pmd->mask;
66*4882a593Smuzhiyun else
67*4882a593Smuzhiyun val |= pmd->mask;
68*4882a593Smuzhiyun __raw_writel(val, power->base);
69*4882a593Smuzhiyun spin_unlock_irqrestore(&power->lock, flags);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun return 0;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
bcm63xx_power_on(struct generic_pm_domain * genpd)74*4882a593Smuzhiyun static int bcm63xx_power_on(struct generic_pm_domain *genpd)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun struct bcm63xx_power_dev *pmd = container_of(genpd,
77*4882a593Smuzhiyun struct bcm63xx_power_dev, genpd);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun return bcm63xx_power_set_state(pmd, true);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
bcm63xx_power_off(struct generic_pm_domain * genpd)82*4882a593Smuzhiyun static int bcm63xx_power_off(struct generic_pm_domain *genpd)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun struct bcm63xx_power_dev *pmd = container_of(genpd,
85*4882a593Smuzhiyun struct bcm63xx_power_dev, genpd);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun return bcm63xx_power_set_state(pmd, false);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
bcm63xx_power_probe(struct platform_device * pdev)90*4882a593Smuzhiyun static int bcm63xx_power_probe(struct platform_device *pdev)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun struct device *dev = &pdev->dev;
93*4882a593Smuzhiyun struct device_node *np = dev->of_node;
94*4882a593Smuzhiyun struct resource *res;
95*4882a593Smuzhiyun const struct bcm63xx_power_data *entry, *table;
96*4882a593Smuzhiyun struct bcm63xx_power *power;
97*4882a593Smuzhiyun unsigned int ndom;
98*4882a593Smuzhiyun uint8_t max_bit = 0;
99*4882a593Smuzhiyun int ret;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun power = devm_kzalloc(dev, sizeof(*power), GFP_KERNEL);
102*4882a593Smuzhiyun if (!power)
103*4882a593Smuzhiyun return -ENOMEM;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
106*4882a593Smuzhiyun power->base = devm_ioremap_resource(&pdev->dev, res);
107*4882a593Smuzhiyun if (IS_ERR(power->base))
108*4882a593Smuzhiyun return PTR_ERR(power->base);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun table = of_device_get_match_data(dev);
111*4882a593Smuzhiyun if (!table)
112*4882a593Smuzhiyun return -EINVAL;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun power->genpd_data.num_domains = 0;
115*4882a593Smuzhiyun ndom = 0;
116*4882a593Smuzhiyun for (entry = table; entry->name; entry++) {
117*4882a593Smuzhiyun max_bit = max(max_bit, entry->bit);
118*4882a593Smuzhiyun ndom++;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun if (!ndom)
122*4882a593Smuzhiyun return -ENODEV;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun power->genpd_data.num_domains = max_bit + 1;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun power->dev = devm_kcalloc(dev, power->genpd_data.num_domains,
127*4882a593Smuzhiyun sizeof(struct bcm63xx_power_dev),
128*4882a593Smuzhiyun GFP_KERNEL);
129*4882a593Smuzhiyun if (!power->dev)
130*4882a593Smuzhiyun return -ENOMEM;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun power->genpd = devm_kcalloc(dev, power->genpd_data.num_domains,
133*4882a593Smuzhiyun sizeof(struct generic_pm_domain *),
134*4882a593Smuzhiyun GFP_KERNEL);
135*4882a593Smuzhiyun if (!power->genpd)
136*4882a593Smuzhiyun return -ENOMEM;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun power->genpd_data.domains = power->genpd;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun ndom = 0;
141*4882a593Smuzhiyun for (entry = table; entry->name; entry++) {
142*4882a593Smuzhiyun struct bcm63xx_power_dev *pmd = &power->dev[ndom];
143*4882a593Smuzhiyun bool is_on;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun pmd->power = power;
146*4882a593Smuzhiyun pmd->mask = BIT(entry->bit);
147*4882a593Smuzhiyun pmd->genpd.name = entry->name;
148*4882a593Smuzhiyun pmd->genpd.flags = entry->flags;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun ret = bcm63xx_power_get_state(pmd, &is_on);
151*4882a593Smuzhiyun if (ret)
152*4882a593Smuzhiyun dev_warn(dev, "unable to get current state for %s\n",
153*4882a593Smuzhiyun pmd->genpd.name);
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun pmd->genpd.power_on = bcm63xx_power_on;
156*4882a593Smuzhiyun pmd->genpd.power_off = bcm63xx_power_off;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun pm_genpd_init(&pmd->genpd, NULL, !is_on);
159*4882a593Smuzhiyun power->genpd[entry->bit] = &pmd->genpd;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun ndom++;
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun spin_lock_init(&power->lock);
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun ret = of_genpd_add_provider_onecell(np, &power->genpd_data);
167*4882a593Smuzhiyun if (ret) {
168*4882a593Smuzhiyun dev_err(dev, "failed to register genpd driver: %d\n", ret);
169*4882a593Smuzhiyun return ret;
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun dev_info(dev, "registered %u power domains\n", ndom);
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun return 0;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun static const struct bcm63xx_power_data bcm6318_power_domains[] = {
178*4882a593Smuzhiyun {
179*4882a593Smuzhiyun .name = "pcie",
180*4882a593Smuzhiyun .bit = BCM6318_POWER_DOMAIN_PCIE,
181*4882a593Smuzhiyun }, {
182*4882a593Smuzhiyun .name = "usb",
183*4882a593Smuzhiyun .bit = BCM6318_POWER_DOMAIN_USB,
184*4882a593Smuzhiyun }, {
185*4882a593Smuzhiyun .name = "ephy0",
186*4882a593Smuzhiyun .bit = BCM6318_POWER_DOMAIN_EPHY0,
187*4882a593Smuzhiyun }, {
188*4882a593Smuzhiyun .name = "ephy1",
189*4882a593Smuzhiyun .bit = BCM6318_POWER_DOMAIN_EPHY1,
190*4882a593Smuzhiyun }, {
191*4882a593Smuzhiyun .name = "ephy2",
192*4882a593Smuzhiyun .bit = BCM6318_POWER_DOMAIN_EPHY2,
193*4882a593Smuzhiyun }, {
194*4882a593Smuzhiyun .name = "ephy3",
195*4882a593Smuzhiyun .bit = BCM6318_POWER_DOMAIN_EPHY3,
196*4882a593Smuzhiyun }, {
197*4882a593Smuzhiyun .name = "ldo2p5",
198*4882a593Smuzhiyun .bit = BCM6318_POWER_DOMAIN_LDO2P5,
199*4882a593Smuzhiyun .flags = GENPD_FLAG_ALWAYS_ON,
200*4882a593Smuzhiyun }, {
201*4882a593Smuzhiyun .name = "ldo2p9",
202*4882a593Smuzhiyun .bit = BCM6318_POWER_DOMAIN_LDO2P9,
203*4882a593Smuzhiyun .flags = GENPD_FLAG_ALWAYS_ON,
204*4882a593Smuzhiyun }, {
205*4882a593Smuzhiyun .name = "sw1p0",
206*4882a593Smuzhiyun .bit = BCM6318_POWER_DOMAIN_SW1P0,
207*4882a593Smuzhiyun .flags = GENPD_FLAG_ALWAYS_ON,
208*4882a593Smuzhiyun }, {
209*4882a593Smuzhiyun .name = "pad",
210*4882a593Smuzhiyun .bit = BCM6318_POWER_DOMAIN_PAD,
211*4882a593Smuzhiyun .flags = GENPD_FLAG_ALWAYS_ON,
212*4882a593Smuzhiyun }, {
213*4882a593Smuzhiyun /* sentinel */
214*4882a593Smuzhiyun },
215*4882a593Smuzhiyun };
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun static const struct bcm63xx_power_data bcm6328_power_domains[] = {
218*4882a593Smuzhiyun {
219*4882a593Smuzhiyun .name = "adsl2-mips",
220*4882a593Smuzhiyun .bit = BCM6328_POWER_DOMAIN_ADSL2_MIPS,
221*4882a593Smuzhiyun }, {
222*4882a593Smuzhiyun .name = "adsl2-phy",
223*4882a593Smuzhiyun .bit = BCM6328_POWER_DOMAIN_ADSL2_PHY,
224*4882a593Smuzhiyun }, {
225*4882a593Smuzhiyun .name = "adsl2-afe",
226*4882a593Smuzhiyun .bit = BCM6328_POWER_DOMAIN_ADSL2_AFE,
227*4882a593Smuzhiyun }, {
228*4882a593Smuzhiyun .name = "sar",
229*4882a593Smuzhiyun .bit = BCM6328_POWER_DOMAIN_SAR,
230*4882a593Smuzhiyun }, {
231*4882a593Smuzhiyun .name = "pcm",
232*4882a593Smuzhiyun .bit = BCM6328_POWER_DOMAIN_PCM,
233*4882a593Smuzhiyun }, {
234*4882a593Smuzhiyun .name = "usbd",
235*4882a593Smuzhiyun .bit = BCM6328_POWER_DOMAIN_USBD,
236*4882a593Smuzhiyun }, {
237*4882a593Smuzhiyun .name = "usbh",
238*4882a593Smuzhiyun .bit = BCM6328_POWER_DOMAIN_USBH,
239*4882a593Smuzhiyun }, {
240*4882a593Smuzhiyun .name = "pcie",
241*4882a593Smuzhiyun .bit = BCM6328_POWER_DOMAIN_PCIE,
242*4882a593Smuzhiyun }, {
243*4882a593Smuzhiyun .name = "robosw",
244*4882a593Smuzhiyun .bit = BCM6328_POWER_DOMAIN_ROBOSW,
245*4882a593Smuzhiyun }, {
246*4882a593Smuzhiyun .name = "ephy",
247*4882a593Smuzhiyun .bit = BCM6328_POWER_DOMAIN_EPHY,
248*4882a593Smuzhiyun }, {
249*4882a593Smuzhiyun /* sentinel */
250*4882a593Smuzhiyun },
251*4882a593Smuzhiyun };
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun static const struct bcm63xx_power_data bcm6362_power_domains[] = {
254*4882a593Smuzhiyun {
255*4882a593Smuzhiyun .name = "sar",
256*4882a593Smuzhiyun .bit = BCM6362_POWER_DOMAIN_SAR,
257*4882a593Smuzhiyun }, {
258*4882a593Smuzhiyun .name = "ipsec",
259*4882a593Smuzhiyun .bit = BCM6362_POWER_DOMAIN_IPSEC,
260*4882a593Smuzhiyun }, {
261*4882a593Smuzhiyun .name = "mips",
262*4882a593Smuzhiyun .bit = BCM6362_POWER_DOMAIN_MIPS,
263*4882a593Smuzhiyun .flags = GENPD_FLAG_ALWAYS_ON,
264*4882a593Smuzhiyun }, {
265*4882a593Smuzhiyun .name = "dect",
266*4882a593Smuzhiyun .bit = BCM6362_POWER_DOMAIN_DECT,
267*4882a593Smuzhiyun }, {
268*4882a593Smuzhiyun .name = "usbh",
269*4882a593Smuzhiyun .bit = BCM6362_POWER_DOMAIN_USBH,
270*4882a593Smuzhiyun }, {
271*4882a593Smuzhiyun .name = "usbd",
272*4882a593Smuzhiyun .bit = BCM6362_POWER_DOMAIN_USBD,
273*4882a593Smuzhiyun }, {
274*4882a593Smuzhiyun .name = "robosw",
275*4882a593Smuzhiyun .bit = BCM6362_POWER_DOMAIN_ROBOSW,
276*4882a593Smuzhiyun }, {
277*4882a593Smuzhiyun .name = "pcm",
278*4882a593Smuzhiyun .bit = BCM6362_POWER_DOMAIN_PCM,
279*4882a593Smuzhiyun }, {
280*4882a593Smuzhiyun .name = "periph",
281*4882a593Smuzhiyun .bit = BCM6362_POWER_DOMAIN_PERIPH,
282*4882a593Smuzhiyun .flags = GENPD_FLAG_ALWAYS_ON,
283*4882a593Smuzhiyun }, {
284*4882a593Smuzhiyun .name = "adsl-phy",
285*4882a593Smuzhiyun .bit = BCM6362_POWER_DOMAIN_ADSL_PHY,
286*4882a593Smuzhiyun }, {
287*4882a593Smuzhiyun .name = "gmii-pads",
288*4882a593Smuzhiyun .bit = BCM6362_POWER_DOMAIN_GMII_PADS,
289*4882a593Smuzhiyun }, {
290*4882a593Smuzhiyun .name = "fap",
291*4882a593Smuzhiyun .bit = BCM6362_POWER_DOMAIN_FAP,
292*4882a593Smuzhiyun }, {
293*4882a593Smuzhiyun .name = "pcie",
294*4882a593Smuzhiyun .bit = BCM6362_POWER_DOMAIN_PCIE,
295*4882a593Smuzhiyun }, {
296*4882a593Smuzhiyun .name = "wlan-pads",
297*4882a593Smuzhiyun .bit = BCM6362_POWER_DOMAIN_WLAN_PADS,
298*4882a593Smuzhiyun }, {
299*4882a593Smuzhiyun /* sentinel */
300*4882a593Smuzhiyun },
301*4882a593Smuzhiyun };
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun static const struct bcm63xx_power_data bcm63268_power_domains[] = {
304*4882a593Smuzhiyun {
305*4882a593Smuzhiyun .name = "sar",
306*4882a593Smuzhiyun .bit = BCM63268_POWER_DOMAIN_SAR,
307*4882a593Smuzhiyun }, {
308*4882a593Smuzhiyun .name = "ipsec",
309*4882a593Smuzhiyun .bit = BCM63268_POWER_DOMAIN_IPSEC,
310*4882a593Smuzhiyun }, {
311*4882a593Smuzhiyun .name = "mips",
312*4882a593Smuzhiyun .bit = BCM63268_POWER_DOMAIN_MIPS,
313*4882a593Smuzhiyun .flags = GENPD_FLAG_ALWAYS_ON,
314*4882a593Smuzhiyun }, {
315*4882a593Smuzhiyun .name = "dect",
316*4882a593Smuzhiyun .bit = BCM63268_POWER_DOMAIN_DECT,
317*4882a593Smuzhiyun }, {
318*4882a593Smuzhiyun .name = "usbh",
319*4882a593Smuzhiyun .bit = BCM63268_POWER_DOMAIN_USBH,
320*4882a593Smuzhiyun }, {
321*4882a593Smuzhiyun .name = "usbd",
322*4882a593Smuzhiyun .bit = BCM63268_POWER_DOMAIN_USBD,
323*4882a593Smuzhiyun }, {
324*4882a593Smuzhiyun .name = "robosw",
325*4882a593Smuzhiyun .bit = BCM63268_POWER_DOMAIN_ROBOSW,
326*4882a593Smuzhiyun }, {
327*4882a593Smuzhiyun .name = "pcm",
328*4882a593Smuzhiyun .bit = BCM63268_POWER_DOMAIN_PCM,
329*4882a593Smuzhiyun }, {
330*4882a593Smuzhiyun .name = "periph",
331*4882a593Smuzhiyun .bit = BCM63268_POWER_DOMAIN_PERIPH,
332*4882a593Smuzhiyun .flags = GENPD_FLAG_ALWAYS_ON,
333*4882a593Smuzhiyun }, {
334*4882a593Smuzhiyun .name = "vdsl-phy",
335*4882a593Smuzhiyun .bit = BCM63268_POWER_DOMAIN_VDSL_PHY,
336*4882a593Smuzhiyun }, {
337*4882a593Smuzhiyun .name = "vdsl-mips",
338*4882a593Smuzhiyun .bit = BCM63268_POWER_DOMAIN_VDSL_MIPS,
339*4882a593Smuzhiyun }, {
340*4882a593Smuzhiyun .name = "fap",
341*4882a593Smuzhiyun .bit = BCM63268_POWER_DOMAIN_FAP,
342*4882a593Smuzhiyun }, {
343*4882a593Smuzhiyun .name = "pcie",
344*4882a593Smuzhiyun .bit = BCM63268_POWER_DOMAIN_PCIE,
345*4882a593Smuzhiyun }, {
346*4882a593Smuzhiyun .name = "wlan-pads",
347*4882a593Smuzhiyun .bit = BCM63268_POWER_DOMAIN_WLAN_PADS,
348*4882a593Smuzhiyun }, {
349*4882a593Smuzhiyun /* sentinel */
350*4882a593Smuzhiyun },
351*4882a593Smuzhiyun };
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun static const struct of_device_id bcm63xx_power_of_match[] = {
354*4882a593Smuzhiyun {
355*4882a593Smuzhiyun .compatible = "brcm,bcm6318-power-controller",
356*4882a593Smuzhiyun .data = &bcm6318_power_domains,
357*4882a593Smuzhiyun }, {
358*4882a593Smuzhiyun .compatible = "brcm,bcm6328-power-controller",
359*4882a593Smuzhiyun .data = &bcm6328_power_domains,
360*4882a593Smuzhiyun }, {
361*4882a593Smuzhiyun .compatible = "brcm,bcm6362-power-controller",
362*4882a593Smuzhiyun .data = &bcm6362_power_domains,
363*4882a593Smuzhiyun }, {
364*4882a593Smuzhiyun .compatible = "brcm,bcm63268-power-controller",
365*4882a593Smuzhiyun .data = &bcm63268_power_domains,
366*4882a593Smuzhiyun }, {
367*4882a593Smuzhiyun /* sentinel */
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun };
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun static struct platform_driver bcm63xx_power_driver = {
372*4882a593Smuzhiyun .driver = {
373*4882a593Smuzhiyun .name = "bcm63xx-power-controller",
374*4882a593Smuzhiyun .of_match_table = bcm63xx_power_of_match,
375*4882a593Smuzhiyun },
376*4882a593Smuzhiyun .probe = bcm63xx_power_probe,
377*4882a593Smuzhiyun };
378*4882a593Smuzhiyun builtin_platform_driver(bcm63xx_power_driver);
379