xref: /OK3568_Linux_fs/kernel/drivers/soc/actions/owl-sps.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Actions Semi Owl Smart Power System (SPS)
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2012 Actions Semi Inc.
6*4882a593Smuzhiyun  * Author: Actions Semi, Inc.
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Copyright (c) 2017 Andreas Färber
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/of_address.h>
12*4882a593Smuzhiyun #include <linux/of_platform.h>
13*4882a593Smuzhiyun #include <linux/pm_domain.h>
14*4882a593Smuzhiyun #include <linux/soc/actions/owl-sps.h>
15*4882a593Smuzhiyun #include <dt-bindings/power/owl-s500-powergate.h>
16*4882a593Smuzhiyun #include <dt-bindings/power/owl-s700-powergate.h>
17*4882a593Smuzhiyun #include <dt-bindings/power/owl-s900-powergate.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun struct owl_sps_domain_info {
20*4882a593Smuzhiyun 	const char *name;
21*4882a593Smuzhiyun 	int pwr_bit;
22*4882a593Smuzhiyun 	int ack_bit;
23*4882a593Smuzhiyun 	unsigned int genpd_flags;
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun struct owl_sps_info {
27*4882a593Smuzhiyun 	unsigned num_domains;
28*4882a593Smuzhiyun 	const struct owl_sps_domain_info *domains;
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun struct owl_sps {
32*4882a593Smuzhiyun 	struct device *dev;
33*4882a593Smuzhiyun 	const struct owl_sps_info *info;
34*4882a593Smuzhiyun 	void __iomem *base;
35*4882a593Smuzhiyun 	struct genpd_onecell_data genpd_data;
36*4882a593Smuzhiyun 	struct generic_pm_domain *domains[];
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define to_owl_pd(gpd) container_of(gpd, struct owl_sps_domain, genpd)
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun struct owl_sps_domain {
42*4882a593Smuzhiyun 	struct generic_pm_domain genpd;
43*4882a593Smuzhiyun 	const struct owl_sps_domain_info *info;
44*4882a593Smuzhiyun 	struct owl_sps *sps;
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun 
owl_sps_set_power(struct owl_sps_domain * pd,bool enable)47*4882a593Smuzhiyun static int owl_sps_set_power(struct owl_sps_domain *pd, bool enable)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun 	u32 pwr_mask, ack_mask;
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun 	ack_mask = BIT(pd->info->ack_bit);
52*4882a593Smuzhiyun 	pwr_mask = BIT(pd->info->pwr_bit);
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	return owl_sps_set_pg(pd->sps->base, pwr_mask, ack_mask, enable);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun 
owl_sps_power_on(struct generic_pm_domain * domain)57*4882a593Smuzhiyun static int owl_sps_power_on(struct generic_pm_domain *domain)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun 	struct owl_sps_domain *pd = to_owl_pd(domain);
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	dev_dbg(pd->sps->dev, "%s power on", pd->info->name);
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	return owl_sps_set_power(pd, true);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun 
owl_sps_power_off(struct generic_pm_domain * domain)66*4882a593Smuzhiyun static int owl_sps_power_off(struct generic_pm_domain *domain)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun 	struct owl_sps_domain *pd = to_owl_pd(domain);
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	dev_dbg(pd->sps->dev, "%s power off", pd->info->name);
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	return owl_sps_set_power(pd, false);
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun 
owl_sps_init_domain(struct owl_sps * sps,int index)75*4882a593Smuzhiyun static int owl_sps_init_domain(struct owl_sps *sps, int index)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun 	struct owl_sps_domain *pd;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	pd = devm_kzalloc(sps->dev, sizeof(*pd), GFP_KERNEL);
80*4882a593Smuzhiyun 	if (!pd)
81*4882a593Smuzhiyun 		return -ENOMEM;
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	pd->info = &sps->info->domains[index];
84*4882a593Smuzhiyun 	pd->sps = sps;
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	pd->genpd.name = pd->info->name;
87*4882a593Smuzhiyun 	pd->genpd.power_on = owl_sps_power_on;
88*4882a593Smuzhiyun 	pd->genpd.power_off = owl_sps_power_off;
89*4882a593Smuzhiyun 	pd->genpd.flags = pd->info->genpd_flags;
90*4882a593Smuzhiyun 	pm_genpd_init(&pd->genpd, NULL, false);
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	sps->genpd_data.domains[index] = &pd->genpd;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	return 0;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun 
owl_sps_probe(struct platform_device * pdev)97*4882a593Smuzhiyun static int owl_sps_probe(struct platform_device *pdev)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun 	const struct of_device_id *match;
100*4882a593Smuzhiyun 	const struct owl_sps_info *sps_info;
101*4882a593Smuzhiyun 	struct owl_sps *sps;
102*4882a593Smuzhiyun 	int i, ret;
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	if (!pdev->dev.of_node) {
105*4882a593Smuzhiyun 		dev_err(&pdev->dev, "no device node\n");
106*4882a593Smuzhiyun 		return -ENODEV;
107*4882a593Smuzhiyun 	}
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	match = of_match_device(pdev->dev.driver->of_match_table, &pdev->dev);
110*4882a593Smuzhiyun 	if (!match || !match->data) {
111*4882a593Smuzhiyun 		dev_err(&pdev->dev, "unknown compatible or missing data\n");
112*4882a593Smuzhiyun 		return -EINVAL;
113*4882a593Smuzhiyun 	}
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	sps_info = match->data;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	sps = devm_kzalloc(&pdev->dev,
118*4882a593Smuzhiyun 			   struct_size(sps, domains, sps_info->num_domains),
119*4882a593Smuzhiyun 			   GFP_KERNEL);
120*4882a593Smuzhiyun 	if (!sps)
121*4882a593Smuzhiyun 		return -ENOMEM;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	sps->base = of_io_request_and_map(pdev->dev.of_node, 0, "owl-sps");
124*4882a593Smuzhiyun 	if (IS_ERR(sps->base)) {
125*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to map sps registers\n");
126*4882a593Smuzhiyun 		return PTR_ERR(sps->base);
127*4882a593Smuzhiyun 	}
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	sps->dev = &pdev->dev;
130*4882a593Smuzhiyun 	sps->info = sps_info;
131*4882a593Smuzhiyun 	sps->genpd_data.domains = sps->domains;
132*4882a593Smuzhiyun 	sps->genpd_data.num_domains = sps_info->num_domains;
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	for (i = 0; i < sps_info->num_domains; i++) {
135*4882a593Smuzhiyun 		ret = owl_sps_init_domain(sps, i);
136*4882a593Smuzhiyun 		if (ret)
137*4882a593Smuzhiyun 			return ret;
138*4882a593Smuzhiyun 	}
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	ret = of_genpd_add_provider_onecell(pdev->dev.of_node, &sps->genpd_data);
141*4882a593Smuzhiyun 	if (ret) {
142*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to add provider (%d)", ret);
143*4882a593Smuzhiyun 		return ret;
144*4882a593Smuzhiyun 	}
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	return 0;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun static const struct owl_sps_domain_info s500_sps_domains[] = {
150*4882a593Smuzhiyun 	[S500_PD_VDE] = {
151*4882a593Smuzhiyun 		.name = "VDE",
152*4882a593Smuzhiyun 		.pwr_bit = 0,
153*4882a593Smuzhiyun 		.ack_bit = 16,
154*4882a593Smuzhiyun 	},
155*4882a593Smuzhiyun 	[S500_PD_VCE_SI] = {
156*4882a593Smuzhiyun 		.name = "VCE_SI",
157*4882a593Smuzhiyun 		.pwr_bit = 1,
158*4882a593Smuzhiyun 		.ack_bit = 17,
159*4882a593Smuzhiyun 	},
160*4882a593Smuzhiyun 	[S500_PD_USB2_1] = {
161*4882a593Smuzhiyun 		.name = "USB2_1",
162*4882a593Smuzhiyun 		.pwr_bit = 2,
163*4882a593Smuzhiyun 		.ack_bit = 18,
164*4882a593Smuzhiyun 	},
165*4882a593Smuzhiyun 	[S500_PD_CPU2] = {
166*4882a593Smuzhiyun 		.name = "CPU2",
167*4882a593Smuzhiyun 		.pwr_bit = 5,
168*4882a593Smuzhiyun 		.ack_bit = 21,
169*4882a593Smuzhiyun 		.genpd_flags = GENPD_FLAG_ALWAYS_ON,
170*4882a593Smuzhiyun 	},
171*4882a593Smuzhiyun 	[S500_PD_CPU3] = {
172*4882a593Smuzhiyun 		.name = "CPU3",
173*4882a593Smuzhiyun 		.pwr_bit = 6,
174*4882a593Smuzhiyun 		.ack_bit = 22,
175*4882a593Smuzhiyun 		.genpd_flags = GENPD_FLAG_ALWAYS_ON,
176*4882a593Smuzhiyun 	},
177*4882a593Smuzhiyun 	[S500_PD_DMA] = {
178*4882a593Smuzhiyun 		.name = "DMA",
179*4882a593Smuzhiyun 		.pwr_bit = 8,
180*4882a593Smuzhiyun 		.ack_bit = 12,
181*4882a593Smuzhiyun 	},
182*4882a593Smuzhiyun 	[S500_PD_DS] = {
183*4882a593Smuzhiyun 		.name = "DS",
184*4882a593Smuzhiyun 		.pwr_bit = 9,
185*4882a593Smuzhiyun 		.ack_bit = 13,
186*4882a593Smuzhiyun 	},
187*4882a593Smuzhiyun 	[S500_PD_USB3] = {
188*4882a593Smuzhiyun 		.name = "USB3",
189*4882a593Smuzhiyun 		.pwr_bit = 10,
190*4882a593Smuzhiyun 		.ack_bit = 14,
191*4882a593Smuzhiyun 	},
192*4882a593Smuzhiyun 	[S500_PD_USB2_0] = {
193*4882a593Smuzhiyun 		.name = "USB2_0",
194*4882a593Smuzhiyun 		.pwr_bit = 11,
195*4882a593Smuzhiyun 		.ack_bit = 15,
196*4882a593Smuzhiyun 	},
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun static const struct owl_sps_info s500_sps_info = {
200*4882a593Smuzhiyun 	.num_domains = ARRAY_SIZE(s500_sps_domains),
201*4882a593Smuzhiyun 	.domains = s500_sps_domains,
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun static const struct owl_sps_domain_info s700_sps_domains[] = {
205*4882a593Smuzhiyun 	[S700_PD_VDE] = {
206*4882a593Smuzhiyun 		.name = "VDE",
207*4882a593Smuzhiyun 		.pwr_bit = 0,
208*4882a593Smuzhiyun 	},
209*4882a593Smuzhiyun 	[S700_PD_VCE_SI] = {
210*4882a593Smuzhiyun 		.name = "VCE_SI",
211*4882a593Smuzhiyun 		.pwr_bit = 1,
212*4882a593Smuzhiyun 	},
213*4882a593Smuzhiyun 	[S700_PD_USB2_1] = {
214*4882a593Smuzhiyun 		.name = "USB2_1",
215*4882a593Smuzhiyun 		.pwr_bit = 2,
216*4882a593Smuzhiyun 	},
217*4882a593Smuzhiyun 	[S700_PD_HDE] = {
218*4882a593Smuzhiyun 		.name = "HDE",
219*4882a593Smuzhiyun 		.pwr_bit = 7,
220*4882a593Smuzhiyun 	},
221*4882a593Smuzhiyun 	[S700_PD_DMA] = {
222*4882a593Smuzhiyun 		.name = "DMA",
223*4882a593Smuzhiyun 		.pwr_bit = 8,
224*4882a593Smuzhiyun 	},
225*4882a593Smuzhiyun 	[S700_PD_DS] = {
226*4882a593Smuzhiyun 		.name = "DS",
227*4882a593Smuzhiyun 		.pwr_bit = 9,
228*4882a593Smuzhiyun 	},
229*4882a593Smuzhiyun 	[S700_PD_USB3] = {
230*4882a593Smuzhiyun 		.name = "USB3",
231*4882a593Smuzhiyun 		.pwr_bit = 10,
232*4882a593Smuzhiyun 	},
233*4882a593Smuzhiyun 	[S700_PD_USB2_0] = {
234*4882a593Smuzhiyun 		.name = "USB2_0",
235*4882a593Smuzhiyun 		.pwr_bit = 11,
236*4882a593Smuzhiyun 	},
237*4882a593Smuzhiyun };
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun static const struct owl_sps_info s700_sps_info = {
240*4882a593Smuzhiyun 	.num_domains = ARRAY_SIZE(s700_sps_domains),
241*4882a593Smuzhiyun 	.domains = s700_sps_domains,
242*4882a593Smuzhiyun };
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun static const struct owl_sps_domain_info s900_sps_domains[] = {
245*4882a593Smuzhiyun 	[S900_PD_GPU_B] = {
246*4882a593Smuzhiyun 		.name = "GPU_B",
247*4882a593Smuzhiyun 		.pwr_bit = 3,
248*4882a593Smuzhiyun 	},
249*4882a593Smuzhiyun 	[S900_PD_VCE] = {
250*4882a593Smuzhiyun 		.name = "VCE",
251*4882a593Smuzhiyun 		.pwr_bit = 4,
252*4882a593Smuzhiyun 	},
253*4882a593Smuzhiyun 	[S900_PD_SENSOR] = {
254*4882a593Smuzhiyun 		.name = "SENSOR",
255*4882a593Smuzhiyun 		.pwr_bit = 5,
256*4882a593Smuzhiyun 	},
257*4882a593Smuzhiyun 	[S900_PD_VDE] = {
258*4882a593Smuzhiyun 		.name = "VDE",
259*4882a593Smuzhiyun 		.pwr_bit = 6,
260*4882a593Smuzhiyun 	},
261*4882a593Smuzhiyun 	[S900_PD_HDE] = {
262*4882a593Smuzhiyun 		.name = "HDE",
263*4882a593Smuzhiyun 		.pwr_bit = 7,
264*4882a593Smuzhiyun 	},
265*4882a593Smuzhiyun 	[S900_PD_USB3] = {
266*4882a593Smuzhiyun 		.name = "USB3",
267*4882a593Smuzhiyun 		.pwr_bit = 8,
268*4882a593Smuzhiyun 	},
269*4882a593Smuzhiyun 	[S900_PD_DDR0] = {
270*4882a593Smuzhiyun 		.name = "DDR0",
271*4882a593Smuzhiyun 		.pwr_bit = 9,
272*4882a593Smuzhiyun 	},
273*4882a593Smuzhiyun 	[S900_PD_DDR1] = {
274*4882a593Smuzhiyun 		.name = "DDR1",
275*4882a593Smuzhiyun 		.pwr_bit = 10,
276*4882a593Smuzhiyun 	},
277*4882a593Smuzhiyun 	[S900_PD_DE] = {
278*4882a593Smuzhiyun 		.name = "DE",
279*4882a593Smuzhiyun 		.pwr_bit = 13,
280*4882a593Smuzhiyun 	},
281*4882a593Smuzhiyun 	[S900_PD_NAND] = {
282*4882a593Smuzhiyun 		.name = "NAND",
283*4882a593Smuzhiyun 		.pwr_bit = 14,
284*4882a593Smuzhiyun 	},
285*4882a593Smuzhiyun 	[S900_PD_USB2_H0] = {
286*4882a593Smuzhiyun 		.name = "USB2_H0",
287*4882a593Smuzhiyun 		.pwr_bit = 15,
288*4882a593Smuzhiyun 	},
289*4882a593Smuzhiyun 	[S900_PD_USB2_H1] = {
290*4882a593Smuzhiyun 		.name = "USB2_H1",
291*4882a593Smuzhiyun 		.pwr_bit = 16,
292*4882a593Smuzhiyun 	},
293*4882a593Smuzhiyun };
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun static const struct owl_sps_info s900_sps_info = {
296*4882a593Smuzhiyun 	.num_domains = ARRAY_SIZE(s900_sps_domains),
297*4882a593Smuzhiyun 	.domains = s900_sps_domains,
298*4882a593Smuzhiyun };
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun static const struct of_device_id owl_sps_of_matches[] = {
301*4882a593Smuzhiyun 	{ .compatible = "actions,s500-sps", .data = &s500_sps_info },
302*4882a593Smuzhiyun 	{ .compatible = "actions,s700-sps", .data = &s700_sps_info },
303*4882a593Smuzhiyun 	{ .compatible = "actions,s900-sps", .data = &s900_sps_info },
304*4882a593Smuzhiyun 	{ }
305*4882a593Smuzhiyun };
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun static struct platform_driver owl_sps_platform_driver = {
308*4882a593Smuzhiyun 	.probe = owl_sps_probe,
309*4882a593Smuzhiyun 	.driver = {
310*4882a593Smuzhiyun 		.name = "owl-sps",
311*4882a593Smuzhiyun 		.of_match_table = owl_sps_of_matches,
312*4882a593Smuzhiyun 		.suppress_bind_attrs = true,
313*4882a593Smuzhiyun 	},
314*4882a593Smuzhiyun };
315*4882a593Smuzhiyun 
owl_sps_init(void)316*4882a593Smuzhiyun static int __init owl_sps_init(void)
317*4882a593Smuzhiyun {
318*4882a593Smuzhiyun 	return platform_driver_register(&owl_sps_platform_driver);
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun postcore_initcall(owl_sps_init);
321