xref: /OK3568_Linux_fs/kernel/drivers/sh/intc/internals.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #include <linux/sh_intc.h>
3*4882a593Smuzhiyun #include <linux/irq.h>
4*4882a593Smuzhiyun #include <linux/irqdomain.h>
5*4882a593Smuzhiyun #include <linux/list.h>
6*4882a593Smuzhiyun #include <linux/kernel.h>
7*4882a593Smuzhiyun #include <linux/types.h>
8*4882a593Smuzhiyun #include <linux/radix-tree.h>
9*4882a593Smuzhiyun #include <linux/device.h>
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
12*4882a593Smuzhiyun 	((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
13*4882a593Smuzhiyun 	 ((addr_e) << 16) | ((addr_d << 24)))
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #define _INTC_SHIFT(h)		(h & 0x1f)
16*4882a593Smuzhiyun #define _INTC_WIDTH(h)		((h >> 5) & 0xf)
17*4882a593Smuzhiyun #define _INTC_FN(h)		((h >> 9) & 0xf)
18*4882a593Smuzhiyun #define _INTC_MODE(h)		((h >> 13) & 0x7)
19*4882a593Smuzhiyun #define _INTC_ADDR_E(h)		((h >> 16) & 0xff)
20*4882a593Smuzhiyun #define _INTC_ADDR_D(h)		((h >> 24) & 0xff)
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #ifdef CONFIG_SMP
23*4882a593Smuzhiyun #define IS_SMP(x)		(x.smp)
24*4882a593Smuzhiyun #define INTC_REG(d, x, c)	(d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
25*4882a593Smuzhiyun #define SMP_NR(d, x)		((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
26*4882a593Smuzhiyun #else
27*4882a593Smuzhiyun #define IS_SMP(x)		0
28*4882a593Smuzhiyun #define INTC_REG(d, x, c)	(d->reg[(x)])
29*4882a593Smuzhiyun #define SMP_NR(d, x)		1
30*4882a593Smuzhiyun #endif
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun struct intc_handle_int {
33*4882a593Smuzhiyun 	unsigned int irq;
34*4882a593Smuzhiyun 	unsigned long handle;
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun struct intc_window {
38*4882a593Smuzhiyun 	phys_addr_t phys;
39*4882a593Smuzhiyun 	void __iomem *virt;
40*4882a593Smuzhiyun 	unsigned long size;
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun struct intc_map_entry {
44*4882a593Smuzhiyun 	intc_enum enum_id;
45*4882a593Smuzhiyun 	struct intc_desc_int *desc;
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun struct intc_subgroup_entry {
49*4882a593Smuzhiyun 	unsigned int pirq;
50*4882a593Smuzhiyun 	intc_enum enum_id;
51*4882a593Smuzhiyun 	unsigned long handle;
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun struct intc_desc_int {
55*4882a593Smuzhiyun 	struct list_head list;
56*4882a593Smuzhiyun 	struct device dev;
57*4882a593Smuzhiyun 	struct radix_tree_root tree;
58*4882a593Smuzhiyun 	raw_spinlock_t lock;
59*4882a593Smuzhiyun 	unsigned int index;
60*4882a593Smuzhiyun 	unsigned long *reg;
61*4882a593Smuzhiyun #ifdef CONFIG_SMP
62*4882a593Smuzhiyun 	unsigned long *smp;
63*4882a593Smuzhiyun #endif
64*4882a593Smuzhiyun 	unsigned int nr_reg;
65*4882a593Smuzhiyun 	struct intc_handle_int *prio;
66*4882a593Smuzhiyun 	unsigned int nr_prio;
67*4882a593Smuzhiyun 	struct intc_handle_int *sense;
68*4882a593Smuzhiyun 	unsigned int nr_sense;
69*4882a593Smuzhiyun 	struct intc_window *window;
70*4882a593Smuzhiyun 	unsigned int nr_windows;
71*4882a593Smuzhiyun 	struct irq_domain *domain;
72*4882a593Smuzhiyun 	struct irq_chip chip;
73*4882a593Smuzhiyun 	bool skip_suspend;
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun enum {
78*4882a593Smuzhiyun 	REG_FN_ERR = 0,
79*4882a593Smuzhiyun 	REG_FN_TEST_BASE = 1,
80*4882a593Smuzhiyun 	REG_FN_WRITE_BASE = 5,
81*4882a593Smuzhiyun 	REG_FN_MODIFY_BASE = 9
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun enum {	MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
85*4882a593Smuzhiyun 	MODE_MASK_REG,       /* Bit(s) set -> interrupt disabled */
86*4882a593Smuzhiyun 	MODE_DUAL_REG,       /* Two registers, set bit to enable / disable */
87*4882a593Smuzhiyun 	MODE_PRIO_REG,       /* Priority value written to enable interrupt */
88*4882a593Smuzhiyun 	MODE_PCLR_REG,       /* Above plus all bits set to disable interrupt */
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun 
get_intc_desc(unsigned int irq)91*4882a593Smuzhiyun static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun 	struct irq_chip *chip = irq_get_chip(irq);
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	return container_of(chip, struct intc_desc_int, chip);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun /*
99*4882a593Smuzhiyun  * Grumble.
100*4882a593Smuzhiyun  */
activate_irq(int irq)101*4882a593Smuzhiyun static inline void activate_irq(int irq)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun 	irq_modify_status(irq, IRQ_NOREQUEST, IRQ_NOPROBE);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun 
intc_handle_int_cmp(const void * a,const void * b)106*4882a593Smuzhiyun static inline int intc_handle_int_cmp(const void *a, const void *b)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun 	const struct intc_handle_int *_a = a;
109*4882a593Smuzhiyun 	const struct intc_handle_int *_b = b;
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	return _a->irq - _b->irq;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun /* access.c */
115*4882a593Smuzhiyun extern unsigned long
116*4882a593Smuzhiyun (*intc_reg_fns[])(unsigned long addr, unsigned long h, unsigned long data);
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun extern unsigned long
119*4882a593Smuzhiyun (*intc_enable_fns[])(unsigned long addr, unsigned long handle,
120*4882a593Smuzhiyun 		     unsigned long (*fn)(unsigned long,
121*4882a593Smuzhiyun 				unsigned long, unsigned long),
122*4882a593Smuzhiyun 		     unsigned int irq);
123*4882a593Smuzhiyun extern unsigned long
124*4882a593Smuzhiyun (*intc_disable_fns[])(unsigned long addr, unsigned long handle,
125*4882a593Smuzhiyun 		      unsigned long (*fn)(unsigned long,
126*4882a593Smuzhiyun 				unsigned long, unsigned long),
127*4882a593Smuzhiyun 		      unsigned int irq);
128*4882a593Smuzhiyun extern unsigned long
129*4882a593Smuzhiyun (*intc_enable_noprio_fns[])(unsigned long addr, unsigned long handle,
130*4882a593Smuzhiyun 		            unsigned long (*fn)(unsigned long,
131*4882a593Smuzhiyun 				unsigned long, unsigned long),
132*4882a593Smuzhiyun 			    unsigned int irq);
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun unsigned long intc_phys_to_virt(struct intc_desc_int *d, unsigned long address);
135*4882a593Smuzhiyun unsigned int intc_get_reg(struct intc_desc_int *d, unsigned long address);
136*4882a593Smuzhiyun unsigned int intc_set_field_from_handle(unsigned int value,
137*4882a593Smuzhiyun 			    unsigned int field_value,
138*4882a593Smuzhiyun 			    unsigned int handle);
139*4882a593Smuzhiyun unsigned long intc_get_field_from_handle(unsigned int value,
140*4882a593Smuzhiyun 					 unsigned int handle);
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun /* balancing.c */
143*4882a593Smuzhiyun #ifdef CONFIG_INTC_BALANCING
144*4882a593Smuzhiyun void intc_balancing_enable(unsigned int irq);
145*4882a593Smuzhiyun void intc_balancing_disable(unsigned int irq);
146*4882a593Smuzhiyun void intc_set_dist_handle(unsigned int irq, struct intc_desc *desc,
147*4882a593Smuzhiyun 			  struct intc_desc_int *d, intc_enum id);
148*4882a593Smuzhiyun #else
intc_balancing_enable(unsigned int irq)149*4882a593Smuzhiyun static inline void intc_balancing_enable(unsigned int irq) { }
intc_balancing_disable(unsigned int irq)150*4882a593Smuzhiyun static inline void intc_balancing_disable(unsigned int irq) { }
151*4882a593Smuzhiyun static inline void
intc_set_dist_handle(unsigned int irq,struct intc_desc * desc,struct intc_desc_int * d,intc_enum id)152*4882a593Smuzhiyun intc_set_dist_handle(unsigned int irq, struct intc_desc *desc,
153*4882a593Smuzhiyun 		     struct intc_desc_int *d, intc_enum id) { }
154*4882a593Smuzhiyun #endif
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun /* chip.c */
157*4882a593Smuzhiyun extern struct irq_chip intc_irq_chip;
158*4882a593Smuzhiyun void _intc_enable(struct irq_data *data, unsigned long handle);
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun /* core.c */
161*4882a593Smuzhiyun extern struct list_head intc_list;
162*4882a593Smuzhiyun extern raw_spinlock_t intc_big_lock;
163*4882a593Smuzhiyun extern struct bus_type intc_subsys;
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun unsigned int intc_get_dfl_prio_level(void);
166*4882a593Smuzhiyun unsigned int intc_get_prio_level(unsigned int irq);
167*4882a593Smuzhiyun void intc_set_prio_level(unsigned int irq, unsigned int level);
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun /* handle.c */
170*4882a593Smuzhiyun unsigned int intc_get_mask_handle(struct intc_desc *desc,
171*4882a593Smuzhiyun 				  struct intc_desc_int *d,
172*4882a593Smuzhiyun 				  intc_enum enum_id, int do_grps);
173*4882a593Smuzhiyun unsigned int intc_get_prio_handle(struct intc_desc *desc,
174*4882a593Smuzhiyun 				  struct intc_desc_int *d,
175*4882a593Smuzhiyun 				  intc_enum enum_id, int do_grps);
176*4882a593Smuzhiyun unsigned int intc_get_sense_handle(struct intc_desc *desc,
177*4882a593Smuzhiyun 				   struct intc_desc_int *d,
178*4882a593Smuzhiyun 				   intc_enum enum_id);
179*4882a593Smuzhiyun void intc_set_ack_handle(unsigned int irq, struct intc_desc *desc,
180*4882a593Smuzhiyun 			 struct intc_desc_int *d, intc_enum id);
181*4882a593Smuzhiyun unsigned long intc_get_ack_handle(unsigned int irq);
182*4882a593Smuzhiyun void intc_enable_disable_enum(struct intc_desc *desc, struct intc_desc_int *d,
183*4882a593Smuzhiyun 			      intc_enum enum_id, int enable);
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun /* irqdomain.c */
186*4882a593Smuzhiyun void intc_irq_domain_init(struct intc_desc_int *d, struct intc_hw_desc *hw);
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun /* virq.c */
189*4882a593Smuzhiyun void intc_subgroup_init(struct intc_desc *desc, struct intc_desc_int *d);
190*4882a593Smuzhiyun void intc_irq_xlate_set(unsigned int irq, intc_enum id, struct intc_desc_int *d);
191*4882a593Smuzhiyun struct intc_map_entry *intc_irq_xlate_get(unsigned int irq);
192