1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyunconfig SH_INTC 3*4882a593Smuzhiyun bool 4*4882a593Smuzhiyun select IRQ_DOMAIN 5*4882a593Smuzhiyun 6*4882a593Smuzhiyunif SH_INTC 7*4882a593Smuzhiyun 8*4882a593Smuzhiyuncomment "Interrupt controller options" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyunconfig INTC_USERIMASK 11*4882a593Smuzhiyun bool "Userspace interrupt masking support" 12*4882a593Smuzhiyun depends on (SUPERH && CPU_SH4A) || COMPILE_TEST 13*4882a593Smuzhiyun help 14*4882a593Smuzhiyun This enables support for hardware-assisted userspace hardirq 15*4882a593Smuzhiyun masking. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun SH-4A and newer interrupt blocks all support a special shadowed 18*4882a593Smuzhiyun page with all non-masking registers obscured when mapped in to 19*4882a593Smuzhiyun userspace. This is primarily for use by userspace device 20*4882a593Smuzhiyun drivers that are using special priority levels. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun If in doubt, say N. 23*4882a593Smuzhiyun 24*4882a593Smuzhiyunconfig INTC_BALANCING 25*4882a593Smuzhiyun bool "Hardware IRQ balancing support" 26*4882a593Smuzhiyun depends on SMP && SUPERH && CPU_SHX3 27*4882a593Smuzhiyun help 28*4882a593Smuzhiyun This enables support for IRQ auto-distribution mode on SH-X3 29*4882a593Smuzhiyun SMP parts. All of the balancing and CPU wakeup decisions are 30*4882a593Smuzhiyun taken care of automatically by hardware for distributed 31*4882a593Smuzhiyun vectors. 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun If in doubt, say N. 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunconfig INTC_MAPPING_DEBUG 36*4882a593Smuzhiyun bool "Expose IRQ to per-controller id mapping via debugfs" 37*4882a593Smuzhiyun depends on DEBUG_FS 38*4882a593Smuzhiyun help 39*4882a593Smuzhiyun This will create a debugfs entry for showing the relationship 40*4882a593Smuzhiyun between system IRQs and the per-controller id tables. 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun If in doubt, say N. 43*4882a593Smuzhiyun 44*4882a593Smuzhiyunendif 45