1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * UFS Host driver for Synopsys Designware Core 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com) 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Authors: Joao Pinto <jpinto@synopsys.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _UFSHCI_DWC_H 11*4882a593Smuzhiyun #define _UFSHCI_DWC_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* DWC HC UFSHCI specific Registers */ 14*4882a593Smuzhiyun enum dwc_specific_registers { 15*4882a593Smuzhiyun DWC_UFS_REG_HCLKDIV = 0xFC, 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Clock Divider Values: Hex equivalent of frequency in MHz */ 19*4882a593Smuzhiyun enum clk_div_values { 20*4882a593Smuzhiyun DWC_UFS_REG_HCLKDIV_DIV_62_5 = 0x3e, 21*4882a593Smuzhiyun DWC_UFS_REG_HCLKDIV_DIV_125 = 0x7d, 22*4882a593Smuzhiyun DWC_UFS_REG_HCLKDIV_DIV_200 = 0xc8, 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Selector Index */ 26*4882a593Smuzhiyun enum selector_index { 27*4882a593Smuzhiyun SELIND_LN0_TX = 0x00, 28*4882a593Smuzhiyun SELIND_LN1_TX = 0x01, 29*4882a593Smuzhiyun SELIND_LN0_RX = 0x04, 30*4882a593Smuzhiyun SELIND_LN1_RX = 0x05, 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #endif /* End of Header */ 34