xref: /OK3568_Linux_fs/kernel/drivers/scsi/ufs/ufshcd.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Universal Flash Storage Host controller driver
4*4882a593Smuzhiyun  * Copyright (C) 2011-2013 Samsung India Software Operations
5*4882a593Smuzhiyun  * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Authors:
8*4882a593Smuzhiyun  *	Santosh Yaraganavi <santosh.sy@samsung.com>
9*4882a593Smuzhiyun  *	Vinayak Holikatti <h.vinayak@samsung.com>
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #ifndef _UFSHCD_H
13*4882a593Smuzhiyun #define _UFSHCD_H
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/kernel.h>
17*4882a593Smuzhiyun #include <linux/init.h>
18*4882a593Smuzhiyun #include <linux/interrupt.h>
19*4882a593Smuzhiyun #include <linux/io.h>
20*4882a593Smuzhiyun #include <linux/delay.h>
21*4882a593Smuzhiyun #include <linux/slab.h>
22*4882a593Smuzhiyun #include <linux/spinlock.h>
23*4882a593Smuzhiyun #include <linux/rwsem.h>
24*4882a593Smuzhiyun #include <linux/workqueue.h>
25*4882a593Smuzhiyun #include <linux/errno.h>
26*4882a593Smuzhiyun #include <linux/types.h>
27*4882a593Smuzhiyun #include <linux/wait.h>
28*4882a593Smuzhiyun #include <linux/bitops.h>
29*4882a593Smuzhiyun #include <linux/pm_runtime.h>
30*4882a593Smuzhiyun #include <linux/clk.h>
31*4882a593Smuzhiyun #include <linux/completion.h>
32*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
33*4882a593Smuzhiyun #include <linux/bitfield.h>
34*4882a593Smuzhiyun #include <linux/devfreq.h>
35*4882a593Smuzhiyun #include <linux/keyslot-manager.h>
36*4882a593Smuzhiyun #include "unipro.h"
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #include <asm/irq.h>
39*4882a593Smuzhiyun #include <asm/byteorder.h>
40*4882a593Smuzhiyun #include <scsi/scsi.h>
41*4882a593Smuzhiyun #include <scsi/scsi_cmnd.h>
42*4882a593Smuzhiyun #include <scsi/scsi_host.h>
43*4882a593Smuzhiyun #include <scsi/scsi_tcq.h>
44*4882a593Smuzhiyun #include <scsi/scsi_dbg.h>
45*4882a593Smuzhiyun #include <scsi/scsi_eh.h>
46*4882a593Smuzhiyun #include <linux/android_kabi.h>
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #include "ufs.h"
49*4882a593Smuzhiyun #include "ufs_quirks.h"
50*4882a593Smuzhiyun #include "ufshci.h"
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #define UFSHCD "ufshcd"
53*4882a593Smuzhiyun #define UFSHCD_DRIVER_VERSION "0.2"
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun struct ufs_hba;
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun enum dev_cmd_type {
58*4882a593Smuzhiyun 	DEV_CMD_TYPE_NOP		= 0x0,
59*4882a593Smuzhiyun 	DEV_CMD_TYPE_QUERY		= 0x1,
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun enum ufs_event_type {
63*4882a593Smuzhiyun 	/* uic specific errors */
64*4882a593Smuzhiyun 	UFS_EVT_PA_ERR = 0,
65*4882a593Smuzhiyun 	UFS_EVT_DL_ERR,
66*4882a593Smuzhiyun 	UFS_EVT_NL_ERR,
67*4882a593Smuzhiyun 	UFS_EVT_TL_ERR,
68*4882a593Smuzhiyun 	UFS_EVT_DME_ERR,
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	/* fatal errors */
71*4882a593Smuzhiyun 	UFS_EVT_AUTO_HIBERN8_ERR,
72*4882a593Smuzhiyun 	UFS_EVT_FATAL_ERR,
73*4882a593Smuzhiyun 	UFS_EVT_LINK_STARTUP_FAIL,
74*4882a593Smuzhiyun 	UFS_EVT_RESUME_ERR,
75*4882a593Smuzhiyun 	UFS_EVT_SUSPEND_ERR,
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	/* abnormal events */
78*4882a593Smuzhiyun 	UFS_EVT_DEV_RESET,
79*4882a593Smuzhiyun 	UFS_EVT_HOST_RESET,
80*4882a593Smuzhiyun 	UFS_EVT_ABORT,
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	UFS_EVT_CNT,
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun /**
86*4882a593Smuzhiyun  * struct uic_command - UIC command structure
87*4882a593Smuzhiyun  * @command: UIC command
88*4882a593Smuzhiyun  * @argument1: UIC command argument 1
89*4882a593Smuzhiyun  * @argument2: UIC command argument 2
90*4882a593Smuzhiyun  * @argument3: UIC command argument 3
91*4882a593Smuzhiyun  * @cmd_active: Indicate if UIC command is outstanding
92*4882a593Smuzhiyun  * @done: UIC command completion
93*4882a593Smuzhiyun  */
94*4882a593Smuzhiyun struct uic_command {
95*4882a593Smuzhiyun 	u32 command;
96*4882a593Smuzhiyun 	u32 argument1;
97*4882a593Smuzhiyun 	u32 argument2;
98*4882a593Smuzhiyun 	u32 argument3;
99*4882a593Smuzhiyun 	int cmd_active;
100*4882a593Smuzhiyun 	struct completion done;
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /* Used to differentiate the power management options */
104*4882a593Smuzhiyun enum ufs_pm_op {
105*4882a593Smuzhiyun 	UFS_RUNTIME_PM,
106*4882a593Smuzhiyun 	UFS_SYSTEM_PM,
107*4882a593Smuzhiyun 	UFS_SHUTDOWN_PM,
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun #define ufshcd_is_runtime_pm(op) ((op) == UFS_RUNTIME_PM)
111*4882a593Smuzhiyun #define ufshcd_is_system_pm(op) ((op) == UFS_SYSTEM_PM)
112*4882a593Smuzhiyun #define ufshcd_is_shutdown_pm(op) ((op) == UFS_SHUTDOWN_PM)
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun /* Host <-> Device UniPro Link state */
115*4882a593Smuzhiyun enum uic_link_state {
116*4882a593Smuzhiyun 	UIC_LINK_OFF_STATE	= 0, /* Link powered down or disabled */
117*4882a593Smuzhiyun 	UIC_LINK_ACTIVE_STATE	= 1, /* Link is in Fast/Slow/Sleep state */
118*4882a593Smuzhiyun 	UIC_LINK_HIBERN8_STATE	= 2, /* Link is in Hibernate state */
119*4882a593Smuzhiyun 	UIC_LINK_BROKEN_STATE	= 3, /* Link is in broken state */
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE)
123*4882a593Smuzhiyun #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \
124*4882a593Smuzhiyun 				    UIC_LINK_ACTIVE_STATE)
125*4882a593Smuzhiyun #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \
126*4882a593Smuzhiyun 				    UIC_LINK_HIBERN8_STATE)
127*4882a593Smuzhiyun #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \
128*4882a593Smuzhiyun 				   UIC_LINK_BROKEN_STATE)
129*4882a593Smuzhiyun #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE)
130*4882a593Smuzhiyun #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \
131*4882a593Smuzhiyun 				    UIC_LINK_ACTIVE_STATE)
132*4882a593Smuzhiyun #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \
133*4882a593Smuzhiyun 				    UIC_LINK_HIBERN8_STATE)
134*4882a593Smuzhiyun #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \
135*4882a593Smuzhiyun 				    UIC_LINK_BROKEN_STATE)
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun #define ufshcd_set_ufs_dev_active(h) \
138*4882a593Smuzhiyun 	((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
139*4882a593Smuzhiyun #define ufshcd_set_ufs_dev_sleep(h) \
140*4882a593Smuzhiyun 	((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
141*4882a593Smuzhiyun #define ufshcd_set_ufs_dev_poweroff(h) \
142*4882a593Smuzhiyun 	((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
143*4882a593Smuzhiyun #define ufshcd_is_ufs_dev_active(h) \
144*4882a593Smuzhiyun 	((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
145*4882a593Smuzhiyun #define ufshcd_is_ufs_dev_sleep(h) \
146*4882a593Smuzhiyun 	((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
147*4882a593Smuzhiyun #define ufshcd_is_ufs_dev_poweroff(h) \
148*4882a593Smuzhiyun 	((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun /*
151*4882a593Smuzhiyun  * UFS Power management levels.
152*4882a593Smuzhiyun  * Each level is in increasing order of power savings.
153*4882a593Smuzhiyun  */
154*4882a593Smuzhiyun enum ufs_pm_level {
155*4882a593Smuzhiyun 	UFS_PM_LVL_0, /* UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE */
156*4882a593Smuzhiyun 	UFS_PM_LVL_1, /* UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE */
157*4882a593Smuzhiyun 	UFS_PM_LVL_2, /* UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE */
158*4882a593Smuzhiyun 	UFS_PM_LVL_3, /* UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE */
159*4882a593Smuzhiyun 	UFS_PM_LVL_4, /* UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE */
160*4882a593Smuzhiyun 	UFS_PM_LVL_5, /* UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE */
161*4882a593Smuzhiyun 	UFS_PM_LVL_MAX
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun struct ufs_pm_lvl_states {
165*4882a593Smuzhiyun 	enum ufs_dev_pwr_mode dev_state;
166*4882a593Smuzhiyun 	enum uic_link_state link_state;
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun /**
170*4882a593Smuzhiyun  * struct ufshcd_lrb - local reference block
171*4882a593Smuzhiyun  * @utr_descriptor_ptr: UTRD address of the command
172*4882a593Smuzhiyun  * @ucd_req_ptr: UCD address of the command
173*4882a593Smuzhiyun  * @ucd_rsp_ptr: Response UPIU address for this command
174*4882a593Smuzhiyun  * @ucd_prdt_ptr: PRDT address of the command
175*4882a593Smuzhiyun  * @utrd_dma_addr: UTRD dma address for debug
176*4882a593Smuzhiyun  * @ucd_prdt_dma_addr: PRDT dma address for debug
177*4882a593Smuzhiyun  * @ucd_rsp_dma_addr: UPIU response dma address for debug
178*4882a593Smuzhiyun  * @ucd_req_dma_addr: UPIU request dma address for debug
179*4882a593Smuzhiyun  * @cmd: pointer to SCSI command
180*4882a593Smuzhiyun  * @sense_buffer: pointer to sense buffer address of the SCSI command
181*4882a593Smuzhiyun  * @sense_bufflen: Length of the sense buffer
182*4882a593Smuzhiyun  * @scsi_status: SCSI status of the command
183*4882a593Smuzhiyun  * @command_type: SCSI, UFS, Query.
184*4882a593Smuzhiyun  * @task_tag: Task tag of the command
185*4882a593Smuzhiyun  * @lun: LUN of the command
186*4882a593Smuzhiyun  * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation)
187*4882a593Smuzhiyun  * @issue_time_stamp: time stamp for debug purposes
188*4882a593Smuzhiyun  * @compl_time_stamp: time stamp for statistics
189*4882a593Smuzhiyun  * @crypto_key_slot: the key slot to use for inline crypto (-1 if none)
190*4882a593Smuzhiyun  * @data_unit_num: the data unit number for the first block for inline crypto
191*4882a593Smuzhiyun  * @req_abort_skip: skip request abort task flag
192*4882a593Smuzhiyun  */
193*4882a593Smuzhiyun struct ufshcd_lrb {
194*4882a593Smuzhiyun 	struct utp_transfer_req_desc *utr_descriptor_ptr;
195*4882a593Smuzhiyun 	struct utp_upiu_req *ucd_req_ptr;
196*4882a593Smuzhiyun 	struct utp_upiu_rsp *ucd_rsp_ptr;
197*4882a593Smuzhiyun 	struct ufshcd_sg_entry *ucd_prdt_ptr;
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	dma_addr_t utrd_dma_addr;
200*4882a593Smuzhiyun 	dma_addr_t ucd_req_dma_addr;
201*4882a593Smuzhiyun 	dma_addr_t ucd_rsp_dma_addr;
202*4882a593Smuzhiyun 	dma_addr_t ucd_prdt_dma_addr;
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	struct scsi_cmnd *cmd;
205*4882a593Smuzhiyun 	u8 *sense_buffer;
206*4882a593Smuzhiyun 	unsigned int sense_bufflen;
207*4882a593Smuzhiyun 	int scsi_status;
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	int command_type;
210*4882a593Smuzhiyun 	int task_tag;
211*4882a593Smuzhiyun 	u8 lun; /* UPIU LUN id field is only 8-bit wide */
212*4882a593Smuzhiyun 	bool intr_cmd;
213*4882a593Smuzhiyun 	ktime_t issue_time_stamp;
214*4882a593Smuzhiyun 	ktime_t compl_time_stamp;
215*4882a593Smuzhiyun #ifdef CONFIG_SCSI_UFS_CRYPTO
216*4882a593Smuzhiyun 	int crypto_key_slot;
217*4882a593Smuzhiyun 	u64 data_unit_num;
218*4882a593Smuzhiyun #endif
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	bool req_abort_skip;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	ANDROID_KABI_RESERVE(1);
223*4882a593Smuzhiyun };
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun /**
226*4882a593Smuzhiyun  * struct ufs_query - holds relevant data structures for query request
227*4882a593Smuzhiyun  * @request: request upiu and function
228*4882a593Smuzhiyun  * @descriptor: buffer for sending/receiving descriptor
229*4882a593Smuzhiyun  * @response: response upiu and response
230*4882a593Smuzhiyun  */
231*4882a593Smuzhiyun struct ufs_query {
232*4882a593Smuzhiyun 	struct ufs_query_req request;
233*4882a593Smuzhiyun 	u8 *descriptor;
234*4882a593Smuzhiyun 	struct ufs_query_res response;
235*4882a593Smuzhiyun };
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun /**
238*4882a593Smuzhiyun  * struct ufs_dev_cmd - all assosiated fields with device management commands
239*4882a593Smuzhiyun  * @type: device management command type - Query, NOP OUT
240*4882a593Smuzhiyun  * @lock: lock to allow one command at a time
241*4882a593Smuzhiyun  * @complete: internal commands completion
242*4882a593Smuzhiyun  */
243*4882a593Smuzhiyun struct ufs_dev_cmd {
244*4882a593Smuzhiyun 	enum dev_cmd_type type;
245*4882a593Smuzhiyun 	struct mutex lock;
246*4882a593Smuzhiyun 	struct completion *complete;
247*4882a593Smuzhiyun 	struct ufs_query query;
248*4882a593Smuzhiyun };
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun /**
251*4882a593Smuzhiyun  * struct ufs_clk_info - UFS clock related info
252*4882a593Smuzhiyun  * @list: list headed by hba->clk_list_head
253*4882a593Smuzhiyun  * @clk: clock node
254*4882a593Smuzhiyun  * @name: clock name
255*4882a593Smuzhiyun  * @max_freq: maximum frequency supported by the clock
256*4882a593Smuzhiyun  * @min_freq: min frequency that can be used for clock scaling
257*4882a593Smuzhiyun  * @curr_freq: indicates the current frequency that it is set to
258*4882a593Smuzhiyun  * @keep_link_active: indicates that the clk should not be disabled if
259*4882a593Smuzhiyun 		      link is active
260*4882a593Smuzhiyun  * @enabled: variable to check against multiple enable/disable
261*4882a593Smuzhiyun  */
262*4882a593Smuzhiyun struct ufs_clk_info {
263*4882a593Smuzhiyun 	struct list_head list;
264*4882a593Smuzhiyun 	struct clk *clk;
265*4882a593Smuzhiyun 	const char *name;
266*4882a593Smuzhiyun 	u32 max_freq;
267*4882a593Smuzhiyun 	u32 min_freq;
268*4882a593Smuzhiyun 	u32 curr_freq;
269*4882a593Smuzhiyun 	bool keep_link_active;
270*4882a593Smuzhiyun 	bool enabled;
271*4882a593Smuzhiyun };
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun enum ufs_notify_change_status {
274*4882a593Smuzhiyun 	PRE_CHANGE,
275*4882a593Smuzhiyun 	POST_CHANGE,
276*4882a593Smuzhiyun };
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun struct ufs_pa_layer_attr {
279*4882a593Smuzhiyun 	u32 gear_rx;
280*4882a593Smuzhiyun 	u32 gear_tx;
281*4882a593Smuzhiyun 	u32 lane_rx;
282*4882a593Smuzhiyun 	u32 lane_tx;
283*4882a593Smuzhiyun 	u32 pwr_rx;
284*4882a593Smuzhiyun 	u32 pwr_tx;
285*4882a593Smuzhiyun 	u32 hs_rate;
286*4882a593Smuzhiyun };
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun struct ufs_pwr_mode_info {
289*4882a593Smuzhiyun 	bool is_valid;
290*4882a593Smuzhiyun 	struct ufs_pa_layer_attr info;
291*4882a593Smuzhiyun };
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun /**
294*4882a593Smuzhiyun  * struct ufs_hba_variant_ops - variant specific callbacks
295*4882a593Smuzhiyun  * @name: variant name
296*4882a593Smuzhiyun  * @init: called when the driver is initialized
297*4882a593Smuzhiyun  * @exit: called to cleanup everything done in init
298*4882a593Smuzhiyun  * @get_ufs_hci_version: called to get UFS HCI version
299*4882a593Smuzhiyun  * @clk_scale_notify: notifies that clks are scaled up/down
300*4882a593Smuzhiyun  * @setup_clocks: called before touching any of the controller registers
301*4882a593Smuzhiyun  * @setup_regulators: called before accessing the host controller
302*4882a593Smuzhiyun  * @hce_enable_notify: called before and after HCE enable bit is set to allow
303*4882a593Smuzhiyun  *                     variant specific Uni-Pro initialization.
304*4882a593Smuzhiyun  * @link_startup_notify: called before and after Link startup is carried out
305*4882a593Smuzhiyun  *                       to allow variant specific Uni-Pro initialization.
306*4882a593Smuzhiyun  * @pwr_change_notify: called before and after a power mode change
307*4882a593Smuzhiyun  *			is carried out to allow vendor spesific capabilities
308*4882a593Smuzhiyun  *			to be set.
309*4882a593Smuzhiyun  * @setup_xfer_req: called before any transfer request is issued
310*4882a593Smuzhiyun  *                  to set some things
311*4882a593Smuzhiyun  * @setup_task_mgmt: called before any task management request is issued
312*4882a593Smuzhiyun  *                  to set some things
313*4882a593Smuzhiyun  * @hibern8_notify: called around hibern8 enter/exit
314*4882a593Smuzhiyun  * @apply_dev_quirks: called to apply device specific quirks
315*4882a593Smuzhiyun  * @suspend: called during host controller PM callback
316*4882a593Smuzhiyun  * @resume: called during host controller PM callback
317*4882a593Smuzhiyun  * @dbg_register_dump: used to dump controller debug information
318*4882a593Smuzhiyun  * @phy_initialization: used to initialize phys
319*4882a593Smuzhiyun  * @device_reset: called to issue a reset pulse on the UFS device
320*4882a593Smuzhiyun  * @program_key: program or evict an inline encryption key
321*4882a593Smuzhiyun  * @event_notify: called to notify important events
322*4882a593Smuzhiyun  */
323*4882a593Smuzhiyun struct ufs_hba_variant_ops {
324*4882a593Smuzhiyun 	const char *name;
325*4882a593Smuzhiyun 	int	(*init)(struct ufs_hba *);
326*4882a593Smuzhiyun 	void    (*exit)(struct ufs_hba *);
327*4882a593Smuzhiyun 	u32	(*get_ufs_hci_version)(struct ufs_hba *);
328*4882a593Smuzhiyun 	int	(*clk_scale_notify)(struct ufs_hba *, bool,
329*4882a593Smuzhiyun 				    enum ufs_notify_change_status);
330*4882a593Smuzhiyun 	int	(*setup_clocks)(struct ufs_hba *, bool,
331*4882a593Smuzhiyun 				enum ufs_notify_change_status);
332*4882a593Smuzhiyun 	int     (*setup_regulators)(struct ufs_hba *, bool);
333*4882a593Smuzhiyun 	int	(*hce_enable_notify)(struct ufs_hba *,
334*4882a593Smuzhiyun 				     enum ufs_notify_change_status);
335*4882a593Smuzhiyun 	int	(*link_startup_notify)(struct ufs_hba *,
336*4882a593Smuzhiyun 				       enum ufs_notify_change_status);
337*4882a593Smuzhiyun 	int	(*pwr_change_notify)(struct ufs_hba *,
338*4882a593Smuzhiyun 					enum ufs_notify_change_status status,
339*4882a593Smuzhiyun 					struct ufs_pa_layer_attr *,
340*4882a593Smuzhiyun 					struct ufs_pa_layer_attr *);
341*4882a593Smuzhiyun 	void	(*setup_xfer_req)(struct ufs_hba *, int, bool);
342*4882a593Smuzhiyun 	void	(*setup_task_mgmt)(struct ufs_hba *, int, u8);
343*4882a593Smuzhiyun 	void    (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme,
344*4882a593Smuzhiyun 					enum ufs_notify_change_status);
345*4882a593Smuzhiyun 	int	(*apply_dev_quirks)(struct ufs_hba *hba);
346*4882a593Smuzhiyun 	void	(*fixup_dev_quirks)(struct ufs_hba *hba);
347*4882a593Smuzhiyun 	int     (*suspend)(struct ufs_hba *, enum ufs_pm_op);
348*4882a593Smuzhiyun 	int     (*resume)(struct ufs_hba *, enum ufs_pm_op);
349*4882a593Smuzhiyun 	void	(*dbg_register_dump)(struct ufs_hba *hba);
350*4882a593Smuzhiyun 	int	(*phy_initialization)(struct ufs_hba *);
351*4882a593Smuzhiyun 	int	(*device_reset)(struct ufs_hba *hba);
352*4882a593Smuzhiyun 	void	(*config_scaling_param)(struct ufs_hba *hba,
353*4882a593Smuzhiyun 					struct devfreq_dev_profile *profile,
354*4882a593Smuzhiyun 					void *data);
355*4882a593Smuzhiyun 	int	(*program_key)(struct ufs_hba *hba,
356*4882a593Smuzhiyun 			       const union ufs_crypto_cfg_entry *cfg, int slot);
357*4882a593Smuzhiyun 	void	(*event_notify)(struct ufs_hba *hba,
358*4882a593Smuzhiyun 				enum ufs_event_type evt, void *data);
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 	ANDROID_KABI_RESERVE(1);
361*4882a593Smuzhiyun 	ANDROID_KABI_RESERVE(2);
362*4882a593Smuzhiyun 	ANDROID_KABI_RESERVE(3);
363*4882a593Smuzhiyun 	ANDROID_KABI_RESERVE(4);
364*4882a593Smuzhiyun };
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun /* clock gating state  */
367*4882a593Smuzhiyun enum clk_gating_state {
368*4882a593Smuzhiyun 	CLKS_OFF,
369*4882a593Smuzhiyun 	CLKS_ON,
370*4882a593Smuzhiyun 	REQ_CLKS_OFF,
371*4882a593Smuzhiyun 	REQ_CLKS_ON,
372*4882a593Smuzhiyun };
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun /**
375*4882a593Smuzhiyun  * struct ufs_clk_gating - UFS clock gating related info
376*4882a593Smuzhiyun  * @gate_work: worker to turn off clocks after some delay as specified in
377*4882a593Smuzhiyun  * delay_ms
378*4882a593Smuzhiyun  * @ungate_work: worker to turn on clocks that will be used in case of
379*4882a593Smuzhiyun  * interrupt context
380*4882a593Smuzhiyun  * @state: the current clocks state
381*4882a593Smuzhiyun  * @delay_ms: gating delay in ms
382*4882a593Smuzhiyun  * @is_suspended: clk gating is suspended when set to 1 which can be used
383*4882a593Smuzhiyun  * during suspend/resume
384*4882a593Smuzhiyun  * @delay_attr: sysfs attribute to control delay_attr
385*4882a593Smuzhiyun  * @enable_attr: sysfs attribute to enable/disable clock gating
386*4882a593Smuzhiyun  * @is_enabled: Indicates the current status of clock gating
387*4882a593Smuzhiyun  * @is_initialized: Indicates whether clock gating is initialized or not
388*4882a593Smuzhiyun  * @active_reqs: number of requests that are pending and should be waited for
389*4882a593Smuzhiyun  * completion before gating clocks.
390*4882a593Smuzhiyun  */
391*4882a593Smuzhiyun struct ufs_clk_gating {
392*4882a593Smuzhiyun 	struct delayed_work gate_work;
393*4882a593Smuzhiyun 	struct work_struct ungate_work;
394*4882a593Smuzhiyun 	enum clk_gating_state state;
395*4882a593Smuzhiyun 	unsigned long delay_ms;
396*4882a593Smuzhiyun 	bool is_suspended;
397*4882a593Smuzhiyun 	struct device_attribute delay_attr;
398*4882a593Smuzhiyun 	struct device_attribute enable_attr;
399*4882a593Smuzhiyun 	bool is_enabled;
400*4882a593Smuzhiyun 	bool is_initialized;
401*4882a593Smuzhiyun 	int active_reqs;
402*4882a593Smuzhiyun 	struct workqueue_struct *clk_gating_workq;
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	ANDROID_KABI_RESERVE(1);
405*4882a593Smuzhiyun };
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun struct ufs_saved_pwr_info {
408*4882a593Smuzhiyun 	struct ufs_pa_layer_attr info;
409*4882a593Smuzhiyun 	bool is_valid;
410*4882a593Smuzhiyun };
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun /**
413*4882a593Smuzhiyun  * struct ufs_clk_scaling - UFS clock scaling related data
414*4882a593Smuzhiyun  * @active_reqs: number of requests that are pending. If this is zero when
415*4882a593Smuzhiyun  * devfreq ->target() function is called then schedule "suspend_work" to
416*4882a593Smuzhiyun  * suspend devfreq.
417*4882a593Smuzhiyun  * @tot_busy_t: Total busy time in current polling window
418*4882a593Smuzhiyun  * @window_start_t: Start time (in jiffies) of the current polling window
419*4882a593Smuzhiyun  * @busy_start_t: Start time of current busy period
420*4882a593Smuzhiyun  * @enable_attr: sysfs attribute to enable/disable clock scaling
421*4882a593Smuzhiyun  * @saved_pwr_info: UFS power mode may also be changed during scaling and this
422*4882a593Smuzhiyun  * one keeps track of previous power mode.
423*4882a593Smuzhiyun  * @workq: workqueue to schedule devfreq suspend/resume work
424*4882a593Smuzhiyun  * @suspend_work: worker to suspend devfreq
425*4882a593Smuzhiyun  * @resume_work: worker to resume devfreq
426*4882a593Smuzhiyun  * @min_gear: lowest HS gear to scale down to
427*4882a593Smuzhiyun  * @is_enabled: tracks if scaling is currently enabled or not, controlled by
428*4882a593Smuzhiyun 		clkscale_enable sysfs node
429*4882a593Smuzhiyun  * @is_allowed: tracks if scaling is currently allowed or not, used to block
430*4882a593Smuzhiyun 		clock scaling which is not invoked from devfreq governor
431*4882a593Smuzhiyun  * @is_initialized: Indicates whether clock scaling is initialized or not
432*4882a593Smuzhiyun  * @is_busy_started: tracks if busy period has started or not
433*4882a593Smuzhiyun  * @is_suspended: tracks if devfreq is suspended or not
434*4882a593Smuzhiyun  */
435*4882a593Smuzhiyun struct ufs_clk_scaling {
436*4882a593Smuzhiyun 	int active_reqs;
437*4882a593Smuzhiyun 	unsigned long tot_busy_t;
438*4882a593Smuzhiyun 	ktime_t window_start_t;
439*4882a593Smuzhiyun 	ktime_t busy_start_t;
440*4882a593Smuzhiyun 	struct device_attribute enable_attr;
441*4882a593Smuzhiyun 	struct ufs_saved_pwr_info saved_pwr_info;
442*4882a593Smuzhiyun 	struct workqueue_struct *workq;
443*4882a593Smuzhiyun 	struct work_struct suspend_work;
444*4882a593Smuzhiyun 	struct work_struct resume_work;
445*4882a593Smuzhiyun 	u32 min_gear;
446*4882a593Smuzhiyun 	bool is_enabled;
447*4882a593Smuzhiyun 	bool is_allowed;
448*4882a593Smuzhiyun 	bool is_initialized;
449*4882a593Smuzhiyun 	bool is_busy_started;
450*4882a593Smuzhiyun 	bool is_suspended;
451*4882a593Smuzhiyun 
452*4882a593Smuzhiyun 	ANDROID_KABI_RESERVE(1);
453*4882a593Smuzhiyun };
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun #define UFS_EVENT_HIST_LENGTH 8
456*4882a593Smuzhiyun /**
457*4882a593Smuzhiyun  * struct ufs_event_hist - keeps history of errors
458*4882a593Smuzhiyun  * @pos: index to indicate cyclic buffer position
459*4882a593Smuzhiyun  * @reg: cyclic buffer for registers value
460*4882a593Smuzhiyun  * @tstamp: cyclic buffer for time stamp
461*4882a593Smuzhiyun  * @cnt: error counter
462*4882a593Smuzhiyun  */
463*4882a593Smuzhiyun struct ufs_event_hist {
464*4882a593Smuzhiyun 	int pos;
465*4882a593Smuzhiyun 	u32 val[UFS_EVENT_HIST_LENGTH];
466*4882a593Smuzhiyun 	ktime_t tstamp[UFS_EVENT_HIST_LENGTH];
467*4882a593Smuzhiyun 	unsigned long long cnt;
468*4882a593Smuzhiyun };
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun /**
471*4882a593Smuzhiyun  * struct ufs_stats - keeps usage/err statistics
472*4882a593Smuzhiyun  * @last_intr_status: record the last interrupt status.
473*4882a593Smuzhiyun  * @last_intr_ts: record the last interrupt timestamp.
474*4882a593Smuzhiyun  * @hibern8_exit_cnt: Counter to keep track of number of exits,
475*4882a593Smuzhiyun  *		reset this after link-startup.
476*4882a593Smuzhiyun  * @last_hibern8_exit_tstamp: Set time after the hibern8 exit.
477*4882a593Smuzhiyun  *		Clear after the first successful command completion.
478*4882a593Smuzhiyun  */
479*4882a593Smuzhiyun struct ufs_stats {
480*4882a593Smuzhiyun 	u32 last_intr_status;
481*4882a593Smuzhiyun 	ktime_t last_intr_ts;
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun 	u32 hibern8_exit_cnt;
484*4882a593Smuzhiyun 	ktime_t last_hibern8_exit_tstamp;
485*4882a593Smuzhiyun 	struct ufs_event_hist event[UFS_EVT_CNT];
486*4882a593Smuzhiyun };
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun enum ufshcd_quirks {
489*4882a593Smuzhiyun 	/* Interrupt aggregation support is broken */
490*4882a593Smuzhiyun 	UFSHCD_QUIRK_BROKEN_INTR_AGGR			= 1 << 0,
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 	/*
493*4882a593Smuzhiyun 	 * delay before each dme command is required as the unipro
494*4882a593Smuzhiyun 	 * layer has shown instabilities
495*4882a593Smuzhiyun 	 */
496*4882a593Smuzhiyun 	UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS		= 1 << 1,
497*4882a593Smuzhiyun 
498*4882a593Smuzhiyun 	/*
499*4882a593Smuzhiyun 	 * If UFS host controller is having issue in processing LCC (Line
500*4882a593Smuzhiyun 	 * Control Command) coming from device then enable this quirk.
501*4882a593Smuzhiyun 	 * When this quirk is enabled, host controller driver should disable
502*4882a593Smuzhiyun 	 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
503*4882a593Smuzhiyun 	 * attribute of device to 0).
504*4882a593Smuzhiyun 	 */
505*4882a593Smuzhiyun 	UFSHCD_QUIRK_BROKEN_LCC				= 1 << 2,
506*4882a593Smuzhiyun 
507*4882a593Smuzhiyun 	/*
508*4882a593Smuzhiyun 	 * The attribute PA_RXHSUNTERMCAP specifies whether or not the
509*4882a593Smuzhiyun 	 * inbound Link supports unterminated line in HS mode. Setting this
510*4882a593Smuzhiyun 	 * attribute to 1 fixes moving to HS gear.
511*4882a593Smuzhiyun 	 */
512*4882a593Smuzhiyun 	UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP		= 1 << 3,
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun 	/*
515*4882a593Smuzhiyun 	 * This quirk needs to be enabled if the host controller only allows
516*4882a593Smuzhiyun 	 * accessing the peer dme attributes in AUTO mode (FAST AUTO or
517*4882a593Smuzhiyun 	 * SLOW AUTO).
518*4882a593Smuzhiyun 	 */
519*4882a593Smuzhiyun 	UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE		= 1 << 4,
520*4882a593Smuzhiyun 
521*4882a593Smuzhiyun 	/*
522*4882a593Smuzhiyun 	 * This quirk needs to be enabled if the host controller doesn't
523*4882a593Smuzhiyun 	 * advertise the correct version in UFS_VER register. If this quirk
524*4882a593Smuzhiyun 	 * is enabled, standard UFS host driver will call the vendor specific
525*4882a593Smuzhiyun 	 * ops (get_ufs_hci_version) to get the correct version.
526*4882a593Smuzhiyun 	 */
527*4882a593Smuzhiyun 	UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION		= 1 << 5,
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun 	/*
530*4882a593Smuzhiyun 	 * Clear handling for transfer/task request list is just opposite.
531*4882a593Smuzhiyun 	 */
532*4882a593Smuzhiyun 	UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR		= 1 << 6,
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun 	/*
535*4882a593Smuzhiyun 	 * This quirk needs to be enabled if host controller doesn't allow
536*4882a593Smuzhiyun 	 * that the interrupt aggregation timer and counter are reset by s/w.
537*4882a593Smuzhiyun 	 */
538*4882a593Smuzhiyun 	UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR		= 1 << 7,
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun 	/*
541*4882a593Smuzhiyun 	 * This quirks needs to be enabled if host controller cannot be
542*4882a593Smuzhiyun 	 * enabled via HCE register.
543*4882a593Smuzhiyun 	 */
544*4882a593Smuzhiyun 	UFSHCI_QUIRK_BROKEN_HCE				= 1 << 8,
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun 	/*
547*4882a593Smuzhiyun 	 * This quirk needs to be enabled if the host controller regards
548*4882a593Smuzhiyun 	 * resolution of the values of PRDTO and PRDTL in UTRD as byte.
549*4882a593Smuzhiyun 	 */
550*4882a593Smuzhiyun 	UFSHCD_QUIRK_PRDT_BYTE_GRAN			= 1 << 9,
551*4882a593Smuzhiyun 
552*4882a593Smuzhiyun 	/*
553*4882a593Smuzhiyun 	 * This quirk needs to be enabled if the host controller reports
554*4882a593Smuzhiyun 	 * OCS FATAL ERROR with device error through sense data
555*4882a593Smuzhiyun 	 */
556*4882a593Smuzhiyun 	UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR		= 1 << 10,
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	/*
559*4882a593Smuzhiyun 	 * This quirk needs to be enabled if the host controller has
560*4882a593Smuzhiyun 	 * auto-hibernate capability but it doesn't work.
561*4882a593Smuzhiyun 	 */
562*4882a593Smuzhiyun 	UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8		= 1 << 11,
563*4882a593Smuzhiyun 
564*4882a593Smuzhiyun 	/*
565*4882a593Smuzhiyun 	 * This quirk needs to disable manual flush for write booster
566*4882a593Smuzhiyun 	 */
567*4882a593Smuzhiyun 	UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL		= 1 << 12,
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun 	/*
570*4882a593Smuzhiyun 	 * This quirk needs to disable unipro timeout values
571*4882a593Smuzhiyun 	 * before power mode change
572*4882a593Smuzhiyun 	 */
573*4882a593Smuzhiyun 	UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13,
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 	/*
576*4882a593Smuzhiyun 	 * This quirk allows only sg entries aligned with page size.
577*4882a593Smuzhiyun 	 */
578*4882a593Smuzhiyun 	UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE		= 1 << 14,
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun 	/*
581*4882a593Smuzhiyun 	 * This quirk needs to be enabled if the host controller does not
582*4882a593Smuzhiyun 	 * support UIC command
583*4882a593Smuzhiyun 	 */
584*4882a593Smuzhiyun 	UFSHCD_QUIRK_BROKEN_UIC_CMD			= 1 << 15,
585*4882a593Smuzhiyun 
586*4882a593Smuzhiyun 	/*
587*4882a593Smuzhiyun 	 * This quirk needs to be enabled if the host controller cannot
588*4882a593Smuzhiyun 	 * support interface configuration.
589*4882a593Smuzhiyun 	 */
590*4882a593Smuzhiyun 	UFSHCD_QUIRK_SKIP_INTERFACE_CONFIGURATION	= 1 << 16,
591*4882a593Smuzhiyun 
592*4882a593Smuzhiyun 	/*
593*4882a593Smuzhiyun 	 * This quirk needs to be enabled if the host controller supports inline
594*4882a593Smuzhiyun 	 * encryption, but it needs to initialize the crypto capabilities in a
595*4882a593Smuzhiyun 	 * nonstandard way and/or it needs to override blk_ksm_ll_ops.  If
596*4882a593Smuzhiyun 	 * enabled, the standard code won't initialize the blk_keyslot_manager;
597*4882a593Smuzhiyun 	 * ufs_hba_variant_ops::init() must do it instead.
598*4882a593Smuzhiyun 	 */
599*4882a593Smuzhiyun 	UFSHCD_QUIRK_CUSTOM_KEYSLOT_MANAGER		= 1 << 20,
600*4882a593Smuzhiyun 
601*4882a593Smuzhiyun 	/*
602*4882a593Smuzhiyun 	 * This quirk needs to be enabled if the host controller supports inline
603*4882a593Smuzhiyun 	 * encryption, but the CRYPTO_GENERAL_ENABLE bit is not implemented and
604*4882a593Smuzhiyun 	 * breaks the HCE sequence if used.
605*4882a593Smuzhiyun 	 */
606*4882a593Smuzhiyun 	UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE		= 1 << 21,
607*4882a593Smuzhiyun 
608*4882a593Smuzhiyun 	/*
609*4882a593Smuzhiyun 	 * This quirk needs to be enabled if the host controller requires that
610*4882a593Smuzhiyun 	 * the PRDT be cleared after each encrypted request because encryption
611*4882a593Smuzhiyun 	 * keys were stored in it.
612*4882a593Smuzhiyun 	 */
613*4882a593Smuzhiyun 	UFSHCD_QUIRK_KEYS_IN_PRDT			= 1 << 22,
614*4882a593Smuzhiyun };
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun enum ufshcd_caps {
617*4882a593Smuzhiyun 	/* Allow dynamic clk gating */
618*4882a593Smuzhiyun 	UFSHCD_CAP_CLK_GATING				= 1 << 0,
619*4882a593Smuzhiyun 
620*4882a593Smuzhiyun 	/* Allow hiberb8 with clk gating */
621*4882a593Smuzhiyun 	UFSHCD_CAP_HIBERN8_WITH_CLK_GATING		= 1 << 1,
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun 	/* Allow dynamic clk scaling */
624*4882a593Smuzhiyun 	UFSHCD_CAP_CLK_SCALING				= 1 << 2,
625*4882a593Smuzhiyun 
626*4882a593Smuzhiyun 	/* Allow auto bkops to enabled during runtime suspend */
627*4882a593Smuzhiyun 	UFSHCD_CAP_AUTO_BKOPS_SUSPEND			= 1 << 3,
628*4882a593Smuzhiyun 
629*4882a593Smuzhiyun 	/*
630*4882a593Smuzhiyun 	 * This capability allows host controller driver to use the UFS HCI's
631*4882a593Smuzhiyun 	 * interrupt aggregation capability.
632*4882a593Smuzhiyun 	 * CAUTION: Enabling this might reduce overall UFS throughput.
633*4882a593Smuzhiyun 	 */
634*4882a593Smuzhiyun 	UFSHCD_CAP_INTR_AGGR				= 1 << 4,
635*4882a593Smuzhiyun 
636*4882a593Smuzhiyun 	/*
637*4882a593Smuzhiyun 	 * This capability allows the device auto-bkops to be always enabled
638*4882a593Smuzhiyun 	 * except during suspend (both runtime and suspend).
639*4882a593Smuzhiyun 	 * Enabling this capability means that device will always be allowed
640*4882a593Smuzhiyun 	 * to do background operation when it's active but it might degrade
641*4882a593Smuzhiyun 	 * the performance of ongoing read/write operations.
642*4882a593Smuzhiyun 	 */
643*4882a593Smuzhiyun 	UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5,
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun 	/*
646*4882a593Smuzhiyun 	 * This capability allows host controller driver to automatically
647*4882a593Smuzhiyun 	 * enable runtime power management by itself instead of waiting
648*4882a593Smuzhiyun 	 * for userspace to control the power management.
649*4882a593Smuzhiyun 	 */
650*4882a593Smuzhiyun 	UFSHCD_CAP_RPM_AUTOSUSPEND			= 1 << 6,
651*4882a593Smuzhiyun 
652*4882a593Smuzhiyun 	/*
653*4882a593Smuzhiyun 	 * This capability allows the host controller driver to turn-on
654*4882a593Smuzhiyun 	 * WriteBooster, if the underlying device supports it and is
655*4882a593Smuzhiyun 	 * provisioned to be used. This would increase the write performance.
656*4882a593Smuzhiyun 	 */
657*4882a593Smuzhiyun 	UFSHCD_CAP_WB_EN				= 1 << 7,
658*4882a593Smuzhiyun 
659*4882a593Smuzhiyun 	/*
660*4882a593Smuzhiyun 	 * This capability allows the host controller driver to use the
661*4882a593Smuzhiyun 	 * inline crypto engine, if it is present
662*4882a593Smuzhiyun 	 */
663*4882a593Smuzhiyun 	UFSHCD_CAP_CRYPTO				= 1 << 8,
664*4882a593Smuzhiyun 
665*4882a593Smuzhiyun 	/*
666*4882a593Smuzhiyun 	 * This capability allows the controller regulators to be put into
667*4882a593Smuzhiyun 	 * lpm mode aggressively during clock gating.
668*4882a593Smuzhiyun 	 * This would increase power savings.
669*4882a593Smuzhiyun 	 */
670*4882a593Smuzhiyun 	UFSHCD_CAP_AGGR_POWER_COLLAPSE			= 1 << 9,
671*4882a593Smuzhiyun };
672*4882a593Smuzhiyun 
673*4882a593Smuzhiyun struct ufs_hba_variant_params {
674*4882a593Smuzhiyun 	struct devfreq_dev_profile devfreq_profile;
675*4882a593Smuzhiyun 	struct devfreq_simple_ondemand_data ondemand_data;
676*4882a593Smuzhiyun 	u16 hba_enable_delay_us;
677*4882a593Smuzhiyun 	u32 wb_flush_threshold;
678*4882a593Smuzhiyun };
679*4882a593Smuzhiyun 
680*4882a593Smuzhiyun #ifdef CONFIG_SCSI_UFS_HPB
681*4882a593Smuzhiyun /**
682*4882a593Smuzhiyun  * struct ufshpb_dev_info - UFSHPB device related info
683*4882a593Smuzhiyun  * @num_lu: the number of user logical unit to check whether all lu finished
684*4882a593Smuzhiyun  *          initialization
685*4882a593Smuzhiyun  * @rgn_size: device reported HPB region size
686*4882a593Smuzhiyun  * @srgn_size: device reported HPB sub-region size
687*4882a593Smuzhiyun  * @slave_conf_cnt: counter to check all lu finished initialization
688*4882a593Smuzhiyun  * @hpb_disabled: flag to check if HPB is disabled
689*4882a593Smuzhiyun  * @max_hpb_single_cmd: device reported bMAX_DATA_SIZE_FOR_SINGLE_CMD value
690*4882a593Smuzhiyun  * @is_legacy: flag to check HPB 1.0
691*4882a593Smuzhiyun  * @control_mode: either host or device
692*4882a593Smuzhiyun  */
693*4882a593Smuzhiyun struct ufshpb_dev_info {
694*4882a593Smuzhiyun 	int num_lu;
695*4882a593Smuzhiyun 	int rgn_size;
696*4882a593Smuzhiyun 	int srgn_size;
697*4882a593Smuzhiyun 	atomic_t slave_conf_cnt;
698*4882a593Smuzhiyun 	bool hpb_disabled;
699*4882a593Smuzhiyun 	u8 max_hpb_single_cmd;
700*4882a593Smuzhiyun 	bool is_legacy;
701*4882a593Smuzhiyun 	u8 control_mode;
702*4882a593Smuzhiyun };
703*4882a593Smuzhiyun #endif
704*4882a593Smuzhiyun 
705*4882a593Smuzhiyun struct ufs_hba_monitor {
706*4882a593Smuzhiyun 	unsigned long chunk_size;
707*4882a593Smuzhiyun 
708*4882a593Smuzhiyun 	unsigned long nr_sec_rw[2];
709*4882a593Smuzhiyun 	ktime_t total_busy[2];
710*4882a593Smuzhiyun 
711*4882a593Smuzhiyun 	unsigned long nr_req[2];
712*4882a593Smuzhiyun 	/* latencies*/
713*4882a593Smuzhiyun 	ktime_t lat_sum[2];
714*4882a593Smuzhiyun 	ktime_t lat_max[2];
715*4882a593Smuzhiyun 	ktime_t lat_min[2];
716*4882a593Smuzhiyun 
717*4882a593Smuzhiyun 	u32 nr_queued[2];
718*4882a593Smuzhiyun 	ktime_t busy_start_ts[2];
719*4882a593Smuzhiyun 
720*4882a593Smuzhiyun 	ktime_t enabled_ts;
721*4882a593Smuzhiyun 	bool enabled;
722*4882a593Smuzhiyun };
723*4882a593Smuzhiyun 
724*4882a593Smuzhiyun /**
725*4882a593Smuzhiyun  * struct ufs_hba - per adapter private structure
726*4882a593Smuzhiyun  * @mmio_base: UFSHCI base register address
727*4882a593Smuzhiyun  * @ucdl_base_addr: UFS Command Descriptor base address
728*4882a593Smuzhiyun  * @utrdl_base_addr: UTP Transfer Request Descriptor base address
729*4882a593Smuzhiyun  * @utmrdl_base_addr: UTP Task Management Descriptor base address
730*4882a593Smuzhiyun  * @ucdl_dma_addr: UFS Command Descriptor DMA address
731*4882a593Smuzhiyun  * @utrdl_dma_addr: UTRDL DMA address
732*4882a593Smuzhiyun  * @utmrdl_dma_addr: UTMRDL DMA address
733*4882a593Smuzhiyun  * @host: Scsi_Host instance of the driver
734*4882a593Smuzhiyun  * @dev: device handle
735*4882a593Smuzhiyun  * @lrb: local reference block
736*4882a593Smuzhiyun  * @cmd_queue: Used to allocate command tags from hba->host->tag_set.
737*4882a593Smuzhiyun  * @outstanding_tasks: Bits representing outstanding task requests
738*4882a593Smuzhiyun  * @outstanding_reqs: Bits representing outstanding transfer requests
739*4882a593Smuzhiyun  * @capabilities: UFS Controller Capabilities
740*4882a593Smuzhiyun  * @nutrs: Transfer Request Queue depth supported by controller
741*4882a593Smuzhiyun  * @nutmrs: Task Management Queue depth supported by controller
742*4882a593Smuzhiyun  * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock.
743*4882a593Smuzhiyun  * @ufs_version: UFS Version to which controller complies
744*4882a593Smuzhiyun  * @vops: pointer to variant specific operations
745*4882a593Smuzhiyun  * @priv: pointer to variant specific private data
746*4882a593Smuzhiyun  * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields)
747*4882a593Smuzhiyun  * @irq: Irq number of the controller
748*4882a593Smuzhiyun  * @active_uic_cmd: handle of active UIC command
749*4882a593Smuzhiyun  * @uic_cmd_mutex: mutex for uic command
750*4882a593Smuzhiyun  * @tmf_tag_set: TMF tag set.
751*4882a593Smuzhiyun  * @tmf_queue: Used to allocate TMF tags.
752*4882a593Smuzhiyun  * @pwr_done: completion for power mode change
753*4882a593Smuzhiyun  * @ufshcd_state: UFSHCD states
754*4882a593Smuzhiyun  * @eh_flags: Error handling flags
755*4882a593Smuzhiyun  * @intr_mask: Interrupt Mask Bits
756*4882a593Smuzhiyun  * @ee_ctrl_mask: Exception event control mask
757*4882a593Smuzhiyun  * @is_powered: flag to check if HBA is powered
758*4882a593Smuzhiyun  * @shutting_down: flag to check if shutdown has been invoked
759*4882a593Smuzhiyun  * @host_sem: semaphore used to serialize concurrent contexts
760*4882a593Smuzhiyun  * @eh_wq: Workqueue that eh_work works on
761*4882a593Smuzhiyun  * @eh_work: Worker to handle UFS errors that require s/w attention
762*4882a593Smuzhiyun  * @eeh_work: Worker to handle exception events
763*4882a593Smuzhiyun  * @errors: HBA errors
764*4882a593Smuzhiyun  * @uic_error: UFS interconnect layer error status
765*4882a593Smuzhiyun  * @saved_err: sticky error mask
766*4882a593Smuzhiyun  * @saved_uic_err: sticky UIC error mask
767*4882a593Smuzhiyun  * @force_reset: flag to force eh_work perform a full reset
768*4882a593Smuzhiyun  * @force_pmc: flag to force a power mode change
769*4882a593Smuzhiyun  * @silence_err_logs: flag to silence error logs
770*4882a593Smuzhiyun  * @dev_cmd: ufs device management command information
771*4882a593Smuzhiyun  * @last_dme_cmd_tstamp: time stamp of the last completed DME command
772*4882a593Smuzhiyun  * @auto_bkops_enabled: to track whether bkops is enabled in device
773*4882a593Smuzhiyun  * @vreg_info: UFS device voltage regulator information
774*4882a593Smuzhiyun  * @clk_list_head: UFS host controller clocks list node head
775*4882a593Smuzhiyun  * @pwr_info: holds current power mode
776*4882a593Smuzhiyun  * @max_pwr_info: keeps the device max valid pwm
777*4882a593Smuzhiyun  * @desc_size: descriptor sizes reported by device
778*4882a593Smuzhiyun  * @urgent_bkops_lvl: keeps track of urgent bkops level for device
779*4882a593Smuzhiyun  * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for
780*4882a593Smuzhiyun  *  device is known or not.
781*4882a593Smuzhiyun  * @scsi_block_reqs_cnt: reference counting for scsi block requests
782*4882a593Smuzhiyun  * @crypto_capabilities: Content of crypto capabilities register (0x100)
783*4882a593Smuzhiyun  * @crypto_cap_array: Array of crypto capabilities
784*4882a593Smuzhiyun  * @crypto_cfg_register: Start of the crypto cfg array
785*4882a593Smuzhiyun  * @ksm: the keyslot manager tied to this hba
786*4882a593Smuzhiyun  */
787*4882a593Smuzhiyun struct ufs_hba {
788*4882a593Smuzhiyun 	void __iomem *mmio_base;
789*4882a593Smuzhiyun 
790*4882a593Smuzhiyun 	/* Virtual memory reference */
791*4882a593Smuzhiyun 	struct utp_transfer_cmd_desc *ucdl_base_addr;
792*4882a593Smuzhiyun 	struct utp_transfer_req_desc *utrdl_base_addr;
793*4882a593Smuzhiyun 	struct utp_task_req_desc *utmrdl_base_addr;
794*4882a593Smuzhiyun 
795*4882a593Smuzhiyun 	/* DMA memory reference */
796*4882a593Smuzhiyun 	dma_addr_t ucdl_dma_addr;
797*4882a593Smuzhiyun 	dma_addr_t utrdl_dma_addr;
798*4882a593Smuzhiyun 	dma_addr_t utmrdl_dma_addr;
799*4882a593Smuzhiyun 
800*4882a593Smuzhiyun 	struct Scsi_Host *host;
801*4882a593Smuzhiyun 	struct device *dev;
802*4882a593Smuzhiyun 	struct request_queue *cmd_queue;
803*4882a593Smuzhiyun 	/*
804*4882a593Smuzhiyun 	 * This field is to keep a reference to "scsi_device" corresponding to
805*4882a593Smuzhiyun 	 * "UFS device" W-LU.
806*4882a593Smuzhiyun 	 */
807*4882a593Smuzhiyun 	struct scsi_device *sdev_ufs_device;
808*4882a593Smuzhiyun 	struct scsi_device *sdev_rpmb;
809*4882a593Smuzhiyun 
810*4882a593Smuzhiyun 	enum ufs_dev_pwr_mode curr_dev_pwr_mode;
811*4882a593Smuzhiyun 	enum uic_link_state uic_link_state;
812*4882a593Smuzhiyun 	/* Desired UFS power management level during runtime PM */
813*4882a593Smuzhiyun 	enum ufs_pm_level rpm_lvl;
814*4882a593Smuzhiyun 	/* Desired UFS power management level during system PM */
815*4882a593Smuzhiyun 	enum ufs_pm_level spm_lvl;
816*4882a593Smuzhiyun 	struct device_attribute rpm_lvl_attr;
817*4882a593Smuzhiyun 	struct device_attribute spm_lvl_attr;
818*4882a593Smuzhiyun 	int pm_op_in_progress;
819*4882a593Smuzhiyun 
820*4882a593Smuzhiyun 	/* Auto-Hibernate Idle Timer register value */
821*4882a593Smuzhiyun 	u32 ahit;
822*4882a593Smuzhiyun 
823*4882a593Smuzhiyun 	struct ufshcd_lrb *lrb;
824*4882a593Smuzhiyun 
825*4882a593Smuzhiyun 	unsigned long outstanding_tasks;
826*4882a593Smuzhiyun 	unsigned long outstanding_reqs;
827*4882a593Smuzhiyun 
828*4882a593Smuzhiyun 	u32 capabilities;
829*4882a593Smuzhiyun 	int nutrs;
830*4882a593Smuzhiyun 	int nutmrs;
831*4882a593Smuzhiyun #if 0
832*4882a593Smuzhiyun 	/*
833*4882a593Smuzhiyun 	 * This has been moved into struct ufs_hba_add_info because of the GKI.
834*4882a593Smuzhiyun 	 */
835*4882a593Smuzhiyun 	u32 reserved_slot;
836*4882a593Smuzhiyun #endif
837*4882a593Smuzhiyun 	u32 ufs_version;
838*4882a593Smuzhiyun 	const struct ufs_hba_variant_ops *vops;
839*4882a593Smuzhiyun 	struct ufs_hba_variant_params *vps;
840*4882a593Smuzhiyun 	void *priv;
841*4882a593Smuzhiyun 	size_t sg_entry_size;
842*4882a593Smuzhiyun 	unsigned int irq;
843*4882a593Smuzhiyun 	bool is_irq_enabled;
844*4882a593Smuzhiyun 	enum ufs_ref_clk_freq dev_ref_clk_freq;
845*4882a593Smuzhiyun 
846*4882a593Smuzhiyun 	unsigned int quirks;	/* Deviations from standard UFSHCI spec. */
847*4882a593Smuzhiyun 
848*4882a593Smuzhiyun 	/* Device deviations from standard UFS device spec. */
849*4882a593Smuzhiyun 	unsigned int dev_quirks;
850*4882a593Smuzhiyun 
851*4882a593Smuzhiyun 	struct blk_mq_tag_set tmf_tag_set;
852*4882a593Smuzhiyun 	struct request_queue *tmf_queue;
853*4882a593Smuzhiyun #if 0
854*4882a593Smuzhiyun 	/*
855*4882a593Smuzhiyun 	 * This has been moved into struct ufs_hba_add_info because of the GKI.
856*4882a593Smuzhiyun 	 */
857*4882a593Smuzhiyun 	struct request **tmf_rqs;
858*4882a593Smuzhiyun #endif
859*4882a593Smuzhiyun 
860*4882a593Smuzhiyun 	struct uic_command *active_uic_cmd;
861*4882a593Smuzhiyun 	struct mutex uic_cmd_mutex;
862*4882a593Smuzhiyun 	struct completion *uic_async_done;
863*4882a593Smuzhiyun 
864*4882a593Smuzhiyun 	u32 ufshcd_state;
865*4882a593Smuzhiyun 	u32 eh_flags;
866*4882a593Smuzhiyun 	u32 intr_mask;
867*4882a593Smuzhiyun 	u16 ee_ctrl_mask;
868*4882a593Smuzhiyun 	bool is_powered;
869*4882a593Smuzhiyun 	bool shutting_down;
870*4882a593Smuzhiyun 	struct semaphore host_sem;
871*4882a593Smuzhiyun 
872*4882a593Smuzhiyun 	/* Work Queues */
873*4882a593Smuzhiyun 	struct workqueue_struct *eh_wq;
874*4882a593Smuzhiyun 	struct work_struct eh_work;
875*4882a593Smuzhiyun 	struct work_struct eeh_work;
876*4882a593Smuzhiyun 
877*4882a593Smuzhiyun 	/* HBA Errors */
878*4882a593Smuzhiyun 	u32 errors;
879*4882a593Smuzhiyun 	u32 uic_error;
880*4882a593Smuzhiyun 	u32 saved_err;
881*4882a593Smuzhiyun 	u32 saved_uic_err;
882*4882a593Smuzhiyun 	struct ufs_stats ufs_stats;
883*4882a593Smuzhiyun 	bool force_reset;
884*4882a593Smuzhiyun 	bool force_pmc;
885*4882a593Smuzhiyun 	bool silence_err_logs;
886*4882a593Smuzhiyun 
887*4882a593Smuzhiyun 	/* Device management request data */
888*4882a593Smuzhiyun 	struct ufs_dev_cmd dev_cmd;
889*4882a593Smuzhiyun 	ktime_t last_dme_cmd_tstamp;
890*4882a593Smuzhiyun 
891*4882a593Smuzhiyun 	/* Keeps information of the UFS device connected to this host */
892*4882a593Smuzhiyun 	struct ufs_dev_info dev_info;
893*4882a593Smuzhiyun 	bool auto_bkops_enabled;
894*4882a593Smuzhiyun 	struct ufs_vreg_info vreg_info;
895*4882a593Smuzhiyun 	struct list_head clk_list_head;
896*4882a593Smuzhiyun 
897*4882a593Smuzhiyun 	bool wlun_dev_clr_ua;
898*4882a593Smuzhiyun 
899*4882a593Smuzhiyun 	/* Number of requests aborts */
900*4882a593Smuzhiyun 	int req_abort_count;
901*4882a593Smuzhiyun 
902*4882a593Smuzhiyun 	/* Number of lanes available (1 or 2) for Rx/Tx */
903*4882a593Smuzhiyun 	u32 lanes_per_direction;
904*4882a593Smuzhiyun 	struct ufs_pa_layer_attr pwr_info;
905*4882a593Smuzhiyun 	struct ufs_pwr_mode_info max_pwr_info;
906*4882a593Smuzhiyun 
907*4882a593Smuzhiyun 	struct ufs_clk_gating clk_gating;
908*4882a593Smuzhiyun 	/* Control to enable/disable host capabilities */
909*4882a593Smuzhiyun 	u32 caps;
910*4882a593Smuzhiyun 
911*4882a593Smuzhiyun 	struct devfreq *devfreq;
912*4882a593Smuzhiyun 	struct ufs_clk_scaling clk_scaling;
913*4882a593Smuzhiyun 	bool is_sys_suspended;
914*4882a593Smuzhiyun 
915*4882a593Smuzhiyun 	enum bkops_status urgent_bkops_lvl;
916*4882a593Smuzhiyun 	bool is_urgent_bkops_lvl_checked;
917*4882a593Smuzhiyun 
918*4882a593Smuzhiyun 	struct rw_semaphore clk_scaling_lock;
919*4882a593Smuzhiyun 	unsigned char desc_size[QUERY_DESC_IDN_MAX];
920*4882a593Smuzhiyun 	atomic_t scsi_block_reqs_cnt;
921*4882a593Smuzhiyun 
922*4882a593Smuzhiyun 	struct device		bsg_dev;
923*4882a593Smuzhiyun 	struct request_queue	*bsg_queue;
924*4882a593Smuzhiyun 	bool wb_buf_flush_enabled;
925*4882a593Smuzhiyun 	bool wb_enabled;
926*4882a593Smuzhiyun 	struct delayed_work rpm_dev_flush_recheck_work;
927*4882a593Smuzhiyun 
928*4882a593Smuzhiyun #if 0
929*4882a593Smuzhiyun 	/* This has been moved into struct ufs_hba_add_info. */
930*4882a593Smuzhiyun 	struct ufshpb_dev_info ufshpb_dev;
931*4882a593Smuzhiyun #endif
932*4882a593Smuzhiyun 
933*4882a593Smuzhiyun 	struct ufs_hba_monitor	monitor;
934*4882a593Smuzhiyun 
935*4882a593Smuzhiyun #ifdef CONFIG_SCSI_UFS_CRYPTO
936*4882a593Smuzhiyun 	union ufs_crypto_capabilities crypto_capabilities;
937*4882a593Smuzhiyun 	union ufs_crypto_cap_entry *crypto_cap_array;
938*4882a593Smuzhiyun 	u32 crypto_cfg_register;
939*4882a593Smuzhiyun 	struct blk_keyslot_manager ksm;
940*4882a593Smuzhiyun #endif
941*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_FS
942*4882a593Smuzhiyun 	struct dentry *debugfs_root;
943*4882a593Smuzhiyun #endif
944*4882a593Smuzhiyun 
945*4882a593Smuzhiyun 	ANDROID_KABI_RESERVE(1);
946*4882a593Smuzhiyun 	ANDROID_KABI_RESERVE(2);
947*4882a593Smuzhiyun 	ANDROID_KABI_RESERVE(3);
948*4882a593Smuzhiyun 	ANDROID_KABI_RESERVE(4);
949*4882a593Smuzhiyun };
950*4882a593Smuzhiyun 
951*4882a593Smuzhiyun /* Returns true if clocks can be gated. Otherwise false */
ufshcd_is_clkgating_allowed(struct ufs_hba * hba)952*4882a593Smuzhiyun static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba)
953*4882a593Smuzhiyun {
954*4882a593Smuzhiyun 	return hba->caps & UFSHCD_CAP_CLK_GATING;
955*4882a593Smuzhiyun }
ufshcd_can_hibern8_during_gating(struct ufs_hba * hba)956*4882a593Smuzhiyun static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba)
957*4882a593Smuzhiyun {
958*4882a593Smuzhiyun 	return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
959*4882a593Smuzhiyun }
ufshcd_is_clkscaling_supported(struct ufs_hba * hba)960*4882a593Smuzhiyun static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba)
961*4882a593Smuzhiyun {
962*4882a593Smuzhiyun 	return hba->caps & UFSHCD_CAP_CLK_SCALING;
963*4882a593Smuzhiyun }
ufshcd_can_autobkops_during_suspend(struct ufs_hba * hba)964*4882a593Smuzhiyun static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba)
965*4882a593Smuzhiyun {
966*4882a593Smuzhiyun 	return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
967*4882a593Smuzhiyun }
ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba * hba)968*4882a593Smuzhiyun static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba)
969*4882a593Smuzhiyun {
970*4882a593Smuzhiyun 	return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND;
971*4882a593Smuzhiyun }
972*4882a593Smuzhiyun 
ufshcd_is_intr_aggr_allowed(struct ufs_hba * hba)973*4882a593Smuzhiyun static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba)
974*4882a593Smuzhiyun {
975*4882a593Smuzhiyun /* DWC UFS Core has the Interrupt aggregation feature but is not detectable*/
976*4882a593Smuzhiyun #ifndef CONFIG_SCSI_UFS_DWC
977*4882a593Smuzhiyun 	if ((hba->caps & UFSHCD_CAP_INTR_AGGR) &&
978*4882a593Smuzhiyun 	    !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR))
979*4882a593Smuzhiyun 		return true;
980*4882a593Smuzhiyun 	else
981*4882a593Smuzhiyun 		return false;
982*4882a593Smuzhiyun #else
983*4882a593Smuzhiyun return true;
984*4882a593Smuzhiyun #endif
985*4882a593Smuzhiyun }
986*4882a593Smuzhiyun 
ufshcd_can_aggressive_pc(struct ufs_hba * hba)987*4882a593Smuzhiyun static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba)
988*4882a593Smuzhiyun {
989*4882a593Smuzhiyun 	return !!(ufshcd_is_link_hibern8(hba) &&
990*4882a593Smuzhiyun 		  (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE));
991*4882a593Smuzhiyun }
992*4882a593Smuzhiyun 
ufshcd_is_auto_hibern8_supported(struct ufs_hba * hba)993*4882a593Smuzhiyun static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba)
994*4882a593Smuzhiyun {
995*4882a593Smuzhiyun 	return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) &&
996*4882a593Smuzhiyun 		!(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8);
997*4882a593Smuzhiyun }
998*4882a593Smuzhiyun 
ufshcd_is_auto_hibern8_enabled(struct ufs_hba * hba)999*4882a593Smuzhiyun static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba)
1000*4882a593Smuzhiyun {
1001*4882a593Smuzhiyun 	return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit) ? true : false;
1002*4882a593Smuzhiyun }
1003*4882a593Smuzhiyun 
ufshcd_is_wb_allowed(struct ufs_hba * hba)1004*4882a593Smuzhiyun static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba)
1005*4882a593Smuzhiyun {
1006*4882a593Smuzhiyun 	return hba->caps & UFSHCD_CAP_WB_EN;
1007*4882a593Smuzhiyun }
1008*4882a593Smuzhiyun 
ufshcd_is_user_access_allowed(struct ufs_hba * hba)1009*4882a593Smuzhiyun static inline bool ufshcd_is_user_access_allowed(struct ufs_hba *hba)
1010*4882a593Smuzhiyun {
1011*4882a593Smuzhiyun 	return !hba->shutting_down;
1012*4882a593Smuzhiyun }
1013*4882a593Smuzhiyun 
1014*4882a593Smuzhiyun #define ufshcd_writel(hba, val, reg)	\
1015*4882a593Smuzhiyun 	writel((val), (hba)->mmio_base + (reg))
1016*4882a593Smuzhiyun #define ufshcd_readl(hba, reg)	\
1017*4882a593Smuzhiyun 	readl((hba)->mmio_base + (reg))
1018*4882a593Smuzhiyun 
1019*4882a593Smuzhiyun /**
1020*4882a593Smuzhiyun  * ufshcd_rmwl - read modify write into a register
1021*4882a593Smuzhiyun  * @hba - per adapter instance
1022*4882a593Smuzhiyun  * @mask - mask to apply on read value
1023*4882a593Smuzhiyun  * @val - actual value to write
1024*4882a593Smuzhiyun  * @reg - register address
1025*4882a593Smuzhiyun  */
ufshcd_rmwl(struct ufs_hba * hba,u32 mask,u32 val,u32 reg)1026*4882a593Smuzhiyun static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)
1027*4882a593Smuzhiyun {
1028*4882a593Smuzhiyun 	u32 tmp;
1029*4882a593Smuzhiyun 
1030*4882a593Smuzhiyun 	tmp = ufshcd_readl(hba, reg);
1031*4882a593Smuzhiyun 	tmp &= ~mask;
1032*4882a593Smuzhiyun 	tmp |= (val & mask);
1033*4882a593Smuzhiyun 	ufshcd_writel(hba, tmp, reg);
1034*4882a593Smuzhiyun }
1035*4882a593Smuzhiyun 
1036*4882a593Smuzhiyun int ufshcd_alloc_host(struct device *, struct ufs_hba **);
1037*4882a593Smuzhiyun void ufshcd_dealloc_host(struct ufs_hba *);
1038*4882a593Smuzhiyun int ufshcd_hba_enable(struct ufs_hba *hba);
1039*4882a593Smuzhiyun int ufshcd_init(struct ufs_hba * , void __iomem * , unsigned int);
1040*4882a593Smuzhiyun int ufshcd_link_recovery(struct ufs_hba *hba);
1041*4882a593Smuzhiyun int ufshcd_make_hba_operational(struct ufs_hba *hba);
1042*4882a593Smuzhiyun void ufshcd_remove(struct ufs_hba *);
1043*4882a593Smuzhiyun int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
1044*4882a593Smuzhiyun void ufshcd_delay_us(unsigned long us, unsigned long tolerance);
1045*4882a593Smuzhiyun int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
1046*4882a593Smuzhiyun 				u32 val, unsigned long interval_us,
1047*4882a593Smuzhiyun 				unsigned long timeout_ms);
1048*4882a593Smuzhiyun void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk);
1049*4882a593Smuzhiyun void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val);
1050*4882a593Smuzhiyun void ufshcd_hba_stop(struct ufs_hba *hba);
1051*4882a593Smuzhiyun 
check_upiu_size(void)1052*4882a593Smuzhiyun static inline void check_upiu_size(void)
1053*4882a593Smuzhiyun {
1054*4882a593Smuzhiyun 	BUILD_BUG_ON(ALIGNED_UPIU_SIZE <
1055*4882a593Smuzhiyun 		GENERAL_UPIU_REQUEST_SIZE + QUERY_DESC_MAX_SIZE);
1056*4882a593Smuzhiyun }
1057*4882a593Smuzhiyun 
1058*4882a593Smuzhiyun /**
1059*4882a593Smuzhiyun  * ufshcd_set_variant - set variant specific data to the hba
1060*4882a593Smuzhiyun  * @hba - per adapter instance
1061*4882a593Smuzhiyun  * @variant - pointer to variant specific data
1062*4882a593Smuzhiyun  */
ufshcd_set_variant(struct ufs_hba * hba,void * variant)1063*4882a593Smuzhiyun static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant)
1064*4882a593Smuzhiyun {
1065*4882a593Smuzhiyun 	BUG_ON(!hba);
1066*4882a593Smuzhiyun 	hba->priv = variant;
1067*4882a593Smuzhiyun }
1068*4882a593Smuzhiyun 
1069*4882a593Smuzhiyun /**
1070*4882a593Smuzhiyun  * ufshcd_get_variant - get variant specific data from the hba
1071*4882a593Smuzhiyun  * @hba - per adapter instance
1072*4882a593Smuzhiyun  */
ufshcd_get_variant(struct ufs_hba * hba)1073*4882a593Smuzhiyun static inline void *ufshcd_get_variant(struct ufs_hba *hba)
1074*4882a593Smuzhiyun {
1075*4882a593Smuzhiyun 	BUG_ON(!hba);
1076*4882a593Smuzhiyun 	return hba->priv;
1077*4882a593Smuzhiyun }
ufshcd_keep_autobkops_enabled_except_suspend(struct ufs_hba * hba)1078*4882a593Smuzhiyun static inline bool ufshcd_keep_autobkops_enabled_except_suspend(
1079*4882a593Smuzhiyun 							struct ufs_hba *hba)
1080*4882a593Smuzhiyun {
1081*4882a593Smuzhiyun 	return hba->caps & UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND;
1082*4882a593Smuzhiyun }
1083*4882a593Smuzhiyun 
ufshcd_wb_get_query_index(struct ufs_hba * hba)1084*4882a593Smuzhiyun static inline u8 ufshcd_wb_get_query_index(struct ufs_hba *hba)
1085*4882a593Smuzhiyun {
1086*4882a593Smuzhiyun 	if (hba->dev_info.b_wb_buffer_type == WB_BUF_MODE_LU_DEDICATED)
1087*4882a593Smuzhiyun 		return hba->dev_info.wb_dedicated_lu;
1088*4882a593Smuzhiyun 	return 0;
1089*4882a593Smuzhiyun }
1090*4882a593Smuzhiyun 
1091*4882a593Smuzhiyun extern int ufshcd_runtime_suspend(struct ufs_hba *hba);
1092*4882a593Smuzhiyun extern int ufshcd_runtime_resume(struct ufs_hba *hba);
1093*4882a593Smuzhiyun extern int ufshcd_runtime_idle(struct ufs_hba *hba);
1094*4882a593Smuzhiyun extern int ufshcd_system_suspend(struct ufs_hba *hba);
1095*4882a593Smuzhiyun extern int ufshcd_system_resume(struct ufs_hba *hba);
1096*4882a593Smuzhiyun extern int ufshcd_shutdown(struct ufs_hba *hba);
1097*4882a593Smuzhiyun extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
1098*4882a593Smuzhiyun 			       u8 attr_set, u32 mib_val, u8 peer);
1099*4882a593Smuzhiyun extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
1100*4882a593Smuzhiyun 			       u32 *mib_val, u8 peer);
1101*4882a593Smuzhiyun extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
1102*4882a593Smuzhiyun 			struct ufs_pa_layer_attr *desired_pwr_mode);
1103*4882a593Smuzhiyun 
1104*4882a593Smuzhiyun /* UIC command interfaces for DME primitives */
1105*4882a593Smuzhiyun #define DME_LOCAL	0
1106*4882a593Smuzhiyun #define DME_PEER	1
1107*4882a593Smuzhiyun #define ATTR_SET_NOR	0	/* NORMAL */
1108*4882a593Smuzhiyun #define ATTR_SET_ST	1	/* STATIC */
1109*4882a593Smuzhiyun 
ufshcd_dme_set(struct ufs_hba * hba,u32 attr_sel,u32 mib_val)1110*4882a593Smuzhiyun static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel,
1111*4882a593Smuzhiyun 				 u32 mib_val)
1112*4882a593Smuzhiyun {
1113*4882a593Smuzhiyun 	return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1114*4882a593Smuzhiyun 				   mib_val, DME_LOCAL);
1115*4882a593Smuzhiyun }
1116*4882a593Smuzhiyun 
ufshcd_dme_st_set(struct ufs_hba * hba,u32 attr_sel,u32 mib_val)1117*4882a593Smuzhiyun static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel,
1118*4882a593Smuzhiyun 				    u32 mib_val)
1119*4882a593Smuzhiyun {
1120*4882a593Smuzhiyun 	return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1121*4882a593Smuzhiyun 				   mib_val, DME_LOCAL);
1122*4882a593Smuzhiyun }
1123*4882a593Smuzhiyun 
ufshcd_dme_peer_set(struct ufs_hba * hba,u32 attr_sel,u32 mib_val)1124*4882a593Smuzhiyun static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel,
1125*4882a593Smuzhiyun 				      u32 mib_val)
1126*4882a593Smuzhiyun {
1127*4882a593Smuzhiyun 	return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1128*4882a593Smuzhiyun 				   mib_val, DME_PEER);
1129*4882a593Smuzhiyun }
1130*4882a593Smuzhiyun 
ufshcd_dme_peer_st_set(struct ufs_hba * hba,u32 attr_sel,u32 mib_val)1131*4882a593Smuzhiyun static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel,
1132*4882a593Smuzhiyun 					 u32 mib_val)
1133*4882a593Smuzhiyun {
1134*4882a593Smuzhiyun 	return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1135*4882a593Smuzhiyun 				   mib_val, DME_PEER);
1136*4882a593Smuzhiyun }
1137*4882a593Smuzhiyun 
ufshcd_dme_get(struct ufs_hba * hba,u32 attr_sel,u32 * mib_val)1138*4882a593Smuzhiyun static inline int ufshcd_dme_get(struct ufs_hba *hba,
1139*4882a593Smuzhiyun 				 u32 attr_sel, u32 *mib_val)
1140*4882a593Smuzhiyun {
1141*4882a593Smuzhiyun 	return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL);
1142*4882a593Smuzhiyun }
1143*4882a593Smuzhiyun 
ufshcd_dme_peer_get(struct ufs_hba * hba,u32 attr_sel,u32 * mib_val)1144*4882a593Smuzhiyun static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
1145*4882a593Smuzhiyun 				      u32 attr_sel, u32 *mib_val)
1146*4882a593Smuzhiyun {
1147*4882a593Smuzhiyun 	return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER);
1148*4882a593Smuzhiyun }
1149*4882a593Smuzhiyun 
ufshcd_is_hs_mode(struct ufs_pa_layer_attr * pwr_info)1150*4882a593Smuzhiyun static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info)
1151*4882a593Smuzhiyun {
1152*4882a593Smuzhiyun 	return (pwr_info->pwr_rx == FAST_MODE ||
1153*4882a593Smuzhiyun 		pwr_info->pwr_rx == FASTAUTO_MODE) &&
1154*4882a593Smuzhiyun 		(pwr_info->pwr_tx == FAST_MODE ||
1155*4882a593Smuzhiyun 		pwr_info->pwr_tx == FASTAUTO_MODE);
1156*4882a593Smuzhiyun }
1157*4882a593Smuzhiyun 
ufshcd_disable_host_tx_lcc(struct ufs_hba * hba)1158*4882a593Smuzhiyun static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba)
1159*4882a593Smuzhiyun {
1160*4882a593Smuzhiyun 	return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0);
1161*4882a593Smuzhiyun }
1162*4882a593Smuzhiyun 
1163*4882a593Smuzhiyun /* Expose Query-Request API */
1164*4882a593Smuzhiyun int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
1165*4882a593Smuzhiyun 				  enum query_opcode opcode,
1166*4882a593Smuzhiyun 				  enum desc_idn idn, u8 index,
1167*4882a593Smuzhiyun 				  u8 selector,
1168*4882a593Smuzhiyun 				  u8 *desc_buf, int *buf_len);
1169*4882a593Smuzhiyun int ufshcd_read_desc_param(struct ufs_hba *hba,
1170*4882a593Smuzhiyun 			   enum desc_idn desc_id,
1171*4882a593Smuzhiyun 			   int desc_index,
1172*4882a593Smuzhiyun 			   u8 param_offset,
1173*4882a593Smuzhiyun 			   u8 *param_read_buf,
1174*4882a593Smuzhiyun 			   u8 param_size);
1175*4882a593Smuzhiyun int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
1176*4882a593Smuzhiyun 		      enum attr_idn idn, u8 index, u8 selector, u32 *attr_val);
1177*4882a593Smuzhiyun int ufshcd_query_attr_retry(struct ufs_hba *hba,
1178*4882a593Smuzhiyun 	enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
1179*4882a593Smuzhiyun 	u32 *attr_val);
1180*4882a593Smuzhiyun int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
1181*4882a593Smuzhiyun 	enum flag_idn idn, u8 index, bool *flag_res);
1182*4882a593Smuzhiyun int ufshcd_query_flag_retry(struct ufs_hba *hba,
1183*4882a593Smuzhiyun 	enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res);
1184*4882a593Smuzhiyun int ufshcd_bkops_ctrl(struct ufs_hba *hba, enum bkops_status status);
1185*4882a593Smuzhiyun 
1186*4882a593Smuzhiyun void ufshcd_auto_hibern8_enable(struct ufs_hba *hba);
1187*4882a593Smuzhiyun void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit);
1188*4882a593Smuzhiyun void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, struct ufs_dev_fix *fixups);
1189*4882a593Smuzhiyun #define SD_ASCII_STD true
1190*4882a593Smuzhiyun #define SD_RAW false
1191*4882a593Smuzhiyun int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
1192*4882a593Smuzhiyun 			    u8 **buf, bool ascii);
1193*4882a593Smuzhiyun 
1194*4882a593Smuzhiyun int ufshcd_hold(struct ufs_hba *hba, bool async);
1195*4882a593Smuzhiyun void ufshcd_release(struct ufs_hba *hba);
1196*4882a593Smuzhiyun 
1197*4882a593Smuzhiyun void ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
1198*4882a593Smuzhiyun 				  int *desc_length);
1199*4882a593Smuzhiyun 
1200*4882a593Smuzhiyun u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba);
1201*4882a593Smuzhiyun 
1202*4882a593Smuzhiyun int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd);
1203*4882a593Smuzhiyun 
1204*4882a593Smuzhiyun int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
1205*4882a593Smuzhiyun 			     struct utp_upiu_req *req_upiu,
1206*4882a593Smuzhiyun 			     struct utp_upiu_req *rsp_upiu,
1207*4882a593Smuzhiyun 			     int msgcode,
1208*4882a593Smuzhiyun 			     u8 *desc_buff, int *buff_len,
1209*4882a593Smuzhiyun 			     enum query_opcode desc_op);
1210*4882a593Smuzhiyun 
1211*4882a593Smuzhiyun /* Wrapper functions for safely calling variant operations */
ufshcd_get_var_name(struct ufs_hba * hba)1212*4882a593Smuzhiyun static inline const char *ufshcd_get_var_name(struct ufs_hba *hba)
1213*4882a593Smuzhiyun {
1214*4882a593Smuzhiyun 	if (hba->vops)
1215*4882a593Smuzhiyun 		return hba->vops->name;
1216*4882a593Smuzhiyun 	return "";
1217*4882a593Smuzhiyun }
1218*4882a593Smuzhiyun 
ufshcd_vops_init(struct ufs_hba * hba)1219*4882a593Smuzhiyun static inline int ufshcd_vops_init(struct ufs_hba *hba)
1220*4882a593Smuzhiyun {
1221*4882a593Smuzhiyun 	if (hba->vops && hba->vops->init)
1222*4882a593Smuzhiyun 		return hba->vops->init(hba);
1223*4882a593Smuzhiyun 
1224*4882a593Smuzhiyun 	return 0;
1225*4882a593Smuzhiyun }
1226*4882a593Smuzhiyun 
ufshcd_vops_exit(struct ufs_hba * hba)1227*4882a593Smuzhiyun static inline void ufshcd_vops_exit(struct ufs_hba *hba)
1228*4882a593Smuzhiyun {
1229*4882a593Smuzhiyun 	if (hba->vops && hba->vops->exit)
1230*4882a593Smuzhiyun 		return hba->vops->exit(hba);
1231*4882a593Smuzhiyun }
1232*4882a593Smuzhiyun 
ufshcd_vops_get_ufs_hci_version(struct ufs_hba * hba)1233*4882a593Smuzhiyun static inline u32 ufshcd_vops_get_ufs_hci_version(struct ufs_hba *hba)
1234*4882a593Smuzhiyun {
1235*4882a593Smuzhiyun 	if (hba->vops && hba->vops->get_ufs_hci_version)
1236*4882a593Smuzhiyun 		return hba->vops->get_ufs_hci_version(hba);
1237*4882a593Smuzhiyun 
1238*4882a593Smuzhiyun 	return ufshcd_readl(hba, REG_UFS_VERSION);
1239*4882a593Smuzhiyun }
1240*4882a593Smuzhiyun 
ufshcd_has_utrlcnr(struct ufs_hba * hba)1241*4882a593Smuzhiyun static inline bool ufshcd_has_utrlcnr(struct ufs_hba *hba)
1242*4882a593Smuzhiyun {
1243*4882a593Smuzhiyun 	return (hba->ufs_version >= ufshci_version(3, 0));
1244*4882a593Smuzhiyun }
1245*4882a593Smuzhiyun 
ufshcd_vops_clk_scale_notify(struct ufs_hba * hba,bool up,enum ufs_notify_change_status status)1246*4882a593Smuzhiyun static inline int ufshcd_vops_clk_scale_notify(struct ufs_hba *hba,
1247*4882a593Smuzhiyun 			bool up, enum ufs_notify_change_status status)
1248*4882a593Smuzhiyun {
1249*4882a593Smuzhiyun 	if (hba->vops && hba->vops->clk_scale_notify)
1250*4882a593Smuzhiyun 		return hba->vops->clk_scale_notify(hba, up, status);
1251*4882a593Smuzhiyun 	return 0;
1252*4882a593Smuzhiyun }
1253*4882a593Smuzhiyun 
ufshcd_vops_event_notify(struct ufs_hba * hba,enum ufs_event_type evt,void * data)1254*4882a593Smuzhiyun static inline void ufshcd_vops_event_notify(struct ufs_hba *hba,
1255*4882a593Smuzhiyun 					    enum ufs_event_type evt,
1256*4882a593Smuzhiyun 					    void *data)
1257*4882a593Smuzhiyun {
1258*4882a593Smuzhiyun 	if (hba->vops && hba->vops->event_notify)
1259*4882a593Smuzhiyun 		hba->vops->event_notify(hba, evt, data);
1260*4882a593Smuzhiyun }
1261*4882a593Smuzhiyun 
ufshcd_vops_setup_clocks(struct ufs_hba * hba,bool on,enum ufs_notify_change_status status)1262*4882a593Smuzhiyun static inline int ufshcd_vops_setup_clocks(struct ufs_hba *hba, bool on,
1263*4882a593Smuzhiyun 					enum ufs_notify_change_status status)
1264*4882a593Smuzhiyun {
1265*4882a593Smuzhiyun 	if (hba->vops && hba->vops->setup_clocks)
1266*4882a593Smuzhiyun 		return hba->vops->setup_clocks(hba, on, status);
1267*4882a593Smuzhiyun 	return 0;
1268*4882a593Smuzhiyun }
1269*4882a593Smuzhiyun 
ufshcd_vops_setup_regulators(struct ufs_hba * hba,bool status)1270*4882a593Smuzhiyun static inline int ufshcd_vops_setup_regulators(struct ufs_hba *hba, bool status)
1271*4882a593Smuzhiyun {
1272*4882a593Smuzhiyun 	if (hba->vops && hba->vops->setup_regulators)
1273*4882a593Smuzhiyun 		return hba->vops->setup_regulators(hba, status);
1274*4882a593Smuzhiyun 
1275*4882a593Smuzhiyun 	return 0;
1276*4882a593Smuzhiyun }
1277*4882a593Smuzhiyun 
ufshcd_vops_hce_enable_notify(struct ufs_hba * hba,bool status)1278*4882a593Smuzhiyun static inline int ufshcd_vops_hce_enable_notify(struct ufs_hba *hba,
1279*4882a593Smuzhiyun 						bool status)
1280*4882a593Smuzhiyun {
1281*4882a593Smuzhiyun 	if (hba->vops && hba->vops->hce_enable_notify)
1282*4882a593Smuzhiyun 		return hba->vops->hce_enable_notify(hba, status);
1283*4882a593Smuzhiyun 
1284*4882a593Smuzhiyun 	return 0;
1285*4882a593Smuzhiyun }
ufshcd_vops_link_startup_notify(struct ufs_hba * hba,bool status)1286*4882a593Smuzhiyun static inline int ufshcd_vops_link_startup_notify(struct ufs_hba *hba,
1287*4882a593Smuzhiyun 						bool status)
1288*4882a593Smuzhiyun {
1289*4882a593Smuzhiyun 	if (hba->vops && hba->vops->link_startup_notify)
1290*4882a593Smuzhiyun 		return hba->vops->link_startup_notify(hba, status);
1291*4882a593Smuzhiyun 
1292*4882a593Smuzhiyun 	return 0;
1293*4882a593Smuzhiyun }
1294*4882a593Smuzhiyun 
ufshcd_vops_pwr_change_notify(struct ufs_hba * hba,bool status,struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)1295*4882a593Smuzhiyun static inline int ufshcd_vops_pwr_change_notify(struct ufs_hba *hba,
1296*4882a593Smuzhiyun 				  bool status,
1297*4882a593Smuzhiyun 				  struct ufs_pa_layer_attr *dev_max_params,
1298*4882a593Smuzhiyun 				  struct ufs_pa_layer_attr *dev_req_params)
1299*4882a593Smuzhiyun {
1300*4882a593Smuzhiyun 	if (hba->vops && hba->vops->pwr_change_notify)
1301*4882a593Smuzhiyun 		return hba->vops->pwr_change_notify(hba, status,
1302*4882a593Smuzhiyun 					dev_max_params, dev_req_params);
1303*4882a593Smuzhiyun 
1304*4882a593Smuzhiyun 	return -ENOTSUPP;
1305*4882a593Smuzhiyun }
1306*4882a593Smuzhiyun 
ufshcd_vops_setup_task_mgmt(struct ufs_hba * hba,int tag,u8 tm_function)1307*4882a593Smuzhiyun static inline void ufshcd_vops_setup_task_mgmt(struct ufs_hba *hba,
1308*4882a593Smuzhiyun 					int tag, u8 tm_function)
1309*4882a593Smuzhiyun {
1310*4882a593Smuzhiyun 	if (hba->vops && hba->vops->setup_task_mgmt)
1311*4882a593Smuzhiyun 		return hba->vops->setup_task_mgmt(hba, tag, tm_function);
1312*4882a593Smuzhiyun }
1313*4882a593Smuzhiyun 
ufshcd_vops_hibern8_notify(struct ufs_hba * hba,enum uic_cmd_dme cmd,enum ufs_notify_change_status status)1314*4882a593Smuzhiyun static inline void ufshcd_vops_hibern8_notify(struct ufs_hba *hba,
1315*4882a593Smuzhiyun 					enum uic_cmd_dme cmd,
1316*4882a593Smuzhiyun 					enum ufs_notify_change_status status)
1317*4882a593Smuzhiyun {
1318*4882a593Smuzhiyun 	if (hba->vops && hba->vops->hibern8_notify)
1319*4882a593Smuzhiyun 		return hba->vops->hibern8_notify(hba, cmd, status);
1320*4882a593Smuzhiyun }
1321*4882a593Smuzhiyun 
ufshcd_vops_apply_dev_quirks(struct ufs_hba * hba)1322*4882a593Smuzhiyun static inline int ufshcd_vops_apply_dev_quirks(struct ufs_hba *hba)
1323*4882a593Smuzhiyun {
1324*4882a593Smuzhiyun 	if (hba->vops && hba->vops->apply_dev_quirks)
1325*4882a593Smuzhiyun 		return hba->vops->apply_dev_quirks(hba);
1326*4882a593Smuzhiyun 	return 0;
1327*4882a593Smuzhiyun }
1328*4882a593Smuzhiyun 
ufshcd_vops_fixup_dev_quirks(struct ufs_hba * hba)1329*4882a593Smuzhiyun static inline void ufshcd_vops_fixup_dev_quirks(struct ufs_hba *hba)
1330*4882a593Smuzhiyun {
1331*4882a593Smuzhiyun 	if (hba->vops && hba->vops->fixup_dev_quirks)
1332*4882a593Smuzhiyun 		hba->vops->fixup_dev_quirks(hba);
1333*4882a593Smuzhiyun }
1334*4882a593Smuzhiyun 
ufshcd_vops_suspend(struct ufs_hba * hba,enum ufs_pm_op op)1335*4882a593Smuzhiyun static inline int ufshcd_vops_suspend(struct ufs_hba *hba, enum ufs_pm_op op)
1336*4882a593Smuzhiyun {
1337*4882a593Smuzhiyun 	if (hba->vops && hba->vops->suspend)
1338*4882a593Smuzhiyun 		return hba->vops->suspend(hba, op);
1339*4882a593Smuzhiyun 
1340*4882a593Smuzhiyun 	return 0;
1341*4882a593Smuzhiyun }
1342*4882a593Smuzhiyun 
ufshcd_vops_resume(struct ufs_hba * hba,enum ufs_pm_op op)1343*4882a593Smuzhiyun static inline int ufshcd_vops_resume(struct ufs_hba *hba, enum ufs_pm_op op)
1344*4882a593Smuzhiyun {
1345*4882a593Smuzhiyun 	if (hba->vops && hba->vops->resume)
1346*4882a593Smuzhiyun 		return hba->vops->resume(hba, op);
1347*4882a593Smuzhiyun 
1348*4882a593Smuzhiyun 	return 0;
1349*4882a593Smuzhiyun }
1350*4882a593Smuzhiyun 
ufshcd_vops_dbg_register_dump(struct ufs_hba * hba)1351*4882a593Smuzhiyun static inline void ufshcd_vops_dbg_register_dump(struct ufs_hba *hba)
1352*4882a593Smuzhiyun {
1353*4882a593Smuzhiyun 	if (hba->vops && hba->vops->dbg_register_dump)
1354*4882a593Smuzhiyun 		hba->vops->dbg_register_dump(hba);
1355*4882a593Smuzhiyun }
1356*4882a593Smuzhiyun 
ufshcd_vops_device_reset(struct ufs_hba * hba)1357*4882a593Smuzhiyun static inline void ufshcd_vops_device_reset(struct ufs_hba *hba)
1358*4882a593Smuzhiyun {
1359*4882a593Smuzhiyun 	if (hba->vops && hba->vops->device_reset) {
1360*4882a593Smuzhiyun 		int err = hba->vops->device_reset(hba);
1361*4882a593Smuzhiyun 
1362*4882a593Smuzhiyun 		if (!err) {
1363*4882a593Smuzhiyun 			ufshcd_set_ufs_dev_active(hba);
1364*4882a593Smuzhiyun 			if (ufshcd_is_wb_allowed(hba)) {
1365*4882a593Smuzhiyun 				hba->wb_enabled = false;
1366*4882a593Smuzhiyun 				hba->wb_buf_flush_enabled = false;
1367*4882a593Smuzhiyun 			}
1368*4882a593Smuzhiyun 		}
1369*4882a593Smuzhiyun 		if (err != -EOPNOTSUPP)
1370*4882a593Smuzhiyun 			ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err);
1371*4882a593Smuzhiyun 	}
1372*4882a593Smuzhiyun }
1373*4882a593Smuzhiyun 
ufshcd_vops_config_scaling_param(struct ufs_hba * hba,struct devfreq_dev_profile * profile,void * data)1374*4882a593Smuzhiyun static inline void ufshcd_vops_config_scaling_param(struct ufs_hba *hba,
1375*4882a593Smuzhiyun 						    struct devfreq_dev_profile
1376*4882a593Smuzhiyun 						    *profile, void *data)
1377*4882a593Smuzhiyun {
1378*4882a593Smuzhiyun 	if (hba->vops && hba->vops->config_scaling_param)
1379*4882a593Smuzhiyun 		hba->vops->config_scaling_param(hba, profile, data);
1380*4882a593Smuzhiyun }
1381*4882a593Smuzhiyun 
1382*4882a593Smuzhiyun extern struct ufs_pm_lvl_states ufs_pm_lvl_states[];
1383*4882a593Smuzhiyun 
1384*4882a593Smuzhiyun /*
1385*4882a593Smuzhiyun  * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
1386*4882a593Smuzhiyun  * @scsi_lun: scsi LUN id
1387*4882a593Smuzhiyun  *
1388*4882a593Smuzhiyun  * Returns UPIU LUN id
1389*4882a593Smuzhiyun  */
ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)1390*4882a593Smuzhiyun static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
1391*4882a593Smuzhiyun {
1392*4882a593Smuzhiyun 	if (scsi_is_wlun(scsi_lun))
1393*4882a593Smuzhiyun 		return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
1394*4882a593Smuzhiyun 			| UFS_UPIU_WLUN_ID;
1395*4882a593Smuzhiyun 	else
1396*4882a593Smuzhiyun 		return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
1397*4882a593Smuzhiyun }
1398*4882a593Smuzhiyun 
1399*4882a593Smuzhiyun int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
1400*4882a593Smuzhiyun 		     const char *prefix);
1401*4882a593Smuzhiyun int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
1402*4882a593Smuzhiyun int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
1403*4882a593Smuzhiyun #endif /* End of Header */
1404