1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * UFS Host driver for Synopsys Designware Core
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Authors: Joao Pinto <jpinto@synopsys.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "ufshcd.h"
11*4882a593Smuzhiyun #include "unipro.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include "ufshcd-dwc.h"
14*4882a593Smuzhiyun #include "ufshci-dwc.h"
15*4882a593Smuzhiyun
ufshcd_dwc_dme_set_attrs(struct ufs_hba * hba,const struct ufshcd_dme_attr_val * v,int n)16*4882a593Smuzhiyun int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba,
17*4882a593Smuzhiyun const struct ufshcd_dme_attr_val *v, int n)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun int ret = 0;
20*4882a593Smuzhiyun int attr_node = 0;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun for (attr_node = 0; attr_node < n; attr_node++) {
23*4882a593Smuzhiyun ret = ufshcd_dme_set_attr(hba, v[attr_node].attr_sel,
24*4882a593Smuzhiyun ATTR_SET_NOR, v[attr_node].mib_val, v[attr_node].peer);
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun if (ret)
27*4882a593Smuzhiyun return ret;
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun return 0;
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun EXPORT_SYMBOL(ufshcd_dwc_dme_set_attrs);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /**
35*4882a593Smuzhiyun * ufshcd_dwc_program_clk_div()
36*4882a593Smuzhiyun * This function programs the clk divider value. This value is needed to
37*4882a593Smuzhiyun * provide 1 microsecond tick to unipro layer.
38*4882a593Smuzhiyun * @hba: Private Structure pointer
39*4882a593Smuzhiyun * @divider_val: clock divider value to be programmed
40*4882a593Smuzhiyun *
41*4882a593Smuzhiyun */
ufshcd_dwc_program_clk_div(struct ufs_hba * hba,u32 divider_val)42*4882a593Smuzhiyun static void ufshcd_dwc_program_clk_div(struct ufs_hba *hba, u32 divider_val)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun ufshcd_writel(hba, divider_val, DWC_UFS_REG_HCLKDIV);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /**
48*4882a593Smuzhiyun * ufshcd_dwc_link_is_up()
49*4882a593Smuzhiyun * Check if link is up
50*4882a593Smuzhiyun * @hba: private structure pointer
51*4882a593Smuzhiyun *
52*4882a593Smuzhiyun * Returns 0 on success, non-zero value on failure
53*4882a593Smuzhiyun */
ufshcd_dwc_link_is_up(struct ufs_hba * hba)54*4882a593Smuzhiyun static int ufshcd_dwc_link_is_up(struct ufs_hba *hba)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun int dme_result = 0;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun ufshcd_dme_get(hba, UIC_ARG_MIB(VS_POWERSTATE), &dme_result);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun if (dme_result == UFSHCD_LINK_IS_UP) {
61*4882a593Smuzhiyun ufshcd_set_link_active(hba);
62*4882a593Smuzhiyun return 0;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun return 1;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /**
69*4882a593Smuzhiyun * ufshcd_dwc_connection_setup()
70*4882a593Smuzhiyun * This function configures both the local side (host) and the peer side
71*4882a593Smuzhiyun * (device) unipro attributes to establish the connection to application/
72*4882a593Smuzhiyun * cport.
73*4882a593Smuzhiyun * This function is not required if the hardware is properly configured to
74*4882a593Smuzhiyun * have this connection setup on reset. But invoking this function does no
75*4882a593Smuzhiyun * harm and should be fine even working with any ufs device.
76*4882a593Smuzhiyun *
77*4882a593Smuzhiyun * @hba: pointer to drivers private data
78*4882a593Smuzhiyun *
79*4882a593Smuzhiyun * Returns 0 on success non-zero value on failure
80*4882a593Smuzhiyun */
ufshcd_dwc_connection_setup(struct ufs_hba * hba)81*4882a593Smuzhiyun static int ufshcd_dwc_connection_setup(struct ufs_hba *hba)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun static const struct ufshcd_dme_attr_val setup_attrs[] = {
84*4882a593Smuzhiyun { UIC_ARG_MIB(T_CONNECTIONSTATE), 0, DME_LOCAL },
85*4882a593Smuzhiyun { UIC_ARG_MIB(N_DEVICEID), 0, DME_LOCAL },
86*4882a593Smuzhiyun { UIC_ARG_MIB(N_DEVICEID_VALID), 0, DME_LOCAL },
87*4882a593Smuzhiyun { UIC_ARG_MIB(T_PEERDEVICEID), 1, DME_LOCAL },
88*4882a593Smuzhiyun { UIC_ARG_MIB(T_PEERCPORTID), 0, DME_LOCAL },
89*4882a593Smuzhiyun { UIC_ARG_MIB(T_TRAFFICCLASS), 0, DME_LOCAL },
90*4882a593Smuzhiyun { UIC_ARG_MIB(T_CPORTFLAGS), 0x6, DME_LOCAL },
91*4882a593Smuzhiyun { UIC_ARG_MIB(T_CPORTMODE), 1, DME_LOCAL },
92*4882a593Smuzhiyun { UIC_ARG_MIB(T_CONNECTIONSTATE), 1, DME_LOCAL },
93*4882a593Smuzhiyun { UIC_ARG_MIB(T_CONNECTIONSTATE), 0, DME_PEER },
94*4882a593Smuzhiyun { UIC_ARG_MIB(N_DEVICEID), 1, DME_PEER },
95*4882a593Smuzhiyun { UIC_ARG_MIB(N_DEVICEID_VALID), 1, DME_PEER },
96*4882a593Smuzhiyun { UIC_ARG_MIB(T_PEERDEVICEID), 1, DME_PEER },
97*4882a593Smuzhiyun { UIC_ARG_MIB(T_PEERCPORTID), 0, DME_PEER },
98*4882a593Smuzhiyun { UIC_ARG_MIB(T_TRAFFICCLASS), 0, DME_PEER },
99*4882a593Smuzhiyun { UIC_ARG_MIB(T_CPORTFLAGS), 0x6, DME_PEER },
100*4882a593Smuzhiyun { UIC_ARG_MIB(T_CPORTMODE), 1, DME_PEER },
101*4882a593Smuzhiyun { UIC_ARG_MIB(T_CONNECTIONSTATE), 1, DME_PEER }
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun return ufshcd_dwc_dme_set_attrs(hba, setup_attrs, ARRAY_SIZE(setup_attrs));
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /**
108*4882a593Smuzhiyun * ufshcd_dwc_link_startup_notify()
109*4882a593Smuzhiyun * UFS Host DWC specific link startup sequence
110*4882a593Smuzhiyun * @hba: private structure pointer
111*4882a593Smuzhiyun * @status: Callback notify status
112*4882a593Smuzhiyun *
113*4882a593Smuzhiyun * Returns 0 on success, non-zero value on failure
114*4882a593Smuzhiyun */
ufshcd_dwc_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)115*4882a593Smuzhiyun int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba,
116*4882a593Smuzhiyun enum ufs_notify_change_status status)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun int err = 0;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun if (status == PRE_CHANGE) {
121*4882a593Smuzhiyun ufshcd_dwc_program_clk_div(hba, DWC_UFS_REG_HCLKDIV_DIV_125);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun if (hba->vops->phy_initialization) {
124*4882a593Smuzhiyun err = hba->vops->phy_initialization(hba);
125*4882a593Smuzhiyun if (err) {
126*4882a593Smuzhiyun dev_err(hba->dev, "Phy setup failed (%d)\n",
127*4882a593Smuzhiyun err);
128*4882a593Smuzhiyun goto out;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun } else { /* POST_CHANGE */
132*4882a593Smuzhiyun err = ufshcd_dwc_link_is_up(hba);
133*4882a593Smuzhiyun if (err) {
134*4882a593Smuzhiyun dev_err(hba->dev, "Link is not up\n");
135*4882a593Smuzhiyun goto out;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun err = ufshcd_dwc_connection_setup(hba);
139*4882a593Smuzhiyun if (err)
140*4882a593Smuzhiyun dev_err(hba->dev, "Connection setup failed (%d)\n",
141*4882a593Smuzhiyun err);
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun out:
145*4882a593Smuzhiyun return err;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun EXPORT_SYMBOL(ufshcd_dwc_link_startup_notify);
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun MODULE_AUTHOR("Joao Pinto <Joao.Pinto@synopsys.com>");
150*4882a593Smuzhiyun MODULE_DESCRIPTION("UFS Host driver for Synopsys Designware Core");
151*4882a593Smuzhiyun MODULE_LICENSE("Dual BSD/GPL");
152