xref: /OK3568_Linux_fs/kernel/drivers/scsi/ufs/ufs.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Universal Flash Storage Host controller driver
4*4882a593Smuzhiyun  * Copyright (C) 2011-2013 Samsung India Software Operations
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Authors:
7*4882a593Smuzhiyun  *	Santosh Yaraganavi <santosh.sy@samsung.com>
8*4882a593Smuzhiyun  *	Vinayak Holikatti <h.vinayak@samsung.com>
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #ifndef _UFS_H
12*4882a593Smuzhiyun #define _UFS_H
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <linux/mutex.h>
15*4882a593Smuzhiyun #include <linux/types.h>
16*4882a593Smuzhiyun #include <linux/android_kabi.h>
17*4882a593Smuzhiyun #include <uapi/scsi/scsi_bsg_ufs.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req))
20*4882a593Smuzhiyun #define QUERY_DESC_MAX_SIZE       255
21*4882a593Smuzhiyun #define QUERY_DESC_MIN_SIZE       2
22*4882a593Smuzhiyun #define QUERY_DESC_HDR_SIZE       2
23*4882a593Smuzhiyun #define QUERY_OSF_SIZE            (GENERAL_UPIU_REQUEST_SIZE - \
24*4882a593Smuzhiyun 					(sizeof(struct utp_upiu_header)))
25*4882a593Smuzhiyun #define UFS_SENSE_SIZE	18
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\
28*4882a593Smuzhiyun 			cpu_to_be32((byte3 << 24) | (byte2 << 16) |\
29*4882a593Smuzhiyun 			 (byte1 << 8) | (byte0))
30*4882a593Smuzhiyun /*
31*4882a593Smuzhiyun  * UFS device may have standard LUs and LUN id could be from 0x00 to
32*4882a593Smuzhiyun  * 0x7F. Standard LUs use "Peripheral Device Addressing Format".
33*4882a593Smuzhiyun  * UFS device may also have the Well Known LUs (also referred as W-LU)
34*4882a593Smuzhiyun  * which again could be from 0x00 to 0x7F. For W-LUs, device only use
35*4882a593Smuzhiyun  * the "Extended Addressing Format" which means the W-LUNs would be
36*4882a593Smuzhiyun  * from 0xc100 (SCSI_W_LUN_BASE) onwards.
37*4882a593Smuzhiyun  * This means max. LUN number reported from UFS device could be 0xC17F.
38*4882a593Smuzhiyun  */
39*4882a593Smuzhiyun #define UFS_UPIU_MAX_UNIT_NUM_ID	0x7F
40*4882a593Smuzhiyun #define UFS_MAX_LUNS		(SCSI_W_LUN_BASE + UFS_UPIU_MAX_UNIT_NUM_ID)
41*4882a593Smuzhiyun #define UFS_UPIU_WLUN_ID	(1 << 7)
42*4882a593Smuzhiyun #define UFS_RPMB_UNIT		0xC4
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun /* WriteBooster buffer is available only for the logical unit from 0 to 7 */
45*4882a593Smuzhiyun #define UFS_UPIU_MAX_WB_LUN_ID	8
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun /* Well known logical unit id in LUN field of UPIU */
48*4882a593Smuzhiyun enum {
49*4882a593Smuzhiyun 	UFS_UPIU_REPORT_LUNS_WLUN	= 0x81,
50*4882a593Smuzhiyun 	UFS_UPIU_UFS_DEVICE_WLUN	= 0xD0,
51*4882a593Smuzhiyun 	UFS_UPIU_BOOT_WLUN		= 0xB0,
52*4882a593Smuzhiyun 	UFS_UPIU_RPMB_WLUN		= 0xC4,
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun /*
56*4882a593Smuzhiyun  * UFS Protocol Information Unit related definitions
57*4882a593Smuzhiyun  */
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun /* Task management functions */
60*4882a593Smuzhiyun enum {
61*4882a593Smuzhiyun 	UFS_ABORT_TASK		= 0x01,
62*4882a593Smuzhiyun 	UFS_ABORT_TASK_SET	= 0x02,
63*4882a593Smuzhiyun 	UFS_CLEAR_TASK_SET	= 0x04,
64*4882a593Smuzhiyun 	UFS_LOGICAL_RESET	= 0x08,
65*4882a593Smuzhiyun 	UFS_QUERY_TASK		= 0x80,
66*4882a593Smuzhiyun 	UFS_QUERY_TASK_SET	= 0x81,
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun /* UTP UPIU Transaction Codes Initiator to Target */
70*4882a593Smuzhiyun enum {
71*4882a593Smuzhiyun 	UPIU_TRANSACTION_NOP_OUT	= 0x00,
72*4882a593Smuzhiyun 	UPIU_TRANSACTION_COMMAND	= 0x01,
73*4882a593Smuzhiyun 	UPIU_TRANSACTION_DATA_OUT	= 0x02,
74*4882a593Smuzhiyun 	UPIU_TRANSACTION_TASK_REQ	= 0x04,
75*4882a593Smuzhiyun 	UPIU_TRANSACTION_QUERY_REQ	= 0x16,
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun /* UTP UPIU Transaction Codes Target to Initiator */
79*4882a593Smuzhiyun enum {
80*4882a593Smuzhiyun 	UPIU_TRANSACTION_NOP_IN		= 0x20,
81*4882a593Smuzhiyun 	UPIU_TRANSACTION_RESPONSE	= 0x21,
82*4882a593Smuzhiyun 	UPIU_TRANSACTION_DATA_IN	= 0x22,
83*4882a593Smuzhiyun 	UPIU_TRANSACTION_TASK_RSP	= 0x24,
84*4882a593Smuzhiyun 	UPIU_TRANSACTION_READY_XFER	= 0x31,
85*4882a593Smuzhiyun 	UPIU_TRANSACTION_QUERY_RSP	= 0x36,
86*4882a593Smuzhiyun 	UPIU_TRANSACTION_REJECT_UPIU	= 0x3F,
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun /* UPIU Read/Write flags */
90*4882a593Smuzhiyun enum {
91*4882a593Smuzhiyun 	UPIU_CMD_FLAGS_NONE	= 0x00,
92*4882a593Smuzhiyun 	UPIU_CMD_FLAGS_WRITE	= 0x20,
93*4882a593Smuzhiyun 	UPIU_CMD_FLAGS_READ	= 0x40,
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun /* UPIU Task Attributes */
97*4882a593Smuzhiyun enum {
98*4882a593Smuzhiyun 	UPIU_TASK_ATTR_SIMPLE	= 0x00,
99*4882a593Smuzhiyun 	UPIU_TASK_ATTR_ORDERED	= 0x01,
100*4882a593Smuzhiyun 	UPIU_TASK_ATTR_HEADQ	= 0x02,
101*4882a593Smuzhiyun 	UPIU_TASK_ATTR_ACA	= 0x03,
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun /* UPIU Query request function */
105*4882a593Smuzhiyun enum {
106*4882a593Smuzhiyun 	UPIU_QUERY_FUNC_STANDARD_READ_REQUEST           = 0x01,
107*4882a593Smuzhiyun 	UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST          = 0x81,
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun /* Flag idn for Query Requests*/
111*4882a593Smuzhiyun enum flag_idn {
112*4882a593Smuzhiyun 	QUERY_FLAG_IDN_FDEVICEINIT			= 0x01,
113*4882a593Smuzhiyun 	QUERY_FLAG_IDN_PERMANENT_WPE			= 0x02,
114*4882a593Smuzhiyun 	QUERY_FLAG_IDN_PWR_ON_WPE			= 0x03,
115*4882a593Smuzhiyun 	QUERY_FLAG_IDN_BKOPS_EN				= 0x04,
116*4882a593Smuzhiyun 	QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE		= 0x05,
117*4882a593Smuzhiyun 	QUERY_FLAG_IDN_PURGE_ENABLE			= 0x06,
118*4882a593Smuzhiyun 	QUERY_FLAG_IDN_RESERVED2			= 0x07,
119*4882a593Smuzhiyun 	QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL		= 0x08,
120*4882a593Smuzhiyun 	QUERY_FLAG_IDN_BUSY_RTC				= 0x09,
121*4882a593Smuzhiyun 	QUERY_FLAG_IDN_RESERVED3			= 0x0A,
122*4882a593Smuzhiyun 	QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE	= 0x0B,
123*4882a593Smuzhiyun 	QUERY_FLAG_IDN_WB_EN                            = 0x0E,
124*4882a593Smuzhiyun 	QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN                 = 0x0F,
125*4882a593Smuzhiyun 	QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8     = 0x10,
126*4882a593Smuzhiyun 	QUERY_FLAG_IDN_HPB_RESET                        = 0x11,
127*4882a593Smuzhiyun 	QUERY_FLAG_IDN_HPB_EN				= 0x12,
128*4882a593Smuzhiyun };
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun /* Attribute idn for Query requests */
131*4882a593Smuzhiyun enum attr_idn {
132*4882a593Smuzhiyun 	QUERY_ATTR_IDN_BOOT_LU_EN		= 0x00,
133*4882a593Smuzhiyun 	QUERY_ATTR_IDN_MAX_HPB_SINGLE_CMD	= 0x01,
134*4882a593Smuzhiyun 	QUERY_ATTR_IDN_POWER_MODE		= 0x02,
135*4882a593Smuzhiyun 	QUERY_ATTR_IDN_ACTIVE_ICC_LVL		= 0x03,
136*4882a593Smuzhiyun 	QUERY_ATTR_IDN_OOO_DATA_EN		= 0x04,
137*4882a593Smuzhiyun 	QUERY_ATTR_IDN_BKOPS_STATUS		= 0x05,
138*4882a593Smuzhiyun 	QUERY_ATTR_IDN_PURGE_STATUS		= 0x06,
139*4882a593Smuzhiyun 	QUERY_ATTR_IDN_MAX_DATA_IN		= 0x07,
140*4882a593Smuzhiyun 	QUERY_ATTR_IDN_MAX_DATA_OUT		= 0x08,
141*4882a593Smuzhiyun 	QUERY_ATTR_IDN_DYN_CAP_NEEDED		= 0x09,
142*4882a593Smuzhiyun 	QUERY_ATTR_IDN_REF_CLK_FREQ		= 0x0A,
143*4882a593Smuzhiyun 	QUERY_ATTR_IDN_CONF_DESC_LOCK		= 0x0B,
144*4882a593Smuzhiyun 	QUERY_ATTR_IDN_MAX_NUM_OF_RTT		= 0x0C,
145*4882a593Smuzhiyun 	QUERY_ATTR_IDN_EE_CONTROL		= 0x0D,
146*4882a593Smuzhiyun 	QUERY_ATTR_IDN_EE_STATUS		= 0x0E,
147*4882a593Smuzhiyun 	QUERY_ATTR_IDN_SECONDS_PASSED		= 0x0F,
148*4882a593Smuzhiyun 	QUERY_ATTR_IDN_CNTX_CONF		= 0x10,
149*4882a593Smuzhiyun 	QUERY_ATTR_IDN_CORR_PRG_BLK_NUM		= 0x11,
150*4882a593Smuzhiyun 	QUERY_ATTR_IDN_RESERVED2		= 0x12,
151*4882a593Smuzhiyun 	QUERY_ATTR_IDN_RESERVED3		= 0x13,
152*4882a593Smuzhiyun 	QUERY_ATTR_IDN_FFU_STATUS		= 0x14,
153*4882a593Smuzhiyun 	QUERY_ATTR_IDN_PSA_STATE		= 0x15,
154*4882a593Smuzhiyun 	QUERY_ATTR_IDN_PSA_DATA_SIZE		= 0x16,
155*4882a593Smuzhiyun 	QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME	= 0x17,
156*4882a593Smuzhiyun 	QUERY_ATTR_IDN_WB_FLUSH_STATUS	        = 0x1C,
157*4882a593Smuzhiyun 	QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE       = 0x1D,
158*4882a593Smuzhiyun 	QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST    = 0x1E,
159*4882a593Smuzhiyun 	QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE        = 0x1F,
160*4882a593Smuzhiyun };
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun /* Descriptor idn for Query requests */
163*4882a593Smuzhiyun enum desc_idn {
164*4882a593Smuzhiyun 	QUERY_DESC_IDN_DEVICE		= 0x0,
165*4882a593Smuzhiyun 	QUERY_DESC_IDN_CONFIGURATION	= 0x1,
166*4882a593Smuzhiyun 	QUERY_DESC_IDN_UNIT		= 0x2,
167*4882a593Smuzhiyun 	QUERY_DESC_IDN_RFU_0		= 0x3,
168*4882a593Smuzhiyun 	QUERY_DESC_IDN_INTERCONNECT	= 0x4,
169*4882a593Smuzhiyun 	QUERY_DESC_IDN_STRING		= 0x5,
170*4882a593Smuzhiyun 	QUERY_DESC_IDN_RFU_1		= 0x6,
171*4882a593Smuzhiyun 	QUERY_DESC_IDN_GEOMETRY		= 0x7,
172*4882a593Smuzhiyun 	QUERY_DESC_IDN_POWER		= 0x8,
173*4882a593Smuzhiyun 	QUERY_DESC_IDN_HEALTH           = 0x9,
174*4882a593Smuzhiyun 	QUERY_DESC_IDN_MAX,
175*4882a593Smuzhiyun };
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun enum desc_header_offset {
178*4882a593Smuzhiyun 	QUERY_DESC_LENGTH_OFFSET	= 0x00,
179*4882a593Smuzhiyun 	QUERY_DESC_DESC_TYPE_OFFSET	= 0x01,
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun /* Unit descriptor parameters offsets in bytes*/
183*4882a593Smuzhiyun enum unit_desc_param {
184*4882a593Smuzhiyun 	UNIT_DESC_PARAM_LEN			= 0x0,
185*4882a593Smuzhiyun 	UNIT_DESC_PARAM_TYPE			= 0x1,
186*4882a593Smuzhiyun 	UNIT_DESC_PARAM_UNIT_INDEX		= 0x2,
187*4882a593Smuzhiyun 	UNIT_DESC_PARAM_LU_ENABLE		= 0x3,
188*4882a593Smuzhiyun 	UNIT_DESC_PARAM_BOOT_LUN_ID		= 0x4,
189*4882a593Smuzhiyun 	UNIT_DESC_PARAM_LU_WR_PROTECT		= 0x5,
190*4882a593Smuzhiyun 	UNIT_DESC_PARAM_LU_Q_DEPTH		= 0x6,
191*4882a593Smuzhiyun 	UNIT_DESC_PARAM_PSA_SENSITIVE		= 0x7,
192*4882a593Smuzhiyun 	UNIT_DESC_PARAM_MEM_TYPE		= 0x8,
193*4882a593Smuzhiyun 	UNIT_DESC_PARAM_DATA_RELIABILITY	= 0x9,
194*4882a593Smuzhiyun 	UNIT_DESC_PARAM_LOGICAL_BLK_SIZE	= 0xA,
195*4882a593Smuzhiyun 	UNIT_DESC_PARAM_LOGICAL_BLK_COUNT	= 0xB,
196*4882a593Smuzhiyun 	UNIT_DESC_PARAM_ERASE_BLK_SIZE		= 0x13,
197*4882a593Smuzhiyun 	UNIT_DESC_PARAM_PROVISIONING_TYPE	= 0x17,
198*4882a593Smuzhiyun 	UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT	= 0x18,
199*4882a593Smuzhiyun 	UNIT_DESC_PARAM_CTX_CAPABILITIES	= 0x20,
200*4882a593Smuzhiyun 	UNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1	= 0x22,
201*4882a593Smuzhiyun 	UNIT_DESC_PARAM_HPB_LU_MAX_ACTIVE_RGNS	= 0x23,
202*4882a593Smuzhiyun 	UNIT_DESC_PARAM_HPB_PIN_RGN_START_OFF	= 0x25,
203*4882a593Smuzhiyun 	UNIT_DESC_PARAM_HPB_NUM_PIN_RGNS	= 0x27,
204*4882a593Smuzhiyun 	UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS	= 0x29,
205*4882a593Smuzhiyun };
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun /* Device descriptor parameters offsets in bytes*/
208*4882a593Smuzhiyun enum device_desc_param {
209*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_LEN			= 0x0,
210*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_TYPE			= 0x1,
211*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_DEVICE_TYPE		= 0x2,
212*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_DEVICE_CLASS		= 0x3,
213*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_DEVICE_SUB_CLASS	= 0x4,
214*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_PRTCL			= 0x5,
215*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_NUM_LU		= 0x6,
216*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_NUM_WLU		= 0x7,
217*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_BOOT_ENBL		= 0x8,
218*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_DESC_ACCSS_ENBL	= 0x9,
219*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_INIT_PWR_MODE		= 0xA,
220*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_HIGH_PR_LUN		= 0xB,
221*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_SEC_RMV_TYPE		= 0xC,
222*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_SEC_LU		= 0xD,
223*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_BKOP_TERM_LT		= 0xE,
224*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_ACTVE_ICC_LVL		= 0xF,
225*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_SPEC_VER		= 0x10,
226*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_MANF_DATE		= 0x12,
227*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_MANF_NAME		= 0x14,
228*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_PRDCT_NAME		= 0x15,
229*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_SN			= 0x16,
230*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_OEM_ID		= 0x17,
231*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_MANF_ID		= 0x18,
232*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_UD_OFFSET		= 0x1A,
233*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_UD_LEN		= 0x1B,
234*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_RTT_CAP		= 0x1C,
235*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_FRQ_RTC		= 0x1D,
236*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_UFS_FEAT		= 0x1F,
237*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_FFU_TMT		= 0x20,
238*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_Q_DPTH		= 0x21,
239*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_DEV_VER		= 0x22,
240*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_NUM_SEC_WPA		= 0x24,
241*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_PSA_MAX_DATA		= 0x25,
242*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_PSA_TMT		= 0x29,
243*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_PRDCT_REV		= 0x2A,
244*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_HPB_VER		= 0x40,
245*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_HPB_CONTROL		= 0x42,
246*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP	= 0x4F,
247*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN	= 0x53,
248*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_WB_TYPE		= 0x54,
249*4882a593Smuzhiyun 	DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS = 0x55,
250*4882a593Smuzhiyun };
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun /* Interconnect descriptor parameters offsets in bytes*/
253*4882a593Smuzhiyun enum interconnect_desc_param {
254*4882a593Smuzhiyun 	INTERCONNECT_DESC_PARAM_LEN		= 0x0,
255*4882a593Smuzhiyun 	INTERCONNECT_DESC_PARAM_TYPE		= 0x1,
256*4882a593Smuzhiyun 	INTERCONNECT_DESC_PARAM_UNIPRO_VER	= 0x2,
257*4882a593Smuzhiyun 	INTERCONNECT_DESC_PARAM_MPHY_VER	= 0x4,
258*4882a593Smuzhiyun };
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun /* Geometry descriptor parameters offsets in bytes*/
261*4882a593Smuzhiyun enum geometry_desc_param {
262*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_LEN			= 0x0,
263*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_TYPE		= 0x1,
264*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_DEV_CAP		= 0x4,
265*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_MAX_NUM_LUN		= 0xC,
266*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_SEG_SIZE		= 0xD,
267*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_ALLOC_UNIT_SIZE	= 0x11,
268*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_MIN_BLK_SIZE	= 0x12,
269*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_OPT_RD_BLK_SIZE	= 0x13,
270*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_OPT_WR_BLK_SIZE	= 0x14,
271*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_MAX_IN_BUF_SIZE	= 0x15,
272*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_MAX_OUT_BUF_SIZE	= 0x16,
273*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_RPMB_RW_SIZE	= 0x17,
274*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_DYN_CAP_RSRC_PLC	= 0x18,
275*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_DATA_ORDER		= 0x19,
276*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_MAX_NUM_CTX		= 0x1A,
277*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_TAG_UNIT_SIZE	= 0x1B,
278*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_TAG_RSRC_SIZE	= 0x1C,
279*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_SEC_RM_TYPES	= 0x1D,
280*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_MEM_TYPES		= 0x1E,
281*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_SCM_MAX_NUM_UNITS	= 0x20,
282*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_SCM_CAP_ADJ_FCTR	= 0x24,
283*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_NPM_MAX_NUM_UNITS	= 0x26,
284*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_NPM_CAP_ADJ_FCTR	= 0x2A,
285*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_ENM1_MAX_NUM_UNITS	= 0x2C,
286*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_ENM1_CAP_ADJ_FCTR	= 0x30,
287*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_ENM2_MAX_NUM_UNITS	= 0x32,
288*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_ENM2_CAP_ADJ_FCTR	= 0x36,
289*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_ENM3_MAX_NUM_UNITS	= 0x38,
290*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_ENM3_CAP_ADJ_FCTR	= 0x3C,
291*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_ENM4_MAX_NUM_UNITS	= 0x3E,
292*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_ENM4_CAP_ADJ_FCTR	= 0x42,
293*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_OPT_LOG_BLK_SIZE	= 0x44,
294*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_HPB_REGION_SIZE	= 0x48,
295*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_HPB_NUMBER_LU	= 0x49,
296*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_HPB_SUBREGION_SIZE	= 0x4A,
297*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS	= 0x4B,
298*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_WB_MAX_ALLOC_UNITS	= 0x4F,
299*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_WB_MAX_WB_LUNS	= 0x53,
300*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_WB_BUFF_CAP_ADJ	= 0x54,
301*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_WB_SUP_RED_TYPE	= 0x55,
302*4882a593Smuzhiyun 	GEOMETRY_DESC_PARAM_WB_SUP_WB_TYPE	= 0x56,
303*4882a593Smuzhiyun };
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun /* Health descriptor parameters offsets in bytes*/
306*4882a593Smuzhiyun enum health_desc_param {
307*4882a593Smuzhiyun 	HEALTH_DESC_PARAM_LEN			= 0x0,
308*4882a593Smuzhiyun 	HEALTH_DESC_PARAM_TYPE			= 0x1,
309*4882a593Smuzhiyun 	HEALTH_DESC_PARAM_EOL_INFO		= 0x2,
310*4882a593Smuzhiyun 	HEALTH_DESC_PARAM_LIFE_TIME_EST_A	= 0x3,
311*4882a593Smuzhiyun 	HEALTH_DESC_PARAM_LIFE_TIME_EST_B	= 0x4,
312*4882a593Smuzhiyun };
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun /* WriteBooster buffer mode */
315*4882a593Smuzhiyun enum {
316*4882a593Smuzhiyun 	WB_BUF_MODE_LU_DEDICATED	= 0x0,
317*4882a593Smuzhiyun 	WB_BUF_MODE_SHARED		= 0x1,
318*4882a593Smuzhiyun };
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun /*
321*4882a593Smuzhiyun  * Logical Unit Write Protect
322*4882a593Smuzhiyun  * 00h: LU not write protected
323*4882a593Smuzhiyun  * 01h: LU write protected when fPowerOnWPEn =1
324*4882a593Smuzhiyun  * 02h: LU permanently write protected when fPermanentWPEn =1
325*4882a593Smuzhiyun  */
326*4882a593Smuzhiyun enum ufs_lu_wp_type {
327*4882a593Smuzhiyun 	UFS_LU_NO_WP		= 0x00,
328*4882a593Smuzhiyun 	UFS_LU_POWER_ON_WP	= 0x01,
329*4882a593Smuzhiyun 	UFS_LU_PERM_WP		= 0x02,
330*4882a593Smuzhiyun };
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun /* bActiveICCLevel parameter current units */
333*4882a593Smuzhiyun enum {
334*4882a593Smuzhiyun 	UFSHCD_NANO_AMP		= 0,
335*4882a593Smuzhiyun 	UFSHCD_MICRO_AMP	= 1,
336*4882a593Smuzhiyun 	UFSHCD_MILI_AMP		= 2,
337*4882a593Smuzhiyun 	UFSHCD_AMP		= 3,
338*4882a593Smuzhiyun };
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun /* Possible values for dExtendedUFSFeaturesSupport */
341*4882a593Smuzhiyun enum {
342*4882a593Smuzhiyun 	UFS_DEV_HPB_SUPPORT		= BIT(7),
343*4882a593Smuzhiyun 	UFS_DEV_WRITE_BOOSTER_SUP	= BIT(8),
344*4882a593Smuzhiyun };
345*4882a593Smuzhiyun #define UFS_DEV_HPB_SUPPORT_VERSION		0x310
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun #define POWER_DESC_MAX_SIZE			0x62
348*4882a593Smuzhiyun #define POWER_DESC_MAX_ACTV_ICC_LVLS		16
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun /* Attribute  bActiveICCLevel parameter bit masks definitions */
351*4882a593Smuzhiyun #define ATTR_ICC_LVL_UNIT_OFFSET	14
352*4882a593Smuzhiyun #define ATTR_ICC_LVL_UNIT_MASK		(0x3 << ATTR_ICC_LVL_UNIT_OFFSET)
353*4882a593Smuzhiyun #define ATTR_ICC_LVL_VALUE_MASK		0x3FF
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun /* Power descriptor parameters offsets in bytes */
356*4882a593Smuzhiyun enum power_desc_param_offset {
357*4882a593Smuzhiyun 	PWR_DESC_LEN			= 0x0,
358*4882a593Smuzhiyun 	PWR_DESC_TYPE			= 0x1,
359*4882a593Smuzhiyun 	PWR_DESC_ACTIVE_LVLS_VCC_0	= 0x2,
360*4882a593Smuzhiyun 	PWR_DESC_ACTIVE_LVLS_VCCQ_0	= 0x22,
361*4882a593Smuzhiyun 	PWR_DESC_ACTIVE_LVLS_VCCQ2_0	= 0x42,
362*4882a593Smuzhiyun };
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun /* Exception event mask values */
365*4882a593Smuzhiyun enum {
366*4882a593Smuzhiyun 	MASK_EE_STATUS		= 0xFFFF,
367*4882a593Smuzhiyun 	MASK_EE_URGENT_BKOPS	= (1 << 2),
368*4882a593Smuzhiyun };
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun /* Background operation status */
371*4882a593Smuzhiyun enum bkops_status {
372*4882a593Smuzhiyun 	BKOPS_STATUS_NO_OP               = 0x0,
373*4882a593Smuzhiyun 	BKOPS_STATUS_NON_CRITICAL        = 0x1,
374*4882a593Smuzhiyun 	BKOPS_STATUS_PERF_IMPACT         = 0x2,
375*4882a593Smuzhiyun 	BKOPS_STATUS_CRITICAL            = 0x3,
376*4882a593Smuzhiyun 	BKOPS_STATUS_MAX		 = BKOPS_STATUS_CRITICAL,
377*4882a593Smuzhiyun };
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun /* UTP QUERY Transaction Specific Fields OpCode */
380*4882a593Smuzhiyun enum query_opcode {
381*4882a593Smuzhiyun 	UPIU_QUERY_OPCODE_NOP		= 0x0,
382*4882a593Smuzhiyun 	UPIU_QUERY_OPCODE_READ_DESC	= 0x1,
383*4882a593Smuzhiyun 	UPIU_QUERY_OPCODE_WRITE_DESC	= 0x2,
384*4882a593Smuzhiyun 	UPIU_QUERY_OPCODE_READ_ATTR	= 0x3,
385*4882a593Smuzhiyun 	UPIU_QUERY_OPCODE_WRITE_ATTR	= 0x4,
386*4882a593Smuzhiyun 	UPIU_QUERY_OPCODE_READ_FLAG	= 0x5,
387*4882a593Smuzhiyun 	UPIU_QUERY_OPCODE_SET_FLAG	= 0x6,
388*4882a593Smuzhiyun 	UPIU_QUERY_OPCODE_CLEAR_FLAG	= 0x7,
389*4882a593Smuzhiyun 	UPIU_QUERY_OPCODE_TOGGLE_FLAG	= 0x8,
390*4882a593Smuzhiyun };
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun /* bRefClkFreq attribute values */
393*4882a593Smuzhiyun enum ufs_ref_clk_freq {
394*4882a593Smuzhiyun 	REF_CLK_FREQ_19_2_MHZ	= 0,
395*4882a593Smuzhiyun 	REF_CLK_FREQ_26_MHZ	= 1,
396*4882a593Smuzhiyun 	REF_CLK_FREQ_38_4_MHZ	= 2,
397*4882a593Smuzhiyun 	REF_CLK_FREQ_52_MHZ	= 3,
398*4882a593Smuzhiyun 	REF_CLK_FREQ_INVAL	= -1,
399*4882a593Smuzhiyun };
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun struct ufs_ref_clk {
402*4882a593Smuzhiyun 	unsigned long freq_hz;
403*4882a593Smuzhiyun 	enum ufs_ref_clk_freq val;
404*4882a593Smuzhiyun };
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun /* Query response result code */
407*4882a593Smuzhiyun enum {
408*4882a593Smuzhiyun 	QUERY_RESULT_SUCCESS                    = 0x00,
409*4882a593Smuzhiyun 	QUERY_RESULT_NOT_READABLE               = 0xF6,
410*4882a593Smuzhiyun 	QUERY_RESULT_NOT_WRITEABLE              = 0xF7,
411*4882a593Smuzhiyun 	QUERY_RESULT_ALREADY_WRITTEN            = 0xF8,
412*4882a593Smuzhiyun 	QUERY_RESULT_INVALID_LENGTH             = 0xF9,
413*4882a593Smuzhiyun 	QUERY_RESULT_INVALID_VALUE              = 0xFA,
414*4882a593Smuzhiyun 	QUERY_RESULT_INVALID_SELECTOR           = 0xFB,
415*4882a593Smuzhiyun 	QUERY_RESULT_INVALID_INDEX              = 0xFC,
416*4882a593Smuzhiyun 	QUERY_RESULT_INVALID_IDN                = 0xFD,
417*4882a593Smuzhiyun 	QUERY_RESULT_INVALID_OPCODE             = 0xFE,
418*4882a593Smuzhiyun 	QUERY_RESULT_GENERAL_FAILURE            = 0xFF,
419*4882a593Smuzhiyun };
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun /* UTP Transfer Request Command Type (CT) */
422*4882a593Smuzhiyun enum {
423*4882a593Smuzhiyun 	UPIU_COMMAND_SET_TYPE_SCSI	= 0x0,
424*4882a593Smuzhiyun 	UPIU_COMMAND_SET_TYPE_UFS	= 0x1,
425*4882a593Smuzhiyun 	UPIU_COMMAND_SET_TYPE_QUERY	= 0x2,
426*4882a593Smuzhiyun };
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun /* UTP Transfer Request Command Offset */
429*4882a593Smuzhiyun #define UPIU_COMMAND_TYPE_OFFSET	28
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun /* Offset of the response code in the UPIU header */
432*4882a593Smuzhiyun #define UPIU_RSP_CODE_OFFSET		8
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun enum {
435*4882a593Smuzhiyun 	MASK_SCSI_STATUS		= 0xFF,
436*4882a593Smuzhiyun 	MASK_TASK_RESPONSE              = 0xFF00,
437*4882a593Smuzhiyun 	MASK_RSP_UPIU_RESULT            = 0xFFFF,
438*4882a593Smuzhiyun 	MASK_QUERY_DATA_SEG_LEN         = 0xFFFF,
439*4882a593Smuzhiyun 	MASK_RSP_UPIU_DATA_SEG_LEN	= 0xFFFF,
440*4882a593Smuzhiyun 	MASK_RSP_EXCEPTION_EVENT        = 0x10000,
441*4882a593Smuzhiyun 	MASK_TM_SERVICE_RESP		= 0xFF,
442*4882a593Smuzhiyun 	MASK_TM_FUNC			= 0xFF,
443*4882a593Smuzhiyun };
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun /* Task management service response */
446*4882a593Smuzhiyun enum {
447*4882a593Smuzhiyun 	UPIU_TASK_MANAGEMENT_FUNC_COMPL		= 0x00,
448*4882a593Smuzhiyun 	UPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTED = 0x04,
449*4882a593Smuzhiyun 	UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED	= 0x08,
450*4882a593Smuzhiyun 	UPIU_TASK_MANAGEMENT_FUNC_FAILED	= 0x05,
451*4882a593Smuzhiyun 	UPIU_INCORRECT_LOGICAL_UNIT_NO		= 0x09,
452*4882a593Smuzhiyun };
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun /* UFS device power modes */
455*4882a593Smuzhiyun enum ufs_dev_pwr_mode {
456*4882a593Smuzhiyun 	UFS_ACTIVE_PWR_MODE	= 1,
457*4882a593Smuzhiyun 	UFS_SLEEP_PWR_MODE	= 2,
458*4882a593Smuzhiyun 	UFS_POWERDOWN_PWR_MODE	= 3,
459*4882a593Smuzhiyun };
460*4882a593Smuzhiyun 
461*4882a593Smuzhiyun #define UFS_WB_BUF_REMAIN_PERCENT(val) ((val) / 10)
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun /**
464*4882a593Smuzhiyun  * struct utp_cmd_rsp - Response UPIU structure
465*4882a593Smuzhiyun  * @residual_transfer_count: Residual transfer count DW-3
466*4882a593Smuzhiyun  * @reserved: Reserved double words DW-4 to DW-7
467*4882a593Smuzhiyun  * @sense_data_len: Sense data length DW-8 U16
468*4882a593Smuzhiyun  * @sense_data: Sense data field DW-8 to DW-12
469*4882a593Smuzhiyun  */
470*4882a593Smuzhiyun struct utp_cmd_rsp {
471*4882a593Smuzhiyun 	__be32 residual_transfer_count;
472*4882a593Smuzhiyun 	__be32 reserved[4];
473*4882a593Smuzhiyun 	__be16 sense_data_len;
474*4882a593Smuzhiyun 	u8 sense_data[UFS_SENSE_SIZE];
475*4882a593Smuzhiyun };
476*4882a593Smuzhiyun 
477*4882a593Smuzhiyun struct ufshpb_active_field {
478*4882a593Smuzhiyun 	__be16 active_rgn;
479*4882a593Smuzhiyun 	__be16 active_srgn;
480*4882a593Smuzhiyun };
481*4882a593Smuzhiyun #define HPB_ACT_FIELD_SIZE 4
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun /**
484*4882a593Smuzhiyun  * struct utp_hpb_rsp - Response UPIU structure
485*4882a593Smuzhiyun  * @residual_transfer_count: Residual transfer count DW-3
486*4882a593Smuzhiyun  * @reserved1: Reserved double words DW-4 to DW-7
487*4882a593Smuzhiyun  * @sense_data_len: Sense data length DW-8 U16
488*4882a593Smuzhiyun  * @desc_type: Descriptor type of sense data
489*4882a593Smuzhiyun  * @additional_len: Additional length of sense data
490*4882a593Smuzhiyun  * @hpb_op: HPB operation type
491*4882a593Smuzhiyun  * @lun: LUN of response UPIU
492*4882a593Smuzhiyun  * @active_rgn_cnt: Active region count
493*4882a593Smuzhiyun  * @inactive_rgn_cnt: Inactive region count
494*4882a593Smuzhiyun  * @hpb_active_field: Recommended to read HPB region and subregion
495*4882a593Smuzhiyun  * @hpb_inactive_field: To be inactivated HPB region and subregion
496*4882a593Smuzhiyun  */
497*4882a593Smuzhiyun struct utp_hpb_rsp {
498*4882a593Smuzhiyun 	__be32 residual_transfer_count;
499*4882a593Smuzhiyun 	__be32 reserved1[4];
500*4882a593Smuzhiyun 	__be16 sense_data_len;
501*4882a593Smuzhiyun 	u8 desc_type;
502*4882a593Smuzhiyun 	u8 additional_len;
503*4882a593Smuzhiyun 	u8 hpb_op;
504*4882a593Smuzhiyun 	u8 lun;
505*4882a593Smuzhiyun 	u8 active_rgn_cnt;
506*4882a593Smuzhiyun 	u8 inactive_rgn_cnt;
507*4882a593Smuzhiyun 	struct ufshpb_active_field hpb_active_field[2];
508*4882a593Smuzhiyun 	__be16 hpb_inactive_field[2];
509*4882a593Smuzhiyun };
510*4882a593Smuzhiyun #define UTP_HPB_RSP_SIZE 40
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun /**
513*4882a593Smuzhiyun  * struct utp_upiu_rsp - general upiu response structure
514*4882a593Smuzhiyun  * @header: UPIU header structure DW-0 to DW-2
515*4882a593Smuzhiyun  * @sr: fields structure for scsi command DW-3 to DW-12
516*4882a593Smuzhiyun  * @qr: fields structure for query request DW-3 to DW-7
517*4882a593Smuzhiyun  */
518*4882a593Smuzhiyun struct utp_upiu_rsp {
519*4882a593Smuzhiyun 	struct utp_upiu_header header;
520*4882a593Smuzhiyun 	union {
521*4882a593Smuzhiyun 		struct utp_cmd_rsp sr;
522*4882a593Smuzhiyun 		struct utp_hpb_rsp hr;
523*4882a593Smuzhiyun 		struct utp_upiu_query qr;
524*4882a593Smuzhiyun 	};
525*4882a593Smuzhiyun };
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun /**
528*4882a593Smuzhiyun  * struct ufs_query_req - parameters for building a query request
529*4882a593Smuzhiyun  * @query_func: UPIU header query function
530*4882a593Smuzhiyun  * @upiu_req: the query request data
531*4882a593Smuzhiyun  */
532*4882a593Smuzhiyun struct ufs_query_req {
533*4882a593Smuzhiyun 	u8 query_func;
534*4882a593Smuzhiyun 	struct utp_upiu_query upiu_req;
535*4882a593Smuzhiyun };
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun /**
538*4882a593Smuzhiyun  * struct ufs_query_resp - UPIU QUERY
539*4882a593Smuzhiyun  * @response: device response code
540*4882a593Smuzhiyun  * @upiu_res: query response data
541*4882a593Smuzhiyun  */
542*4882a593Smuzhiyun struct ufs_query_res {
543*4882a593Smuzhiyun 	u8 response;
544*4882a593Smuzhiyun 	struct utp_upiu_query upiu_res;
545*4882a593Smuzhiyun };
546*4882a593Smuzhiyun 
547*4882a593Smuzhiyun #define UFS_VREG_VCC_MIN_UV	   2700000 /* uV */
548*4882a593Smuzhiyun #define UFS_VREG_VCC_MAX_UV	   3600000 /* uV */
549*4882a593Smuzhiyun #define UFS_VREG_VCC_1P8_MIN_UV    1700000 /* uV */
550*4882a593Smuzhiyun #define UFS_VREG_VCC_1P8_MAX_UV    1950000 /* uV */
551*4882a593Smuzhiyun #define UFS_VREG_VCCQ_MIN_UV	   1140000 /* uV */
552*4882a593Smuzhiyun #define UFS_VREG_VCCQ_MAX_UV	   1260000 /* uV */
553*4882a593Smuzhiyun #define UFS_VREG_VCCQ2_MIN_UV	   1700000 /* uV */
554*4882a593Smuzhiyun #define UFS_VREG_VCCQ2_MAX_UV	   1950000 /* uV */
555*4882a593Smuzhiyun 
556*4882a593Smuzhiyun /*
557*4882a593Smuzhiyun  * VCCQ & VCCQ2 current requirement when UFS device is in sleep state
558*4882a593Smuzhiyun  * and link is in Hibern8 state.
559*4882a593Smuzhiyun  */
560*4882a593Smuzhiyun #define UFS_VREG_LPM_LOAD_UA	1000 /* uA */
561*4882a593Smuzhiyun 
562*4882a593Smuzhiyun struct ufs_vreg {
563*4882a593Smuzhiyun 	struct regulator *reg;
564*4882a593Smuzhiyun 	const char *name;
565*4882a593Smuzhiyun 	bool always_on;
566*4882a593Smuzhiyun 	bool enabled;
567*4882a593Smuzhiyun 	int min_uV;
568*4882a593Smuzhiyun 	int max_uV;
569*4882a593Smuzhiyun 	int max_uA;
570*4882a593Smuzhiyun };
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun struct ufs_vreg_info {
573*4882a593Smuzhiyun 	struct ufs_vreg *vcc;
574*4882a593Smuzhiyun 	struct ufs_vreg *vccq;
575*4882a593Smuzhiyun 	struct ufs_vreg *vccq2;
576*4882a593Smuzhiyun 	struct ufs_vreg *vdd_hba;
577*4882a593Smuzhiyun };
578*4882a593Smuzhiyun 
579*4882a593Smuzhiyun struct ufs_dev_info {
580*4882a593Smuzhiyun 	bool f_power_on_wp_en;
581*4882a593Smuzhiyun 	/* Keeps information if any of the LU is power on write protected */
582*4882a593Smuzhiyun 	bool is_lu_power_on_wp;
583*4882a593Smuzhiyun 	/* Maximum number of general LU supported by the UFS device */
584*4882a593Smuzhiyun 	u8 max_lu_supported;
585*4882a593Smuzhiyun 	u8 wb_dedicated_lu;
586*4882a593Smuzhiyun 	u16 wmanufacturerid;
587*4882a593Smuzhiyun 	/*UFS device Product Name */
588*4882a593Smuzhiyun 	u8 *model;
589*4882a593Smuzhiyun 	u16 wspecversion;
590*4882a593Smuzhiyun 	u32 clk_gating_wait_us;
591*4882a593Smuzhiyun 	u32 d_ext_ufs_feature_sup;
592*4882a593Smuzhiyun 	u8 b_wb_buffer_type;
593*4882a593Smuzhiyun 	u32 d_wb_alloc_units;
594*4882a593Smuzhiyun 	bool b_rpm_dev_flush_capable;
595*4882a593Smuzhiyun 	u8 b_presrv_uspc_en;
596*4882a593Smuzhiyun 	/* UFS HPB related flag */
597*4882a593Smuzhiyun 	bool	hpb_enabled;
598*4882a593Smuzhiyun 	ANDROID_KABI_RESERVE(1);
599*4882a593Smuzhiyun };
600*4882a593Smuzhiyun 
601*4882a593Smuzhiyun /**
602*4882a593Smuzhiyun  * ufs_is_valid_unit_desc_lun - checks if the given LUN has a unit descriptor
603*4882a593Smuzhiyun  * @dev_info: pointer of instance of struct ufs_dev_info
604*4882a593Smuzhiyun  * @lun: LU number to check
605*4882a593Smuzhiyun  * @return: true if the lun has a matching unit descriptor, false otherwise
606*4882a593Smuzhiyun  */
ufs_is_valid_unit_desc_lun(struct ufs_dev_info * dev_info,u8 lun,u8 param_offset)607*4882a593Smuzhiyun static inline bool ufs_is_valid_unit_desc_lun(struct ufs_dev_info *dev_info,
608*4882a593Smuzhiyun 		u8 lun, u8 param_offset)
609*4882a593Smuzhiyun {
610*4882a593Smuzhiyun 	if (!dev_info || !dev_info->max_lu_supported) {
611*4882a593Smuzhiyun 		pr_err("Max General LU supported by UFS isn't initialized\n");
612*4882a593Smuzhiyun 		return false;
613*4882a593Smuzhiyun 	}
614*4882a593Smuzhiyun 	/* WB is available only for the logical unit from 0 to 7 */
615*4882a593Smuzhiyun 	if (param_offset == UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS)
616*4882a593Smuzhiyun 		return lun < UFS_UPIU_MAX_WB_LUN_ID;
617*4882a593Smuzhiyun 	return lun == UFS_UPIU_RPMB_WLUN || (lun < dev_info->max_lu_supported);
618*4882a593Smuzhiyun }
619*4882a593Smuzhiyun 
620*4882a593Smuzhiyun #endif /* End of Header */
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