1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2017, HiSilicon. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef UFS_HISI_H_ 7*4882a593Smuzhiyun #define UFS_HISI_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define HBRN8_POLL_TOUT_MS 1000 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * ufs sysctrl specific define 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun #define PSW_POWER_CTRL (0x04) 15*4882a593Smuzhiyun #define PHY_ISO_EN (0x08) 16*4882a593Smuzhiyun #define HC_LP_CTRL (0x0C) 17*4882a593Smuzhiyun #define PHY_CLK_CTRL (0x10) 18*4882a593Smuzhiyun #define PSW_CLK_CTRL (0x14) 19*4882a593Smuzhiyun #define CLOCK_GATE_BYPASS (0x18) 20*4882a593Smuzhiyun #define RESET_CTRL_EN (0x1C) 21*4882a593Smuzhiyun #define UFS_SYSCTRL (0x5C) 22*4882a593Smuzhiyun #define UFS_DEVICE_RESET_CTRL (0x60) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define BIT_UFS_PSW_ISO_CTRL (1 << 16) 25*4882a593Smuzhiyun #define BIT_UFS_PSW_MTCMOS_EN (1 << 0) 26*4882a593Smuzhiyun #define BIT_UFS_REFCLK_ISO_EN (1 << 16) 27*4882a593Smuzhiyun #define BIT_UFS_PHY_ISO_CTRL (1 << 0) 28*4882a593Smuzhiyun #define BIT_SYSCTRL_LP_ISOL_EN (1 << 16) 29*4882a593Smuzhiyun #define BIT_SYSCTRL_PWR_READY (1 << 8) 30*4882a593Smuzhiyun #define BIT_SYSCTRL_REF_CLOCK_EN (1 << 24) 31*4882a593Smuzhiyun #define MASK_SYSCTRL_REF_CLOCK_SEL (0x3 << 8) 32*4882a593Smuzhiyun #define MASK_SYSCTRL_CFG_CLOCK_FREQ (0xFF) 33*4882a593Smuzhiyun #define UFS_FREQ_CFG_CLK (0x39) 34*4882a593Smuzhiyun #define BIT_SYSCTRL_PSW_CLK_EN (1 << 4) 35*4882a593Smuzhiyun #define MASK_UFS_CLK_GATE_BYPASS (0x3F) 36*4882a593Smuzhiyun #define BIT_SYSCTRL_LP_RESET_N (1 << 0) 37*4882a593Smuzhiyun #define BIT_UFS_REFCLK_SRC_SEl (1 << 0) 38*4882a593Smuzhiyun #define MASK_UFS_SYSCRTL_BYPASS (0x3F << 16) 39*4882a593Smuzhiyun #define MASK_UFS_DEVICE_RESET (0x1 << 16) 40*4882a593Smuzhiyun #define BIT_UFS_DEVICE_RESET (0x1) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* 43*4882a593Smuzhiyun * M-TX Configuration Attributes for Hixxxx 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun #define MPHY_TX_FSM_STATE 0x41 46*4882a593Smuzhiyun #define TX_FSM_HIBERN8 0x1 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * Hixxxx UFS HC specific Registers 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun enum { 52*4882a593Smuzhiyun UFS_REG_OCPTHRTL = 0xc0, 53*4882a593Smuzhiyun UFS_REG_OOCPR = 0xc4, 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun UFS_REG_CDACFG = 0xd0, 56*4882a593Smuzhiyun UFS_REG_CDATX1 = 0xd4, 57*4882a593Smuzhiyun UFS_REG_CDATX2 = 0xd8, 58*4882a593Smuzhiyun UFS_REG_CDARX1 = 0xdc, 59*4882a593Smuzhiyun UFS_REG_CDARX2 = 0xe0, 60*4882a593Smuzhiyun UFS_REG_CDASTA = 0xe4, 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun UFS_REG_LBMCFG = 0xf0, 63*4882a593Smuzhiyun UFS_REG_LBMSTA = 0xf4, 64*4882a593Smuzhiyun UFS_REG_UFSMODE = 0xf8, 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun UFS_REG_HCLKDIV = 0xfc, 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* AHIT - Auto-Hibernate Idle Timer */ 70*4882a593Smuzhiyun #define UFS_AHIT_AH8ITV_MASK 0x3FF 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* REG UFS_REG_OCPTHRTL definition */ 73*4882a593Smuzhiyun #define UFS_HCLKDIV_NORMAL_VALUE 0xE4 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* vendor specific pre-defined parameters */ 76*4882a593Smuzhiyun #define SLOW 1 77*4882a593Smuzhiyun #define FAST 2 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define UFS_HISI_LIMIT_NUM_LANES_RX 2 80*4882a593Smuzhiyun #define UFS_HISI_LIMIT_NUM_LANES_TX 2 81*4882a593Smuzhiyun #define UFS_HISI_LIMIT_HSGEAR_RX UFS_HS_G3 82*4882a593Smuzhiyun #define UFS_HISI_LIMIT_HSGEAR_TX UFS_HS_G3 83*4882a593Smuzhiyun #define UFS_HISI_LIMIT_PWMGEAR_RX UFS_PWM_G4 84*4882a593Smuzhiyun #define UFS_HISI_LIMIT_PWMGEAR_TX UFS_PWM_G4 85*4882a593Smuzhiyun #define UFS_HISI_LIMIT_RX_PWR_PWM SLOW_MODE 86*4882a593Smuzhiyun #define UFS_HISI_LIMIT_TX_PWR_PWM SLOW_MODE 87*4882a593Smuzhiyun #define UFS_HISI_LIMIT_RX_PWR_HS FAST_MODE 88*4882a593Smuzhiyun #define UFS_HISI_LIMIT_TX_PWR_HS FAST_MODE 89*4882a593Smuzhiyun #define UFS_HISI_LIMIT_HS_RATE PA_HS_MODE_B 90*4882a593Smuzhiyun #define UFS_HISI_LIMIT_DESIRED_MODE FAST 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define UFS_HISI_CAP_RESERVED BIT(0) 93*4882a593Smuzhiyun #define UFS_HISI_CAP_PHY10nm BIT(1) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun struct ufs_hisi_host { 96*4882a593Smuzhiyun struct ufs_hba *hba; 97*4882a593Smuzhiyun void __iomem *ufs_sys_ctrl; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun struct reset_control *rst; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun uint64_t caps; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun bool in_suspend; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define ufs_sys_ctrl_writel(host, val, reg) \ 107*4882a593Smuzhiyun writel((val), (host)->ufs_sys_ctrl + (reg)) 108*4882a593Smuzhiyun #define ufs_sys_ctrl_readl(host, reg) readl((host)->ufs_sys_ctrl + (reg)) 109*4882a593Smuzhiyun #define ufs_sys_ctrl_set_bits(host, mask, reg) \ 110*4882a593Smuzhiyun ufs_sys_ctrl_writel( \ 111*4882a593Smuzhiyun (host), ((mask) | (ufs_sys_ctrl_readl((host), (reg)))), (reg)) 112*4882a593Smuzhiyun #define ufs_sys_ctrl_clr_bits(host, mask, reg) \ 113*4882a593Smuzhiyun ufs_sys_ctrl_writel((host), \ 114*4882a593Smuzhiyun ((~(mask)) & (ufs_sys_ctrl_readl((host), (reg)))), \ 115*4882a593Smuzhiyun (reg)) 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #endif /* UFS_HISI_H_ */ 118