1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /* sun3x_esp.c: ESP front-end for Sun3x systems.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2007,2008 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/kernel.h>
8*4882a593Smuzhiyun #include <linux/gfp.h>
9*4882a593Smuzhiyun #include <linux/types.h>
10*4882a593Smuzhiyun #include <linux/delay.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/dma-mapping.h>
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/io.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <asm/sun3x.h>
19*4882a593Smuzhiyun #include <asm/dma.h>
20*4882a593Smuzhiyun #include <asm/dvma.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* DMA controller reg offsets */
23*4882a593Smuzhiyun #define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
24*4882a593Smuzhiyun #define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
25*4882a593Smuzhiyun #define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
26*4882a593Smuzhiyun #define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #include <scsi/scsi_host.h>
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #include "esp_scsi.h"
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define DRV_MODULE_NAME "sun3x_esp"
33*4882a593Smuzhiyun #define PFX DRV_MODULE_NAME ": "
34*4882a593Smuzhiyun #define DRV_VERSION "1.000"
35*4882a593Smuzhiyun #define DRV_MODULE_RELDATE "Nov 1, 2007"
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /*
38*4882a593Smuzhiyun * m68k always assumes readl/writel operate on little endian
39*4882a593Smuzhiyun * mmio space; this is wrong at least for Sun3x, so we
40*4882a593Smuzhiyun * need to workaround this until a proper way is found
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun #if 0
43*4882a593Smuzhiyun #define dma_read32(REG) \
44*4882a593Smuzhiyun readl(esp->dma_regs + (REG))
45*4882a593Smuzhiyun #define dma_write32(VAL, REG) \
46*4882a593Smuzhiyun writel((VAL), esp->dma_regs + (REG))
47*4882a593Smuzhiyun #else
48*4882a593Smuzhiyun #define dma_read32(REG) \
49*4882a593Smuzhiyun *(volatile u32 *)(esp->dma_regs + (REG))
50*4882a593Smuzhiyun #define dma_write32(VAL, REG) \
51*4882a593Smuzhiyun do { *(volatile u32 *)(esp->dma_regs + (REG)) = (VAL); } while (0)
52*4882a593Smuzhiyun #endif
53*4882a593Smuzhiyun
sun3x_esp_write8(struct esp * esp,u8 val,unsigned long reg)54*4882a593Smuzhiyun static void sun3x_esp_write8(struct esp *esp, u8 val, unsigned long reg)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun writeb(val, esp->regs + (reg * 4UL));
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
sun3x_esp_read8(struct esp * esp,unsigned long reg)59*4882a593Smuzhiyun static u8 sun3x_esp_read8(struct esp *esp, unsigned long reg)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun return readb(esp->regs + (reg * 4UL));
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
sun3x_esp_irq_pending(struct esp * esp)64*4882a593Smuzhiyun static int sun3x_esp_irq_pending(struct esp *esp)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
67*4882a593Smuzhiyun return 1;
68*4882a593Smuzhiyun return 0;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
sun3x_esp_reset_dma(struct esp * esp)71*4882a593Smuzhiyun static void sun3x_esp_reset_dma(struct esp *esp)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun u32 val;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun val = dma_read32(DMA_CSR);
76*4882a593Smuzhiyun dma_write32(val | DMA_RST_SCSI, DMA_CSR);
77*4882a593Smuzhiyun dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /* Enable interrupts. */
80*4882a593Smuzhiyun val = dma_read32(DMA_CSR);
81*4882a593Smuzhiyun dma_write32(val | DMA_INT_ENAB, DMA_CSR);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
sun3x_esp_dma_drain(struct esp * esp)84*4882a593Smuzhiyun static void sun3x_esp_dma_drain(struct esp *esp)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun u32 csr;
87*4882a593Smuzhiyun int lim;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun csr = dma_read32(DMA_CSR);
90*4882a593Smuzhiyun if (!(csr & DMA_FIFO_ISDRAIN))
91*4882a593Smuzhiyun return;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun lim = 1000;
96*4882a593Smuzhiyun while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
97*4882a593Smuzhiyun if (--lim == 0) {
98*4882a593Smuzhiyun printk(KERN_ALERT PFX "esp%d: DMA will not drain!\n",
99*4882a593Smuzhiyun esp->host->unique_id);
100*4882a593Smuzhiyun break;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun udelay(1);
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
sun3x_esp_dma_invalidate(struct esp * esp)106*4882a593Smuzhiyun static void sun3x_esp_dma_invalidate(struct esp *esp)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun u32 val;
109*4882a593Smuzhiyun int lim;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun lim = 1000;
112*4882a593Smuzhiyun while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
113*4882a593Smuzhiyun if (--lim == 0) {
114*4882a593Smuzhiyun printk(KERN_ALERT PFX "esp%d: DMA will not "
115*4882a593Smuzhiyun "invalidate!\n", esp->host->unique_id);
116*4882a593Smuzhiyun break;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun udelay(1);
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun val &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB);
122*4882a593Smuzhiyun val |= DMA_FIFO_INV;
123*4882a593Smuzhiyun dma_write32(val, DMA_CSR);
124*4882a593Smuzhiyun val &= ~DMA_FIFO_INV;
125*4882a593Smuzhiyun dma_write32(val, DMA_CSR);
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
sun3x_esp_send_dma_cmd(struct esp * esp,u32 addr,u32 esp_count,u32 dma_count,int write,u8 cmd)128*4882a593Smuzhiyun static void sun3x_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
129*4882a593Smuzhiyun u32 dma_count, int write, u8 cmd)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun u32 csr;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun BUG_ON(!(cmd & ESP_CMD_DMA));
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun sun3x_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
136*4882a593Smuzhiyun sun3x_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
137*4882a593Smuzhiyun csr = dma_read32(DMA_CSR);
138*4882a593Smuzhiyun csr |= DMA_ENABLE;
139*4882a593Smuzhiyun if (write)
140*4882a593Smuzhiyun csr |= DMA_ST_WRITE;
141*4882a593Smuzhiyun else
142*4882a593Smuzhiyun csr &= ~DMA_ST_WRITE;
143*4882a593Smuzhiyun dma_write32(csr, DMA_CSR);
144*4882a593Smuzhiyun dma_write32(addr, DMA_ADDR);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun scsi_esp_cmd(esp, cmd);
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
sun3x_esp_dma_error(struct esp * esp)149*4882a593Smuzhiyun static int sun3x_esp_dma_error(struct esp *esp)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun u32 csr = dma_read32(DMA_CSR);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun if (csr & DMA_HNDL_ERROR)
154*4882a593Smuzhiyun return 1;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun return 0;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun static const struct esp_driver_ops sun3x_esp_ops = {
160*4882a593Smuzhiyun .esp_write8 = sun3x_esp_write8,
161*4882a593Smuzhiyun .esp_read8 = sun3x_esp_read8,
162*4882a593Smuzhiyun .irq_pending = sun3x_esp_irq_pending,
163*4882a593Smuzhiyun .reset_dma = sun3x_esp_reset_dma,
164*4882a593Smuzhiyun .dma_drain = sun3x_esp_dma_drain,
165*4882a593Smuzhiyun .dma_invalidate = sun3x_esp_dma_invalidate,
166*4882a593Smuzhiyun .send_dma_cmd = sun3x_esp_send_dma_cmd,
167*4882a593Smuzhiyun .dma_error = sun3x_esp_dma_error,
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun
esp_sun3x_probe(struct platform_device * dev)170*4882a593Smuzhiyun static int esp_sun3x_probe(struct platform_device *dev)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun struct scsi_host_template *tpnt = &scsi_esp_template;
173*4882a593Smuzhiyun struct Scsi_Host *host;
174*4882a593Smuzhiyun struct esp *esp;
175*4882a593Smuzhiyun struct resource *res;
176*4882a593Smuzhiyun int err = -ENOMEM;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun host = scsi_host_alloc(tpnt, sizeof(struct esp));
179*4882a593Smuzhiyun if (!host)
180*4882a593Smuzhiyun goto fail;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun host->max_id = 8;
183*4882a593Smuzhiyun esp = shost_priv(host);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun esp->host = host;
186*4882a593Smuzhiyun esp->dev = &dev->dev;
187*4882a593Smuzhiyun esp->ops = &sun3x_esp_ops;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun res = platform_get_resource(dev, IORESOURCE_MEM, 0);
190*4882a593Smuzhiyun if (!res || !res->start)
191*4882a593Smuzhiyun goto fail_unlink;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun esp->regs = ioremap(res->start, 0x20);
194*4882a593Smuzhiyun if (!esp->regs)
195*4882a593Smuzhiyun goto fail_unmap_regs;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun res = platform_get_resource(dev, IORESOURCE_MEM, 1);
198*4882a593Smuzhiyun if (!res || !res->start)
199*4882a593Smuzhiyun goto fail_unmap_regs;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun esp->dma_regs = ioremap(res->start, 0x10);
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun esp->command_block = dma_alloc_coherent(esp->dev, 16,
204*4882a593Smuzhiyun &esp->command_block_dma,
205*4882a593Smuzhiyun GFP_KERNEL);
206*4882a593Smuzhiyun if (!esp->command_block)
207*4882a593Smuzhiyun goto fail_unmap_regs_dma;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun host->irq = err = platform_get_irq(dev, 0);
210*4882a593Smuzhiyun if (err < 0)
211*4882a593Smuzhiyun goto fail_unmap_command_block;
212*4882a593Smuzhiyun err = request_irq(host->irq, scsi_esp_intr, IRQF_SHARED,
213*4882a593Smuzhiyun "SUN3X ESP", esp);
214*4882a593Smuzhiyun if (err < 0)
215*4882a593Smuzhiyun goto fail_unmap_command_block;
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun esp->scsi_id = 7;
218*4882a593Smuzhiyun esp->host->this_id = esp->scsi_id;
219*4882a593Smuzhiyun esp->scsi_id_mask = (1 << esp->scsi_id);
220*4882a593Smuzhiyun esp->cfreq = 20000000;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun dev_set_drvdata(&dev->dev, esp);
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun err = scsi_esp_register(esp);
225*4882a593Smuzhiyun if (err)
226*4882a593Smuzhiyun goto fail_free_irq;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun return 0;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun fail_free_irq:
231*4882a593Smuzhiyun free_irq(host->irq, esp);
232*4882a593Smuzhiyun fail_unmap_command_block:
233*4882a593Smuzhiyun dma_free_coherent(esp->dev, 16,
234*4882a593Smuzhiyun esp->command_block,
235*4882a593Smuzhiyun esp->command_block_dma);
236*4882a593Smuzhiyun fail_unmap_regs_dma:
237*4882a593Smuzhiyun iounmap(esp->dma_regs);
238*4882a593Smuzhiyun fail_unmap_regs:
239*4882a593Smuzhiyun iounmap(esp->regs);
240*4882a593Smuzhiyun fail_unlink:
241*4882a593Smuzhiyun scsi_host_put(host);
242*4882a593Smuzhiyun fail:
243*4882a593Smuzhiyun return err;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun
esp_sun3x_remove(struct platform_device * dev)246*4882a593Smuzhiyun static int esp_sun3x_remove(struct platform_device *dev)
247*4882a593Smuzhiyun {
248*4882a593Smuzhiyun struct esp *esp = dev_get_drvdata(&dev->dev);
249*4882a593Smuzhiyun unsigned int irq = esp->host->irq;
250*4882a593Smuzhiyun u32 val;
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun scsi_esp_unregister(esp);
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun /* Disable interrupts. */
255*4882a593Smuzhiyun val = dma_read32(DMA_CSR);
256*4882a593Smuzhiyun dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun free_irq(irq, esp);
259*4882a593Smuzhiyun dma_free_coherent(esp->dev, 16,
260*4882a593Smuzhiyun esp->command_block,
261*4882a593Smuzhiyun esp->command_block_dma);
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun scsi_host_put(esp->host);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun return 0;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun static struct platform_driver esp_sun3x_driver = {
269*4882a593Smuzhiyun .probe = esp_sun3x_probe,
270*4882a593Smuzhiyun .remove = esp_sun3x_remove,
271*4882a593Smuzhiyun .driver = {
272*4882a593Smuzhiyun .name = "sun3x_esp",
273*4882a593Smuzhiyun },
274*4882a593Smuzhiyun };
275*4882a593Smuzhiyun module_platform_driver(esp_sun3x_driver);
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun MODULE_DESCRIPTION("Sun3x ESP SCSI driver");
278*4882a593Smuzhiyun MODULE_AUTHOR("Thomas Bogendoerfer (tsbogend@alpha.franken.de)");
279*4882a593Smuzhiyun MODULE_LICENSE("GPL");
280*4882a593Smuzhiyun MODULE_VERSION(DRV_VERSION);
281*4882a593Smuzhiyun MODULE_ALIAS("platform:sun3x_esp");
282