1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * driver for Microsemi PQI-based storage controllers 4*4882a593Smuzhiyun * Copyright (c) 2019-2020 Microchip Technology Inc. and its subsidiaries 5*4882a593Smuzhiyun * Copyright (c) 2016-2018 Microsemi Corporation 6*4882a593Smuzhiyun * Copyright (c) 2016 PMC-Sierra, Inc. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Questions/Comments/Bugfixes to storagedev@microchip.com 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #if !defined(_SMARTPQI_SIS_H) 13*4882a593Smuzhiyun #define _SMARTPQI_SIS_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun int sis_wait_for_ctrl_ready(struct pqi_ctrl_info *ctrl_info); 16*4882a593Smuzhiyun int sis_wait_for_ctrl_ready_resume(struct pqi_ctrl_info *ctrl_info); 17*4882a593Smuzhiyun bool sis_is_firmware_running(struct pqi_ctrl_info *ctrl_info); 18*4882a593Smuzhiyun bool sis_is_kernel_up(struct pqi_ctrl_info *ctrl_info); 19*4882a593Smuzhiyun int sis_get_ctrl_properties(struct pqi_ctrl_info *ctrl_info); 20*4882a593Smuzhiyun int sis_get_pqi_capabilities(struct pqi_ctrl_info *ctrl_info); 21*4882a593Smuzhiyun int sis_init_base_struct_addr(struct pqi_ctrl_info *ctrl_info); 22*4882a593Smuzhiyun void sis_enable_msix(struct pqi_ctrl_info *ctrl_info); 23*4882a593Smuzhiyun void sis_enable_intx(struct pqi_ctrl_info *ctrl_info); 24*4882a593Smuzhiyun void sis_shutdown_ctrl(struct pqi_ctrl_info *ctrl_info); 25*4882a593Smuzhiyun int sis_pqi_reset_quiesce(struct pqi_ctrl_info *ctrl_info); 26*4882a593Smuzhiyun int sis_reenable_sis_mode(struct pqi_ctrl_info *ctrl_info); 27*4882a593Smuzhiyun void sis_write_driver_scratch(struct pqi_ctrl_info *ctrl_info, u32 value); 28*4882a593Smuzhiyun u32 sis_read_driver_scratch(struct pqi_ctrl_info *ctrl_info); 29*4882a593Smuzhiyun void sis_soft_reset(struct pqi_ctrl_info *ctrl_info); 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #endif /* _SMARTPQI_SIS_H */ 32