1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* to be used by qlogicfas and qlogic_cs */ 3*4882a593Smuzhiyun #ifndef __QLOGICFAS408_H 4*4882a593Smuzhiyun #define __QLOGICFAS408_H 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun /*----------------------------------------------------------------*/ 7*4882a593Smuzhiyun /* Configuration */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* Set the following to max out the speed of the PIO PseudoDMA transfers, 10*4882a593Smuzhiyun again, 0 tends to be slower, but more stable. */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define QL_TURBO_PDMA 1 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* This should be 1 to enable parity detection */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define QL_ENABLE_PARITY 1 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* This will reset all devices when the driver is initialized (during bootup). 19*4882a593Smuzhiyun The other linux drivers don't do this, but the DOS drivers do, and after 20*4882a593Smuzhiyun using DOS or some kind of crash or lockup this will bring things back 21*4882a593Smuzhiyun without requiring a cold boot. It does take some time to recover from a 22*4882a593Smuzhiyun reset, so it is slower, and I have seen timeouts so that devices weren't 23*4882a593Smuzhiyun recognized when this was set. */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define QL_RESET_AT_START 0 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* crystal frequency in megahertz (for offset 5 and 9) 28*4882a593Smuzhiyun Please set this for your card. Most Qlogic cards are 40 Mhz. The 29*4882a593Smuzhiyun Control Concepts ISA (not VLB) is 24 Mhz */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define XTALFREQ 40 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /**********/ 34*4882a593Smuzhiyun /* DANGER! modify these at your own risk */ 35*4882a593Smuzhiyun /* SLOWCABLE can usually be reset to zero if you have a clean setup and 36*4882a593Smuzhiyun proper termination. The rest are for synchronous transfers and other 37*4882a593Smuzhiyun advanced features if your device can transfer faster than 5Mb/sec. 38*4882a593Smuzhiyun If you are really curious, email me for a quick howto until I have 39*4882a593Smuzhiyun something official */ 40*4882a593Smuzhiyun /**********/ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /*****/ 43*4882a593Smuzhiyun /* config register 1 (offset 8) options */ 44*4882a593Smuzhiyun /* This needs to be set to 1 if your cabling is long or noisy */ 45*4882a593Smuzhiyun #define SLOWCABLE 1 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /*****/ 48*4882a593Smuzhiyun /* offset 0xc */ 49*4882a593Smuzhiyun /* This will set fast (10Mhz) synchronous timing when set to 1 50*4882a593Smuzhiyun For this to have an effect, FASTCLK must also be 1 */ 51*4882a593Smuzhiyun #define FASTSCSI 0 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* This when set to 1 will set a faster sync transfer rate */ 54*4882a593Smuzhiyun #define FASTCLK 0 /*(XTALFREQ>25?1:0)*/ 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /*****/ 57*4882a593Smuzhiyun /* offset 6 */ 58*4882a593Smuzhiyun /* This is the sync transfer divisor, XTALFREQ/X will be the maximum 59*4882a593Smuzhiyun achievable data rate (assuming the rest of the system is capable 60*4882a593Smuzhiyun and set properly) */ 61*4882a593Smuzhiyun #define SYNCXFRPD 5 /*(XTALFREQ/5)*/ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /*****/ 64*4882a593Smuzhiyun /* offset 7 */ 65*4882a593Smuzhiyun /* This is the count of how many synchronous transfers can take place 66*4882a593Smuzhiyun i.e. how many reqs can occur before an ack is given. 67*4882a593Smuzhiyun The maximum value for this is 15, the upper bits can modify 68*4882a593Smuzhiyun REQ/ACK assertion and deassertion during synchronous transfers 69*4882a593Smuzhiyun If this is 0, the bus will only transfer asynchronously */ 70*4882a593Smuzhiyun #define SYNCOFFST 0 71*4882a593Smuzhiyun /* for the curious, bits 7&6 control the deassertion delay in 1/2 cycles 72*4882a593Smuzhiyun of the 40Mhz clock. If FASTCLK is 1, specifying 01 (1/2) will 73*4882a593Smuzhiyun cause the deassertion to be early by 1/2 clock. Bits 5&4 control 74*4882a593Smuzhiyun the assertion delay, also in 1/2 clocks (FASTCLK is ignored here). */ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /*----------------------------------------------------------------*/ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun struct qlogicfas408_priv { 79*4882a593Smuzhiyun int qbase; /* Port */ 80*4882a593Smuzhiyun int qinitid; /* initiator ID */ 81*4882a593Smuzhiyun int qabort; /* Flag to cause an abort */ 82*4882a593Smuzhiyun int qlirq; /* IRQ being used */ 83*4882a593Smuzhiyun int int_type; /* type of irq, 2 for ISA board, 0 for PCMCIA */ 84*4882a593Smuzhiyun char qinfo[80]; /* description */ 85*4882a593Smuzhiyun struct scsi_cmnd *qlcmd; /* current command being processed */ 86*4882a593Smuzhiyun struct Scsi_Host *shost; /* pointer back to host */ 87*4882a593Smuzhiyun struct qlogicfas408_priv *next; /* next private struct */ 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* The qlogic card uses two register maps - These macros select which one */ 91*4882a593Smuzhiyun #define REG0 ( outb( inb( qbase + 0xd ) & 0x7f , qbase + 0xd ), outb( 4 , qbase + 0xd )) 92*4882a593Smuzhiyun #define REG1 ( outb( inb( qbase + 0xd ) | 0x80 , qbase + 0xd ), outb( 0xb4 | int_type, qbase + 0xd )) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* following is watchdog timeout in microseconds */ 95*4882a593Smuzhiyun #define WATCHDOG 5000000 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /*----------------------------------------------------------------*/ 98*4882a593Smuzhiyun /* the following will set the monitor border color (useful to find 99*4882a593Smuzhiyun where something crashed or gets stuck at and as a simple profiler) */ 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define rtrc(i) {} 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define get_priv_by_cmd(x) (struct qlogicfas408_priv *)&((x)->device->host->hostdata[0]) 104*4882a593Smuzhiyun #define get_priv_by_host(x) (struct qlogicfas408_priv *)&((x)->hostdata[0]) 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun irqreturn_t qlogicfas408_ihandl(int irq, void *dev_id); 107*4882a593Smuzhiyun int qlogicfas408_queuecommand(struct Scsi_Host *h, struct scsi_cmnd * cmd); 108*4882a593Smuzhiyun int qlogicfas408_biosparam(struct scsi_device * disk, 109*4882a593Smuzhiyun struct block_device *dev, 110*4882a593Smuzhiyun sector_t capacity, int ip[]); 111*4882a593Smuzhiyun int qlogicfas408_abort(struct scsi_cmnd * cmd); 112*4882a593Smuzhiyun extern int qlogicfas408_host_reset(struct scsi_cmnd *cmd); 113*4882a593Smuzhiyun const char *qlogicfas408_info(struct Scsi_Host *host); 114*4882a593Smuzhiyun int qlogicfas408_get_chip_type(int qbase, int int_type); 115*4882a593Smuzhiyun void qlogicfas408_setup(int qbase, int id, int int_type); 116*4882a593Smuzhiyun int qlogicfas408_detect(int qbase, int int_type); 117*4882a593Smuzhiyun void qlogicfas408_disable_ints(struct qlogicfas408_priv *priv); 118*4882a593Smuzhiyun #endif /* __QLOGICFAS408_H */ 119*4882a593Smuzhiyun 120