xref: /OK3568_Linux_fs/kernel/drivers/scsi/qla2xxx/qla_mr.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * QLogic Fibre Channel HBA Driver
4*4882a593Smuzhiyun  * Copyright (c)  2003-2014 QLogic Corporation
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun #include "qla_def.h"
7*4882a593Smuzhiyun #include <linux/delay.h>
8*4882a593Smuzhiyun #include <linux/ktime.h>
9*4882a593Smuzhiyun #include <linux/pci.h>
10*4882a593Smuzhiyun #include <linux/ratelimit.h>
11*4882a593Smuzhiyun #include <linux/vmalloc.h>
12*4882a593Smuzhiyun #include <scsi/scsi_tcq.h>
13*4882a593Smuzhiyun #include <linux/utsname.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun /* QLAFX00 specific Mailbox implementation functions */
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun /*
19*4882a593Smuzhiyun  * qlafx00_mailbox_command
20*4882a593Smuzhiyun  *	Issue mailbox command and waits for completion.
21*4882a593Smuzhiyun  *
22*4882a593Smuzhiyun  * Input:
23*4882a593Smuzhiyun  *	ha = adapter block pointer.
24*4882a593Smuzhiyun  *	mcp = driver internal mbx struct pointer.
25*4882a593Smuzhiyun  *
26*4882a593Smuzhiyun  * Output:
27*4882a593Smuzhiyun  *	mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
28*4882a593Smuzhiyun  *
29*4882a593Smuzhiyun  * Returns:
30*4882a593Smuzhiyun  *	0 : QLA_SUCCESS = cmd performed success
31*4882a593Smuzhiyun  *	1 : QLA_FUNCTION_FAILED   (error encountered)
32*4882a593Smuzhiyun  *	6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
33*4882a593Smuzhiyun  *
34*4882a593Smuzhiyun  * Context:
35*4882a593Smuzhiyun  *	Kernel context.
36*4882a593Smuzhiyun  */
37*4882a593Smuzhiyun static int
qlafx00_mailbox_command(scsi_qla_host_t * vha,struct mbx_cmd_32 * mcp)38*4882a593Smuzhiyun qlafx00_mailbox_command(scsi_qla_host_t *vha, struct mbx_cmd_32 *mcp)
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun 	int		rval;
42*4882a593Smuzhiyun 	unsigned long    flags = 0;
43*4882a593Smuzhiyun 	device_reg_t *reg;
44*4882a593Smuzhiyun 	uint8_t		abort_active;
45*4882a593Smuzhiyun 	uint8_t		io_lock_on;
46*4882a593Smuzhiyun 	uint16_t	command = 0;
47*4882a593Smuzhiyun 	uint32_t	*iptr;
48*4882a593Smuzhiyun 	__le32 __iomem *optr;
49*4882a593Smuzhiyun 	uint32_t	cnt;
50*4882a593Smuzhiyun 	uint32_t	mboxes;
51*4882a593Smuzhiyun 	unsigned long	wait_time;
52*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
53*4882a593Smuzhiyun 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	if (ha->pdev->error_state == pci_channel_io_perm_failure) {
56*4882a593Smuzhiyun 		ql_log(ql_log_warn, vha, 0x115c,
57*4882a593Smuzhiyun 		    "PCI channel failed permanently, exiting.\n");
58*4882a593Smuzhiyun 		return QLA_FUNCTION_TIMEOUT;
59*4882a593Smuzhiyun 	}
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	if (vha->device_flags & DFLG_DEV_FAILED) {
62*4882a593Smuzhiyun 		ql_log(ql_log_warn, vha, 0x115f,
63*4882a593Smuzhiyun 		    "Device in failed state, exiting.\n");
64*4882a593Smuzhiyun 		return QLA_FUNCTION_TIMEOUT;
65*4882a593Smuzhiyun 	}
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	reg = ha->iobase;
68*4882a593Smuzhiyun 	io_lock_on = base_vha->flags.init_done;
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	rval = QLA_SUCCESS;
71*4882a593Smuzhiyun 	abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	if (ha->flags.pci_channel_io_perm_failure) {
74*4882a593Smuzhiyun 		ql_log(ql_log_warn, vha, 0x1175,
75*4882a593Smuzhiyun 		    "Perm failure on EEH timeout MBX, exiting.\n");
76*4882a593Smuzhiyun 		return QLA_FUNCTION_TIMEOUT;
77*4882a593Smuzhiyun 	}
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	if (ha->flags.isp82xx_fw_hung) {
80*4882a593Smuzhiyun 		/* Setting Link-Down error */
81*4882a593Smuzhiyun 		mcp->mb[0] = MBS_LINK_DOWN_ERROR;
82*4882a593Smuzhiyun 		ql_log(ql_log_warn, vha, 0x1176,
83*4882a593Smuzhiyun 		    "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
84*4882a593Smuzhiyun 		rval = QLA_FUNCTION_FAILED;
85*4882a593Smuzhiyun 		goto premature_exit;
86*4882a593Smuzhiyun 	}
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	/*
89*4882a593Smuzhiyun 	 * Wait for active mailbox commands to finish by waiting at most tov
90*4882a593Smuzhiyun 	 * seconds. This is to serialize actual issuing of mailbox cmds during
91*4882a593Smuzhiyun 	 * non ISP abort time.
92*4882a593Smuzhiyun 	 */
93*4882a593Smuzhiyun 	if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
94*4882a593Smuzhiyun 		/* Timeout occurred. Return error. */
95*4882a593Smuzhiyun 		ql_log(ql_log_warn, vha, 0x1177,
96*4882a593Smuzhiyun 		    "Cmd access timeout, cmd=0x%x, Exiting.\n",
97*4882a593Smuzhiyun 		    mcp->mb[0]);
98*4882a593Smuzhiyun 		return QLA_FUNCTION_TIMEOUT;
99*4882a593Smuzhiyun 	}
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	ha->flags.mbox_busy = 1;
102*4882a593Smuzhiyun 	/* Save mailbox command for debug */
103*4882a593Smuzhiyun 	ha->mcp32 = mcp;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	ql_dbg(ql_dbg_mbx, vha, 0x1178,
106*4882a593Smuzhiyun 	    "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	spin_lock_irqsave(&ha->hardware_lock, flags);
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	/* Load mailbox registers. */
111*4882a593Smuzhiyun 	optr = &reg->ispfx00.mailbox0;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	iptr = mcp->mb;
114*4882a593Smuzhiyun 	command = mcp->mb[0];
115*4882a593Smuzhiyun 	mboxes = mcp->out_mb;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	for (cnt = 0; cnt < ha->mbx_count; cnt++) {
118*4882a593Smuzhiyun 		if (mboxes & BIT_0)
119*4882a593Smuzhiyun 			wrt_reg_dword(optr, *iptr);
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 		mboxes >>= 1;
122*4882a593Smuzhiyun 		optr++;
123*4882a593Smuzhiyun 		iptr++;
124*4882a593Smuzhiyun 	}
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	/* Issue set host interrupt command to send cmd out. */
127*4882a593Smuzhiyun 	ha->flags.mbox_int = 0;
128*4882a593Smuzhiyun 	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1172,
131*4882a593Smuzhiyun 	    (uint8_t *)mcp->mb, 16);
132*4882a593Smuzhiyun 	ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1173,
133*4882a593Smuzhiyun 	    ((uint8_t *)mcp->mb + 0x10), 16);
134*4882a593Smuzhiyun 	ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1174,
135*4882a593Smuzhiyun 	    ((uint8_t *)mcp->mb + 0x20), 8);
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	/* Unlock mbx registers and wait for interrupt */
138*4882a593Smuzhiyun 	ql_dbg(ql_dbg_mbx, vha, 0x1179,
139*4882a593Smuzhiyun 	    "Going to unlock irq & waiting for interrupts. "
140*4882a593Smuzhiyun 	    "jiffies=%lx.\n", jiffies);
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	/* Wait for mbx cmd completion until timeout */
143*4882a593Smuzhiyun 	if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
144*4882a593Smuzhiyun 		set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 		QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
147*4882a593Smuzhiyun 		spin_unlock_irqrestore(&ha->hardware_lock, flags);
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 		WARN_ON_ONCE(wait_for_completion_timeout(&ha->mbx_intr_comp,
150*4882a593Smuzhiyun 							 mcp->tov * HZ) != 0);
151*4882a593Smuzhiyun 	} else {
152*4882a593Smuzhiyun 		ql_dbg(ql_dbg_mbx, vha, 0x112c,
153*4882a593Smuzhiyun 		    "Cmd=%x Polling Mode.\n", command);
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 		QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
156*4882a593Smuzhiyun 		spin_unlock_irqrestore(&ha->hardware_lock, flags);
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 		wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
159*4882a593Smuzhiyun 		while (!ha->flags.mbox_int) {
160*4882a593Smuzhiyun 			if (time_after(jiffies, wait_time))
161*4882a593Smuzhiyun 				break;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 			/* Check for pending interrupts. */
164*4882a593Smuzhiyun 			qla2x00_poll(ha->rsp_q_map[0]);
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 			if (!ha->flags.mbox_int &&
167*4882a593Smuzhiyun 			    !(IS_QLA2200(ha) &&
168*4882a593Smuzhiyun 			    command == MBC_LOAD_RISC_RAM_EXTENDED))
169*4882a593Smuzhiyun 				usleep_range(10000, 11000);
170*4882a593Smuzhiyun 		} /* while */
171*4882a593Smuzhiyun 		ql_dbg(ql_dbg_mbx, vha, 0x112d,
172*4882a593Smuzhiyun 		    "Waited %d sec.\n",
173*4882a593Smuzhiyun 		    (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
174*4882a593Smuzhiyun 	}
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 	/* Check whether we timed out */
177*4882a593Smuzhiyun 	if (ha->flags.mbox_int) {
178*4882a593Smuzhiyun 		uint32_t *iptr2;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 		ql_dbg(ql_dbg_mbx, vha, 0x112e,
181*4882a593Smuzhiyun 		    "Cmd=%x completed.\n", command);
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 		/* Got interrupt. Clear the flag. */
184*4882a593Smuzhiyun 		ha->flags.mbox_int = 0;
185*4882a593Smuzhiyun 		clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 		if (ha->mailbox_out32[0] != MBS_COMMAND_COMPLETE)
188*4882a593Smuzhiyun 			rval = QLA_FUNCTION_FAILED;
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 		/* Load return mailbox registers. */
191*4882a593Smuzhiyun 		iptr2 = mcp->mb;
192*4882a593Smuzhiyun 		iptr = (uint32_t *)&ha->mailbox_out32[0];
193*4882a593Smuzhiyun 		mboxes = mcp->in_mb;
194*4882a593Smuzhiyun 		for (cnt = 0; cnt < ha->mbx_count; cnt++) {
195*4882a593Smuzhiyun 			if (mboxes & BIT_0)
196*4882a593Smuzhiyun 				*iptr2 = *iptr;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 			mboxes >>= 1;
199*4882a593Smuzhiyun 			iptr2++;
200*4882a593Smuzhiyun 			iptr++;
201*4882a593Smuzhiyun 		}
202*4882a593Smuzhiyun 	} else {
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 		rval = QLA_FUNCTION_TIMEOUT;
205*4882a593Smuzhiyun 	}
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	ha->flags.mbox_busy = 0;
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	/* Clean up */
210*4882a593Smuzhiyun 	ha->mcp32 = NULL;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
213*4882a593Smuzhiyun 		ql_dbg(ql_dbg_mbx, vha, 0x113a,
214*4882a593Smuzhiyun 		    "checking for additional resp interrupt.\n");
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 		/* polling mode for non isp_abort commands. */
217*4882a593Smuzhiyun 		qla2x00_poll(ha->rsp_q_map[0]);
218*4882a593Smuzhiyun 	}
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	if (rval == QLA_FUNCTION_TIMEOUT &&
221*4882a593Smuzhiyun 	    mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
222*4882a593Smuzhiyun 		if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
223*4882a593Smuzhiyun 		    ha->flags.eeh_busy) {
224*4882a593Smuzhiyun 			/* not in dpc. schedule it for dpc to take over. */
225*4882a593Smuzhiyun 			ql_dbg(ql_dbg_mbx, vha, 0x115d,
226*4882a593Smuzhiyun 			    "Timeout, schedule isp_abort_needed.\n");
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 			if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
229*4882a593Smuzhiyun 			    !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
230*4882a593Smuzhiyun 			    !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 				ql_log(ql_log_info, base_vha, 0x115e,
233*4882a593Smuzhiyun 				    "Mailbox cmd timeout occurred, cmd=0x%x, "
234*4882a593Smuzhiyun 				    "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
235*4882a593Smuzhiyun 				    "abort.\n", command, mcp->mb[0],
236*4882a593Smuzhiyun 				    ha->flags.eeh_busy);
237*4882a593Smuzhiyun 				set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
238*4882a593Smuzhiyun 				qla2xxx_wake_dpc(vha);
239*4882a593Smuzhiyun 			}
240*4882a593Smuzhiyun 		} else if (!abort_active) {
241*4882a593Smuzhiyun 			/* call abort directly since we are in the DPC thread */
242*4882a593Smuzhiyun 			ql_dbg(ql_dbg_mbx, vha, 0x1160,
243*4882a593Smuzhiyun 			    "Timeout, calling abort_isp.\n");
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 			if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
246*4882a593Smuzhiyun 			    !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
247*4882a593Smuzhiyun 			    !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun 				ql_log(ql_log_info, base_vha, 0x1161,
250*4882a593Smuzhiyun 				    "Mailbox cmd timeout occurred, cmd=0x%x, "
251*4882a593Smuzhiyun 				    "mb[0]=0x%x. Scheduling ISP abort ",
252*4882a593Smuzhiyun 				    command, mcp->mb[0]);
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 				set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
255*4882a593Smuzhiyun 				clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
256*4882a593Smuzhiyun 				if (ha->isp_ops->abort_isp(vha)) {
257*4882a593Smuzhiyun 					/* Failed. retry later. */
258*4882a593Smuzhiyun 					set_bit(ISP_ABORT_NEEDED,
259*4882a593Smuzhiyun 					    &vha->dpc_flags);
260*4882a593Smuzhiyun 				}
261*4882a593Smuzhiyun 				clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
262*4882a593Smuzhiyun 				ql_dbg(ql_dbg_mbx, vha, 0x1162,
263*4882a593Smuzhiyun 				    "Finished abort_isp.\n");
264*4882a593Smuzhiyun 			}
265*4882a593Smuzhiyun 		}
266*4882a593Smuzhiyun 	}
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun premature_exit:
269*4882a593Smuzhiyun 	/* Allow next mbx cmd to come in. */
270*4882a593Smuzhiyun 	complete(&ha->mbx_cmd_comp);
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	if (rval) {
273*4882a593Smuzhiyun 		ql_log(ql_log_warn, base_vha, 0x1163,
274*4882a593Smuzhiyun 		       "**** Failed=%x mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
275*4882a593Smuzhiyun 		       rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
276*4882a593Smuzhiyun 		       command);
277*4882a593Smuzhiyun 	} else {
278*4882a593Smuzhiyun 		ql_dbg(ql_dbg_mbx, base_vha, 0x1164, "Done %s.\n", __func__);
279*4882a593Smuzhiyun 	}
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 	return rval;
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun /*
285*4882a593Smuzhiyun  * qlafx00_driver_shutdown
286*4882a593Smuzhiyun  *	Indicate a driver shutdown to firmware.
287*4882a593Smuzhiyun  *
288*4882a593Smuzhiyun  * Input:
289*4882a593Smuzhiyun  *	ha = adapter block pointer.
290*4882a593Smuzhiyun  *
291*4882a593Smuzhiyun  * Returns:
292*4882a593Smuzhiyun  *	local function return status code.
293*4882a593Smuzhiyun  *
294*4882a593Smuzhiyun  * Context:
295*4882a593Smuzhiyun  *	Kernel context.
296*4882a593Smuzhiyun  */
297*4882a593Smuzhiyun int
qlafx00_driver_shutdown(scsi_qla_host_t * vha,int tmo)298*4882a593Smuzhiyun qlafx00_driver_shutdown(scsi_qla_host_t *vha, int tmo)
299*4882a593Smuzhiyun {
300*4882a593Smuzhiyun 	int rval;
301*4882a593Smuzhiyun 	struct mbx_cmd_32 mc;
302*4882a593Smuzhiyun 	struct mbx_cmd_32 *mcp = &mc;
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1166,
305*4882a593Smuzhiyun 	    "Entered %s.\n", __func__);
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	mcp->mb[0] = MBC_MR_DRV_SHUTDOWN;
308*4882a593Smuzhiyun 	mcp->out_mb = MBX_0;
309*4882a593Smuzhiyun 	mcp->in_mb = MBX_0;
310*4882a593Smuzhiyun 	if (tmo)
311*4882a593Smuzhiyun 		mcp->tov = tmo;
312*4882a593Smuzhiyun 	else
313*4882a593Smuzhiyun 		mcp->tov = MBX_TOV_SECONDS;
314*4882a593Smuzhiyun 	mcp->flags = 0;
315*4882a593Smuzhiyun 	rval = qlafx00_mailbox_command(vha, mcp);
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	if (rval != QLA_SUCCESS) {
318*4882a593Smuzhiyun 		ql_dbg(ql_dbg_mbx, vha, 0x1167,
319*4882a593Smuzhiyun 		    "Failed=%x.\n", rval);
320*4882a593Smuzhiyun 	} else {
321*4882a593Smuzhiyun 		ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1168,
322*4882a593Smuzhiyun 		    "Done %s.\n", __func__);
323*4882a593Smuzhiyun 	}
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	return rval;
326*4882a593Smuzhiyun }
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun /*
329*4882a593Smuzhiyun  * qlafx00_get_firmware_state
330*4882a593Smuzhiyun  *	Get adapter firmware state.
331*4882a593Smuzhiyun  *
332*4882a593Smuzhiyun  * Input:
333*4882a593Smuzhiyun  *	ha = adapter block pointer.
334*4882a593Smuzhiyun  *	TARGET_QUEUE_LOCK must be released.
335*4882a593Smuzhiyun  *	ADAPTER_STATE_LOCK must be released.
336*4882a593Smuzhiyun  *
337*4882a593Smuzhiyun  * Returns:
338*4882a593Smuzhiyun  *	qla7xxx local function return status code.
339*4882a593Smuzhiyun  *
340*4882a593Smuzhiyun  * Context:
341*4882a593Smuzhiyun  *	Kernel context.
342*4882a593Smuzhiyun  */
343*4882a593Smuzhiyun static int
qlafx00_get_firmware_state(scsi_qla_host_t * vha,uint32_t * states)344*4882a593Smuzhiyun qlafx00_get_firmware_state(scsi_qla_host_t *vha, uint32_t *states)
345*4882a593Smuzhiyun {
346*4882a593Smuzhiyun 	int rval;
347*4882a593Smuzhiyun 	struct mbx_cmd_32 mc;
348*4882a593Smuzhiyun 	struct mbx_cmd_32 *mcp = &mc;
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1169,
351*4882a593Smuzhiyun 	    "Entered %s.\n", __func__);
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 	mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
354*4882a593Smuzhiyun 	mcp->out_mb = MBX_0;
355*4882a593Smuzhiyun 	mcp->in_mb = MBX_1|MBX_0;
356*4882a593Smuzhiyun 	mcp->tov = MBX_TOV_SECONDS;
357*4882a593Smuzhiyun 	mcp->flags = 0;
358*4882a593Smuzhiyun 	rval = qlafx00_mailbox_command(vha, mcp);
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 	/* Return firmware states. */
361*4882a593Smuzhiyun 	states[0] = mcp->mb[1];
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	if (rval != QLA_SUCCESS) {
364*4882a593Smuzhiyun 		ql_dbg(ql_dbg_mbx, vha, 0x116a,
365*4882a593Smuzhiyun 		    "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
366*4882a593Smuzhiyun 	} else {
367*4882a593Smuzhiyun 		ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116b,
368*4882a593Smuzhiyun 		    "Done %s.\n", __func__);
369*4882a593Smuzhiyun 	}
370*4882a593Smuzhiyun 	return rval;
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun /*
374*4882a593Smuzhiyun  * qlafx00_init_firmware
375*4882a593Smuzhiyun  *	Initialize adapter firmware.
376*4882a593Smuzhiyun  *
377*4882a593Smuzhiyun  * Input:
378*4882a593Smuzhiyun  *	ha = adapter block pointer.
379*4882a593Smuzhiyun  *	dptr = Initialization control block pointer.
380*4882a593Smuzhiyun  *	size = size of initialization control block.
381*4882a593Smuzhiyun  *	TARGET_QUEUE_LOCK must be released.
382*4882a593Smuzhiyun  *	ADAPTER_STATE_LOCK must be released.
383*4882a593Smuzhiyun  *
384*4882a593Smuzhiyun  * Returns:
385*4882a593Smuzhiyun  *	qlafx00 local function return status code.
386*4882a593Smuzhiyun  *
387*4882a593Smuzhiyun  * Context:
388*4882a593Smuzhiyun  *	Kernel context.
389*4882a593Smuzhiyun  */
390*4882a593Smuzhiyun int
qlafx00_init_firmware(scsi_qla_host_t * vha,uint16_t size)391*4882a593Smuzhiyun qlafx00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
392*4882a593Smuzhiyun {
393*4882a593Smuzhiyun 	int rval;
394*4882a593Smuzhiyun 	struct mbx_cmd_32 mc;
395*4882a593Smuzhiyun 	struct mbx_cmd_32 *mcp = &mc;
396*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116c,
399*4882a593Smuzhiyun 	    "Entered %s.\n", __func__);
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun 	mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun 	mcp->mb[1] = 0;
404*4882a593Smuzhiyun 	mcp->mb[2] = MSD(ha->init_cb_dma);
405*4882a593Smuzhiyun 	mcp->mb[3] = LSD(ha->init_cb_dma);
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun 	mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
408*4882a593Smuzhiyun 	mcp->in_mb = MBX_0;
409*4882a593Smuzhiyun 	mcp->buf_size = size;
410*4882a593Smuzhiyun 	mcp->flags = MBX_DMA_OUT;
411*4882a593Smuzhiyun 	mcp->tov = MBX_TOV_SECONDS;
412*4882a593Smuzhiyun 	rval = qlafx00_mailbox_command(vha, mcp);
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	if (rval != QLA_SUCCESS) {
415*4882a593Smuzhiyun 		ql_dbg(ql_dbg_mbx, vha, 0x116d,
416*4882a593Smuzhiyun 		    "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
417*4882a593Smuzhiyun 	} else {
418*4882a593Smuzhiyun 		ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116e,
419*4882a593Smuzhiyun 		    "Done %s.\n", __func__);
420*4882a593Smuzhiyun 	}
421*4882a593Smuzhiyun 	return rval;
422*4882a593Smuzhiyun }
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun /*
425*4882a593Smuzhiyun  * qlafx00_mbx_reg_test
426*4882a593Smuzhiyun  */
427*4882a593Smuzhiyun static int
qlafx00_mbx_reg_test(scsi_qla_host_t * vha)428*4882a593Smuzhiyun qlafx00_mbx_reg_test(scsi_qla_host_t *vha)
429*4882a593Smuzhiyun {
430*4882a593Smuzhiyun 	int rval;
431*4882a593Smuzhiyun 	struct mbx_cmd_32 mc;
432*4882a593Smuzhiyun 	struct mbx_cmd_32 *mcp = &mc;
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116f,
435*4882a593Smuzhiyun 	    "Entered %s.\n", __func__);
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun 	mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
439*4882a593Smuzhiyun 	mcp->mb[1] = 0xAAAA;
440*4882a593Smuzhiyun 	mcp->mb[2] = 0x5555;
441*4882a593Smuzhiyun 	mcp->mb[3] = 0xAA55;
442*4882a593Smuzhiyun 	mcp->mb[4] = 0x55AA;
443*4882a593Smuzhiyun 	mcp->mb[5] = 0xA5A5;
444*4882a593Smuzhiyun 	mcp->mb[6] = 0x5A5A;
445*4882a593Smuzhiyun 	mcp->mb[7] = 0x2525;
446*4882a593Smuzhiyun 	mcp->mb[8] = 0xBBBB;
447*4882a593Smuzhiyun 	mcp->mb[9] = 0x6666;
448*4882a593Smuzhiyun 	mcp->mb[10] = 0xBB66;
449*4882a593Smuzhiyun 	mcp->mb[11] = 0x66BB;
450*4882a593Smuzhiyun 	mcp->mb[12] = 0xB6B6;
451*4882a593Smuzhiyun 	mcp->mb[13] = 0x6B6B;
452*4882a593Smuzhiyun 	mcp->mb[14] = 0x3636;
453*4882a593Smuzhiyun 	mcp->mb[15] = 0xCCCC;
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun 	mcp->out_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
457*4882a593Smuzhiyun 			MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
458*4882a593Smuzhiyun 	mcp->in_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
459*4882a593Smuzhiyun 			MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
460*4882a593Smuzhiyun 	mcp->buf_size = 0;
461*4882a593Smuzhiyun 	mcp->flags = MBX_DMA_OUT;
462*4882a593Smuzhiyun 	mcp->tov = MBX_TOV_SECONDS;
463*4882a593Smuzhiyun 	rval = qlafx00_mailbox_command(vha, mcp);
464*4882a593Smuzhiyun 	if (rval == QLA_SUCCESS) {
465*4882a593Smuzhiyun 		if (mcp->mb[17] != 0xAAAA || mcp->mb[18] != 0x5555 ||
466*4882a593Smuzhiyun 		    mcp->mb[19] != 0xAA55 || mcp->mb[20] != 0x55AA)
467*4882a593Smuzhiyun 			rval = QLA_FUNCTION_FAILED;
468*4882a593Smuzhiyun 		if (mcp->mb[21] != 0xA5A5 || mcp->mb[22] != 0x5A5A ||
469*4882a593Smuzhiyun 		    mcp->mb[23] != 0x2525 || mcp->mb[24] != 0xBBBB)
470*4882a593Smuzhiyun 			rval = QLA_FUNCTION_FAILED;
471*4882a593Smuzhiyun 		if (mcp->mb[25] != 0x6666 || mcp->mb[26] != 0xBB66 ||
472*4882a593Smuzhiyun 		    mcp->mb[27] != 0x66BB || mcp->mb[28] != 0xB6B6)
473*4882a593Smuzhiyun 			rval = QLA_FUNCTION_FAILED;
474*4882a593Smuzhiyun 		if (mcp->mb[29] != 0x6B6B || mcp->mb[30] != 0x3636 ||
475*4882a593Smuzhiyun 		    mcp->mb[31] != 0xCCCC)
476*4882a593Smuzhiyun 			rval = QLA_FUNCTION_FAILED;
477*4882a593Smuzhiyun 	}
478*4882a593Smuzhiyun 
479*4882a593Smuzhiyun 	if (rval != QLA_SUCCESS) {
480*4882a593Smuzhiyun 		ql_dbg(ql_dbg_mbx, vha, 0x1170,
481*4882a593Smuzhiyun 		    "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
482*4882a593Smuzhiyun 	} else {
483*4882a593Smuzhiyun 		ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1171,
484*4882a593Smuzhiyun 		    "Done %s.\n", __func__);
485*4882a593Smuzhiyun 	}
486*4882a593Smuzhiyun 	return rval;
487*4882a593Smuzhiyun }
488*4882a593Smuzhiyun 
489*4882a593Smuzhiyun /**
490*4882a593Smuzhiyun  * qlafx00_pci_config() - Setup ISPFx00 PCI configuration registers.
491*4882a593Smuzhiyun  * @vha: HA context
492*4882a593Smuzhiyun  *
493*4882a593Smuzhiyun  * Returns 0 on success.
494*4882a593Smuzhiyun  */
495*4882a593Smuzhiyun int
qlafx00_pci_config(scsi_qla_host_t * vha)496*4882a593Smuzhiyun qlafx00_pci_config(scsi_qla_host_t *vha)
497*4882a593Smuzhiyun {
498*4882a593Smuzhiyun 	uint16_t w;
499*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun 	pci_set_master(ha->pdev);
502*4882a593Smuzhiyun 	pci_try_set_mwi(ha->pdev);
503*4882a593Smuzhiyun 
504*4882a593Smuzhiyun 	pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
505*4882a593Smuzhiyun 	w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
506*4882a593Smuzhiyun 	w &= ~PCI_COMMAND_INTX_DISABLE;
507*4882a593Smuzhiyun 	pci_write_config_word(ha->pdev, PCI_COMMAND, w);
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun 	/* PCIe -- adjust Maximum Read Request Size (2048). */
510*4882a593Smuzhiyun 	if (pci_is_pcie(ha->pdev))
511*4882a593Smuzhiyun 		pcie_set_readrq(ha->pdev, 2048);
512*4882a593Smuzhiyun 
513*4882a593Smuzhiyun 	ha->chip_revision = ha->pdev->revision;
514*4882a593Smuzhiyun 
515*4882a593Smuzhiyun 	return QLA_SUCCESS;
516*4882a593Smuzhiyun }
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun /**
519*4882a593Smuzhiyun  * qlafx00_warm_reset() - Perform warm reset of iSA(CPUs being reset on SOC).
520*4882a593Smuzhiyun  * @vha: HA context
521*4882a593Smuzhiyun  *
522*4882a593Smuzhiyun  */
523*4882a593Smuzhiyun static inline void
qlafx00_soc_cpu_reset(scsi_qla_host_t * vha)524*4882a593Smuzhiyun qlafx00_soc_cpu_reset(scsi_qla_host_t *vha)
525*4882a593Smuzhiyun {
526*4882a593Smuzhiyun 	unsigned long flags = 0;
527*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
528*4882a593Smuzhiyun 	int i, core;
529*4882a593Smuzhiyun 	uint32_t cnt;
530*4882a593Smuzhiyun 	uint32_t reg_val;
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun 	spin_lock_irqsave(&ha->hardware_lock, flags);
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun 	QLAFX00_SET_HBA_SOC_REG(ha, 0x80004, 0);
535*4882a593Smuzhiyun 	QLAFX00_SET_HBA_SOC_REG(ha, 0x82004, 0);
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun 	/* stop the XOR DMA engines */
538*4882a593Smuzhiyun 	QLAFX00_SET_HBA_SOC_REG(ha, 0x60920, 0x02);
539*4882a593Smuzhiyun 	QLAFX00_SET_HBA_SOC_REG(ha, 0x60924, 0x02);
540*4882a593Smuzhiyun 	QLAFX00_SET_HBA_SOC_REG(ha, 0xf0920, 0x02);
541*4882a593Smuzhiyun 	QLAFX00_SET_HBA_SOC_REG(ha, 0xf0924, 0x02);
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun 	/* stop the IDMA engines */
544*4882a593Smuzhiyun 	reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60840);
545*4882a593Smuzhiyun 	reg_val &= ~(1<<12);
546*4882a593Smuzhiyun 	QLAFX00_SET_HBA_SOC_REG(ha, 0x60840, reg_val);
547*4882a593Smuzhiyun 
548*4882a593Smuzhiyun 	reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60844);
549*4882a593Smuzhiyun 	reg_val &= ~(1<<12);
550*4882a593Smuzhiyun 	QLAFX00_SET_HBA_SOC_REG(ha, 0x60844, reg_val);
551*4882a593Smuzhiyun 
552*4882a593Smuzhiyun 	reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60848);
553*4882a593Smuzhiyun 	reg_val &= ~(1<<12);
554*4882a593Smuzhiyun 	QLAFX00_SET_HBA_SOC_REG(ha, 0x60848, reg_val);
555*4882a593Smuzhiyun 
556*4882a593Smuzhiyun 	reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x6084C);
557*4882a593Smuzhiyun 	reg_val &= ~(1<<12);
558*4882a593Smuzhiyun 	QLAFX00_SET_HBA_SOC_REG(ha, 0x6084C, reg_val);
559*4882a593Smuzhiyun 
560*4882a593Smuzhiyun 	for (i = 0; i < 100000; i++) {
561*4882a593Smuzhiyun 		if ((QLAFX00_GET_HBA_SOC_REG(ha, 0xd0000) & 0x10000000) == 0 &&
562*4882a593Smuzhiyun 		    (QLAFX00_GET_HBA_SOC_REG(ha, 0x10600) & 0x1) == 0)
563*4882a593Smuzhiyun 			break;
564*4882a593Smuzhiyun 		udelay(100);
565*4882a593Smuzhiyun 	}
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun 	/* Set all 4 cores in reset */
568*4882a593Smuzhiyun 	for (i = 0; i < 4; i++) {
569*4882a593Smuzhiyun 		QLAFX00_SET_HBA_SOC_REG(ha,
570*4882a593Smuzhiyun 		    (SOC_SW_RST_CONTROL_REG_CORE0 + 8*i), (0xF01));
571*4882a593Smuzhiyun 		QLAFX00_SET_HBA_SOC_REG(ha,
572*4882a593Smuzhiyun 		    (SOC_SW_RST_CONTROL_REG_CORE0 + 4 + 8*i), (0x01010101));
573*4882a593Smuzhiyun 	}
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 	/* Reset all units in Fabric */
576*4882a593Smuzhiyun 	QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x011f0101));
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun 	/* */
579*4882a593Smuzhiyun 	QLAFX00_SET_HBA_SOC_REG(ha, 0x10610, 1);
580*4882a593Smuzhiyun 	QLAFX00_SET_HBA_SOC_REG(ha, 0x10600, 0);
581*4882a593Smuzhiyun 
582*4882a593Smuzhiyun 	/* Set all 4 core Memory Power Down Registers */
583*4882a593Smuzhiyun 	for (i = 0; i < 5; i++) {
584*4882a593Smuzhiyun 		QLAFX00_SET_HBA_SOC_REG(ha,
585*4882a593Smuzhiyun 		    (SOC_PWR_MANAGEMENT_PWR_DOWN_REG + 4*i), (0x0));
586*4882a593Smuzhiyun 	}
587*4882a593Smuzhiyun 
588*4882a593Smuzhiyun 	/* Reset all interrupt control registers */
589*4882a593Smuzhiyun 	for (i = 0; i < 115; i++) {
590*4882a593Smuzhiyun 		QLAFX00_SET_HBA_SOC_REG(ha,
591*4882a593Smuzhiyun 		    (SOC_INTERRUPT_SOURCE_I_CONTROL_REG + 4*i), (0x0));
592*4882a593Smuzhiyun 	}
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun 	/* Reset Timers control registers. per core */
595*4882a593Smuzhiyun 	for (core = 0; core < 4; core++)
596*4882a593Smuzhiyun 		for (i = 0; i < 8; i++)
597*4882a593Smuzhiyun 			QLAFX00_SET_HBA_SOC_REG(ha,
598*4882a593Smuzhiyun 			    (SOC_CORE_TIMER_REG + 0x100*core + 4*i), (0x0));
599*4882a593Smuzhiyun 
600*4882a593Smuzhiyun 	/* Reset per core IRQ ack register */
601*4882a593Smuzhiyun 	for (core = 0; core < 4; core++)
602*4882a593Smuzhiyun 		QLAFX00_SET_HBA_SOC_REG(ha,
603*4882a593Smuzhiyun 		    (SOC_IRQ_ACK_REG + 0x100*core), (0x3FF));
604*4882a593Smuzhiyun 
605*4882a593Smuzhiyun 	/* Set Fabric control and config to defaults */
606*4882a593Smuzhiyun 	QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONTROL_REG, (0x2));
607*4882a593Smuzhiyun 	QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONFIG_REG, (0x3));
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 	/* Kick in Fabric units */
610*4882a593Smuzhiyun 	QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x0));
611*4882a593Smuzhiyun 
612*4882a593Smuzhiyun 	/* Kick in Core0 to start boot process */
613*4882a593Smuzhiyun 	QLAFX00_SET_HBA_SOC_REG(ha, SOC_SW_RST_CONTROL_REG_CORE0, (0xF00));
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
616*4882a593Smuzhiyun 
617*4882a593Smuzhiyun 	/* Wait 10secs for soft-reset to complete. */
618*4882a593Smuzhiyun 	for (cnt = 10; cnt; cnt--) {
619*4882a593Smuzhiyun 		msleep(1000);
620*4882a593Smuzhiyun 		barrier();
621*4882a593Smuzhiyun 	}
622*4882a593Smuzhiyun }
623*4882a593Smuzhiyun 
624*4882a593Smuzhiyun /**
625*4882a593Smuzhiyun  * qlafx00_soft_reset() - Soft Reset ISPFx00.
626*4882a593Smuzhiyun  * @vha: HA context
627*4882a593Smuzhiyun  *
628*4882a593Smuzhiyun  * Returns 0 on success.
629*4882a593Smuzhiyun  */
630*4882a593Smuzhiyun int
qlafx00_soft_reset(scsi_qla_host_t * vha)631*4882a593Smuzhiyun qlafx00_soft_reset(scsi_qla_host_t *vha)
632*4882a593Smuzhiyun {
633*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
634*4882a593Smuzhiyun 	int rval = QLA_FUNCTION_FAILED;
635*4882a593Smuzhiyun 
636*4882a593Smuzhiyun 	if (unlikely(pci_channel_offline(ha->pdev) &&
637*4882a593Smuzhiyun 	    ha->flags.pci_channel_io_perm_failure))
638*4882a593Smuzhiyun 		return rval;
639*4882a593Smuzhiyun 
640*4882a593Smuzhiyun 	ha->isp_ops->disable_intrs(ha);
641*4882a593Smuzhiyun 	qlafx00_soc_cpu_reset(vha);
642*4882a593Smuzhiyun 
643*4882a593Smuzhiyun 	return QLA_SUCCESS;
644*4882a593Smuzhiyun }
645*4882a593Smuzhiyun 
646*4882a593Smuzhiyun /**
647*4882a593Smuzhiyun  * qlafx00_chip_diag() - Test ISPFx00 for proper operation.
648*4882a593Smuzhiyun  * @vha: HA context
649*4882a593Smuzhiyun  *
650*4882a593Smuzhiyun  * Returns 0 on success.
651*4882a593Smuzhiyun  */
652*4882a593Smuzhiyun int
qlafx00_chip_diag(scsi_qla_host_t * vha)653*4882a593Smuzhiyun qlafx00_chip_diag(scsi_qla_host_t *vha)
654*4882a593Smuzhiyun {
655*4882a593Smuzhiyun 	int rval = 0;
656*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
657*4882a593Smuzhiyun 	struct req_que *req = ha->req_q_map[0];
658*4882a593Smuzhiyun 
659*4882a593Smuzhiyun 	ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun 	rval = qlafx00_mbx_reg_test(vha);
662*4882a593Smuzhiyun 	if (rval) {
663*4882a593Smuzhiyun 		ql_log(ql_log_warn, vha, 0x1165,
664*4882a593Smuzhiyun 		    "Failed mailbox send register test\n");
665*4882a593Smuzhiyun 	} else {
666*4882a593Smuzhiyun 		/* Flag a successful rval */
667*4882a593Smuzhiyun 		rval = QLA_SUCCESS;
668*4882a593Smuzhiyun 	}
669*4882a593Smuzhiyun 	return rval;
670*4882a593Smuzhiyun }
671*4882a593Smuzhiyun 
672*4882a593Smuzhiyun void
qlafx00_config_rings(struct scsi_qla_host * vha)673*4882a593Smuzhiyun qlafx00_config_rings(struct scsi_qla_host *vha)
674*4882a593Smuzhiyun {
675*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
676*4882a593Smuzhiyun 	struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
677*4882a593Smuzhiyun 
678*4882a593Smuzhiyun 	wrt_reg_dword(&reg->req_q_in, 0);
679*4882a593Smuzhiyun 	wrt_reg_dword(&reg->req_q_out, 0);
680*4882a593Smuzhiyun 
681*4882a593Smuzhiyun 	wrt_reg_dword(&reg->rsp_q_in, 0);
682*4882a593Smuzhiyun 	wrt_reg_dword(&reg->rsp_q_out, 0);
683*4882a593Smuzhiyun 
684*4882a593Smuzhiyun 	/* PCI posting */
685*4882a593Smuzhiyun 	rd_reg_dword(&reg->rsp_q_out);
686*4882a593Smuzhiyun }
687*4882a593Smuzhiyun 
688*4882a593Smuzhiyun char *
qlafx00_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)689*4882a593Smuzhiyun qlafx00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
690*4882a593Smuzhiyun {
691*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
692*4882a593Smuzhiyun 
693*4882a593Smuzhiyun 	if (pci_is_pcie(ha->pdev))
694*4882a593Smuzhiyun 		strlcpy(str, "PCIe iSA", str_len);
695*4882a593Smuzhiyun 	return str;
696*4882a593Smuzhiyun }
697*4882a593Smuzhiyun 
698*4882a593Smuzhiyun char *
qlafx00_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)699*4882a593Smuzhiyun qlafx00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
700*4882a593Smuzhiyun {
701*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
702*4882a593Smuzhiyun 
703*4882a593Smuzhiyun 	snprintf(str, size, "%s", ha->mr.fw_version);
704*4882a593Smuzhiyun 	return str;
705*4882a593Smuzhiyun }
706*4882a593Smuzhiyun 
707*4882a593Smuzhiyun void
qlafx00_enable_intrs(struct qla_hw_data * ha)708*4882a593Smuzhiyun qlafx00_enable_intrs(struct qla_hw_data *ha)
709*4882a593Smuzhiyun {
710*4882a593Smuzhiyun 	unsigned long flags = 0;
711*4882a593Smuzhiyun 
712*4882a593Smuzhiyun 	spin_lock_irqsave(&ha->hardware_lock, flags);
713*4882a593Smuzhiyun 	ha->interrupts_on = 1;
714*4882a593Smuzhiyun 	QLAFX00_ENABLE_ICNTRL_REG(ha);
715*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
716*4882a593Smuzhiyun }
717*4882a593Smuzhiyun 
718*4882a593Smuzhiyun void
qlafx00_disable_intrs(struct qla_hw_data * ha)719*4882a593Smuzhiyun qlafx00_disable_intrs(struct qla_hw_data *ha)
720*4882a593Smuzhiyun {
721*4882a593Smuzhiyun 	unsigned long flags = 0;
722*4882a593Smuzhiyun 
723*4882a593Smuzhiyun 	spin_lock_irqsave(&ha->hardware_lock, flags);
724*4882a593Smuzhiyun 	ha->interrupts_on = 0;
725*4882a593Smuzhiyun 	QLAFX00_DISABLE_ICNTRL_REG(ha);
726*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
727*4882a593Smuzhiyun }
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun int
qlafx00_abort_target(fc_port_t * fcport,uint64_t l,int tag)730*4882a593Smuzhiyun qlafx00_abort_target(fc_port_t *fcport, uint64_t l, int tag)
731*4882a593Smuzhiyun {
732*4882a593Smuzhiyun 	return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
733*4882a593Smuzhiyun }
734*4882a593Smuzhiyun 
735*4882a593Smuzhiyun int
qlafx00_lun_reset(fc_port_t * fcport,uint64_t l,int tag)736*4882a593Smuzhiyun qlafx00_lun_reset(fc_port_t *fcport, uint64_t l, int tag)
737*4882a593Smuzhiyun {
738*4882a593Smuzhiyun 	return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
739*4882a593Smuzhiyun }
740*4882a593Smuzhiyun 
741*4882a593Smuzhiyun int
qlafx00_iospace_config(struct qla_hw_data * ha)742*4882a593Smuzhiyun qlafx00_iospace_config(struct qla_hw_data *ha)
743*4882a593Smuzhiyun {
744*4882a593Smuzhiyun 	if (pci_request_selected_regions(ha->pdev, ha->bars,
745*4882a593Smuzhiyun 	    QLA2XXX_DRIVER_NAME)) {
746*4882a593Smuzhiyun 		ql_log_pci(ql_log_fatal, ha->pdev, 0x014e,
747*4882a593Smuzhiyun 		    "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
748*4882a593Smuzhiyun 		    pci_name(ha->pdev));
749*4882a593Smuzhiyun 		goto iospace_error_exit;
750*4882a593Smuzhiyun 	}
751*4882a593Smuzhiyun 
752*4882a593Smuzhiyun 	/* Use MMIO operations for all accesses. */
753*4882a593Smuzhiyun 	if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
754*4882a593Smuzhiyun 		ql_log_pci(ql_log_warn, ha->pdev, 0x014f,
755*4882a593Smuzhiyun 		    "Invalid pci I/O region size (%s).\n",
756*4882a593Smuzhiyun 		    pci_name(ha->pdev));
757*4882a593Smuzhiyun 		goto iospace_error_exit;
758*4882a593Smuzhiyun 	}
759*4882a593Smuzhiyun 	if (pci_resource_len(ha->pdev, 0) < BAR0_LEN_FX00) {
760*4882a593Smuzhiyun 		ql_log_pci(ql_log_warn, ha->pdev, 0x0127,
761*4882a593Smuzhiyun 		    "Invalid PCI mem BAR0 region size (%s), aborting\n",
762*4882a593Smuzhiyun 			pci_name(ha->pdev));
763*4882a593Smuzhiyun 		goto iospace_error_exit;
764*4882a593Smuzhiyun 	}
765*4882a593Smuzhiyun 
766*4882a593Smuzhiyun 	ha->cregbase =
767*4882a593Smuzhiyun 	    ioremap(pci_resource_start(ha->pdev, 0), BAR0_LEN_FX00);
768*4882a593Smuzhiyun 	if (!ha->cregbase) {
769*4882a593Smuzhiyun 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0128,
770*4882a593Smuzhiyun 		    "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
771*4882a593Smuzhiyun 		goto iospace_error_exit;
772*4882a593Smuzhiyun 	}
773*4882a593Smuzhiyun 
774*4882a593Smuzhiyun 	if (!(pci_resource_flags(ha->pdev, 2) & IORESOURCE_MEM)) {
775*4882a593Smuzhiyun 		ql_log_pci(ql_log_warn, ha->pdev, 0x0129,
776*4882a593Smuzhiyun 		    "region #2 not an MMIO resource (%s), aborting\n",
777*4882a593Smuzhiyun 		    pci_name(ha->pdev));
778*4882a593Smuzhiyun 		goto iospace_error_exit;
779*4882a593Smuzhiyun 	}
780*4882a593Smuzhiyun 	if (pci_resource_len(ha->pdev, 2) < BAR2_LEN_FX00) {
781*4882a593Smuzhiyun 		ql_log_pci(ql_log_warn, ha->pdev, 0x012a,
782*4882a593Smuzhiyun 		    "Invalid PCI mem BAR2 region size (%s), aborting\n",
783*4882a593Smuzhiyun 			pci_name(ha->pdev));
784*4882a593Smuzhiyun 		goto iospace_error_exit;
785*4882a593Smuzhiyun 	}
786*4882a593Smuzhiyun 
787*4882a593Smuzhiyun 	ha->iobase =
788*4882a593Smuzhiyun 	    ioremap(pci_resource_start(ha->pdev, 2), BAR2_LEN_FX00);
789*4882a593Smuzhiyun 	if (!ha->iobase) {
790*4882a593Smuzhiyun 		ql_log_pci(ql_log_fatal, ha->pdev, 0x012b,
791*4882a593Smuzhiyun 		    "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
792*4882a593Smuzhiyun 		goto iospace_error_exit;
793*4882a593Smuzhiyun 	}
794*4882a593Smuzhiyun 
795*4882a593Smuzhiyun 	/* Determine queue resources */
796*4882a593Smuzhiyun 	ha->max_req_queues = ha->max_rsp_queues = 1;
797*4882a593Smuzhiyun 
798*4882a593Smuzhiyun 	ql_log_pci(ql_log_info, ha->pdev, 0x012c,
799*4882a593Smuzhiyun 	    "Bars 0x%x, iobase0 0x%p, iobase2 0x%p\n",
800*4882a593Smuzhiyun 	    ha->bars, ha->cregbase, ha->iobase);
801*4882a593Smuzhiyun 
802*4882a593Smuzhiyun 	return 0;
803*4882a593Smuzhiyun 
804*4882a593Smuzhiyun iospace_error_exit:
805*4882a593Smuzhiyun 	return -ENOMEM;
806*4882a593Smuzhiyun }
807*4882a593Smuzhiyun 
808*4882a593Smuzhiyun static void
qlafx00_save_queue_ptrs(struct scsi_qla_host * vha)809*4882a593Smuzhiyun qlafx00_save_queue_ptrs(struct scsi_qla_host *vha)
810*4882a593Smuzhiyun {
811*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
812*4882a593Smuzhiyun 	struct req_que *req = ha->req_q_map[0];
813*4882a593Smuzhiyun 	struct rsp_que *rsp = ha->rsp_q_map[0];
814*4882a593Smuzhiyun 
815*4882a593Smuzhiyun 	req->length_fx00 = req->length;
816*4882a593Smuzhiyun 	req->ring_fx00 = req->ring;
817*4882a593Smuzhiyun 	req->dma_fx00 = req->dma;
818*4882a593Smuzhiyun 
819*4882a593Smuzhiyun 	rsp->length_fx00 = rsp->length;
820*4882a593Smuzhiyun 	rsp->ring_fx00 = rsp->ring;
821*4882a593Smuzhiyun 	rsp->dma_fx00 = rsp->dma;
822*4882a593Smuzhiyun 
823*4882a593Smuzhiyun 	ql_dbg(ql_dbg_init, vha, 0x012d,
824*4882a593Smuzhiyun 	    "req: %p, ring_fx00: %p, length_fx00: 0x%x,"
825*4882a593Smuzhiyun 	    "req->dma_fx00: 0x%llx\n", req, req->ring_fx00,
826*4882a593Smuzhiyun 	    req->length_fx00, (u64)req->dma_fx00);
827*4882a593Smuzhiyun 
828*4882a593Smuzhiyun 	ql_dbg(ql_dbg_init, vha, 0x012e,
829*4882a593Smuzhiyun 	    "rsp: %p, ring_fx00: %p, length_fx00: 0x%x,"
830*4882a593Smuzhiyun 	    "rsp->dma_fx00: 0x%llx\n", rsp, rsp->ring_fx00,
831*4882a593Smuzhiyun 	    rsp->length_fx00, (u64)rsp->dma_fx00);
832*4882a593Smuzhiyun }
833*4882a593Smuzhiyun 
834*4882a593Smuzhiyun static int
qlafx00_config_queues(struct scsi_qla_host * vha)835*4882a593Smuzhiyun qlafx00_config_queues(struct scsi_qla_host *vha)
836*4882a593Smuzhiyun {
837*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
838*4882a593Smuzhiyun 	struct req_que *req = ha->req_q_map[0];
839*4882a593Smuzhiyun 	struct rsp_que *rsp = ha->rsp_q_map[0];
840*4882a593Smuzhiyun 	dma_addr_t bar2_hdl = pci_resource_start(ha->pdev, 2);
841*4882a593Smuzhiyun 
842*4882a593Smuzhiyun 	req->length = ha->req_que_len;
843*4882a593Smuzhiyun 	req->ring = (void __force *)ha->iobase + ha->req_que_off;
844*4882a593Smuzhiyun 	req->dma = bar2_hdl + ha->req_que_off;
845*4882a593Smuzhiyun 	if ((!req->ring) || (req->length == 0)) {
846*4882a593Smuzhiyun 		ql_log_pci(ql_log_info, ha->pdev, 0x012f,
847*4882a593Smuzhiyun 		    "Unable to allocate memory for req_ring\n");
848*4882a593Smuzhiyun 		return QLA_FUNCTION_FAILED;
849*4882a593Smuzhiyun 	}
850*4882a593Smuzhiyun 
851*4882a593Smuzhiyun 	ql_dbg(ql_dbg_init, vha, 0x0130,
852*4882a593Smuzhiyun 	    "req: %p req_ring pointer %p req len 0x%x "
853*4882a593Smuzhiyun 	    "req off 0x%x\n, req->dma: 0x%llx",
854*4882a593Smuzhiyun 	    req, req->ring, req->length,
855*4882a593Smuzhiyun 	    ha->req_que_off, (u64)req->dma);
856*4882a593Smuzhiyun 
857*4882a593Smuzhiyun 	rsp->length = ha->rsp_que_len;
858*4882a593Smuzhiyun 	rsp->ring = (void __force *)ha->iobase + ha->rsp_que_off;
859*4882a593Smuzhiyun 	rsp->dma = bar2_hdl + ha->rsp_que_off;
860*4882a593Smuzhiyun 	if ((!rsp->ring) || (rsp->length == 0)) {
861*4882a593Smuzhiyun 		ql_log_pci(ql_log_info, ha->pdev, 0x0131,
862*4882a593Smuzhiyun 		    "Unable to allocate memory for rsp_ring\n");
863*4882a593Smuzhiyun 		return QLA_FUNCTION_FAILED;
864*4882a593Smuzhiyun 	}
865*4882a593Smuzhiyun 
866*4882a593Smuzhiyun 	ql_dbg(ql_dbg_init, vha, 0x0132,
867*4882a593Smuzhiyun 	    "rsp: %p rsp_ring pointer %p rsp len 0x%x "
868*4882a593Smuzhiyun 	    "rsp off 0x%x, rsp->dma: 0x%llx\n",
869*4882a593Smuzhiyun 	    rsp, rsp->ring, rsp->length,
870*4882a593Smuzhiyun 	    ha->rsp_que_off, (u64)rsp->dma);
871*4882a593Smuzhiyun 
872*4882a593Smuzhiyun 	return QLA_SUCCESS;
873*4882a593Smuzhiyun }
874*4882a593Smuzhiyun 
875*4882a593Smuzhiyun static int
qlafx00_init_fw_ready(scsi_qla_host_t * vha)876*4882a593Smuzhiyun qlafx00_init_fw_ready(scsi_qla_host_t *vha)
877*4882a593Smuzhiyun {
878*4882a593Smuzhiyun 	int rval = 0;
879*4882a593Smuzhiyun 	unsigned long wtime;
880*4882a593Smuzhiyun 	uint16_t wait_time;	/* Wait time */
881*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
882*4882a593Smuzhiyun 	struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
883*4882a593Smuzhiyun 	uint32_t aenmbx, aenmbx7 = 0;
884*4882a593Smuzhiyun 	uint32_t pseudo_aen;
885*4882a593Smuzhiyun 	uint32_t state[5];
886*4882a593Smuzhiyun 	bool done = false;
887*4882a593Smuzhiyun 
888*4882a593Smuzhiyun 	/* 30 seconds wait - Adjust if required */
889*4882a593Smuzhiyun 	wait_time = 30;
890*4882a593Smuzhiyun 
891*4882a593Smuzhiyun 	pseudo_aen = rd_reg_dword(&reg->pseudoaen);
892*4882a593Smuzhiyun 	if (pseudo_aen == 1) {
893*4882a593Smuzhiyun 		aenmbx7 = rd_reg_dword(&reg->initval7);
894*4882a593Smuzhiyun 		ha->mbx_intr_code = MSW(aenmbx7);
895*4882a593Smuzhiyun 		ha->rqstq_intr_code = LSW(aenmbx7);
896*4882a593Smuzhiyun 		rval = qlafx00_driver_shutdown(vha, 10);
897*4882a593Smuzhiyun 		if (rval != QLA_SUCCESS)
898*4882a593Smuzhiyun 			qlafx00_soft_reset(vha);
899*4882a593Smuzhiyun 	}
900*4882a593Smuzhiyun 
901*4882a593Smuzhiyun 	/* wait time before firmware ready */
902*4882a593Smuzhiyun 	wtime = jiffies + (wait_time * HZ);
903*4882a593Smuzhiyun 	do {
904*4882a593Smuzhiyun 		aenmbx = rd_reg_dword(&reg->aenmailbox0);
905*4882a593Smuzhiyun 		barrier();
906*4882a593Smuzhiyun 		ql_dbg(ql_dbg_mbx, vha, 0x0133,
907*4882a593Smuzhiyun 		    "aenmbx: 0x%x\n", aenmbx);
908*4882a593Smuzhiyun 
909*4882a593Smuzhiyun 		switch (aenmbx) {
910*4882a593Smuzhiyun 		case MBA_FW_NOT_STARTED:
911*4882a593Smuzhiyun 		case MBA_FW_STARTING:
912*4882a593Smuzhiyun 			break;
913*4882a593Smuzhiyun 
914*4882a593Smuzhiyun 		case MBA_SYSTEM_ERR:
915*4882a593Smuzhiyun 		case MBA_REQ_TRANSFER_ERR:
916*4882a593Smuzhiyun 		case MBA_RSP_TRANSFER_ERR:
917*4882a593Smuzhiyun 		case MBA_FW_INIT_FAILURE:
918*4882a593Smuzhiyun 			qlafx00_soft_reset(vha);
919*4882a593Smuzhiyun 			break;
920*4882a593Smuzhiyun 
921*4882a593Smuzhiyun 		case MBA_FW_RESTART_CMPLT:
922*4882a593Smuzhiyun 			/* Set the mbx and rqstq intr code */
923*4882a593Smuzhiyun 			aenmbx7 = rd_reg_dword(&reg->aenmailbox7);
924*4882a593Smuzhiyun 			ha->mbx_intr_code = MSW(aenmbx7);
925*4882a593Smuzhiyun 			ha->rqstq_intr_code = LSW(aenmbx7);
926*4882a593Smuzhiyun 			ha->req_que_off = rd_reg_dword(&reg->aenmailbox1);
927*4882a593Smuzhiyun 			ha->rsp_que_off = rd_reg_dword(&reg->aenmailbox3);
928*4882a593Smuzhiyun 			ha->req_que_len = rd_reg_dword(&reg->aenmailbox5);
929*4882a593Smuzhiyun 			ha->rsp_que_len = rd_reg_dword(&reg->aenmailbox6);
930*4882a593Smuzhiyun 			wrt_reg_dword(&reg->aenmailbox0, 0);
931*4882a593Smuzhiyun 			rd_reg_dword_relaxed(&reg->aenmailbox0);
932*4882a593Smuzhiyun 			ql_dbg(ql_dbg_init, vha, 0x0134,
933*4882a593Smuzhiyun 			    "f/w returned mbx_intr_code: 0x%x, "
934*4882a593Smuzhiyun 			    "rqstq_intr_code: 0x%x\n",
935*4882a593Smuzhiyun 			    ha->mbx_intr_code, ha->rqstq_intr_code);
936*4882a593Smuzhiyun 			QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
937*4882a593Smuzhiyun 			rval = QLA_SUCCESS;
938*4882a593Smuzhiyun 			done = true;
939*4882a593Smuzhiyun 			break;
940*4882a593Smuzhiyun 
941*4882a593Smuzhiyun 		default:
942*4882a593Smuzhiyun 			if ((aenmbx & 0xFF00) == MBA_FW_INIT_INPROGRESS)
943*4882a593Smuzhiyun 				break;
944*4882a593Smuzhiyun 
945*4882a593Smuzhiyun 			/* If fw is apparently not ready. In order to continue,
946*4882a593Smuzhiyun 			 * we might need to issue Mbox cmd, but the problem is
947*4882a593Smuzhiyun 			 * that the DoorBell vector values that come with the
948*4882a593Smuzhiyun 			 * 8060 AEN are most likely gone by now (and thus no
949*4882a593Smuzhiyun 			 * bell would be rung on the fw side when mbox cmd is
950*4882a593Smuzhiyun 			 * issued). We have to therefore grab the 8060 AEN
951*4882a593Smuzhiyun 			 * shadow regs (filled in by FW when the last 8060
952*4882a593Smuzhiyun 			 * AEN was being posted).
953*4882a593Smuzhiyun 			 * Do the following to determine what is needed in
954*4882a593Smuzhiyun 			 * order to get the FW ready:
955*4882a593Smuzhiyun 			 * 1. reload the 8060 AEN values from the shadow regs
956*4882a593Smuzhiyun 			 * 2. clear int status to get rid of possible pending
957*4882a593Smuzhiyun 			 *    interrupts
958*4882a593Smuzhiyun 			 * 3. issue Get FW State Mbox cmd to determine fw state
959*4882a593Smuzhiyun 			 * Set the mbx and rqstq intr code from Shadow Regs
960*4882a593Smuzhiyun 			 */
961*4882a593Smuzhiyun 			aenmbx7 = rd_reg_dword(&reg->initval7);
962*4882a593Smuzhiyun 			ha->mbx_intr_code = MSW(aenmbx7);
963*4882a593Smuzhiyun 			ha->rqstq_intr_code = LSW(aenmbx7);
964*4882a593Smuzhiyun 			ha->req_que_off = rd_reg_dword(&reg->initval1);
965*4882a593Smuzhiyun 			ha->rsp_que_off = rd_reg_dword(&reg->initval3);
966*4882a593Smuzhiyun 			ha->req_que_len = rd_reg_dword(&reg->initval5);
967*4882a593Smuzhiyun 			ha->rsp_que_len = rd_reg_dword(&reg->initval6);
968*4882a593Smuzhiyun 			ql_dbg(ql_dbg_init, vha, 0x0135,
969*4882a593Smuzhiyun 			    "f/w returned mbx_intr_code: 0x%x, "
970*4882a593Smuzhiyun 			    "rqstq_intr_code: 0x%x\n",
971*4882a593Smuzhiyun 			    ha->mbx_intr_code, ha->rqstq_intr_code);
972*4882a593Smuzhiyun 			QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
973*4882a593Smuzhiyun 
974*4882a593Smuzhiyun 			/* Get the FW state */
975*4882a593Smuzhiyun 			rval = qlafx00_get_firmware_state(vha, state);
976*4882a593Smuzhiyun 			if (rval != QLA_SUCCESS) {
977*4882a593Smuzhiyun 				/* Retry if timer has not expired */
978*4882a593Smuzhiyun 				break;
979*4882a593Smuzhiyun 			}
980*4882a593Smuzhiyun 
981*4882a593Smuzhiyun 			if (state[0] == FSTATE_FX00_CONFIG_WAIT) {
982*4882a593Smuzhiyun 				/* Firmware is waiting to be
983*4882a593Smuzhiyun 				 * initialized by driver
984*4882a593Smuzhiyun 				 */
985*4882a593Smuzhiyun 				rval = QLA_SUCCESS;
986*4882a593Smuzhiyun 				done = true;
987*4882a593Smuzhiyun 				break;
988*4882a593Smuzhiyun 			}
989*4882a593Smuzhiyun 
990*4882a593Smuzhiyun 			/* Issue driver shutdown and wait until f/w recovers.
991*4882a593Smuzhiyun 			 * Driver should continue to poll until 8060 AEN is
992*4882a593Smuzhiyun 			 * received indicating firmware recovery.
993*4882a593Smuzhiyun 			 */
994*4882a593Smuzhiyun 			ql_dbg(ql_dbg_init, vha, 0x0136,
995*4882a593Smuzhiyun 			    "Sending Driver shutdown fw_state 0x%x\n",
996*4882a593Smuzhiyun 			    state[0]);
997*4882a593Smuzhiyun 
998*4882a593Smuzhiyun 			rval = qlafx00_driver_shutdown(vha, 10);
999*4882a593Smuzhiyun 			if (rval != QLA_SUCCESS) {
1000*4882a593Smuzhiyun 				rval = QLA_FUNCTION_FAILED;
1001*4882a593Smuzhiyun 				break;
1002*4882a593Smuzhiyun 			}
1003*4882a593Smuzhiyun 			msleep(500);
1004*4882a593Smuzhiyun 
1005*4882a593Smuzhiyun 			wtime = jiffies + (wait_time * HZ);
1006*4882a593Smuzhiyun 			break;
1007*4882a593Smuzhiyun 		}
1008*4882a593Smuzhiyun 
1009*4882a593Smuzhiyun 		if (!done) {
1010*4882a593Smuzhiyun 			if (time_after_eq(jiffies, wtime)) {
1011*4882a593Smuzhiyun 				ql_dbg(ql_dbg_init, vha, 0x0137,
1012*4882a593Smuzhiyun 				    "Init f/w failed: aen[7]: 0x%x\n",
1013*4882a593Smuzhiyun 				    rd_reg_dword(&reg->aenmailbox7));
1014*4882a593Smuzhiyun 				rval = QLA_FUNCTION_FAILED;
1015*4882a593Smuzhiyun 				done = true;
1016*4882a593Smuzhiyun 				break;
1017*4882a593Smuzhiyun 			}
1018*4882a593Smuzhiyun 			/* Delay for a while */
1019*4882a593Smuzhiyun 			msleep(500);
1020*4882a593Smuzhiyun 		}
1021*4882a593Smuzhiyun 	} while (!done);
1022*4882a593Smuzhiyun 
1023*4882a593Smuzhiyun 	if (rval)
1024*4882a593Smuzhiyun 		ql_dbg(ql_dbg_init, vha, 0x0138,
1025*4882a593Smuzhiyun 		    "%s **** FAILED ****.\n", __func__);
1026*4882a593Smuzhiyun 	else
1027*4882a593Smuzhiyun 		ql_dbg(ql_dbg_init, vha, 0x0139,
1028*4882a593Smuzhiyun 		    "%s **** SUCCESS ****.\n", __func__);
1029*4882a593Smuzhiyun 
1030*4882a593Smuzhiyun 	return rval;
1031*4882a593Smuzhiyun }
1032*4882a593Smuzhiyun 
1033*4882a593Smuzhiyun /*
1034*4882a593Smuzhiyun  * qlafx00_fw_ready() - Waits for firmware ready.
1035*4882a593Smuzhiyun  * @ha: HA context
1036*4882a593Smuzhiyun  *
1037*4882a593Smuzhiyun  * Returns 0 on success.
1038*4882a593Smuzhiyun  */
1039*4882a593Smuzhiyun int
qlafx00_fw_ready(scsi_qla_host_t * vha)1040*4882a593Smuzhiyun qlafx00_fw_ready(scsi_qla_host_t *vha)
1041*4882a593Smuzhiyun {
1042*4882a593Smuzhiyun 	int		rval;
1043*4882a593Smuzhiyun 	unsigned long	wtime;
1044*4882a593Smuzhiyun 	uint16_t	wait_time;	/* Wait time if loop is coming ready */
1045*4882a593Smuzhiyun 	uint32_t	state[5];
1046*4882a593Smuzhiyun 
1047*4882a593Smuzhiyun 	rval = QLA_SUCCESS;
1048*4882a593Smuzhiyun 
1049*4882a593Smuzhiyun 	wait_time = 10;
1050*4882a593Smuzhiyun 
1051*4882a593Smuzhiyun 	/* wait time before firmware ready */
1052*4882a593Smuzhiyun 	wtime = jiffies + (wait_time * HZ);
1053*4882a593Smuzhiyun 
1054*4882a593Smuzhiyun 	/* Wait for ISP to finish init */
1055*4882a593Smuzhiyun 	if (!vha->flags.init_done)
1056*4882a593Smuzhiyun 		ql_dbg(ql_dbg_init, vha, 0x013a,
1057*4882a593Smuzhiyun 		    "Waiting for init to complete...\n");
1058*4882a593Smuzhiyun 
1059*4882a593Smuzhiyun 	do {
1060*4882a593Smuzhiyun 		rval = qlafx00_get_firmware_state(vha, state);
1061*4882a593Smuzhiyun 
1062*4882a593Smuzhiyun 		if (rval == QLA_SUCCESS) {
1063*4882a593Smuzhiyun 			if (state[0] == FSTATE_FX00_INITIALIZED) {
1064*4882a593Smuzhiyun 				ql_dbg(ql_dbg_init, vha, 0x013b,
1065*4882a593Smuzhiyun 				    "fw_state=%x\n", state[0]);
1066*4882a593Smuzhiyun 				rval = QLA_SUCCESS;
1067*4882a593Smuzhiyun 					break;
1068*4882a593Smuzhiyun 			}
1069*4882a593Smuzhiyun 		}
1070*4882a593Smuzhiyun 		rval = QLA_FUNCTION_FAILED;
1071*4882a593Smuzhiyun 
1072*4882a593Smuzhiyun 		if (time_after_eq(jiffies, wtime))
1073*4882a593Smuzhiyun 			break;
1074*4882a593Smuzhiyun 
1075*4882a593Smuzhiyun 		/* Delay for a while */
1076*4882a593Smuzhiyun 		msleep(500);
1077*4882a593Smuzhiyun 
1078*4882a593Smuzhiyun 		ql_dbg(ql_dbg_init, vha, 0x013c,
1079*4882a593Smuzhiyun 		    "fw_state=%x curr time=%lx.\n", state[0], jiffies);
1080*4882a593Smuzhiyun 	} while (1);
1081*4882a593Smuzhiyun 
1082*4882a593Smuzhiyun 
1083*4882a593Smuzhiyun 	if (rval)
1084*4882a593Smuzhiyun 		ql_dbg(ql_dbg_init, vha, 0x013d,
1085*4882a593Smuzhiyun 		    "Firmware ready **** FAILED ****.\n");
1086*4882a593Smuzhiyun 	else
1087*4882a593Smuzhiyun 		ql_dbg(ql_dbg_init, vha, 0x013e,
1088*4882a593Smuzhiyun 		    "Firmware ready **** SUCCESS ****.\n");
1089*4882a593Smuzhiyun 
1090*4882a593Smuzhiyun 	return rval;
1091*4882a593Smuzhiyun }
1092*4882a593Smuzhiyun 
1093*4882a593Smuzhiyun static int
qlafx00_find_all_targets(scsi_qla_host_t * vha,struct list_head * new_fcports)1094*4882a593Smuzhiyun qlafx00_find_all_targets(scsi_qla_host_t *vha,
1095*4882a593Smuzhiyun 	struct list_head *new_fcports)
1096*4882a593Smuzhiyun {
1097*4882a593Smuzhiyun 	int		rval;
1098*4882a593Smuzhiyun 	uint16_t	tgt_id;
1099*4882a593Smuzhiyun 	fc_port_t	*fcport, *new_fcport;
1100*4882a593Smuzhiyun 	int		found;
1101*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
1102*4882a593Smuzhiyun 
1103*4882a593Smuzhiyun 	rval = QLA_SUCCESS;
1104*4882a593Smuzhiyun 
1105*4882a593Smuzhiyun 	if (!test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
1106*4882a593Smuzhiyun 		return QLA_FUNCTION_FAILED;
1107*4882a593Smuzhiyun 
1108*4882a593Smuzhiyun 	if ((atomic_read(&vha->loop_down_timer) ||
1109*4882a593Smuzhiyun 	     STATE_TRANSITION(vha))) {
1110*4882a593Smuzhiyun 		atomic_set(&vha->loop_down_timer, 0);
1111*4882a593Smuzhiyun 		set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1112*4882a593Smuzhiyun 		return QLA_FUNCTION_FAILED;
1113*4882a593Smuzhiyun 	}
1114*4882a593Smuzhiyun 
1115*4882a593Smuzhiyun 	ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x2088,
1116*4882a593Smuzhiyun 	    "Listing Target bit map...\n");
1117*4882a593Smuzhiyun 	ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha, 0x2089,
1118*4882a593Smuzhiyun 	    ha->gid_list, 32);
1119*4882a593Smuzhiyun 
1120*4882a593Smuzhiyun 	/* Allocate temporary rmtport for any new rmtports discovered. */
1121*4882a593Smuzhiyun 	new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1122*4882a593Smuzhiyun 	if (new_fcport == NULL)
1123*4882a593Smuzhiyun 		return QLA_MEMORY_ALLOC_FAILED;
1124*4882a593Smuzhiyun 
1125*4882a593Smuzhiyun 	for_each_set_bit(tgt_id, (void *)ha->gid_list,
1126*4882a593Smuzhiyun 	    QLAFX00_TGT_NODE_LIST_SIZE) {
1127*4882a593Smuzhiyun 
1128*4882a593Smuzhiyun 		/* Send get target node info */
1129*4882a593Smuzhiyun 		new_fcport->tgt_id = tgt_id;
1130*4882a593Smuzhiyun 		rval = qlafx00_fx_disc(vha, new_fcport,
1131*4882a593Smuzhiyun 		    FXDISC_GET_TGT_NODE_INFO);
1132*4882a593Smuzhiyun 		if (rval != QLA_SUCCESS) {
1133*4882a593Smuzhiyun 			ql_log(ql_log_warn, vha, 0x208a,
1134*4882a593Smuzhiyun 			    "Target info scan failed -- assuming zero-entry "
1135*4882a593Smuzhiyun 			    "result...\n");
1136*4882a593Smuzhiyun 			continue;
1137*4882a593Smuzhiyun 		}
1138*4882a593Smuzhiyun 
1139*4882a593Smuzhiyun 		/* Locate matching device in database. */
1140*4882a593Smuzhiyun 		found = 0;
1141*4882a593Smuzhiyun 		list_for_each_entry(fcport, &vha->vp_fcports, list) {
1142*4882a593Smuzhiyun 			if (memcmp(new_fcport->port_name,
1143*4882a593Smuzhiyun 			    fcport->port_name, WWN_SIZE))
1144*4882a593Smuzhiyun 				continue;
1145*4882a593Smuzhiyun 
1146*4882a593Smuzhiyun 			found++;
1147*4882a593Smuzhiyun 
1148*4882a593Smuzhiyun 			/*
1149*4882a593Smuzhiyun 			 * If tgt_id is same and state FCS_ONLINE, nothing
1150*4882a593Smuzhiyun 			 * changed.
1151*4882a593Smuzhiyun 			 */
1152*4882a593Smuzhiyun 			if (fcport->tgt_id == new_fcport->tgt_id &&
1153*4882a593Smuzhiyun 			    atomic_read(&fcport->state) == FCS_ONLINE)
1154*4882a593Smuzhiyun 				break;
1155*4882a593Smuzhiyun 
1156*4882a593Smuzhiyun 			/*
1157*4882a593Smuzhiyun 			 * Tgt ID changed or device was marked to be updated.
1158*4882a593Smuzhiyun 			 */
1159*4882a593Smuzhiyun 			ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x208b,
1160*4882a593Smuzhiyun 			    "TGT-ID Change(%s): Present tgt id: "
1161*4882a593Smuzhiyun 			    "0x%x state: 0x%x "
1162*4882a593Smuzhiyun 			    "wwnn = %llx wwpn = %llx.\n",
1163*4882a593Smuzhiyun 			    __func__, fcport->tgt_id,
1164*4882a593Smuzhiyun 			    atomic_read(&fcport->state),
1165*4882a593Smuzhiyun 			    (unsigned long long)wwn_to_u64(fcport->node_name),
1166*4882a593Smuzhiyun 			    (unsigned long long)wwn_to_u64(fcport->port_name));
1167*4882a593Smuzhiyun 
1168*4882a593Smuzhiyun 			ql_log(ql_log_info, vha, 0x208c,
1169*4882a593Smuzhiyun 			    "TGT-ID Announce(%s): Discovered tgt "
1170*4882a593Smuzhiyun 			    "id 0x%x wwnn = %llx "
1171*4882a593Smuzhiyun 			    "wwpn = %llx.\n", __func__, new_fcport->tgt_id,
1172*4882a593Smuzhiyun 			    (unsigned long long)
1173*4882a593Smuzhiyun 			    wwn_to_u64(new_fcport->node_name),
1174*4882a593Smuzhiyun 			    (unsigned long long)
1175*4882a593Smuzhiyun 			    wwn_to_u64(new_fcport->port_name));
1176*4882a593Smuzhiyun 
1177*4882a593Smuzhiyun 			if (atomic_read(&fcport->state) != FCS_ONLINE) {
1178*4882a593Smuzhiyun 				fcport->old_tgt_id = fcport->tgt_id;
1179*4882a593Smuzhiyun 				fcport->tgt_id = new_fcport->tgt_id;
1180*4882a593Smuzhiyun 				ql_log(ql_log_info, vha, 0x208d,
1181*4882a593Smuzhiyun 				   "TGT-ID: New fcport Added: %p\n", fcport);
1182*4882a593Smuzhiyun 				qla2x00_update_fcport(vha, fcport);
1183*4882a593Smuzhiyun 			} else {
1184*4882a593Smuzhiyun 				ql_log(ql_log_info, vha, 0x208e,
1185*4882a593Smuzhiyun 				    " Existing TGT-ID %x did not get "
1186*4882a593Smuzhiyun 				    " offline event from firmware.\n",
1187*4882a593Smuzhiyun 				    fcport->old_tgt_id);
1188*4882a593Smuzhiyun 				qla2x00_mark_device_lost(vha, fcport, 0);
1189*4882a593Smuzhiyun 				set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1190*4882a593Smuzhiyun 				qla2x00_free_fcport(new_fcport);
1191*4882a593Smuzhiyun 				return rval;
1192*4882a593Smuzhiyun 			}
1193*4882a593Smuzhiyun 			break;
1194*4882a593Smuzhiyun 		}
1195*4882a593Smuzhiyun 
1196*4882a593Smuzhiyun 		if (found)
1197*4882a593Smuzhiyun 			continue;
1198*4882a593Smuzhiyun 
1199*4882a593Smuzhiyun 		/* If device was not in our fcports list, then add it. */
1200*4882a593Smuzhiyun 		list_add_tail(&new_fcport->list, new_fcports);
1201*4882a593Smuzhiyun 
1202*4882a593Smuzhiyun 		/* Allocate a new replacement fcport. */
1203*4882a593Smuzhiyun 		new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1204*4882a593Smuzhiyun 		if (new_fcport == NULL)
1205*4882a593Smuzhiyun 			return QLA_MEMORY_ALLOC_FAILED;
1206*4882a593Smuzhiyun 	}
1207*4882a593Smuzhiyun 
1208*4882a593Smuzhiyun 	qla2x00_free_fcport(new_fcport);
1209*4882a593Smuzhiyun 	return rval;
1210*4882a593Smuzhiyun }
1211*4882a593Smuzhiyun 
1212*4882a593Smuzhiyun /*
1213*4882a593Smuzhiyun  * qlafx00_configure_all_targets
1214*4882a593Smuzhiyun  *      Setup target devices with node ID's.
1215*4882a593Smuzhiyun  *
1216*4882a593Smuzhiyun  * Input:
1217*4882a593Smuzhiyun  *      ha = adapter block pointer.
1218*4882a593Smuzhiyun  *
1219*4882a593Smuzhiyun  * Returns:
1220*4882a593Smuzhiyun  *      0 = success.
1221*4882a593Smuzhiyun  *      BIT_0 = error
1222*4882a593Smuzhiyun  */
1223*4882a593Smuzhiyun static int
qlafx00_configure_all_targets(scsi_qla_host_t * vha)1224*4882a593Smuzhiyun qlafx00_configure_all_targets(scsi_qla_host_t *vha)
1225*4882a593Smuzhiyun {
1226*4882a593Smuzhiyun 	int rval;
1227*4882a593Smuzhiyun 	fc_port_t *fcport, *rmptemp;
1228*4882a593Smuzhiyun 	LIST_HEAD(new_fcports);
1229*4882a593Smuzhiyun 
1230*4882a593Smuzhiyun 	rval = qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1231*4882a593Smuzhiyun 	    FXDISC_GET_TGT_NODE_LIST);
1232*4882a593Smuzhiyun 	if (rval != QLA_SUCCESS) {
1233*4882a593Smuzhiyun 		set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1234*4882a593Smuzhiyun 		return rval;
1235*4882a593Smuzhiyun 	}
1236*4882a593Smuzhiyun 
1237*4882a593Smuzhiyun 	rval = qlafx00_find_all_targets(vha, &new_fcports);
1238*4882a593Smuzhiyun 	if (rval != QLA_SUCCESS) {
1239*4882a593Smuzhiyun 		set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1240*4882a593Smuzhiyun 		return rval;
1241*4882a593Smuzhiyun 	}
1242*4882a593Smuzhiyun 
1243*4882a593Smuzhiyun 	/*
1244*4882a593Smuzhiyun 	 * Delete all previous devices marked lost.
1245*4882a593Smuzhiyun 	 */
1246*4882a593Smuzhiyun 	list_for_each_entry(fcport, &vha->vp_fcports, list) {
1247*4882a593Smuzhiyun 		if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1248*4882a593Smuzhiyun 			break;
1249*4882a593Smuzhiyun 
1250*4882a593Smuzhiyun 		if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) {
1251*4882a593Smuzhiyun 			if (fcport->port_type != FCT_INITIATOR)
1252*4882a593Smuzhiyun 				qla2x00_mark_device_lost(vha, fcport, 0);
1253*4882a593Smuzhiyun 		}
1254*4882a593Smuzhiyun 	}
1255*4882a593Smuzhiyun 
1256*4882a593Smuzhiyun 	/*
1257*4882a593Smuzhiyun 	 * Add the new devices to our devices list.
1258*4882a593Smuzhiyun 	 */
1259*4882a593Smuzhiyun 	list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
1260*4882a593Smuzhiyun 		if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1261*4882a593Smuzhiyun 			break;
1262*4882a593Smuzhiyun 
1263*4882a593Smuzhiyun 		qla2x00_update_fcport(vha, fcport);
1264*4882a593Smuzhiyun 		list_move_tail(&fcport->list, &vha->vp_fcports);
1265*4882a593Smuzhiyun 		ql_log(ql_log_info, vha, 0x208f,
1266*4882a593Smuzhiyun 		    "Attach new target id 0x%x wwnn = %llx "
1267*4882a593Smuzhiyun 		    "wwpn = %llx.\n",
1268*4882a593Smuzhiyun 		    fcport->tgt_id,
1269*4882a593Smuzhiyun 		    (unsigned long long)wwn_to_u64(fcport->node_name),
1270*4882a593Smuzhiyun 		    (unsigned long long)wwn_to_u64(fcport->port_name));
1271*4882a593Smuzhiyun 	}
1272*4882a593Smuzhiyun 
1273*4882a593Smuzhiyun 	/* Free all new device structures not processed. */
1274*4882a593Smuzhiyun 	list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
1275*4882a593Smuzhiyun 		list_del(&fcport->list);
1276*4882a593Smuzhiyun 		qla2x00_free_fcport(fcport);
1277*4882a593Smuzhiyun 	}
1278*4882a593Smuzhiyun 
1279*4882a593Smuzhiyun 	return rval;
1280*4882a593Smuzhiyun }
1281*4882a593Smuzhiyun 
1282*4882a593Smuzhiyun /*
1283*4882a593Smuzhiyun  * qlafx00_configure_devices
1284*4882a593Smuzhiyun  *      Updates Fibre Channel Device Database with what is actually on loop.
1285*4882a593Smuzhiyun  *
1286*4882a593Smuzhiyun  * Input:
1287*4882a593Smuzhiyun  *      ha                = adapter block pointer.
1288*4882a593Smuzhiyun  *
1289*4882a593Smuzhiyun  * Returns:
1290*4882a593Smuzhiyun  *      0 = success.
1291*4882a593Smuzhiyun  *      1 = error.
1292*4882a593Smuzhiyun  *      2 = database was full and device was not configured.
1293*4882a593Smuzhiyun  */
1294*4882a593Smuzhiyun int
qlafx00_configure_devices(scsi_qla_host_t * vha)1295*4882a593Smuzhiyun qlafx00_configure_devices(scsi_qla_host_t *vha)
1296*4882a593Smuzhiyun {
1297*4882a593Smuzhiyun 	int  rval;
1298*4882a593Smuzhiyun 	unsigned long flags;
1299*4882a593Smuzhiyun 
1300*4882a593Smuzhiyun 	rval = QLA_SUCCESS;
1301*4882a593Smuzhiyun 
1302*4882a593Smuzhiyun 	flags = vha->dpc_flags;
1303*4882a593Smuzhiyun 
1304*4882a593Smuzhiyun 	ql_dbg(ql_dbg_disc, vha, 0x2090,
1305*4882a593Smuzhiyun 	    "Configure devices -- dpc flags =0x%lx\n", flags);
1306*4882a593Smuzhiyun 
1307*4882a593Smuzhiyun 	rval = qlafx00_configure_all_targets(vha);
1308*4882a593Smuzhiyun 
1309*4882a593Smuzhiyun 	if (rval == QLA_SUCCESS) {
1310*4882a593Smuzhiyun 		if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1311*4882a593Smuzhiyun 			rval = QLA_FUNCTION_FAILED;
1312*4882a593Smuzhiyun 		} else {
1313*4882a593Smuzhiyun 			atomic_set(&vha->loop_state, LOOP_READY);
1314*4882a593Smuzhiyun 			ql_log(ql_log_info, vha, 0x2091,
1315*4882a593Smuzhiyun 			    "Device Ready\n");
1316*4882a593Smuzhiyun 		}
1317*4882a593Smuzhiyun 	}
1318*4882a593Smuzhiyun 
1319*4882a593Smuzhiyun 	if (rval) {
1320*4882a593Smuzhiyun 		ql_dbg(ql_dbg_disc, vha, 0x2092,
1321*4882a593Smuzhiyun 		    "%s *** FAILED ***.\n", __func__);
1322*4882a593Smuzhiyun 	} else {
1323*4882a593Smuzhiyun 		ql_dbg(ql_dbg_disc, vha, 0x2093,
1324*4882a593Smuzhiyun 		    "%s: exiting normally.\n", __func__);
1325*4882a593Smuzhiyun 	}
1326*4882a593Smuzhiyun 	return rval;
1327*4882a593Smuzhiyun }
1328*4882a593Smuzhiyun 
1329*4882a593Smuzhiyun static void
qlafx00_abort_isp_cleanup(scsi_qla_host_t * vha,bool critemp)1330*4882a593Smuzhiyun qlafx00_abort_isp_cleanup(scsi_qla_host_t *vha, bool critemp)
1331*4882a593Smuzhiyun {
1332*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
1333*4882a593Smuzhiyun 	fc_port_t *fcport;
1334*4882a593Smuzhiyun 
1335*4882a593Smuzhiyun 	vha->flags.online = 0;
1336*4882a593Smuzhiyun 	ha->mr.fw_hbt_en = 0;
1337*4882a593Smuzhiyun 
1338*4882a593Smuzhiyun 	if (!critemp) {
1339*4882a593Smuzhiyun 		ha->flags.chip_reset_done = 0;
1340*4882a593Smuzhiyun 		clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1341*4882a593Smuzhiyun 		vha->qla_stats.total_isp_aborts++;
1342*4882a593Smuzhiyun 		ql_log(ql_log_info, vha, 0x013f,
1343*4882a593Smuzhiyun 		    "Performing ISP error recovery - ha = %p.\n", ha);
1344*4882a593Smuzhiyun 		ha->isp_ops->reset_chip(vha);
1345*4882a593Smuzhiyun 	}
1346*4882a593Smuzhiyun 
1347*4882a593Smuzhiyun 	if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
1348*4882a593Smuzhiyun 		atomic_set(&vha->loop_state, LOOP_DOWN);
1349*4882a593Smuzhiyun 		atomic_set(&vha->loop_down_timer,
1350*4882a593Smuzhiyun 		    QLAFX00_LOOP_DOWN_TIME);
1351*4882a593Smuzhiyun 	} else {
1352*4882a593Smuzhiyun 		if (!atomic_read(&vha->loop_down_timer))
1353*4882a593Smuzhiyun 			atomic_set(&vha->loop_down_timer,
1354*4882a593Smuzhiyun 			    QLAFX00_LOOP_DOWN_TIME);
1355*4882a593Smuzhiyun 	}
1356*4882a593Smuzhiyun 
1357*4882a593Smuzhiyun 	/* Clear all async request states across all VPs. */
1358*4882a593Smuzhiyun 	list_for_each_entry(fcport, &vha->vp_fcports, list) {
1359*4882a593Smuzhiyun 		fcport->flags = 0;
1360*4882a593Smuzhiyun 		if (atomic_read(&fcport->state) == FCS_ONLINE)
1361*4882a593Smuzhiyun 			qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1362*4882a593Smuzhiyun 	}
1363*4882a593Smuzhiyun 
1364*4882a593Smuzhiyun 	if (!ha->flags.eeh_busy) {
1365*4882a593Smuzhiyun 		if (critemp) {
1366*4882a593Smuzhiyun 			qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
1367*4882a593Smuzhiyun 		} else {
1368*4882a593Smuzhiyun 			/* Requeue all commands in outstanding command list. */
1369*4882a593Smuzhiyun 			qla2x00_abort_all_cmds(vha, DID_RESET << 16);
1370*4882a593Smuzhiyun 		}
1371*4882a593Smuzhiyun 	}
1372*4882a593Smuzhiyun 
1373*4882a593Smuzhiyun 	qla2x00_free_irqs(vha);
1374*4882a593Smuzhiyun 	if (critemp)
1375*4882a593Smuzhiyun 		set_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags);
1376*4882a593Smuzhiyun 	else
1377*4882a593Smuzhiyun 		set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
1378*4882a593Smuzhiyun 
1379*4882a593Smuzhiyun 	/* Clear the Interrupts */
1380*4882a593Smuzhiyun 	QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
1381*4882a593Smuzhiyun 
1382*4882a593Smuzhiyun 	ql_log(ql_log_info, vha, 0x0140,
1383*4882a593Smuzhiyun 	    "%s Done done - ha=%p.\n", __func__, ha);
1384*4882a593Smuzhiyun }
1385*4882a593Smuzhiyun 
1386*4882a593Smuzhiyun /**
1387*4882a593Smuzhiyun  * qlafx00_init_response_q_entries() - Initializes response queue entries.
1388*4882a593Smuzhiyun  * @rsp: response queue
1389*4882a593Smuzhiyun  *
1390*4882a593Smuzhiyun  * Beginning of request ring has initialization control block already built
1391*4882a593Smuzhiyun  * by nvram config routine.
1392*4882a593Smuzhiyun  *
1393*4882a593Smuzhiyun  * Returns 0 on success.
1394*4882a593Smuzhiyun  */
1395*4882a593Smuzhiyun void
qlafx00_init_response_q_entries(struct rsp_que * rsp)1396*4882a593Smuzhiyun qlafx00_init_response_q_entries(struct rsp_que *rsp)
1397*4882a593Smuzhiyun {
1398*4882a593Smuzhiyun 	uint16_t cnt;
1399*4882a593Smuzhiyun 	response_t *pkt;
1400*4882a593Smuzhiyun 
1401*4882a593Smuzhiyun 	rsp->ring_ptr = rsp->ring;
1402*4882a593Smuzhiyun 	rsp->ring_index    = 0;
1403*4882a593Smuzhiyun 	rsp->status_srb = NULL;
1404*4882a593Smuzhiyun 	pkt = rsp->ring_ptr;
1405*4882a593Smuzhiyun 	for (cnt = 0; cnt < rsp->length; cnt++) {
1406*4882a593Smuzhiyun 		pkt->signature = RESPONSE_PROCESSED;
1407*4882a593Smuzhiyun 		wrt_reg_dword((void __force __iomem *)&pkt->signature,
1408*4882a593Smuzhiyun 		    RESPONSE_PROCESSED);
1409*4882a593Smuzhiyun 		pkt++;
1410*4882a593Smuzhiyun 	}
1411*4882a593Smuzhiyun }
1412*4882a593Smuzhiyun 
1413*4882a593Smuzhiyun int
qlafx00_rescan_isp(scsi_qla_host_t * vha)1414*4882a593Smuzhiyun qlafx00_rescan_isp(scsi_qla_host_t *vha)
1415*4882a593Smuzhiyun {
1416*4882a593Smuzhiyun 	uint32_t status = QLA_FUNCTION_FAILED;
1417*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
1418*4882a593Smuzhiyun 	struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
1419*4882a593Smuzhiyun 	uint32_t aenmbx7;
1420*4882a593Smuzhiyun 
1421*4882a593Smuzhiyun 	qla2x00_request_irqs(ha, ha->rsp_q_map[0]);
1422*4882a593Smuzhiyun 
1423*4882a593Smuzhiyun 	aenmbx7 = rd_reg_dword(&reg->aenmailbox7);
1424*4882a593Smuzhiyun 	ha->mbx_intr_code = MSW(aenmbx7);
1425*4882a593Smuzhiyun 	ha->rqstq_intr_code = LSW(aenmbx7);
1426*4882a593Smuzhiyun 	ha->req_que_off = rd_reg_dword(&reg->aenmailbox1);
1427*4882a593Smuzhiyun 	ha->rsp_que_off = rd_reg_dword(&reg->aenmailbox3);
1428*4882a593Smuzhiyun 	ha->req_que_len = rd_reg_dword(&reg->aenmailbox5);
1429*4882a593Smuzhiyun 	ha->rsp_que_len = rd_reg_dword(&reg->aenmailbox6);
1430*4882a593Smuzhiyun 
1431*4882a593Smuzhiyun 	ql_dbg(ql_dbg_disc, vha, 0x2094,
1432*4882a593Smuzhiyun 	    "fw returned mbx_intr_code: 0x%x, rqstq_intr_code: 0x%x "
1433*4882a593Smuzhiyun 	    " Req que offset 0x%x Rsp que offset 0x%x\n",
1434*4882a593Smuzhiyun 	    ha->mbx_intr_code, ha->rqstq_intr_code,
1435*4882a593Smuzhiyun 	    ha->req_que_off, ha->rsp_que_len);
1436*4882a593Smuzhiyun 
1437*4882a593Smuzhiyun 	/* Clear the Interrupts */
1438*4882a593Smuzhiyun 	QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
1439*4882a593Smuzhiyun 
1440*4882a593Smuzhiyun 	status = qla2x00_init_rings(vha);
1441*4882a593Smuzhiyun 	if (!status) {
1442*4882a593Smuzhiyun 		vha->flags.online = 1;
1443*4882a593Smuzhiyun 
1444*4882a593Smuzhiyun 		/* if no cable then assume it's good */
1445*4882a593Smuzhiyun 		if ((vha->device_flags & DFLG_NO_CABLE))
1446*4882a593Smuzhiyun 			status = 0;
1447*4882a593Smuzhiyun 		/* Register system information */
1448*4882a593Smuzhiyun 		if (qlafx00_fx_disc(vha,
1449*4882a593Smuzhiyun 		    &vha->hw->mr.fcport, FXDISC_REG_HOST_INFO))
1450*4882a593Smuzhiyun 			ql_dbg(ql_dbg_disc, vha, 0x2095,
1451*4882a593Smuzhiyun 			    "failed to register host info\n");
1452*4882a593Smuzhiyun 	}
1453*4882a593Smuzhiyun 	scsi_unblock_requests(vha->host);
1454*4882a593Smuzhiyun 	return status;
1455*4882a593Smuzhiyun }
1456*4882a593Smuzhiyun 
1457*4882a593Smuzhiyun void
qlafx00_timer_routine(scsi_qla_host_t * vha)1458*4882a593Smuzhiyun qlafx00_timer_routine(scsi_qla_host_t *vha)
1459*4882a593Smuzhiyun {
1460*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
1461*4882a593Smuzhiyun 	uint32_t fw_heart_beat;
1462*4882a593Smuzhiyun 	uint32_t aenmbx0;
1463*4882a593Smuzhiyun 	struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
1464*4882a593Smuzhiyun 	uint32_t tempc;
1465*4882a593Smuzhiyun 
1466*4882a593Smuzhiyun 	/* Check firmware health */
1467*4882a593Smuzhiyun 	if (ha->mr.fw_hbt_cnt)
1468*4882a593Smuzhiyun 		ha->mr.fw_hbt_cnt--;
1469*4882a593Smuzhiyun 	else {
1470*4882a593Smuzhiyun 		if ((!ha->flags.mr_reset_hdlr_active) &&
1471*4882a593Smuzhiyun 		    (!test_bit(UNLOADING, &vha->dpc_flags)) &&
1472*4882a593Smuzhiyun 		    (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
1473*4882a593Smuzhiyun 		    (ha->mr.fw_hbt_en)) {
1474*4882a593Smuzhiyun 			fw_heart_beat = rd_reg_dword(&reg->fwheartbeat);
1475*4882a593Smuzhiyun 			if (fw_heart_beat != ha->mr.old_fw_hbt_cnt) {
1476*4882a593Smuzhiyun 				ha->mr.old_fw_hbt_cnt = fw_heart_beat;
1477*4882a593Smuzhiyun 				ha->mr.fw_hbt_miss_cnt = 0;
1478*4882a593Smuzhiyun 			} else {
1479*4882a593Smuzhiyun 				ha->mr.fw_hbt_miss_cnt++;
1480*4882a593Smuzhiyun 				if (ha->mr.fw_hbt_miss_cnt ==
1481*4882a593Smuzhiyun 				    QLAFX00_HEARTBEAT_MISS_CNT) {
1482*4882a593Smuzhiyun 					set_bit(ISP_ABORT_NEEDED,
1483*4882a593Smuzhiyun 					    &vha->dpc_flags);
1484*4882a593Smuzhiyun 					qla2xxx_wake_dpc(vha);
1485*4882a593Smuzhiyun 					ha->mr.fw_hbt_miss_cnt = 0;
1486*4882a593Smuzhiyun 				}
1487*4882a593Smuzhiyun 			}
1488*4882a593Smuzhiyun 		}
1489*4882a593Smuzhiyun 		ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
1490*4882a593Smuzhiyun 	}
1491*4882a593Smuzhiyun 
1492*4882a593Smuzhiyun 	if (test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags)) {
1493*4882a593Smuzhiyun 		/* Reset recovery to be performed in timer routine */
1494*4882a593Smuzhiyun 		aenmbx0 = rd_reg_dword(&reg->aenmailbox0);
1495*4882a593Smuzhiyun 		if (ha->mr.fw_reset_timer_exp) {
1496*4882a593Smuzhiyun 			set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1497*4882a593Smuzhiyun 			qla2xxx_wake_dpc(vha);
1498*4882a593Smuzhiyun 			ha->mr.fw_reset_timer_exp = 0;
1499*4882a593Smuzhiyun 		} else if (aenmbx0 == MBA_FW_RESTART_CMPLT) {
1500*4882a593Smuzhiyun 			/* Wake up DPC to rescan the targets */
1501*4882a593Smuzhiyun 			set_bit(FX00_TARGET_SCAN, &vha->dpc_flags);
1502*4882a593Smuzhiyun 			clear_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
1503*4882a593Smuzhiyun 			qla2xxx_wake_dpc(vha);
1504*4882a593Smuzhiyun 			ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
1505*4882a593Smuzhiyun 		} else if ((aenmbx0 == MBA_FW_STARTING) &&
1506*4882a593Smuzhiyun 		    (!ha->mr.fw_hbt_en)) {
1507*4882a593Smuzhiyun 			ha->mr.fw_hbt_en = 1;
1508*4882a593Smuzhiyun 		} else if (!ha->mr.fw_reset_timer_tick) {
1509*4882a593Smuzhiyun 			if (aenmbx0 == ha->mr.old_aenmbx0_state)
1510*4882a593Smuzhiyun 				ha->mr.fw_reset_timer_exp = 1;
1511*4882a593Smuzhiyun 			ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
1512*4882a593Smuzhiyun 		} else if (aenmbx0 == 0xFFFFFFFF) {
1513*4882a593Smuzhiyun 			uint32_t data0, data1;
1514*4882a593Smuzhiyun 
1515*4882a593Smuzhiyun 			data0 = QLAFX00_RD_REG(ha,
1516*4882a593Smuzhiyun 			    QLAFX00_BAR1_BASE_ADDR_REG);
1517*4882a593Smuzhiyun 			data1 = QLAFX00_RD_REG(ha,
1518*4882a593Smuzhiyun 			    QLAFX00_PEX0_WIN0_BASE_ADDR_REG);
1519*4882a593Smuzhiyun 
1520*4882a593Smuzhiyun 			data0 &= 0xffff0000;
1521*4882a593Smuzhiyun 			data1 &= 0x0000ffff;
1522*4882a593Smuzhiyun 
1523*4882a593Smuzhiyun 			QLAFX00_WR_REG(ha,
1524*4882a593Smuzhiyun 			    QLAFX00_PEX0_WIN0_BASE_ADDR_REG,
1525*4882a593Smuzhiyun 			    (data0 | data1));
1526*4882a593Smuzhiyun 		} else if ((aenmbx0 & 0xFF00) == MBA_FW_POLL_STATE) {
1527*4882a593Smuzhiyun 			ha->mr.fw_reset_timer_tick =
1528*4882a593Smuzhiyun 			    QLAFX00_MAX_RESET_INTERVAL;
1529*4882a593Smuzhiyun 		} else if (aenmbx0 == MBA_FW_RESET_FCT) {
1530*4882a593Smuzhiyun 			ha->mr.fw_reset_timer_tick =
1531*4882a593Smuzhiyun 			    QLAFX00_MAX_RESET_INTERVAL;
1532*4882a593Smuzhiyun 		}
1533*4882a593Smuzhiyun 		if (ha->mr.old_aenmbx0_state != aenmbx0) {
1534*4882a593Smuzhiyun 			ha->mr.old_aenmbx0_state = aenmbx0;
1535*4882a593Smuzhiyun 			ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
1536*4882a593Smuzhiyun 		}
1537*4882a593Smuzhiyun 		ha->mr.fw_reset_timer_tick--;
1538*4882a593Smuzhiyun 	}
1539*4882a593Smuzhiyun 	if (test_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags)) {
1540*4882a593Smuzhiyun 		/*
1541*4882a593Smuzhiyun 		 * Critical temperature recovery to be
1542*4882a593Smuzhiyun 		 * performed in timer routine
1543*4882a593Smuzhiyun 		 */
1544*4882a593Smuzhiyun 		if (ha->mr.fw_critemp_timer_tick == 0) {
1545*4882a593Smuzhiyun 			tempc = QLAFX00_GET_TEMPERATURE(ha);
1546*4882a593Smuzhiyun 			ql_dbg(ql_dbg_timer, vha, 0x6012,
1547*4882a593Smuzhiyun 			    "ISPFx00(%s): Critical temp timer, "
1548*4882a593Smuzhiyun 			    "current SOC temperature: %d\n",
1549*4882a593Smuzhiyun 			    __func__, tempc);
1550*4882a593Smuzhiyun 			if (tempc < ha->mr.critical_temperature) {
1551*4882a593Smuzhiyun 				set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1552*4882a593Smuzhiyun 				clear_bit(FX00_CRITEMP_RECOVERY,
1553*4882a593Smuzhiyun 				    &vha->dpc_flags);
1554*4882a593Smuzhiyun 				qla2xxx_wake_dpc(vha);
1555*4882a593Smuzhiyun 			}
1556*4882a593Smuzhiyun 			ha->mr.fw_critemp_timer_tick =
1557*4882a593Smuzhiyun 			    QLAFX00_CRITEMP_INTERVAL;
1558*4882a593Smuzhiyun 		} else {
1559*4882a593Smuzhiyun 			ha->mr.fw_critemp_timer_tick--;
1560*4882a593Smuzhiyun 		}
1561*4882a593Smuzhiyun 	}
1562*4882a593Smuzhiyun 	if (ha->mr.host_info_resend) {
1563*4882a593Smuzhiyun 		/*
1564*4882a593Smuzhiyun 		 * Incomplete host info might be sent to firmware
1565*4882a593Smuzhiyun 		 * durinng system boot - info should be resend
1566*4882a593Smuzhiyun 		 */
1567*4882a593Smuzhiyun 		if (ha->mr.hinfo_resend_timer_tick == 0) {
1568*4882a593Smuzhiyun 			ha->mr.host_info_resend = false;
1569*4882a593Smuzhiyun 			set_bit(FX00_HOST_INFO_RESEND, &vha->dpc_flags);
1570*4882a593Smuzhiyun 			ha->mr.hinfo_resend_timer_tick =
1571*4882a593Smuzhiyun 			    QLAFX00_HINFO_RESEND_INTERVAL;
1572*4882a593Smuzhiyun 			qla2xxx_wake_dpc(vha);
1573*4882a593Smuzhiyun 		} else {
1574*4882a593Smuzhiyun 			ha->mr.hinfo_resend_timer_tick--;
1575*4882a593Smuzhiyun 		}
1576*4882a593Smuzhiyun 	}
1577*4882a593Smuzhiyun 
1578*4882a593Smuzhiyun }
1579*4882a593Smuzhiyun 
1580*4882a593Smuzhiyun /*
1581*4882a593Smuzhiyun  *  qlfx00a_reset_initialize
1582*4882a593Smuzhiyun  *      Re-initialize after a iSA device reset.
1583*4882a593Smuzhiyun  *
1584*4882a593Smuzhiyun  * Input:
1585*4882a593Smuzhiyun  *      ha  = adapter block pointer.
1586*4882a593Smuzhiyun  *
1587*4882a593Smuzhiyun  * Returns:
1588*4882a593Smuzhiyun  *      0 = success
1589*4882a593Smuzhiyun  */
1590*4882a593Smuzhiyun int
qlafx00_reset_initialize(scsi_qla_host_t * vha)1591*4882a593Smuzhiyun qlafx00_reset_initialize(scsi_qla_host_t *vha)
1592*4882a593Smuzhiyun {
1593*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
1594*4882a593Smuzhiyun 
1595*4882a593Smuzhiyun 	if (vha->device_flags & DFLG_DEV_FAILED) {
1596*4882a593Smuzhiyun 		ql_dbg(ql_dbg_init, vha, 0x0142,
1597*4882a593Smuzhiyun 		    "Device in failed state\n");
1598*4882a593Smuzhiyun 		return QLA_SUCCESS;
1599*4882a593Smuzhiyun 	}
1600*4882a593Smuzhiyun 
1601*4882a593Smuzhiyun 	ha->flags.mr_reset_hdlr_active = 1;
1602*4882a593Smuzhiyun 
1603*4882a593Smuzhiyun 	if (vha->flags.online) {
1604*4882a593Smuzhiyun 		scsi_block_requests(vha->host);
1605*4882a593Smuzhiyun 		qlafx00_abort_isp_cleanup(vha, false);
1606*4882a593Smuzhiyun 	}
1607*4882a593Smuzhiyun 
1608*4882a593Smuzhiyun 	ql_log(ql_log_info, vha, 0x0143,
1609*4882a593Smuzhiyun 	    "(%s): succeeded.\n", __func__);
1610*4882a593Smuzhiyun 	ha->flags.mr_reset_hdlr_active = 0;
1611*4882a593Smuzhiyun 	return QLA_SUCCESS;
1612*4882a593Smuzhiyun }
1613*4882a593Smuzhiyun 
1614*4882a593Smuzhiyun /*
1615*4882a593Smuzhiyun  *  qlafx00_abort_isp
1616*4882a593Smuzhiyun  *      Resets ISP and aborts all outstanding commands.
1617*4882a593Smuzhiyun  *
1618*4882a593Smuzhiyun  * Input:
1619*4882a593Smuzhiyun  *      ha  = adapter block pointer.
1620*4882a593Smuzhiyun  *
1621*4882a593Smuzhiyun  * Returns:
1622*4882a593Smuzhiyun  *      0 = success
1623*4882a593Smuzhiyun  */
1624*4882a593Smuzhiyun int
qlafx00_abort_isp(scsi_qla_host_t * vha)1625*4882a593Smuzhiyun qlafx00_abort_isp(scsi_qla_host_t *vha)
1626*4882a593Smuzhiyun {
1627*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
1628*4882a593Smuzhiyun 
1629*4882a593Smuzhiyun 	if (vha->flags.online) {
1630*4882a593Smuzhiyun 		if (unlikely(pci_channel_offline(ha->pdev) &&
1631*4882a593Smuzhiyun 		    ha->flags.pci_channel_io_perm_failure)) {
1632*4882a593Smuzhiyun 			clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1633*4882a593Smuzhiyun 			return QLA_SUCCESS;
1634*4882a593Smuzhiyun 		}
1635*4882a593Smuzhiyun 
1636*4882a593Smuzhiyun 		scsi_block_requests(vha->host);
1637*4882a593Smuzhiyun 		qlafx00_abort_isp_cleanup(vha, false);
1638*4882a593Smuzhiyun 	} else {
1639*4882a593Smuzhiyun 		scsi_block_requests(vha->host);
1640*4882a593Smuzhiyun 		clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1641*4882a593Smuzhiyun 		vha->qla_stats.total_isp_aborts++;
1642*4882a593Smuzhiyun 		ha->isp_ops->reset_chip(vha);
1643*4882a593Smuzhiyun 		set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
1644*4882a593Smuzhiyun 		/* Clear the Interrupts */
1645*4882a593Smuzhiyun 		QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
1646*4882a593Smuzhiyun 	}
1647*4882a593Smuzhiyun 
1648*4882a593Smuzhiyun 	ql_log(ql_log_info, vha, 0x0145,
1649*4882a593Smuzhiyun 	    "(%s): succeeded.\n", __func__);
1650*4882a593Smuzhiyun 
1651*4882a593Smuzhiyun 	return QLA_SUCCESS;
1652*4882a593Smuzhiyun }
1653*4882a593Smuzhiyun 
1654*4882a593Smuzhiyun static inline fc_port_t*
qlafx00_get_fcport(struct scsi_qla_host * vha,int tgt_id)1655*4882a593Smuzhiyun qlafx00_get_fcport(struct scsi_qla_host *vha, int tgt_id)
1656*4882a593Smuzhiyun {
1657*4882a593Smuzhiyun 	fc_port_t	*fcport;
1658*4882a593Smuzhiyun 
1659*4882a593Smuzhiyun 	/* Check for matching device in remote port list. */
1660*4882a593Smuzhiyun 	list_for_each_entry(fcport, &vha->vp_fcports, list) {
1661*4882a593Smuzhiyun 		if (fcport->tgt_id == tgt_id) {
1662*4882a593Smuzhiyun 			ql_dbg(ql_dbg_async, vha, 0x5072,
1663*4882a593Smuzhiyun 			    "Matching fcport(%p) found with TGT-ID: 0x%x "
1664*4882a593Smuzhiyun 			    "and Remote TGT_ID: 0x%x\n",
1665*4882a593Smuzhiyun 			    fcport, fcport->tgt_id, tgt_id);
1666*4882a593Smuzhiyun 			return fcport;
1667*4882a593Smuzhiyun 		}
1668*4882a593Smuzhiyun 	}
1669*4882a593Smuzhiyun 	return NULL;
1670*4882a593Smuzhiyun }
1671*4882a593Smuzhiyun 
1672*4882a593Smuzhiyun static void
qlafx00_tgt_detach(struct scsi_qla_host * vha,int tgt_id)1673*4882a593Smuzhiyun qlafx00_tgt_detach(struct scsi_qla_host *vha, int tgt_id)
1674*4882a593Smuzhiyun {
1675*4882a593Smuzhiyun 	fc_port_t	*fcport;
1676*4882a593Smuzhiyun 
1677*4882a593Smuzhiyun 	ql_log(ql_log_info, vha, 0x5073,
1678*4882a593Smuzhiyun 	    "Detach TGT-ID: 0x%x\n", tgt_id);
1679*4882a593Smuzhiyun 
1680*4882a593Smuzhiyun 	fcport = qlafx00_get_fcport(vha, tgt_id);
1681*4882a593Smuzhiyun 	if (!fcport)
1682*4882a593Smuzhiyun 		return;
1683*4882a593Smuzhiyun 
1684*4882a593Smuzhiyun 	qla2x00_mark_device_lost(vha, fcport, 0);
1685*4882a593Smuzhiyun 
1686*4882a593Smuzhiyun 	return;
1687*4882a593Smuzhiyun }
1688*4882a593Smuzhiyun 
1689*4882a593Smuzhiyun void
qlafx00_process_aen(struct scsi_qla_host * vha,struct qla_work_evt * evt)1690*4882a593Smuzhiyun qlafx00_process_aen(struct scsi_qla_host *vha, struct qla_work_evt *evt)
1691*4882a593Smuzhiyun {
1692*4882a593Smuzhiyun 	uint32_t aen_code, aen_data;
1693*4882a593Smuzhiyun 
1694*4882a593Smuzhiyun 	aen_code = FCH_EVT_VENDOR_UNIQUE;
1695*4882a593Smuzhiyun 	aen_data = evt->u.aenfx.evtcode;
1696*4882a593Smuzhiyun 
1697*4882a593Smuzhiyun 	switch (evt->u.aenfx.evtcode) {
1698*4882a593Smuzhiyun 	case QLAFX00_MBA_PORT_UPDATE:		/* Port database update */
1699*4882a593Smuzhiyun 		if (evt->u.aenfx.mbx[1] == 0) {
1700*4882a593Smuzhiyun 			if (evt->u.aenfx.mbx[2] == 1) {
1701*4882a593Smuzhiyun 				if (!vha->flags.fw_tgt_reported)
1702*4882a593Smuzhiyun 					vha->flags.fw_tgt_reported = 1;
1703*4882a593Smuzhiyun 				atomic_set(&vha->loop_down_timer, 0);
1704*4882a593Smuzhiyun 				atomic_set(&vha->loop_state, LOOP_UP);
1705*4882a593Smuzhiyun 				set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1706*4882a593Smuzhiyun 				qla2xxx_wake_dpc(vha);
1707*4882a593Smuzhiyun 			} else if (evt->u.aenfx.mbx[2] == 2) {
1708*4882a593Smuzhiyun 				qlafx00_tgt_detach(vha, evt->u.aenfx.mbx[3]);
1709*4882a593Smuzhiyun 			}
1710*4882a593Smuzhiyun 		} else if (evt->u.aenfx.mbx[1] == 0xffff) {
1711*4882a593Smuzhiyun 			if (evt->u.aenfx.mbx[2] == 1) {
1712*4882a593Smuzhiyun 				if (!vha->flags.fw_tgt_reported)
1713*4882a593Smuzhiyun 					vha->flags.fw_tgt_reported = 1;
1714*4882a593Smuzhiyun 				set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1715*4882a593Smuzhiyun 			} else if (evt->u.aenfx.mbx[2] == 2) {
1716*4882a593Smuzhiyun 				vha->device_flags |= DFLG_NO_CABLE;
1717*4882a593Smuzhiyun 				qla2x00_mark_all_devices_lost(vha);
1718*4882a593Smuzhiyun 			}
1719*4882a593Smuzhiyun 		}
1720*4882a593Smuzhiyun 		break;
1721*4882a593Smuzhiyun 	case QLAFX00_MBA_LINK_UP:
1722*4882a593Smuzhiyun 		aen_code = FCH_EVT_LINKUP;
1723*4882a593Smuzhiyun 		aen_data = 0;
1724*4882a593Smuzhiyun 		break;
1725*4882a593Smuzhiyun 	case QLAFX00_MBA_LINK_DOWN:
1726*4882a593Smuzhiyun 		aen_code = FCH_EVT_LINKDOWN;
1727*4882a593Smuzhiyun 		aen_data = 0;
1728*4882a593Smuzhiyun 		break;
1729*4882a593Smuzhiyun 	case QLAFX00_MBA_TEMP_CRIT:	/* Critical temperature event */
1730*4882a593Smuzhiyun 		ql_log(ql_log_info, vha, 0x5082,
1731*4882a593Smuzhiyun 		    "Process critical temperature event "
1732*4882a593Smuzhiyun 		    "aenmb[0]: %x\n",
1733*4882a593Smuzhiyun 		    evt->u.aenfx.evtcode);
1734*4882a593Smuzhiyun 		scsi_block_requests(vha->host);
1735*4882a593Smuzhiyun 		qlafx00_abort_isp_cleanup(vha, true);
1736*4882a593Smuzhiyun 		scsi_unblock_requests(vha->host);
1737*4882a593Smuzhiyun 		break;
1738*4882a593Smuzhiyun 	}
1739*4882a593Smuzhiyun 
1740*4882a593Smuzhiyun 	fc_host_post_event(vha->host, fc_get_event_number(),
1741*4882a593Smuzhiyun 	    aen_code, aen_data);
1742*4882a593Smuzhiyun }
1743*4882a593Smuzhiyun 
1744*4882a593Smuzhiyun static void
qlafx00_update_host_attr(scsi_qla_host_t * vha,struct port_info_data * pinfo)1745*4882a593Smuzhiyun qlafx00_update_host_attr(scsi_qla_host_t *vha, struct port_info_data *pinfo)
1746*4882a593Smuzhiyun {
1747*4882a593Smuzhiyun 	u64 port_name = 0, node_name = 0;
1748*4882a593Smuzhiyun 
1749*4882a593Smuzhiyun 	port_name = (unsigned long long)wwn_to_u64(pinfo->port_name);
1750*4882a593Smuzhiyun 	node_name = (unsigned long long)wwn_to_u64(pinfo->node_name);
1751*4882a593Smuzhiyun 
1752*4882a593Smuzhiyun 	fc_host_node_name(vha->host) = node_name;
1753*4882a593Smuzhiyun 	fc_host_port_name(vha->host) = port_name;
1754*4882a593Smuzhiyun 	if (!pinfo->port_type)
1755*4882a593Smuzhiyun 		vha->hw->current_topology = ISP_CFG_F;
1756*4882a593Smuzhiyun 	if (pinfo->link_status == QLAFX00_LINK_STATUS_UP)
1757*4882a593Smuzhiyun 		atomic_set(&vha->loop_state, LOOP_READY);
1758*4882a593Smuzhiyun 	else if (pinfo->link_status == QLAFX00_LINK_STATUS_DOWN)
1759*4882a593Smuzhiyun 		atomic_set(&vha->loop_state, LOOP_DOWN);
1760*4882a593Smuzhiyun 	vha->hw->link_data_rate = (uint16_t)pinfo->link_config;
1761*4882a593Smuzhiyun }
1762*4882a593Smuzhiyun 
1763*4882a593Smuzhiyun static void
qla2x00_fxdisc_iocb_timeout(void * data)1764*4882a593Smuzhiyun qla2x00_fxdisc_iocb_timeout(void *data)
1765*4882a593Smuzhiyun {
1766*4882a593Smuzhiyun 	srb_t *sp = data;
1767*4882a593Smuzhiyun 	struct srb_iocb *lio = &sp->u.iocb_cmd;
1768*4882a593Smuzhiyun 
1769*4882a593Smuzhiyun 	complete(&lio->u.fxiocb.fxiocb_comp);
1770*4882a593Smuzhiyun }
1771*4882a593Smuzhiyun 
qla2x00_fxdisc_sp_done(srb_t * sp,int res)1772*4882a593Smuzhiyun static void qla2x00_fxdisc_sp_done(srb_t *sp, int res)
1773*4882a593Smuzhiyun {
1774*4882a593Smuzhiyun 	struct srb_iocb *lio = &sp->u.iocb_cmd;
1775*4882a593Smuzhiyun 
1776*4882a593Smuzhiyun 	complete(&lio->u.fxiocb.fxiocb_comp);
1777*4882a593Smuzhiyun }
1778*4882a593Smuzhiyun 
1779*4882a593Smuzhiyun int
qlafx00_fx_disc(scsi_qla_host_t * vha,fc_port_t * fcport,uint16_t fx_type)1780*4882a593Smuzhiyun qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
1781*4882a593Smuzhiyun {
1782*4882a593Smuzhiyun 	srb_t *sp;
1783*4882a593Smuzhiyun 	struct srb_iocb *fdisc;
1784*4882a593Smuzhiyun 	int rval = QLA_FUNCTION_FAILED;
1785*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
1786*4882a593Smuzhiyun 	struct host_system_info *phost_info;
1787*4882a593Smuzhiyun 	struct register_host_info *preg_hsi;
1788*4882a593Smuzhiyun 	struct new_utsname *p_sysid = NULL;
1789*4882a593Smuzhiyun 
1790*4882a593Smuzhiyun 	sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1791*4882a593Smuzhiyun 	if (!sp)
1792*4882a593Smuzhiyun 		goto done;
1793*4882a593Smuzhiyun 
1794*4882a593Smuzhiyun 	sp->type = SRB_FXIOCB_DCMD;
1795*4882a593Smuzhiyun 	sp->name = "fxdisc";
1796*4882a593Smuzhiyun 
1797*4882a593Smuzhiyun 	fdisc = &sp->u.iocb_cmd;
1798*4882a593Smuzhiyun 	fdisc->timeout = qla2x00_fxdisc_iocb_timeout;
1799*4882a593Smuzhiyun 	qla2x00_init_timer(sp, FXDISC_TIMEOUT);
1800*4882a593Smuzhiyun 
1801*4882a593Smuzhiyun 	switch (fx_type) {
1802*4882a593Smuzhiyun 	case FXDISC_GET_CONFIG_INFO:
1803*4882a593Smuzhiyun 	fdisc->u.fxiocb.flags =
1804*4882a593Smuzhiyun 		    SRB_FXDISC_RESP_DMA_VALID;
1805*4882a593Smuzhiyun 		fdisc->u.fxiocb.rsp_len = sizeof(struct config_info_data);
1806*4882a593Smuzhiyun 		break;
1807*4882a593Smuzhiyun 	case FXDISC_GET_PORT_INFO:
1808*4882a593Smuzhiyun 		fdisc->u.fxiocb.flags =
1809*4882a593Smuzhiyun 		    SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
1810*4882a593Smuzhiyun 		fdisc->u.fxiocb.rsp_len = QLAFX00_PORT_DATA_INFO;
1811*4882a593Smuzhiyun 		fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->port_id);
1812*4882a593Smuzhiyun 		break;
1813*4882a593Smuzhiyun 	case FXDISC_GET_TGT_NODE_INFO:
1814*4882a593Smuzhiyun 		fdisc->u.fxiocb.flags =
1815*4882a593Smuzhiyun 		    SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
1816*4882a593Smuzhiyun 		fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_INFO;
1817*4882a593Smuzhiyun 		fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->tgt_id);
1818*4882a593Smuzhiyun 		break;
1819*4882a593Smuzhiyun 	case FXDISC_GET_TGT_NODE_LIST:
1820*4882a593Smuzhiyun 		fdisc->u.fxiocb.flags =
1821*4882a593Smuzhiyun 		    SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
1822*4882a593Smuzhiyun 		fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_LIST_SIZE;
1823*4882a593Smuzhiyun 		break;
1824*4882a593Smuzhiyun 	case FXDISC_REG_HOST_INFO:
1825*4882a593Smuzhiyun 		fdisc->u.fxiocb.flags = SRB_FXDISC_REQ_DMA_VALID;
1826*4882a593Smuzhiyun 		fdisc->u.fxiocb.req_len = sizeof(struct register_host_info);
1827*4882a593Smuzhiyun 		p_sysid = utsname();
1828*4882a593Smuzhiyun 		if (!p_sysid) {
1829*4882a593Smuzhiyun 			ql_log(ql_log_warn, vha, 0x303c,
1830*4882a593Smuzhiyun 			    "Not able to get the system information\n");
1831*4882a593Smuzhiyun 			goto done_free_sp;
1832*4882a593Smuzhiyun 		}
1833*4882a593Smuzhiyun 		break;
1834*4882a593Smuzhiyun 	case FXDISC_ABORT_IOCTL:
1835*4882a593Smuzhiyun 	default:
1836*4882a593Smuzhiyun 		break;
1837*4882a593Smuzhiyun 	}
1838*4882a593Smuzhiyun 
1839*4882a593Smuzhiyun 	if (fdisc->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
1840*4882a593Smuzhiyun 		fdisc->u.fxiocb.req_addr = dma_alloc_coherent(&ha->pdev->dev,
1841*4882a593Smuzhiyun 		    fdisc->u.fxiocb.req_len,
1842*4882a593Smuzhiyun 		    &fdisc->u.fxiocb.req_dma_handle, GFP_KERNEL);
1843*4882a593Smuzhiyun 		if (!fdisc->u.fxiocb.req_addr)
1844*4882a593Smuzhiyun 			goto done_free_sp;
1845*4882a593Smuzhiyun 
1846*4882a593Smuzhiyun 		if (fx_type == FXDISC_REG_HOST_INFO) {
1847*4882a593Smuzhiyun 			preg_hsi = (struct register_host_info *)
1848*4882a593Smuzhiyun 				fdisc->u.fxiocb.req_addr;
1849*4882a593Smuzhiyun 			phost_info = &preg_hsi->hsi;
1850*4882a593Smuzhiyun 			memset(preg_hsi, 0, sizeof(struct register_host_info));
1851*4882a593Smuzhiyun 			phost_info->os_type = OS_TYPE_LINUX;
1852*4882a593Smuzhiyun 			strlcpy(phost_info->sysname, p_sysid->sysname,
1853*4882a593Smuzhiyun 				sizeof(phost_info->sysname));
1854*4882a593Smuzhiyun 			strlcpy(phost_info->nodename, p_sysid->nodename,
1855*4882a593Smuzhiyun 				sizeof(phost_info->nodename));
1856*4882a593Smuzhiyun 			if (!strcmp(phost_info->nodename, "(none)"))
1857*4882a593Smuzhiyun 				ha->mr.host_info_resend = true;
1858*4882a593Smuzhiyun 			strlcpy(phost_info->release, p_sysid->release,
1859*4882a593Smuzhiyun 				sizeof(phost_info->release));
1860*4882a593Smuzhiyun 			strlcpy(phost_info->version, p_sysid->version,
1861*4882a593Smuzhiyun 				sizeof(phost_info->version));
1862*4882a593Smuzhiyun 			strlcpy(phost_info->machine, p_sysid->machine,
1863*4882a593Smuzhiyun 				sizeof(phost_info->machine));
1864*4882a593Smuzhiyun 			strlcpy(phost_info->domainname, p_sysid->domainname,
1865*4882a593Smuzhiyun 				sizeof(phost_info->domainname));
1866*4882a593Smuzhiyun 			strlcpy(phost_info->hostdriver, QLA2XXX_VERSION,
1867*4882a593Smuzhiyun 				sizeof(phost_info->hostdriver));
1868*4882a593Smuzhiyun 			preg_hsi->utc = (uint64_t)ktime_get_real_seconds();
1869*4882a593Smuzhiyun 			ql_dbg(ql_dbg_init, vha, 0x0149,
1870*4882a593Smuzhiyun 			    "ISP%04X: Host registration with firmware\n",
1871*4882a593Smuzhiyun 			    ha->pdev->device);
1872*4882a593Smuzhiyun 			ql_dbg(ql_dbg_init, vha, 0x014a,
1873*4882a593Smuzhiyun 			    "os_type = '%d', sysname = '%s', nodname = '%s'\n",
1874*4882a593Smuzhiyun 			    phost_info->os_type,
1875*4882a593Smuzhiyun 			    phost_info->sysname,
1876*4882a593Smuzhiyun 			    phost_info->nodename);
1877*4882a593Smuzhiyun 			ql_dbg(ql_dbg_init, vha, 0x014b,
1878*4882a593Smuzhiyun 			    "release = '%s', version = '%s'\n",
1879*4882a593Smuzhiyun 			    phost_info->release,
1880*4882a593Smuzhiyun 			    phost_info->version);
1881*4882a593Smuzhiyun 			ql_dbg(ql_dbg_init, vha, 0x014c,
1882*4882a593Smuzhiyun 			    "machine = '%s' "
1883*4882a593Smuzhiyun 			    "domainname = '%s', hostdriver = '%s'\n",
1884*4882a593Smuzhiyun 			    phost_info->machine,
1885*4882a593Smuzhiyun 			    phost_info->domainname,
1886*4882a593Smuzhiyun 			    phost_info->hostdriver);
1887*4882a593Smuzhiyun 			ql_dump_buffer(ql_dbg_init + ql_dbg_disc, vha, 0x014d,
1888*4882a593Smuzhiyun 			    phost_info, sizeof(*phost_info));
1889*4882a593Smuzhiyun 		}
1890*4882a593Smuzhiyun 	}
1891*4882a593Smuzhiyun 
1892*4882a593Smuzhiyun 	if (fdisc->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
1893*4882a593Smuzhiyun 		fdisc->u.fxiocb.rsp_addr = dma_alloc_coherent(&ha->pdev->dev,
1894*4882a593Smuzhiyun 		    fdisc->u.fxiocb.rsp_len,
1895*4882a593Smuzhiyun 		    &fdisc->u.fxiocb.rsp_dma_handle, GFP_KERNEL);
1896*4882a593Smuzhiyun 		if (!fdisc->u.fxiocb.rsp_addr)
1897*4882a593Smuzhiyun 			goto done_unmap_req;
1898*4882a593Smuzhiyun 	}
1899*4882a593Smuzhiyun 
1900*4882a593Smuzhiyun 	fdisc->u.fxiocb.req_func_type = cpu_to_le16(fx_type);
1901*4882a593Smuzhiyun 	sp->done = qla2x00_fxdisc_sp_done;
1902*4882a593Smuzhiyun 
1903*4882a593Smuzhiyun 	rval = qla2x00_start_sp(sp);
1904*4882a593Smuzhiyun 	if (rval != QLA_SUCCESS)
1905*4882a593Smuzhiyun 		goto done_unmap_dma;
1906*4882a593Smuzhiyun 
1907*4882a593Smuzhiyun 	wait_for_completion(&fdisc->u.fxiocb.fxiocb_comp);
1908*4882a593Smuzhiyun 
1909*4882a593Smuzhiyun 	if (fx_type == FXDISC_GET_CONFIG_INFO) {
1910*4882a593Smuzhiyun 		struct config_info_data *pinfo =
1911*4882a593Smuzhiyun 		    (struct config_info_data *) fdisc->u.fxiocb.rsp_addr;
1912*4882a593Smuzhiyun 		strlcpy(vha->hw->model_number, pinfo->model_num,
1913*4882a593Smuzhiyun 			ARRAY_SIZE(vha->hw->model_number));
1914*4882a593Smuzhiyun 		strlcpy(vha->hw->model_desc, pinfo->model_description,
1915*4882a593Smuzhiyun 			ARRAY_SIZE(vha->hw->model_desc));
1916*4882a593Smuzhiyun 		memcpy(&vha->hw->mr.symbolic_name, pinfo->symbolic_name,
1917*4882a593Smuzhiyun 		    sizeof(vha->hw->mr.symbolic_name));
1918*4882a593Smuzhiyun 		memcpy(&vha->hw->mr.serial_num, pinfo->serial_num,
1919*4882a593Smuzhiyun 		    sizeof(vha->hw->mr.serial_num));
1920*4882a593Smuzhiyun 		memcpy(&vha->hw->mr.hw_version, pinfo->hw_version,
1921*4882a593Smuzhiyun 		    sizeof(vha->hw->mr.hw_version));
1922*4882a593Smuzhiyun 		memcpy(&vha->hw->mr.fw_version, pinfo->fw_version,
1923*4882a593Smuzhiyun 		    sizeof(vha->hw->mr.fw_version));
1924*4882a593Smuzhiyun 		strim(vha->hw->mr.fw_version);
1925*4882a593Smuzhiyun 		memcpy(&vha->hw->mr.uboot_version, pinfo->uboot_version,
1926*4882a593Smuzhiyun 		    sizeof(vha->hw->mr.uboot_version));
1927*4882a593Smuzhiyun 		memcpy(&vha->hw->mr.fru_serial_num, pinfo->fru_serial_num,
1928*4882a593Smuzhiyun 		    sizeof(vha->hw->mr.fru_serial_num));
1929*4882a593Smuzhiyun 		vha->hw->mr.critical_temperature =
1930*4882a593Smuzhiyun 		    (pinfo->nominal_temp_value) ?
1931*4882a593Smuzhiyun 		    pinfo->nominal_temp_value : QLAFX00_CRITEMP_THRSHLD;
1932*4882a593Smuzhiyun 		ha->mr.extended_io_enabled = (pinfo->enabled_capabilities &
1933*4882a593Smuzhiyun 		    QLAFX00_EXTENDED_IO_EN_MASK) != 0;
1934*4882a593Smuzhiyun 	} else if (fx_type == FXDISC_GET_PORT_INFO) {
1935*4882a593Smuzhiyun 		struct port_info_data *pinfo =
1936*4882a593Smuzhiyun 		    (struct port_info_data *) fdisc->u.fxiocb.rsp_addr;
1937*4882a593Smuzhiyun 		memcpy(vha->node_name, pinfo->node_name, WWN_SIZE);
1938*4882a593Smuzhiyun 		memcpy(vha->port_name, pinfo->port_name, WWN_SIZE);
1939*4882a593Smuzhiyun 		vha->d_id.b.domain = pinfo->port_id[0];
1940*4882a593Smuzhiyun 		vha->d_id.b.area = pinfo->port_id[1];
1941*4882a593Smuzhiyun 		vha->d_id.b.al_pa = pinfo->port_id[2];
1942*4882a593Smuzhiyun 		qlafx00_update_host_attr(vha, pinfo);
1943*4882a593Smuzhiyun 		ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0141,
1944*4882a593Smuzhiyun 		    pinfo, 16);
1945*4882a593Smuzhiyun 	} else if (fx_type == FXDISC_GET_TGT_NODE_INFO) {
1946*4882a593Smuzhiyun 		struct qlafx00_tgt_node_info *pinfo =
1947*4882a593Smuzhiyun 		    (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
1948*4882a593Smuzhiyun 		memcpy(fcport->node_name, pinfo->tgt_node_wwnn, WWN_SIZE);
1949*4882a593Smuzhiyun 		memcpy(fcport->port_name, pinfo->tgt_node_wwpn, WWN_SIZE);
1950*4882a593Smuzhiyun 		fcport->port_type = FCT_TARGET;
1951*4882a593Smuzhiyun 		ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0144,
1952*4882a593Smuzhiyun 		    pinfo, 16);
1953*4882a593Smuzhiyun 	} else if (fx_type == FXDISC_GET_TGT_NODE_LIST) {
1954*4882a593Smuzhiyun 		struct qlafx00_tgt_node_info *pinfo =
1955*4882a593Smuzhiyun 		    (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
1956*4882a593Smuzhiyun 		ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0146,
1957*4882a593Smuzhiyun 		    pinfo, 16);
1958*4882a593Smuzhiyun 		memcpy(vha->hw->gid_list, pinfo, QLAFX00_TGT_NODE_LIST_SIZE);
1959*4882a593Smuzhiyun 	} else if (fx_type == FXDISC_ABORT_IOCTL)
1960*4882a593Smuzhiyun 		fdisc->u.fxiocb.result =
1961*4882a593Smuzhiyun 		    (fdisc->u.fxiocb.result ==
1962*4882a593Smuzhiyun 			cpu_to_le32(QLAFX00_IOCTL_ICOB_ABORT_SUCCESS)) ?
1963*4882a593Smuzhiyun 		    cpu_to_le32(QLA_SUCCESS) : cpu_to_le32(QLA_FUNCTION_FAILED);
1964*4882a593Smuzhiyun 
1965*4882a593Smuzhiyun 	rval = le32_to_cpu(fdisc->u.fxiocb.result);
1966*4882a593Smuzhiyun 
1967*4882a593Smuzhiyun done_unmap_dma:
1968*4882a593Smuzhiyun 	if (fdisc->u.fxiocb.rsp_addr)
1969*4882a593Smuzhiyun 		dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.rsp_len,
1970*4882a593Smuzhiyun 		    fdisc->u.fxiocb.rsp_addr, fdisc->u.fxiocb.rsp_dma_handle);
1971*4882a593Smuzhiyun 
1972*4882a593Smuzhiyun done_unmap_req:
1973*4882a593Smuzhiyun 	if (fdisc->u.fxiocb.req_addr)
1974*4882a593Smuzhiyun 		dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.req_len,
1975*4882a593Smuzhiyun 		    fdisc->u.fxiocb.req_addr, fdisc->u.fxiocb.req_dma_handle);
1976*4882a593Smuzhiyun done_free_sp:
1977*4882a593Smuzhiyun 	sp->free(sp);
1978*4882a593Smuzhiyun done:
1979*4882a593Smuzhiyun 	return rval;
1980*4882a593Smuzhiyun }
1981*4882a593Smuzhiyun 
1982*4882a593Smuzhiyun /*
1983*4882a593Smuzhiyun  * qlafx00_initialize_adapter
1984*4882a593Smuzhiyun  *      Initialize board.
1985*4882a593Smuzhiyun  *
1986*4882a593Smuzhiyun  * Input:
1987*4882a593Smuzhiyun  *      ha = adapter block pointer.
1988*4882a593Smuzhiyun  *
1989*4882a593Smuzhiyun  * Returns:
1990*4882a593Smuzhiyun  *      0 = success
1991*4882a593Smuzhiyun  */
1992*4882a593Smuzhiyun int
qlafx00_initialize_adapter(scsi_qla_host_t * vha)1993*4882a593Smuzhiyun qlafx00_initialize_adapter(scsi_qla_host_t *vha)
1994*4882a593Smuzhiyun {
1995*4882a593Smuzhiyun 	int	rval;
1996*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
1997*4882a593Smuzhiyun 	uint32_t tempc;
1998*4882a593Smuzhiyun 
1999*4882a593Smuzhiyun 	/* Clear adapter flags. */
2000*4882a593Smuzhiyun 	vha->flags.online = 0;
2001*4882a593Smuzhiyun 	ha->flags.chip_reset_done = 0;
2002*4882a593Smuzhiyun 	vha->flags.reset_active = 0;
2003*4882a593Smuzhiyun 	ha->flags.pci_channel_io_perm_failure = 0;
2004*4882a593Smuzhiyun 	ha->flags.eeh_busy = 0;
2005*4882a593Smuzhiyun 	atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
2006*4882a593Smuzhiyun 	atomic_set(&vha->loop_state, LOOP_DOWN);
2007*4882a593Smuzhiyun 	vha->device_flags = DFLG_NO_CABLE;
2008*4882a593Smuzhiyun 	vha->dpc_flags = 0;
2009*4882a593Smuzhiyun 	vha->flags.management_server_logged_in = 0;
2010*4882a593Smuzhiyun 	ha->isp_abort_cnt = 0;
2011*4882a593Smuzhiyun 	ha->beacon_blink_led = 0;
2012*4882a593Smuzhiyun 
2013*4882a593Smuzhiyun 	set_bit(0, ha->req_qid_map);
2014*4882a593Smuzhiyun 	set_bit(0, ha->rsp_qid_map);
2015*4882a593Smuzhiyun 
2016*4882a593Smuzhiyun 	ql_dbg(ql_dbg_init, vha, 0x0147,
2017*4882a593Smuzhiyun 	    "Configuring PCI space...\n");
2018*4882a593Smuzhiyun 
2019*4882a593Smuzhiyun 	rval = ha->isp_ops->pci_config(vha);
2020*4882a593Smuzhiyun 	if (rval) {
2021*4882a593Smuzhiyun 		ql_log(ql_log_warn, vha, 0x0148,
2022*4882a593Smuzhiyun 		    "Unable to configure PCI space.\n");
2023*4882a593Smuzhiyun 		return rval;
2024*4882a593Smuzhiyun 	}
2025*4882a593Smuzhiyun 
2026*4882a593Smuzhiyun 	rval = qlafx00_init_fw_ready(vha);
2027*4882a593Smuzhiyun 	if (rval != QLA_SUCCESS)
2028*4882a593Smuzhiyun 		return rval;
2029*4882a593Smuzhiyun 
2030*4882a593Smuzhiyun 	qlafx00_save_queue_ptrs(vha);
2031*4882a593Smuzhiyun 
2032*4882a593Smuzhiyun 	rval = qlafx00_config_queues(vha);
2033*4882a593Smuzhiyun 	if (rval != QLA_SUCCESS)
2034*4882a593Smuzhiyun 		return rval;
2035*4882a593Smuzhiyun 
2036*4882a593Smuzhiyun 	/*
2037*4882a593Smuzhiyun 	 * Allocate the array of outstanding commands
2038*4882a593Smuzhiyun 	 * now that we know the firmware resources.
2039*4882a593Smuzhiyun 	 */
2040*4882a593Smuzhiyun 	rval = qla2x00_alloc_outstanding_cmds(ha, vha->req);
2041*4882a593Smuzhiyun 	if (rval != QLA_SUCCESS)
2042*4882a593Smuzhiyun 		return rval;
2043*4882a593Smuzhiyun 
2044*4882a593Smuzhiyun 	rval = qla2x00_init_rings(vha);
2045*4882a593Smuzhiyun 	ha->flags.chip_reset_done = 1;
2046*4882a593Smuzhiyun 
2047*4882a593Smuzhiyun 	tempc = QLAFX00_GET_TEMPERATURE(ha);
2048*4882a593Smuzhiyun 	ql_dbg(ql_dbg_init, vha, 0x0152,
2049*4882a593Smuzhiyun 	    "ISPFx00(%s): Critical temp timer, current SOC temperature: 0x%x\n",
2050*4882a593Smuzhiyun 	    __func__, tempc);
2051*4882a593Smuzhiyun 
2052*4882a593Smuzhiyun 	return rval;
2053*4882a593Smuzhiyun }
2054*4882a593Smuzhiyun 
2055*4882a593Smuzhiyun uint32_t
qlafx00_fw_state_show(struct device * dev,struct device_attribute * attr,char * buf)2056*4882a593Smuzhiyun qlafx00_fw_state_show(struct device *dev, struct device_attribute *attr,
2057*4882a593Smuzhiyun 		      char *buf)
2058*4882a593Smuzhiyun {
2059*4882a593Smuzhiyun 	scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
2060*4882a593Smuzhiyun 	int rval = QLA_FUNCTION_FAILED;
2061*4882a593Smuzhiyun 	uint32_t state[1];
2062*4882a593Smuzhiyun 
2063*4882a593Smuzhiyun 	if (qla2x00_reset_active(vha))
2064*4882a593Smuzhiyun 		ql_log(ql_log_warn, vha, 0x70ce,
2065*4882a593Smuzhiyun 		    "ISP reset active.\n");
2066*4882a593Smuzhiyun 	else if (!vha->hw->flags.eeh_busy) {
2067*4882a593Smuzhiyun 		rval = qlafx00_get_firmware_state(vha, state);
2068*4882a593Smuzhiyun 	}
2069*4882a593Smuzhiyun 	if (rval != QLA_SUCCESS)
2070*4882a593Smuzhiyun 		memset(state, -1, sizeof(state));
2071*4882a593Smuzhiyun 
2072*4882a593Smuzhiyun 	return state[0];
2073*4882a593Smuzhiyun }
2074*4882a593Smuzhiyun 
2075*4882a593Smuzhiyun void
qlafx00_get_host_speed(struct Scsi_Host * shost)2076*4882a593Smuzhiyun qlafx00_get_host_speed(struct Scsi_Host *shost)
2077*4882a593Smuzhiyun {
2078*4882a593Smuzhiyun 	struct qla_hw_data *ha = ((struct scsi_qla_host *)
2079*4882a593Smuzhiyun 					(shost_priv(shost)))->hw;
2080*4882a593Smuzhiyun 	u32 speed = FC_PORTSPEED_UNKNOWN;
2081*4882a593Smuzhiyun 
2082*4882a593Smuzhiyun 	switch (ha->link_data_rate) {
2083*4882a593Smuzhiyun 	case QLAFX00_PORT_SPEED_2G:
2084*4882a593Smuzhiyun 		speed = FC_PORTSPEED_2GBIT;
2085*4882a593Smuzhiyun 		break;
2086*4882a593Smuzhiyun 	case QLAFX00_PORT_SPEED_4G:
2087*4882a593Smuzhiyun 		speed = FC_PORTSPEED_4GBIT;
2088*4882a593Smuzhiyun 		break;
2089*4882a593Smuzhiyun 	case QLAFX00_PORT_SPEED_8G:
2090*4882a593Smuzhiyun 		speed = FC_PORTSPEED_8GBIT;
2091*4882a593Smuzhiyun 		break;
2092*4882a593Smuzhiyun 	case QLAFX00_PORT_SPEED_10G:
2093*4882a593Smuzhiyun 		speed = FC_PORTSPEED_10GBIT;
2094*4882a593Smuzhiyun 		break;
2095*4882a593Smuzhiyun 	}
2096*4882a593Smuzhiyun 	fc_host_speed(shost) = speed;
2097*4882a593Smuzhiyun }
2098*4882a593Smuzhiyun 
2099*4882a593Smuzhiyun /** QLAFX00 specific ISR implementation functions */
2100*4882a593Smuzhiyun 
2101*4882a593Smuzhiyun static inline void
qlafx00_handle_sense(srb_t * sp,uint8_t * sense_data,uint32_t par_sense_len,uint32_t sense_len,struct rsp_que * rsp,int res)2102*4882a593Smuzhiyun qlafx00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
2103*4882a593Smuzhiyun 		     uint32_t sense_len, struct rsp_que *rsp, int res)
2104*4882a593Smuzhiyun {
2105*4882a593Smuzhiyun 	struct scsi_qla_host *vha = sp->vha;
2106*4882a593Smuzhiyun 	struct scsi_cmnd *cp = GET_CMD_SP(sp);
2107*4882a593Smuzhiyun 	uint32_t track_sense_len;
2108*4882a593Smuzhiyun 
2109*4882a593Smuzhiyun 	SET_FW_SENSE_LEN(sp, sense_len);
2110*4882a593Smuzhiyun 
2111*4882a593Smuzhiyun 	if (sense_len >= SCSI_SENSE_BUFFERSIZE)
2112*4882a593Smuzhiyun 		sense_len = SCSI_SENSE_BUFFERSIZE;
2113*4882a593Smuzhiyun 
2114*4882a593Smuzhiyun 	SET_CMD_SENSE_LEN(sp, sense_len);
2115*4882a593Smuzhiyun 	SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
2116*4882a593Smuzhiyun 	track_sense_len = sense_len;
2117*4882a593Smuzhiyun 
2118*4882a593Smuzhiyun 	if (sense_len > par_sense_len)
2119*4882a593Smuzhiyun 		sense_len = par_sense_len;
2120*4882a593Smuzhiyun 
2121*4882a593Smuzhiyun 	memcpy(cp->sense_buffer, sense_data, sense_len);
2122*4882a593Smuzhiyun 
2123*4882a593Smuzhiyun 	SET_FW_SENSE_LEN(sp, GET_FW_SENSE_LEN(sp) - sense_len);
2124*4882a593Smuzhiyun 
2125*4882a593Smuzhiyun 	SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
2126*4882a593Smuzhiyun 	track_sense_len -= sense_len;
2127*4882a593Smuzhiyun 	SET_CMD_SENSE_LEN(sp, track_sense_len);
2128*4882a593Smuzhiyun 
2129*4882a593Smuzhiyun 	ql_dbg(ql_dbg_io, vha, 0x304d,
2130*4882a593Smuzhiyun 	    "sense_len=0x%x par_sense_len=0x%x track_sense_len=0x%x.\n",
2131*4882a593Smuzhiyun 	    sense_len, par_sense_len, track_sense_len);
2132*4882a593Smuzhiyun 	if (GET_FW_SENSE_LEN(sp) > 0) {
2133*4882a593Smuzhiyun 		rsp->status_srb = sp;
2134*4882a593Smuzhiyun 		cp->result = res;
2135*4882a593Smuzhiyun 	}
2136*4882a593Smuzhiyun 
2137*4882a593Smuzhiyun 	if (sense_len) {
2138*4882a593Smuzhiyun 		ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x3039,
2139*4882a593Smuzhiyun 		    "Check condition Sense data, nexus%ld:%d:%llu cmd=%p.\n",
2140*4882a593Smuzhiyun 		    sp->vha->host_no, cp->device->id, cp->device->lun,
2141*4882a593Smuzhiyun 		    cp);
2142*4882a593Smuzhiyun 		ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3049,
2143*4882a593Smuzhiyun 		    cp->sense_buffer, sense_len);
2144*4882a593Smuzhiyun 	}
2145*4882a593Smuzhiyun }
2146*4882a593Smuzhiyun 
2147*4882a593Smuzhiyun static void
qlafx00_tm_iocb_entry(scsi_qla_host_t * vha,struct req_que * req,struct tsk_mgmt_entry_fx00 * pkt,srb_t * sp,__le16 sstatus,__le16 cpstatus)2148*4882a593Smuzhiyun qlafx00_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
2149*4882a593Smuzhiyun 		      struct tsk_mgmt_entry_fx00 *pkt, srb_t *sp,
2150*4882a593Smuzhiyun 		      __le16 sstatus, __le16 cpstatus)
2151*4882a593Smuzhiyun {
2152*4882a593Smuzhiyun 	struct srb_iocb *tmf;
2153*4882a593Smuzhiyun 
2154*4882a593Smuzhiyun 	tmf = &sp->u.iocb_cmd;
2155*4882a593Smuzhiyun 	if (cpstatus != cpu_to_le16((uint16_t)CS_COMPLETE) ||
2156*4882a593Smuzhiyun 	    (sstatus & cpu_to_le16((uint16_t)SS_RESPONSE_INFO_LEN_VALID)))
2157*4882a593Smuzhiyun 		cpstatus = cpu_to_le16((uint16_t)CS_INCOMPLETE);
2158*4882a593Smuzhiyun 	tmf->u.tmf.comp_status = cpstatus;
2159*4882a593Smuzhiyun 	sp->done(sp, 0);
2160*4882a593Smuzhiyun }
2161*4882a593Smuzhiyun 
2162*4882a593Smuzhiyun static void
qlafx00_abort_iocb_entry(scsi_qla_host_t * vha,struct req_que * req,struct abort_iocb_entry_fx00 * pkt)2163*4882a593Smuzhiyun qlafx00_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
2164*4882a593Smuzhiyun 			 struct abort_iocb_entry_fx00 *pkt)
2165*4882a593Smuzhiyun {
2166*4882a593Smuzhiyun 	const char func[] = "ABT_IOCB";
2167*4882a593Smuzhiyun 	srb_t *sp;
2168*4882a593Smuzhiyun 	struct srb_iocb *abt;
2169*4882a593Smuzhiyun 
2170*4882a593Smuzhiyun 	sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2171*4882a593Smuzhiyun 	if (!sp)
2172*4882a593Smuzhiyun 		return;
2173*4882a593Smuzhiyun 
2174*4882a593Smuzhiyun 	abt = &sp->u.iocb_cmd;
2175*4882a593Smuzhiyun 	abt->u.abt.comp_status = pkt->tgt_id_sts;
2176*4882a593Smuzhiyun 	sp->done(sp, 0);
2177*4882a593Smuzhiyun }
2178*4882a593Smuzhiyun 
2179*4882a593Smuzhiyun static void
qlafx00_ioctl_iosb_entry(scsi_qla_host_t * vha,struct req_que * req,struct ioctl_iocb_entry_fx00 * pkt)2180*4882a593Smuzhiyun qlafx00_ioctl_iosb_entry(scsi_qla_host_t *vha, struct req_que *req,
2181*4882a593Smuzhiyun 			 struct ioctl_iocb_entry_fx00 *pkt)
2182*4882a593Smuzhiyun {
2183*4882a593Smuzhiyun 	const char func[] = "IOSB_IOCB";
2184*4882a593Smuzhiyun 	srb_t *sp;
2185*4882a593Smuzhiyun 	struct bsg_job *bsg_job;
2186*4882a593Smuzhiyun 	struct fc_bsg_reply *bsg_reply;
2187*4882a593Smuzhiyun 	struct srb_iocb *iocb_job;
2188*4882a593Smuzhiyun 	int res = 0;
2189*4882a593Smuzhiyun 	struct qla_mt_iocb_rsp_fx00 fstatus;
2190*4882a593Smuzhiyun 	uint8_t	*fw_sts_ptr;
2191*4882a593Smuzhiyun 
2192*4882a593Smuzhiyun 	sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2193*4882a593Smuzhiyun 	if (!sp)
2194*4882a593Smuzhiyun 		return;
2195*4882a593Smuzhiyun 
2196*4882a593Smuzhiyun 	if (sp->type == SRB_FXIOCB_DCMD) {
2197*4882a593Smuzhiyun 		iocb_job = &sp->u.iocb_cmd;
2198*4882a593Smuzhiyun 		iocb_job->u.fxiocb.seq_number = pkt->seq_no;
2199*4882a593Smuzhiyun 		iocb_job->u.fxiocb.fw_flags = pkt->fw_iotcl_flags;
2200*4882a593Smuzhiyun 		iocb_job->u.fxiocb.result = pkt->status;
2201*4882a593Smuzhiyun 		if (iocb_job->u.fxiocb.flags & SRB_FXDISC_RSP_DWRD_VALID)
2202*4882a593Smuzhiyun 			iocb_job->u.fxiocb.req_data =
2203*4882a593Smuzhiyun 			    pkt->dataword_r;
2204*4882a593Smuzhiyun 	} else {
2205*4882a593Smuzhiyun 		bsg_job = sp->u.bsg_job;
2206*4882a593Smuzhiyun 		bsg_reply = bsg_job->reply;
2207*4882a593Smuzhiyun 
2208*4882a593Smuzhiyun 		memset(&fstatus, 0, sizeof(struct qla_mt_iocb_rsp_fx00));
2209*4882a593Smuzhiyun 
2210*4882a593Smuzhiyun 		fstatus.reserved_1 = pkt->reserved_0;
2211*4882a593Smuzhiyun 		fstatus.func_type = pkt->comp_func_num;
2212*4882a593Smuzhiyun 		fstatus.ioctl_flags = pkt->fw_iotcl_flags;
2213*4882a593Smuzhiyun 		fstatus.ioctl_data = pkt->dataword_r;
2214*4882a593Smuzhiyun 		fstatus.adapid = pkt->adapid;
2215*4882a593Smuzhiyun 		fstatus.reserved_2 = pkt->dataword_r_extra;
2216*4882a593Smuzhiyun 		fstatus.res_count = pkt->residuallen;
2217*4882a593Smuzhiyun 		fstatus.status = pkt->status;
2218*4882a593Smuzhiyun 		fstatus.seq_number = pkt->seq_no;
2219*4882a593Smuzhiyun 		memcpy(fstatus.reserved_3,
2220*4882a593Smuzhiyun 		    pkt->reserved_2, 20 * sizeof(uint8_t));
2221*4882a593Smuzhiyun 
2222*4882a593Smuzhiyun 		fw_sts_ptr = bsg_job->reply + sizeof(struct fc_bsg_reply);
2223*4882a593Smuzhiyun 
2224*4882a593Smuzhiyun 		memcpy(fw_sts_ptr, &fstatus, sizeof(fstatus));
2225*4882a593Smuzhiyun 		bsg_job->reply_len = sizeof(struct fc_bsg_reply) +
2226*4882a593Smuzhiyun 			sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t);
2227*4882a593Smuzhiyun 
2228*4882a593Smuzhiyun 		ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
2229*4882a593Smuzhiyun 		    sp->vha, 0x5080, pkt, sizeof(*pkt));
2230*4882a593Smuzhiyun 
2231*4882a593Smuzhiyun 		ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
2232*4882a593Smuzhiyun 		    sp->vha, 0x5074,
2233*4882a593Smuzhiyun 		    fw_sts_ptr, sizeof(fstatus));
2234*4882a593Smuzhiyun 
2235*4882a593Smuzhiyun 		res = bsg_reply->result = DID_OK << 16;
2236*4882a593Smuzhiyun 		bsg_reply->reply_payload_rcv_len =
2237*4882a593Smuzhiyun 		    bsg_job->reply_payload.payload_len;
2238*4882a593Smuzhiyun 	}
2239*4882a593Smuzhiyun 	sp->done(sp, res);
2240*4882a593Smuzhiyun }
2241*4882a593Smuzhiyun 
2242*4882a593Smuzhiyun /**
2243*4882a593Smuzhiyun  * qlafx00_status_entry() - Process a Status IOCB entry.
2244*4882a593Smuzhiyun  * @vha: SCSI driver HA context
2245*4882a593Smuzhiyun  * @rsp: response queue
2246*4882a593Smuzhiyun  * @pkt: Entry pointer
2247*4882a593Smuzhiyun  */
2248*4882a593Smuzhiyun static void
qlafx00_status_entry(scsi_qla_host_t * vha,struct rsp_que * rsp,void * pkt)2249*4882a593Smuzhiyun qlafx00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
2250*4882a593Smuzhiyun {
2251*4882a593Smuzhiyun 	srb_t		*sp;
2252*4882a593Smuzhiyun 	fc_port_t	*fcport;
2253*4882a593Smuzhiyun 	struct scsi_cmnd *cp;
2254*4882a593Smuzhiyun 	struct sts_entry_fx00 *sts;
2255*4882a593Smuzhiyun 	__le16		comp_status;
2256*4882a593Smuzhiyun 	__le16		scsi_status;
2257*4882a593Smuzhiyun 	__le16		lscsi_status;
2258*4882a593Smuzhiyun 	int32_t		resid;
2259*4882a593Smuzhiyun 	uint32_t	sense_len, par_sense_len, rsp_info_len, resid_len,
2260*4882a593Smuzhiyun 	    fw_resid_len;
2261*4882a593Smuzhiyun 	uint8_t		*rsp_info = NULL, *sense_data = NULL;
2262*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
2263*4882a593Smuzhiyun 	uint32_t hindex, handle;
2264*4882a593Smuzhiyun 	uint16_t que;
2265*4882a593Smuzhiyun 	struct req_que *req;
2266*4882a593Smuzhiyun 	int logit = 1;
2267*4882a593Smuzhiyun 	int res = 0;
2268*4882a593Smuzhiyun 
2269*4882a593Smuzhiyun 	sts = (struct sts_entry_fx00 *) pkt;
2270*4882a593Smuzhiyun 
2271*4882a593Smuzhiyun 	comp_status = sts->comp_status;
2272*4882a593Smuzhiyun 	scsi_status = sts->scsi_status & cpu_to_le16((uint16_t)SS_MASK);
2273*4882a593Smuzhiyun 	hindex = sts->handle;
2274*4882a593Smuzhiyun 	handle = LSW(hindex);
2275*4882a593Smuzhiyun 
2276*4882a593Smuzhiyun 	que = MSW(hindex);
2277*4882a593Smuzhiyun 	req = ha->req_q_map[que];
2278*4882a593Smuzhiyun 
2279*4882a593Smuzhiyun 	/* Validate handle. */
2280*4882a593Smuzhiyun 	if (handle < req->num_outstanding_cmds)
2281*4882a593Smuzhiyun 		sp = req->outstanding_cmds[handle];
2282*4882a593Smuzhiyun 	else
2283*4882a593Smuzhiyun 		sp = NULL;
2284*4882a593Smuzhiyun 
2285*4882a593Smuzhiyun 	if (sp == NULL) {
2286*4882a593Smuzhiyun 		ql_dbg(ql_dbg_io, vha, 0x3034,
2287*4882a593Smuzhiyun 		    "Invalid status handle (0x%x).\n", handle);
2288*4882a593Smuzhiyun 
2289*4882a593Smuzhiyun 		set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2290*4882a593Smuzhiyun 		qla2xxx_wake_dpc(vha);
2291*4882a593Smuzhiyun 		return;
2292*4882a593Smuzhiyun 	}
2293*4882a593Smuzhiyun 
2294*4882a593Smuzhiyun 	if (sp->type == SRB_TM_CMD) {
2295*4882a593Smuzhiyun 		req->outstanding_cmds[handle] = NULL;
2296*4882a593Smuzhiyun 		qlafx00_tm_iocb_entry(vha, req, pkt, sp,
2297*4882a593Smuzhiyun 		    scsi_status, comp_status);
2298*4882a593Smuzhiyun 		return;
2299*4882a593Smuzhiyun 	}
2300*4882a593Smuzhiyun 
2301*4882a593Smuzhiyun 	/* Fast path completion. */
2302*4882a593Smuzhiyun 	if (comp_status == CS_COMPLETE && scsi_status == 0) {
2303*4882a593Smuzhiyun 		qla2x00_process_completed_request(vha, req, handle);
2304*4882a593Smuzhiyun 		return;
2305*4882a593Smuzhiyun 	}
2306*4882a593Smuzhiyun 
2307*4882a593Smuzhiyun 	req->outstanding_cmds[handle] = NULL;
2308*4882a593Smuzhiyun 	cp = GET_CMD_SP(sp);
2309*4882a593Smuzhiyun 	if (cp == NULL) {
2310*4882a593Smuzhiyun 		ql_dbg(ql_dbg_io, vha, 0x3048,
2311*4882a593Smuzhiyun 		    "Command already returned (0x%x/%p).\n",
2312*4882a593Smuzhiyun 		    handle, sp);
2313*4882a593Smuzhiyun 
2314*4882a593Smuzhiyun 		return;
2315*4882a593Smuzhiyun 	}
2316*4882a593Smuzhiyun 
2317*4882a593Smuzhiyun 	lscsi_status = scsi_status & cpu_to_le16((uint16_t)STATUS_MASK);
2318*4882a593Smuzhiyun 
2319*4882a593Smuzhiyun 	fcport = sp->fcport;
2320*4882a593Smuzhiyun 
2321*4882a593Smuzhiyun 	sense_len = par_sense_len = rsp_info_len = resid_len =
2322*4882a593Smuzhiyun 		fw_resid_len = 0;
2323*4882a593Smuzhiyun 	if (scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID))
2324*4882a593Smuzhiyun 		sense_len = sts->sense_len;
2325*4882a593Smuzhiyun 	if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
2326*4882a593Smuzhiyun 	    | (uint16_t)SS_RESIDUAL_OVER)))
2327*4882a593Smuzhiyun 		resid_len = le32_to_cpu(sts->residual_len);
2328*4882a593Smuzhiyun 	if (comp_status == cpu_to_le16((uint16_t)CS_DATA_UNDERRUN))
2329*4882a593Smuzhiyun 		fw_resid_len = le32_to_cpu(sts->residual_len);
2330*4882a593Smuzhiyun 	rsp_info = sense_data = sts->data;
2331*4882a593Smuzhiyun 	par_sense_len = sizeof(sts->data);
2332*4882a593Smuzhiyun 
2333*4882a593Smuzhiyun 	/* Check for overrun. */
2334*4882a593Smuzhiyun 	if (comp_status == CS_COMPLETE &&
2335*4882a593Smuzhiyun 	    scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_OVER))
2336*4882a593Smuzhiyun 		comp_status = cpu_to_le16((uint16_t)CS_DATA_OVERRUN);
2337*4882a593Smuzhiyun 
2338*4882a593Smuzhiyun 	/*
2339*4882a593Smuzhiyun 	 * Based on Host and scsi status generate status code for Linux
2340*4882a593Smuzhiyun 	 */
2341*4882a593Smuzhiyun 	switch (le16_to_cpu(comp_status)) {
2342*4882a593Smuzhiyun 	case CS_COMPLETE:
2343*4882a593Smuzhiyun 	case CS_QUEUE_FULL:
2344*4882a593Smuzhiyun 		if (scsi_status == 0) {
2345*4882a593Smuzhiyun 			res = DID_OK << 16;
2346*4882a593Smuzhiyun 			break;
2347*4882a593Smuzhiyun 		}
2348*4882a593Smuzhiyun 		if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
2349*4882a593Smuzhiyun 		    | (uint16_t)SS_RESIDUAL_OVER))) {
2350*4882a593Smuzhiyun 			resid = resid_len;
2351*4882a593Smuzhiyun 			scsi_set_resid(cp, resid);
2352*4882a593Smuzhiyun 
2353*4882a593Smuzhiyun 			if (!lscsi_status &&
2354*4882a593Smuzhiyun 			    ((unsigned)(scsi_bufflen(cp) - resid) <
2355*4882a593Smuzhiyun 			     cp->underflow)) {
2356*4882a593Smuzhiyun 				ql_dbg(ql_dbg_io, fcport->vha, 0x3050,
2357*4882a593Smuzhiyun 				    "Mid-layer underflow "
2358*4882a593Smuzhiyun 				    "detected (0x%x of 0x%x bytes).\n",
2359*4882a593Smuzhiyun 				    resid, scsi_bufflen(cp));
2360*4882a593Smuzhiyun 
2361*4882a593Smuzhiyun 				res = DID_ERROR << 16;
2362*4882a593Smuzhiyun 				break;
2363*4882a593Smuzhiyun 			}
2364*4882a593Smuzhiyun 		}
2365*4882a593Smuzhiyun 		res = DID_OK << 16 | le16_to_cpu(lscsi_status);
2366*4882a593Smuzhiyun 
2367*4882a593Smuzhiyun 		if (lscsi_status ==
2368*4882a593Smuzhiyun 		    cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
2369*4882a593Smuzhiyun 			ql_dbg(ql_dbg_io, fcport->vha, 0x3051,
2370*4882a593Smuzhiyun 			    "QUEUE FULL detected.\n");
2371*4882a593Smuzhiyun 			break;
2372*4882a593Smuzhiyun 		}
2373*4882a593Smuzhiyun 		logit = 0;
2374*4882a593Smuzhiyun 		if (lscsi_status != cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
2375*4882a593Smuzhiyun 			break;
2376*4882a593Smuzhiyun 
2377*4882a593Smuzhiyun 		memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
2378*4882a593Smuzhiyun 		if (!(scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
2379*4882a593Smuzhiyun 			break;
2380*4882a593Smuzhiyun 
2381*4882a593Smuzhiyun 		qlafx00_handle_sense(sp, sense_data, par_sense_len, sense_len,
2382*4882a593Smuzhiyun 		    rsp, res);
2383*4882a593Smuzhiyun 		break;
2384*4882a593Smuzhiyun 
2385*4882a593Smuzhiyun 	case CS_DATA_UNDERRUN:
2386*4882a593Smuzhiyun 		/* Use F/W calculated residual length. */
2387*4882a593Smuzhiyun 		if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
2388*4882a593Smuzhiyun 			resid = fw_resid_len;
2389*4882a593Smuzhiyun 		else
2390*4882a593Smuzhiyun 			resid = resid_len;
2391*4882a593Smuzhiyun 		scsi_set_resid(cp, resid);
2392*4882a593Smuzhiyun 		if (scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_UNDER)) {
2393*4882a593Smuzhiyun 			if ((IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
2394*4882a593Smuzhiyun 			    && fw_resid_len != resid_len) {
2395*4882a593Smuzhiyun 				ql_dbg(ql_dbg_io, fcport->vha, 0x3052,
2396*4882a593Smuzhiyun 				    "Dropped frame(s) detected "
2397*4882a593Smuzhiyun 				    "(0x%x of 0x%x bytes).\n",
2398*4882a593Smuzhiyun 				    resid, scsi_bufflen(cp));
2399*4882a593Smuzhiyun 
2400*4882a593Smuzhiyun 				res = DID_ERROR << 16 |
2401*4882a593Smuzhiyun 				    le16_to_cpu(lscsi_status);
2402*4882a593Smuzhiyun 				goto check_scsi_status;
2403*4882a593Smuzhiyun 			}
2404*4882a593Smuzhiyun 
2405*4882a593Smuzhiyun 			if (!lscsi_status &&
2406*4882a593Smuzhiyun 			    ((unsigned)(scsi_bufflen(cp) - resid) <
2407*4882a593Smuzhiyun 			    cp->underflow)) {
2408*4882a593Smuzhiyun 				ql_dbg(ql_dbg_io, fcport->vha, 0x3053,
2409*4882a593Smuzhiyun 				    "Mid-layer underflow "
2410*4882a593Smuzhiyun 				    "detected (0x%x of 0x%x bytes, "
2411*4882a593Smuzhiyun 				    "cp->underflow: 0x%x).\n",
2412*4882a593Smuzhiyun 				    resid, scsi_bufflen(cp), cp->underflow);
2413*4882a593Smuzhiyun 
2414*4882a593Smuzhiyun 				res = DID_ERROR << 16;
2415*4882a593Smuzhiyun 				break;
2416*4882a593Smuzhiyun 			}
2417*4882a593Smuzhiyun 		} else if (lscsi_status !=
2418*4882a593Smuzhiyun 		    cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL) &&
2419*4882a593Smuzhiyun 		    lscsi_status != cpu_to_le16((uint16_t)SAM_STAT_BUSY)) {
2420*4882a593Smuzhiyun 			/*
2421*4882a593Smuzhiyun 			 * scsi status of task set and busy are considered
2422*4882a593Smuzhiyun 			 * to be task not completed.
2423*4882a593Smuzhiyun 			 */
2424*4882a593Smuzhiyun 
2425*4882a593Smuzhiyun 			ql_dbg(ql_dbg_io, fcport->vha, 0x3054,
2426*4882a593Smuzhiyun 			    "Dropped frame(s) detected (0x%x "
2427*4882a593Smuzhiyun 			    "of 0x%x bytes).\n", resid,
2428*4882a593Smuzhiyun 			    scsi_bufflen(cp));
2429*4882a593Smuzhiyun 
2430*4882a593Smuzhiyun 			res = DID_ERROR << 16 | le16_to_cpu(lscsi_status);
2431*4882a593Smuzhiyun 			goto check_scsi_status;
2432*4882a593Smuzhiyun 		} else {
2433*4882a593Smuzhiyun 			ql_dbg(ql_dbg_io, fcport->vha, 0x3055,
2434*4882a593Smuzhiyun 			    "scsi_status: 0x%x, lscsi_status: 0x%x\n",
2435*4882a593Smuzhiyun 			    scsi_status, lscsi_status);
2436*4882a593Smuzhiyun 		}
2437*4882a593Smuzhiyun 
2438*4882a593Smuzhiyun 		res = DID_OK << 16 | le16_to_cpu(lscsi_status);
2439*4882a593Smuzhiyun 		logit = 0;
2440*4882a593Smuzhiyun 
2441*4882a593Smuzhiyun check_scsi_status:
2442*4882a593Smuzhiyun 		/*
2443*4882a593Smuzhiyun 		 * Check to see if SCSI Status is non zero. If so report SCSI
2444*4882a593Smuzhiyun 		 * Status.
2445*4882a593Smuzhiyun 		 */
2446*4882a593Smuzhiyun 		if (lscsi_status != 0) {
2447*4882a593Smuzhiyun 			if (lscsi_status ==
2448*4882a593Smuzhiyun 			    cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
2449*4882a593Smuzhiyun 				ql_dbg(ql_dbg_io, fcport->vha, 0x3056,
2450*4882a593Smuzhiyun 				    "QUEUE FULL detected.\n");
2451*4882a593Smuzhiyun 				logit = 1;
2452*4882a593Smuzhiyun 				break;
2453*4882a593Smuzhiyun 			}
2454*4882a593Smuzhiyun 			if (lscsi_status !=
2455*4882a593Smuzhiyun 			    cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
2456*4882a593Smuzhiyun 				break;
2457*4882a593Smuzhiyun 
2458*4882a593Smuzhiyun 			memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
2459*4882a593Smuzhiyun 			if (!(scsi_status &
2460*4882a593Smuzhiyun 			    cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
2461*4882a593Smuzhiyun 				break;
2462*4882a593Smuzhiyun 
2463*4882a593Smuzhiyun 			qlafx00_handle_sense(sp, sense_data, par_sense_len,
2464*4882a593Smuzhiyun 			    sense_len, rsp, res);
2465*4882a593Smuzhiyun 		}
2466*4882a593Smuzhiyun 		break;
2467*4882a593Smuzhiyun 
2468*4882a593Smuzhiyun 	case CS_PORT_LOGGED_OUT:
2469*4882a593Smuzhiyun 	case CS_PORT_CONFIG_CHG:
2470*4882a593Smuzhiyun 	case CS_PORT_BUSY:
2471*4882a593Smuzhiyun 	case CS_INCOMPLETE:
2472*4882a593Smuzhiyun 	case CS_PORT_UNAVAILABLE:
2473*4882a593Smuzhiyun 	case CS_TIMEOUT:
2474*4882a593Smuzhiyun 	case CS_RESET:
2475*4882a593Smuzhiyun 
2476*4882a593Smuzhiyun 		/*
2477*4882a593Smuzhiyun 		 * We are going to have the fc class block the rport
2478*4882a593Smuzhiyun 		 * while we try to recover so instruct the mid layer
2479*4882a593Smuzhiyun 		 * to requeue until the class decides how to handle this.
2480*4882a593Smuzhiyun 		 */
2481*4882a593Smuzhiyun 		res = DID_TRANSPORT_DISRUPTED << 16;
2482*4882a593Smuzhiyun 
2483*4882a593Smuzhiyun 		ql_dbg(ql_dbg_io, fcport->vha, 0x3057,
2484*4882a593Smuzhiyun 		    "Port down status: port-state=0x%x.\n",
2485*4882a593Smuzhiyun 		    atomic_read(&fcport->state));
2486*4882a593Smuzhiyun 
2487*4882a593Smuzhiyun 		if (atomic_read(&fcport->state) == FCS_ONLINE)
2488*4882a593Smuzhiyun 			qla2x00_mark_device_lost(fcport->vha, fcport, 1);
2489*4882a593Smuzhiyun 		break;
2490*4882a593Smuzhiyun 
2491*4882a593Smuzhiyun 	case CS_ABORTED:
2492*4882a593Smuzhiyun 		res = DID_RESET << 16;
2493*4882a593Smuzhiyun 		break;
2494*4882a593Smuzhiyun 
2495*4882a593Smuzhiyun 	default:
2496*4882a593Smuzhiyun 		res = DID_ERROR << 16;
2497*4882a593Smuzhiyun 		break;
2498*4882a593Smuzhiyun 	}
2499*4882a593Smuzhiyun 
2500*4882a593Smuzhiyun 	if (logit)
2501*4882a593Smuzhiyun 		ql_dbg(ql_dbg_io, fcport->vha, 0x3058,
2502*4882a593Smuzhiyun 		    "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%llu "
2503*4882a593Smuzhiyun 		    "tgt_id: 0x%x lscsi_status: 0x%x cdb=%10phN len=0x%x "
2504*4882a593Smuzhiyun 		    "rsp_info=%p resid=0x%x fw_resid=0x%x sense_len=0x%x, "
2505*4882a593Smuzhiyun 		    "par_sense_len=0x%x, rsp_info_len=0x%x\n",
2506*4882a593Smuzhiyun 		    comp_status, scsi_status, res, vha->host_no,
2507*4882a593Smuzhiyun 		    cp->device->id, cp->device->lun, fcport->tgt_id,
2508*4882a593Smuzhiyun 		    lscsi_status, cp->cmnd, scsi_bufflen(cp),
2509*4882a593Smuzhiyun 		    rsp_info, resid_len, fw_resid_len, sense_len,
2510*4882a593Smuzhiyun 		    par_sense_len, rsp_info_len);
2511*4882a593Smuzhiyun 
2512*4882a593Smuzhiyun 	if (rsp->status_srb == NULL)
2513*4882a593Smuzhiyun 		sp->done(sp, res);
2514*4882a593Smuzhiyun 	else
2515*4882a593Smuzhiyun 		WARN_ON_ONCE(true);
2516*4882a593Smuzhiyun }
2517*4882a593Smuzhiyun 
2518*4882a593Smuzhiyun /**
2519*4882a593Smuzhiyun  * qlafx00_status_cont_entry() - Process a Status Continuations entry.
2520*4882a593Smuzhiyun  * @rsp: response queue
2521*4882a593Smuzhiyun  * @pkt: Entry pointer
2522*4882a593Smuzhiyun  *
2523*4882a593Smuzhiyun  * Extended sense data.
2524*4882a593Smuzhiyun  */
2525*4882a593Smuzhiyun static void
qlafx00_status_cont_entry(struct rsp_que * rsp,sts_cont_entry_t * pkt)2526*4882a593Smuzhiyun qlafx00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
2527*4882a593Smuzhiyun {
2528*4882a593Smuzhiyun 	uint8_t	sense_sz = 0;
2529*4882a593Smuzhiyun 	struct qla_hw_data *ha = rsp->hw;
2530*4882a593Smuzhiyun 	struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
2531*4882a593Smuzhiyun 	srb_t *sp = rsp->status_srb;
2532*4882a593Smuzhiyun 	struct scsi_cmnd *cp;
2533*4882a593Smuzhiyun 	uint32_t sense_len;
2534*4882a593Smuzhiyun 	uint8_t *sense_ptr;
2535*4882a593Smuzhiyun 
2536*4882a593Smuzhiyun 	if (!sp) {
2537*4882a593Smuzhiyun 		ql_dbg(ql_dbg_io, vha, 0x3037,
2538*4882a593Smuzhiyun 		    "no SP, sp = %p\n", sp);
2539*4882a593Smuzhiyun 		return;
2540*4882a593Smuzhiyun 	}
2541*4882a593Smuzhiyun 
2542*4882a593Smuzhiyun 	if (!GET_FW_SENSE_LEN(sp)) {
2543*4882a593Smuzhiyun 		ql_dbg(ql_dbg_io, vha, 0x304b,
2544*4882a593Smuzhiyun 		    "no fw sense data, sp = %p\n", sp);
2545*4882a593Smuzhiyun 		return;
2546*4882a593Smuzhiyun 	}
2547*4882a593Smuzhiyun 	cp = GET_CMD_SP(sp);
2548*4882a593Smuzhiyun 	if (cp == NULL) {
2549*4882a593Smuzhiyun 		ql_log(ql_log_warn, vha, 0x303b,
2550*4882a593Smuzhiyun 		    "cmd is NULL: already returned to OS (sp=%p).\n", sp);
2551*4882a593Smuzhiyun 
2552*4882a593Smuzhiyun 		rsp->status_srb = NULL;
2553*4882a593Smuzhiyun 		return;
2554*4882a593Smuzhiyun 	}
2555*4882a593Smuzhiyun 
2556*4882a593Smuzhiyun 	if (!GET_CMD_SENSE_LEN(sp)) {
2557*4882a593Smuzhiyun 		ql_dbg(ql_dbg_io, vha, 0x304c,
2558*4882a593Smuzhiyun 		    "no sense data, sp = %p\n", sp);
2559*4882a593Smuzhiyun 	} else {
2560*4882a593Smuzhiyun 		sense_len = GET_CMD_SENSE_LEN(sp);
2561*4882a593Smuzhiyun 		sense_ptr = GET_CMD_SENSE_PTR(sp);
2562*4882a593Smuzhiyun 		ql_dbg(ql_dbg_io, vha, 0x304f,
2563*4882a593Smuzhiyun 		    "sp=%p sense_len=0x%x sense_ptr=%p.\n",
2564*4882a593Smuzhiyun 		    sp, sense_len, sense_ptr);
2565*4882a593Smuzhiyun 
2566*4882a593Smuzhiyun 		if (sense_len > sizeof(pkt->data))
2567*4882a593Smuzhiyun 			sense_sz = sizeof(pkt->data);
2568*4882a593Smuzhiyun 		else
2569*4882a593Smuzhiyun 			sense_sz = sense_len;
2570*4882a593Smuzhiyun 
2571*4882a593Smuzhiyun 		/* Move sense data. */
2572*4882a593Smuzhiyun 		ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304e,
2573*4882a593Smuzhiyun 		    pkt, sizeof(*pkt));
2574*4882a593Smuzhiyun 		memcpy(sense_ptr, pkt->data, sense_sz);
2575*4882a593Smuzhiyun 		ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304a,
2576*4882a593Smuzhiyun 		    sense_ptr, sense_sz);
2577*4882a593Smuzhiyun 
2578*4882a593Smuzhiyun 		sense_len -= sense_sz;
2579*4882a593Smuzhiyun 		sense_ptr += sense_sz;
2580*4882a593Smuzhiyun 
2581*4882a593Smuzhiyun 		SET_CMD_SENSE_PTR(sp, sense_ptr);
2582*4882a593Smuzhiyun 		SET_CMD_SENSE_LEN(sp, sense_len);
2583*4882a593Smuzhiyun 	}
2584*4882a593Smuzhiyun 	sense_len = GET_FW_SENSE_LEN(sp);
2585*4882a593Smuzhiyun 	sense_len = (sense_len > sizeof(pkt->data)) ?
2586*4882a593Smuzhiyun 	    (sense_len - sizeof(pkt->data)) : 0;
2587*4882a593Smuzhiyun 	SET_FW_SENSE_LEN(sp, sense_len);
2588*4882a593Smuzhiyun 
2589*4882a593Smuzhiyun 	/* Place command on done queue. */
2590*4882a593Smuzhiyun 	if (sense_len == 0) {
2591*4882a593Smuzhiyun 		rsp->status_srb = NULL;
2592*4882a593Smuzhiyun 		sp->done(sp, cp->result);
2593*4882a593Smuzhiyun 	} else {
2594*4882a593Smuzhiyun 		WARN_ON_ONCE(true);
2595*4882a593Smuzhiyun 	}
2596*4882a593Smuzhiyun }
2597*4882a593Smuzhiyun 
2598*4882a593Smuzhiyun /**
2599*4882a593Smuzhiyun  * qlafx00_multistatus_entry() - Process Multi response queue entries.
2600*4882a593Smuzhiyun  * @vha: SCSI driver HA context
2601*4882a593Smuzhiyun  * @rsp: response queue
2602*4882a593Smuzhiyun  * @pkt: received packet
2603*4882a593Smuzhiyun  */
2604*4882a593Smuzhiyun static void
qlafx00_multistatus_entry(struct scsi_qla_host * vha,struct rsp_que * rsp,void * pkt)2605*4882a593Smuzhiyun qlafx00_multistatus_entry(struct scsi_qla_host *vha,
2606*4882a593Smuzhiyun 	struct rsp_que *rsp, void *pkt)
2607*4882a593Smuzhiyun {
2608*4882a593Smuzhiyun 	srb_t		*sp;
2609*4882a593Smuzhiyun 	struct multi_sts_entry_fx00 *stsmfx;
2610*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
2611*4882a593Smuzhiyun 	uint32_t handle, hindex, handle_count, i;
2612*4882a593Smuzhiyun 	uint16_t que;
2613*4882a593Smuzhiyun 	struct req_que *req;
2614*4882a593Smuzhiyun 	__le32 *handle_ptr;
2615*4882a593Smuzhiyun 
2616*4882a593Smuzhiyun 	stsmfx = (struct multi_sts_entry_fx00 *) pkt;
2617*4882a593Smuzhiyun 
2618*4882a593Smuzhiyun 	handle_count = stsmfx->handle_count;
2619*4882a593Smuzhiyun 
2620*4882a593Smuzhiyun 	if (handle_count > MAX_HANDLE_COUNT) {
2621*4882a593Smuzhiyun 		ql_dbg(ql_dbg_io, vha, 0x3035,
2622*4882a593Smuzhiyun 		    "Invalid handle count (0x%x).\n", handle_count);
2623*4882a593Smuzhiyun 		set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2624*4882a593Smuzhiyun 		qla2xxx_wake_dpc(vha);
2625*4882a593Smuzhiyun 		return;
2626*4882a593Smuzhiyun 	}
2627*4882a593Smuzhiyun 
2628*4882a593Smuzhiyun 	handle_ptr =  &stsmfx->handles[0];
2629*4882a593Smuzhiyun 
2630*4882a593Smuzhiyun 	for (i = 0; i < handle_count; i++) {
2631*4882a593Smuzhiyun 		hindex = le32_to_cpu(*handle_ptr);
2632*4882a593Smuzhiyun 		handle = LSW(hindex);
2633*4882a593Smuzhiyun 		que = MSW(hindex);
2634*4882a593Smuzhiyun 		req = ha->req_q_map[que];
2635*4882a593Smuzhiyun 
2636*4882a593Smuzhiyun 		/* Validate handle. */
2637*4882a593Smuzhiyun 		if (handle < req->num_outstanding_cmds)
2638*4882a593Smuzhiyun 			sp = req->outstanding_cmds[handle];
2639*4882a593Smuzhiyun 		else
2640*4882a593Smuzhiyun 			sp = NULL;
2641*4882a593Smuzhiyun 
2642*4882a593Smuzhiyun 		if (sp == NULL) {
2643*4882a593Smuzhiyun 			ql_dbg(ql_dbg_io, vha, 0x3044,
2644*4882a593Smuzhiyun 			    "Invalid status handle (0x%x).\n", handle);
2645*4882a593Smuzhiyun 			set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2646*4882a593Smuzhiyun 			qla2xxx_wake_dpc(vha);
2647*4882a593Smuzhiyun 			return;
2648*4882a593Smuzhiyun 		}
2649*4882a593Smuzhiyun 		qla2x00_process_completed_request(vha, req, handle);
2650*4882a593Smuzhiyun 		handle_ptr++;
2651*4882a593Smuzhiyun 	}
2652*4882a593Smuzhiyun }
2653*4882a593Smuzhiyun 
2654*4882a593Smuzhiyun /**
2655*4882a593Smuzhiyun  * qlafx00_error_entry() - Process an error entry.
2656*4882a593Smuzhiyun  * @vha: SCSI driver HA context
2657*4882a593Smuzhiyun  * @rsp: response queue
2658*4882a593Smuzhiyun  * @pkt: Entry pointer
2659*4882a593Smuzhiyun  */
2660*4882a593Smuzhiyun static void
qlafx00_error_entry(scsi_qla_host_t * vha,struct rsp_que * rsp,struct sts_entry_fx00 * pkt)2661*4882a593Smuzhiyun qlafx00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp,
2662*4882a593Smuzhiyun 		    struct sts_entry_fx00 *pkt)
2663*4882a593Smuzhiyun {
2664*4882a593Smuzhiyun 	srb_t *sp;
2665*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
2666*4882a593Smuzhiyun 	const char func[] = "ERROR-IOCB";
2667*4882a593Smuzhiyun 	uint16_t que = 0;
2668*4882a593Smuzhiyun 	struct req_que *req = NULL;
2669*4882a593Smuzhiyun 	int res = DID_ERROR << 16;
2670*4882a593Smuzhiyun 
2671*4882a593Smuzhiyun 	req = ha->req_q_map[que];
2672*4882a593Smuzhiyun 
2673*4882a593Smuzhiyun 	sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2674*4882a593Smuzhiyun 	if (sp) {
2675*4882a593Smuzhiyun 		sp->done(sp, res);
2676*4882a593Smuzhiyun 		return;
2677*4882a593Smuzhiyun 	}
2678*4882a593Smuzhiyun 
2679*4882a593Smuzhiyun 	set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2680*4882a593Smuzhiyun 	qla2xxx_wake_dpc(vha);
2681*4882a593Smuzhiyun }
2682*4882a593Smuzhiyun 
2683*4882a593Smuzhiyun /**
2684*4882a593Smuzhiyun  * qlafx00_process_response_queue() - Process response queue entries.
2685*4882a593Smuzhiyun  * @vha: SCSI driver HA context
2686*4882a593Smuzhiyun  * @rsp: response queue
2687*4882a593Smuzhiyun  */
2688*4882a593Smuzhiyun static void
qlafx00_process_response_queue(struct scsi_qla_host * vha,struct rsp_que * rsp)2689*4882a593Smuzhiyun qlafx00_process_response_queue(struct scsi_qla_host *vha,
2690*4882a593Smuzhiyun 	struct rsp_que *rsp)
2691*4882a593Smuzhiyun {
2692*4882a593Smuzhiyun 	struct sts_entry_fx00 *pkt;
2693*4882a593Smuzhiyun 	response_t *lptr;
2694*4882a593Smuzhiyun 	uint16_t lreq_q_in = 0;
2695*4882a593Smuzhiyun 	uint16_t lreq_q_out = 0;
2696*4882a593Smuzhiyun 
2697*4882a593Smuzhiyun 	lreq_q_in = rd_reg_dword(rsp->rsp_q_in);
2698*4882a593Smuzhiyun 	lreq_q_out = rsp->ring_index;
2699*4882a593Smuzhiyun 
2700*4882a593Smuzhiyun 	while (lreq_q_in != lreq_q_out) {
2701*4882a593Smuzhiyun 		lptr = rsp->ring_ptr;
2702*4882a593Smuzhiyun 		memcpy_fromio(rsp->rsp_pkt, (void __iomem *)lptr,
2703*4882a593Smuzhiyun 		    sizeof(rsp->rsp_pkt));
2704*4882a593Smuzhiyun 		pkt = (struct sts_entry_fx00 *)rsp->rsp_pkt;
2705*4882a593Smuzhiyun 
2706*4882a593Smuzhiyun 		rsp->ring_index++;
2707*4882a593Smuzhiyun 		lreq_q_out++;
2708*4882a593Smuzhiyun 		if (rsp->ring_index == rsp->length) {
2709*4882a593Smuzhiyun 			lreq_q_out = 0;
2710*4882a593Smuzhiyun 			rsp->ring_index = 0;
2711*4882a593Smuzhiyun 			rsp->ring_ptr = rsp->ring;
2712*4882a593Smuzhiyun 		} else {
2713*4882a593Smuzhiyun 			rsp->ring_ptr++;
2714*4882a593Smuzhiyun 		}
2715*4882a593Smuzhiyun 
2716*4882a593Smuzhiyun 		if (pkt->entry_status != 0 &&
2717*4882a593Smuzhiyun 		    pkt->entry_type != IOCTL_IOSB_TYPE_FX00) {
2718*4882a593Smuzhiyun 			ql_dbg(ql_dbg_async, vha, 0x507f,
2719*4882a593Smuzhiyun 			       "type of error status in response: 0x%x\n",
2720*4882a593Smuzhiyun 			       pkt->entry_status);
2721*4882a593Smuzhiyun 			qlafx00_error_entry(vha, rsp,
2722*4882a593Smuzhiyun 					    (struct sts_entry_fx00 *)pkt);
2723*4882a593Smuzhiyun 			continue;
2724*4882a593Smuzhiyun 		}
2725*4882a593Smuzhiyun 
2726*4882a593Smuzhiyun 		switch (pkt->entry_type) {
2727*4882a593Smuzhiyun 		case STATUS_TYPE_FX00:
2728*4882a593Smuzhiyun 			qlafx00_status_entry(vha, rsp, pkt);
2729*4882a593Smuzhiyun 			break;
2730*4882a593Smuzhiyun 
2731*4882a593Smuzhiyun 		case STATUS_CONT_TYPE_FX00:
2732*4882a593Smuzhiyun 			qlafx00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
2733*4882a593Smuzhiyun 			break;
2734*4882a593Smuzhiyun 
2735*4882a593Smuzhiyun 		case MULTI_STATUS_TYPE_FX00:
2736*4882a593Smuzhiyun 			qlafx00_multistatus_entry(vha, rsp, pkt);
2737*4882a593Smuzhiyun 			break;
2738*4882a593Smuzhiyun 
2739*4882a593Smuzhiyun 		case ABORT_IOCB_TYPE_FX00:
2740*4882a593Smuzhiyun 			qlafx00_abort_iocb_entry(vha, rsp->req,
2741*4882a593Smuzhiyun 			   (struct abort_iocb_entry_fx00 *)pkt);
2742*4882a593Smuzhiyun 			break;
2743*4882a593Smuzhiyun 
2744*4882a593Smuzhiyun 		case IOCTL_IOSB_TYPE_FX00:
2745*4882a593Smuzhiyun 			qlafx00_ioctl_iosb_entry(vha, rsp->req,
2746*4882a593Smuzhiyun 			    (struct ioctl_iocb_entry_fx00 *)pkt);
2747*4882a593Smuzhiyun 			break;
2748*4882a593Smuzhiyun 		default:
2749*4882a593Smuzhiyun 			/* Type Not Supported. */
2750*4882a593Smuzhiyun 			ql_dbg(ql_dbg_async, vha, 0x5081,
2751*4882a593Smuzhiyun 			    "Received unknown response pkt type %x "
2752*4882a593Smuzhiyun 			    "entry status=%x.\n",
2753*4882a593Smuzhiyun 			    pkt->entry_type, pkt->entry_status);
2754*4882a593Smuzhiyun 			break;
2755*4882a593Smuzhiyun 		}
2756*4882a593Smuzhiyun 	}
2757*4882a593Smuzhiyun 
2758*4882a593Smuzhiyun 	/* Adjust ring index */
2759*4882a593Smuzhiyun 	wrt_reg_dword(rsp->rsp_q_out, rsp->ring_index);
2760*4882a593Smuzhiyun }
2761*4882a593Smuzhiyun 
2762*4882a593Smuzhiyun /**
2763*4882a593Smuzhiyun  * qlafx00_async_event() - Process aynchronous events.
2764*4882a593Smuzhiyun  * @vha: SCSI driver HA context
2765*4882a593Smuzhiyun  */
2766*4882a593Smuzhiyun static void
qlafx00_async_event(scsi_qla_host_t * vha)2767*4882a593Smuzhiyun qlafx00_async_event(scsi_qla_host_t *vha)
2768*4882a593Smuzhiyun {
2769*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
2770*4882a593Smuzhiyun 	struct device_reg_fx00 __iomem *reg;
2771*4882a593Smuzhiyun 	int data_size = 1;
2772*4882a593Smuzhiyun 
2773*4882a593Smuzhiyun 	reg = &ha->iobase->ispfx00;
2774*4882a593Smuzhiyun 	/* Setup to process RIO completion. */
2775*4882a593Smuzhiyun 	switch (ha->aenmb[0]) {
2776*4882a593Smuzhiyun 	case QLAFX00_MBA_SYSTEM_ERR:		/* System Error */
2777*4882a593Smuzhiyun 		ql_log(ql_log_warn, vha, 0x5079,
2778*4882a593Smuzhiyun 		    "ISP System Error - mbx1=%x\n", ha->aenmb[0]);
2779*4882a593Smuzhiyun 		set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2780*4882a593Smuzhiyun 		break;
2781*4882a593Smuzhiyun 
2782*4882a593Smuzhiyun 	case QLAFX00_MBA_SHUTDOWN_RQSTD:	/* Shutdown requested */
2783*4882a593Smuzhiyun 		ql_dbg(ql_dbg_async, vha, 0x5076,
2784*4882a593Smuzhiyun 		    "Asynchronous FW shutdown requested.\n");
2785*4882a593Smuzhiyun 		set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2786*4882a593Smuzhiyun 		qla2xxx_wake_dpc(vha);
2787*4882a593Smuzhiyun 		break;
2788*4882a593Smuzhiyun 
2789*4882a593Smuzhiyun 	case QLAFX00_MBA_PORT_UPDATE:		/* Port database update */
2790*4882a593Smuzhiyun 		ha->aenmb[1] = rd_reg_dword(&reg->aenmailbox1);
2791*4882a593Smuzhiyun 		ha->aenmb[2] = rd_reg_dword(&reg->aenmailbox2);
2792*4882a593Smuzhiyun 		ha->aenmb[3] = rd_reg_dword(&reg->aenmailbox3);
2793*4882a593Smuzhiyun 		ql_dbg(ql_dbg_async, vha, 0x5077,
2794*4882a593Smuzhiyun 		    "Asynchronous port Update received "
2795*4882a593Smuzhiyun 		    "aenmb[0]: %x, aenmb[1]: %x, aenmb[2]: %x, aenmb[3]: %x\n",
2796*4882a593Smuzhiyun 		    ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3]);
2797*4882a593Smuzhiyun 		data_size = 4;
2798*4882a593Smuzhiyun 		break;
2799*4882a593Smuzhiyun 
2800*4882a593Smuzhiyun 	case QLAFX00_MBA_TEMP_OVER:	/* Over temperature event */
2801*4882a593Smuzhiyun 		ql_log(ql_log_info, vha, 0x5085,
2802*4882a593Smuzhiyun 		    "Asynchronous over temperature event received "
2803*4882a593Smuzhiyun 		    "aenmb[0]: %x\n",
2804*4882a593Smuzhiyun 		    ha->aenmb[0]);
2805*4882a593Smuzhiyun 		break;
2806*4882a593Smuzhiyun 
2807*4882a593Smuzhiyun 	case QLAFX00_MBA_TEMP_NORM:	/* Normal temperature event */
2808*4882a593Smuzhiyun 		ql_log(ql_log_info, vha, 0x5086,
2809*4882a593Smuzhiyun 		    "Asynchronous normal temperature event received "
2810*4882a593Smuzhiyun 		    "aenmb[0]: %x\n",
2811*4882a593Smuzhiyun 		    ha->aenmb[0]);
2812*4882a593Smuzhiyun 		break;
2813*4882a593Smuzhiyun 
2814*4882a593Smuzhiyun 	case QLAFX00_MBA_TEMP_CRIT:	/* Critical temperature event */
2815*4882a593Smuzhiyun 		ql_log(ql_log_info, vha, 0x5083,
2816*4882a593Smuzhiyun 		    "Asynchronous critical temperature event received "
2817*4882a593Smuzhiyun 		    "aenmb[0]: %x\n",
2818*4882a593Smuzhiyun 		ha->aenmb[0]);
2819*4882a593Smuzhiyun 		break;
2820*4882a593Smuzhiyun 
2821*4882a593Smuzhiyun 	default:
2822*4882a593Smuzhiyun 		ha->aenmb[1] = rd_reg_dword(&reg->aenmailbox1);
2823*4882a593Smuzhiyun 		ha->aenmb[2] = rd_reg_dword(&reg->aenmailbox2);
2824*4882a593Smuzhiyun 		ha->aenmb[3] = rd_reg_dword(&reg->aenmailbox3);
2825*4882a593Smuzhiyun 		ha->aenmb[4] = rd_reg_dword(&reg->aenmailbox4);
2826*4882a593Smuzhiyun 		ha->aenmb[5] = rd_reg_dword(&reg->aenmailbox5);
2827*4882a593Smuzhiyun 		ha->aenmb[6] = rd_reg_dword(&reg->aenmailbox6);
2828*4882a593Smuzhiyun 		ha->aenmb[7] = rd_reg_dword(&reg->aenmailbox7);
2829*4882a593Smuzhiyun 		ql_dbg(ql_dbg_async, vha, 0x5078,
2830*4882a593Smuzhiyun 		    "AEN:%04x %04x %04x %04x :%04x %04x %04x %04x\n",
2831*4882a593Smuzhiyun 		    ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3],
2832*4882a593Smuzhiyun 		    ha->aenmb[4], ha->aenmb[5], ha->aenmb[6], ha->aenmb[7]);
2833*4882a593Smuzhiyun 		break;
2834*4882a593Smuzhiyun 	}
2835*4882a593Smuzhiyun 	qlafx00_post_aenfx_work(vha, ha->aenmb[0],
2836*4882a593Smuzhiyun 	    (uint32_t *)ha->aenmb, data_size);
2837*4882a593Smuzhiyun }
2838*4882a593Smuzhiyun 
2839*4882a593Smuzhiyun /**
2840*4882a593Smuzhiyun  * qlafx00x_mbx_completion() - Process mailbox command completions.
2841*4882a593Smuzhiyun  * @vha: SCSI driver HA context
2842*4882a593Smuzhiyun  * @mb0: value to be written into mailbox register 0
2843*4882a593Smuzhiyun  */
2844*4882a593Smuzhiyun static void
qlafx00_mbx_completion(scsi_qla_host_t * vha,uint32_t mb0)2845*4882a593Smuzhiyun qlafx00_mbx_completion(scsi_qla_host_t *vha, uint32_t mb0)
2846*4882a593Smuzhiyun {
2847*4882a593Smuzhiyun 	uint16_t	cnt;
2848*4882a593Smuzhiyun 	__le32 __iomem *wptr;
2849*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
2850*4882a593Smuzhiyun 	struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
2851*4882a593Smuzhiyun 
2852*4882a593Smuzhiyun 	if (!ha->mcp32)
2853*4882a593Smuzhiyun 		ql_dbg(ql_dbg_async, vha, 0x507e, "MBX pointer ERROR.\n");
2854*4882a593Smuzhiyun 
2855*4882a593Smuzhiyun 	/* Load return mailbox registers. */
2856*4882a593Smuzhiyun 	ha->flags.mbox_int = 1;
2857*4882a593Smuzhiyun 	ha->mailbox_out32[0] = mb0;
2858*4882a593Smuzhiyun 	wptr = &reg->mailbox17;
2859*4882a593Smuzhiyun 
2860*4882a593Smuzhiyun 	for (cnt = 1; cnt < ha->mbx_count; cnt++) {
2861*4882a593Smuzhiyun 		ha->mailbox_out32[cnt] = rd_reg_dword(wptr);
2862*4882a593Smuzhiyun 		wptr++;
2863*4882a593Smuzhiyun 	}
2864*4882a593Smuzhiyun }
2865*4882a593Smuzhiyun 
2866*4882a593Smuzhiyun /**
2867*4882a593Smuzhiyun  * qlafx00_intr_handler() - Process interrupts for the ISPFX00.
2868*4882a593Smuzhiyun  * @irq: interrupt number
2869*4882a593Smuzhiyun  * @dev_id: SCSI driver HA context
2870*4882a593Smuzhiyun  *
2871*4882a593Smuzhiyun  * Called by system whenever the host adapter generates an interrupt.
2872*4882a593Smuzhiyun  *
2873*4882a593Smuzhiyun  * Returns handled flag.
2874*4882a593Smuzhiyun  */
2875*4882a593Smuzhiyun irqreturn_t
qlafx00_intr_handler(int irq,void * dev_id)2876*4882a593Smuzhiyun qlafx00_intr_handler(int irq, void *dev_id)
2877*4882a593Smuzhiyun {
2878*4882a593Smuzhiyun 	scsi_qla_host_t	*vha;
2879*4882a593Smuzhiyun 	struct qla_hw_data *ha;
2880*4882a593Smuzhiyun 	struct device_reg_fx00 __iomem *reg;
2881*4882a593Smuzhiyun 	int		status;
2882*4882a593Smuzhiyun 	unsigned long	iter;
2883*4882a593Smuzhiyun 	uint32_t	stat;
2884*4882a593Smuzhiyun 	uint32_t	mb[8];
2885*4882a593Smuzhiyun 	struct rsp_que *rsp;
2886*4882a593Smuzhiyun 	unsigned long	flags;
2887*4882a593Smuzhiyun 	uint32_t clr_intr = 0;
2888*4882a593Smuzhiyun 	uint32_t intr_stat = 0;
2889*4882a593Smuzhiyun 
2890*4882a593Smuzhiyun 	rsp = (struct rsp_que *) dev_id;
2891*4882a593Smuzhiyun 	if (!rsp) {
2892*4882a593Smuzhiyun 		ql_log(ql_log_info, NULL, 0x507d,
2893*4882a593Smuzhiyun 		    "%s: NULL response queue pointer.\n", __func__);
2894*4882a593Smuzhiyun 		return IRQ_NONE;
2895*4882a593Smuzhiyun 	}
2896*4882a593Smuzhiyun 
2897*4882a593Smuzhiyun 	ha = rsp->hw;
2898*4882a593Smuzhiyun 	reg = &ha->iobase->ispfx00;
2899*4882a593Smuzhiyun 	status = 0;
2900*4882a593Smuzhiyun 
2901*4882a593Smuzhiyun 	if (unlikely(pci_channel_offline(ha->pdev)))
2902*4882a593Smuzhiyun 		return IRQ_HANDLED;
2903*4882a593Smuzhiyun 
2904*4882a593Smuzhiyun 	spin_lock_irqsave(&ha->hardware_lock, flags);
2905*4882a593Smuzhiyun 	vha = pci_get_drvdata(ha->pdev);
2906*4882a593Smuzhiyun 	for (iter = 50; iter--; clr_intr = 0) {
2907*4882a593Smuzhiyun 		stat = QLAFX00_RD_INTR_REG(ha);
2908*4882a593Smuzhiyun 		if (qla2x00_check_reg32_for_disconnect(vha, stat))
2909*4882a593Smuzhiyun 			break;
2910*4882a593Smuzhiyun 		intr_stat = stat & QLAFX00_HST_INT_STS_BITS;
2911*4882a593Smuzhiyun 		if (!intr_stat)
2912*4882a593Smuzhiyun 			break;
2913*4882a593Smuzhiyun 
2914*4882a593Smuzhiyun 		if (stat & QLAFX00_INTR_MB_CMPLT) {
2915*4882a593Smuzhiyun 			mb[0] = rd_reg_dword(&reg->mailbox16);
2916*4882a593Smuzhiyun 			qlafx00_mbx_completion(vha, mb[0]);
2917*4882a593Smuzhiyun 			status |= MBX_INTERRUPT;
2918*4882a593Smuzhiyun 			clr_intr |= QLAFX00_INTR_MB_CMPLT;
2919*4882a593Smuzhiyun 		}
2920*4882a593Smuzhiyun 		if (intr_stat & QLAFX00_INTR_ASYNC_CMPLT) {
2921*4882a593Smuzhiyun 			ha->aenmb[0] = rd_reg_dword(&reg->aenmailbox0);
2922*4882a593Smuzhiyun 			qlafx00_async_event(vha);
2923*4882a593Smuzhiyun 			clr_intr |= QLAFX00_INTR_ASYNC_CMPLT;
2924*4882a593Smuzhiyun 		}
2925*4882a593Smuzhiyun 		if (intr_stat & QLAFX00_INTR_RSP_CMPLT) {
2926*4882a593Smuzhiyun 			qlafx00_process_response_queue(vha, rsp);
2927*4882a593Smuzhiyun 			clr_intr |= QLAFX00_INTR_RSP_CMPLT;
2928*4882a593Smuzhiyun 		}
2929*4882a593Smuzhiyun 
2930*4882a593Smuzhiyun 		QLAFX00_CLR_INTR_REG(ha, clr_intr);
2931*4882a593Smuzhiyun 		QLAFX00_RD_INTR_REG(ha);
2932*4882a593Smuzhiyun 	}
2933*4882a593Smuzhiyun 
2934*4882a593Smuzhiyun 	qla2x00_handle_mbx_completion(ha, status);
2935*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
2936*4882a593Smuzhiyun 
2937*4882a593Smuzhiyun 	return IRQ_HANDLED;
2938*4882a593Smuzhiyun }
2939*4882a593Smuzhiyun 
2940*4882a593Smuzhiyun /** QLAFX00 specific IOCB implementation functions */
2941*4882a593Smuzhiyun 
2942*4882a593Smuzhiyun static inline cont_a64_entry_t *
qlafx00_prep_cont_type1_iocb(struct req_que * req,cont_a64_entry_t * lcont_pkt)2943*4882a593Smuzhiyun qlafx00_prep_cont_type1_iocb(struct req_que *req,
2944*4882a593Smuzhiyun 			     cont_a64_entry_t *lcont_pkt)
2945*4882a593Smuzhiyun {
2946*4882a593Smuzhiyun 	cont_a64_entry_t *cont_pkt;
2947*4882a593Smuzhiyun 
2948*4882a593Smuzhiyun 	/* Adjust ring index. */
2949*4882a593Smuzhiyun 	req->ring_index++;
2950*4882a593Smuzhiyun 	if (req->ring_index == req->length) {
2951*4882a593Smuzhiyun 		req->ring_index = 0;
2952*4882a593Smuzhiyun 		req->ring_ptr = req->ring;
2953*4882a593Smuzhiyun 	} else {
2954*4882a593Smuzhiyun 		req->ring_ptr++;
2955*4882a593Smuzhiyun 	}
2956*4882a593Smuzhiyun 
2957*4882a593Smuzhiyun 	cont_pkt = (cont_a64_entry_t *)req->ring_ptr;
2958*4882a593Smuzhiyun 
2959*4882a593Smuzhiyun 	/* Load packet defaults. */
2960*4882a593Smuzhiyun 	lcont_pkt->entry_type = CONTINUE_A64_TYPE_FX00;
2961*4882a593Smuzhiyun 
2962*4882a593Smuzhiyun 	return cont_pkt;
2963*4882a593Smuzhiyun }
2964*4882a593Smuzhiyun 
2965*4882a593Smuzhiyun static inline void
qlafx00_build_scsi_iocbs(srb_t * sp,struct cmd_type_7_fx00 * cmd_pkt,uint16_t tot_dsds,struct cmd_type_7_fx00 * lcmd_pkt)2966*4882a593Smuzhiyun qlafx00_build_scsi_iocbs(srb_t *sp, struct cmd_type_7_fx00 *cmd_pkt,
2967*4882a593Smuzhiyun 			 uint16_t tot_dsds, struct cmd_type_7_fx00 *lcmd_pkt)
2968*4882a593Smuzhiyun {
2969*4882a593Smuzhiyun 	uint16_t	avail_dsds;
2970*4882a593Smuzhiyun 	struct dsd64	*cur_dsd;
2971*4882a593Smuzhiyun 	scsi_qla_host_t	*vha;
2972*4882a593Smuzhiyun 	struct scsi_cmnd *cmd;
2973*4882a593Smuzhiyun 	struct scatterlist *sg;
2974*4882a593Smuzhiyun 	int i, cont;
2975*4882a593Smuzhiyun 	struct req_que *req;
2976*4882a593Smuzhiyun 	cont_a64_entry_t lcont_pkt;
2977*4882a593Smuzhiyun 	cont_a64_entry_t *cont_pkt;
2978*4882a593Smuzhiyun 
2979*4882a593Smuzhiyun 	vha = sp->vha;
2980*4882a593Smuzhiyun 	req = vha->req;
2981*4882a593Smuzhiyun 
2982*4882a593Smuzhiyun 	cmd = GET_CMD_SP(sp);
2983*4882a593Smuzhiyun 	cont = 0;
2984*4882a593Smuzhiyun 	cont_pkt = NULL;
2985*4882a593Smuzhiyun 
2986*4882a593Smuzhiyun 	/* Update entry type to indicate Command Type 3 IOCB */
2987*4882a593Smuzhiyun 	lcmd_pkt->entry_type = FX00_COMMAND_TYPE_7;
2988*4882a593Smuzhiyun 
2989*4882a593Smuzhiyun 	/* No data transfer */
2990*4882a593Smuzhiyun 	if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
2991*4882a593Smuzhiyun 		lcmd_pkt->byte_count = cpu_to_le32(0);
2992*4882a593Smuzhiyun 		return;
2993*4882a593Smuzhiyun 	}
2994*4882a593Smuzhiyun 
2995*4882a593Smuzhiyun 	/* Set transfer direction */
2996*4882a593Smuzhiyun 	if (cmd->sc_data_direction == DMA_TO_DEVICE) {
2997*4882a593Smuzhiyun 		lcmd_pkt->cntrl_flags = TMF_WRITE_DATA;
2998*4882a593Smuzhiyun 		vha->qla_stats.output_bytes += scsi_bufflen(cmd);
2999*4882a593Smuzhiyun 	} else if (cmd->sc_data_direction == DMA_FROM_DEVICE) {
3000*4882a593Smuzhiyun 		lcmd_pkt->cntrl_flags = TMF_READ_DATA;
3001*4882a593Smuzhiyun 		vha->qla_stats.input_bytes += scsi_bufflen(cmd);
3002*4882a593Smuzhiyun 	}
3003*4882a593Smuzhiyun 
3004*4882a593Smuzhiyun 	/* One DSD is available in the Command Type 3 IOCB */
3005*4882a593Smuzhiyun 	avail_dsds = 1;
3006*4882a593Smuzhiyun 	cur_dsd = &lcmd_pkt->dsd;
3007*4882a593Smuzhiyun 
3008*4882a593Smuzhiyun 	/* Load data segments */
3009*4882a593Smuzhiyun 	scsi_for_each_sg(cmd, sg, tot_dsds, i) {
3010*4882a593Smuzhiyun 		/* Allocate additional continuation packets? */
3011*4882a593Smuzhiyun 		if (avail_dsds == 0) {
3012*4882a593Smuzhiyun 			/*
3013*4882a593Smuzhiyun 			 * Five DSDs are available in the Continuation
3014*4882a593Smuzhiyun 			 * Type 1 IOCB.
3015*4882a593Smuzhiyun 			 */
3016*4882a593Smuzhiyun 			memset(&lcont_pkt, 0, REQUEST_ENTRY_SIZE);
3017*4882a593Smuzhiyun 			cont_pkt =
3018*4882a593Smuzhiyun 			    qlafx00_prep_cont_type1_iocb(req, &lcont_pkt);
3019*4882a593Smuzhiyun 			cur_dsd = lcont_pkt.dsd;
3020*4882a593Smuzhiyun 			avail_dsds = 5;
3021*4882a593Smuzhiyun 			cont = 1;
3022*4882a593Smuzhiyun 		}
3023*4882a593Smuzhiyun 
3024*4882a593Smuzhiyun 		append_dsd64(&cur_dsd, sg);
3025*4882a593Smuzhiyun 		avail_dsds--;
3026*4882a593Smuzhiyun 		if (avail_dsds == 0 && cont == 1) {
3027*4882a593Smuzhiyun 			cont = 0;
3028*4882a593Smuzhiyun 			memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
3029*4882a593Smuzhiyun 			    sizeof(lcont_pkt));
3030*4882a593Smuzhiyun 		}
3031*4882a593Smuzhiyun 
3032*4882a593Smuzhiyun 	}
3033*4882a593Smuzhiyun 	if (avail_dsds != 0 && cont == 1) {
3034*4882a593Smuzhiyun 		memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
3035*4882a593Smuzhiyun 		    sizeof(lcont_pkt));
3036*4882a593Smuzhiyun 	}
3037*4882a593Smuzhiyun }
3038*4882a593Smuzhiyun 
3039*4882a593Smuzhiyun /**
3040*4882a593Smuzhiyun  * qlafx00_start_scsi() - Send a SCSI command to the ISP
3041*4882a593Smuzhiyun  * @sp: command to send to the ISP
3042*4882a593Smuzhiyun  *
3043*4882a593Smuzhiyun  * Returns non-zero if a failure occurred, else zero.
3044*4882a593Smuzhiyun  */
3045*4882a593Smuzhiyun int
qlafx00_start_scsi(srb_t * sp)3046*4882a593Smuzhiyun qlafx00_start_scsi(srb_t *sp)
3047*4882a593Smuzhiyun {
3048*4882a593Smuzhiyun 	int		nseg;
3049*4882a593Smuzhiyun 	unsigned long   flags;
3050*4882a593Smuzhiyun 	uint32_t	handle;
3051*4882a593Smuzhiyun 	uint16_t	cnt;
3052*4882a593Smuzhiyun 	uint16_t	req_cnt;
3053*4882a593Smuzhiyun 	uint16_t	tot_dsds;
3054*4882a593Smuzhiyun 	struct req_que *req = NULL;
3055*4882a593Smuzhiyun 	struct rsp_que *rsp = NULL;
3056*4882a593Smuzhiyun 	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
3057*4882a593Smuzhiyun 	struct scsi_qla_host *vha = sp->vha;
3058*4882a593Smuzhiyun 	struct qla_hw_data *ha = vha->hw;
3059*4882a593Smuzhiyun 	struct cmd_type_7_fx00 *cmd_pkt;
3060*4882a593Smuzhiyun 	struct cmd_type_7_fx00 lcmd_pkt;
3061*4882a593Smuzhiyun 	struct scsi_lun llun;
3062*4882a593Smuzhiyun 
3063*4882a593Smuzhiyun 	/* Setup device pointers. */
3064*4882a593Smuzhiyun 	rsp = ha->rsp_q_map[0];
3065*4882a593Smuzhiyun 	req = vha->req;
3066*4882a593Smuzhiyun 
3067*4882a593Smuzhiyun 	/* So we know we haven't pci_map'ed anything yet */
3068*4882a593Smuzhiyun 	tot_dsds = 0;
3069*4882a593Smuzhiyun 
3070*4882a593Smuzhiyun 	/* Acquire ring specific lock */
3071*4882a593Smuzhiyun 	spin_lock_irqsave(&ha->hardware_lock, flags);
3072*4882a593Smuzhiyun 
3073*4882a593Smuzhiyun 	handle = qla2xxx_get_next_handle(req);
3074*4882a593Smuzhiyun 	if (handle == 0)
3075*4882a593Smuzhiyun 		goto queuing_error;
3076*4882a593Smuzhiyun 
3077*4882a593Smuzhiyun 	/* Map the sg table so we have an accurate count of sg entries needed */
3078*4882a593Smuzhiyun 	if (scsi_sg_count(cmd)) {
3079*4882a593Smuzhiyun 		nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd),
3080*4882a593Smuzhiyun 		    scsi_sg_count(cmd), cmd->sc_data_direction);
3081*4882a593Smuzhiyun 		if (unlikely(!nseg))
3082*4882a593Smuzhiyun 			goto queuing_error;
3083*4882a593Smuzhiyun 	} else
3084*4882a593Smuzhiyun 		nseg = 0;
3085*4882a593Smuzhiyun 
3086*4882a593Smuzhiyun 	tot_dsds = nseg;
3087*4882a593Smuzhiyun 	req_cnt = qla24xx_calc_iocbs(vha, tot_dsds);
3088*4882a593Smuzhiyun 	if (req->cnt < (req_cnt + 2)) {
3089*4882a593Smuzhiyun 		cnt = rd_reg_dword_relaxed(req->req_q_out);
3090*4882a593Smuzhiyun 
3091*4882a593Smuzhiyun 		if (req->ring_index < cnt)
3092*4882a593Smuzhiyun 			req->cnt = cnt - req->ring_index;
3093*4882a593Smuzhiyun 		else
3094*4882a593Smuzhiyun 			req->cnt = req->length -
3095*4882a593Smuzhiyun 				(req->ring_index - cnt);
3096*4882a593Smuzhiyun 		if (req->cnt < (req_cnt + 2))
3097*4882a593Smuzhiyun 			goto queuing_error;
3098*4882a593Smuzhiyun 	}
3099*4882a593Smuzhiyun 
3100*4882a593Smuzhiyun 	/* Build command packet. */
3101*4882a593Smuzhiyun 	req->current_outstanding_cmd = handle;
3102*4882a593Smuzhiyun 	req->outstanding_cmds[handle] = sp;
3103*4882a593Smuzhiyun 	sp->handle = handle;
3104*4882a593Smuzhiyun 	cmd->host_scribble = (unsigned char *)(unsigned long)handle;
3105*4882a593Smuzhiyun 	req->cnt -= req_cnt;
3106*4882a593Smuzhiyun 
3107*4882a593Smuzhiyun 	cmd_pkt = (struct cmd_type_7_fx00 *)req->ring_ptr;
3108*4882a593Smuzhiyun 
3109*4882a593Smuzhiyun 	memset(&lcmd_pkt, 0, REQUEST_ENTRY_SIZE);
3110*4882a593Smuzhiyun 
3111*4882a593Smuzhiyun 	lcmd_pkt.handle = make_handle(req->id, sp->handle);
3112*4882a593Smuzhiyun 	lcmd_pkt.reserved_0 = 0;
3113*4882a593Smuzhiyun 	lcmd_pkt.port_path_ctrl = 0;
3114*4882a593Smuzhiyun 	lcmd_pkt.reserved_1 = 0;
3115*4882a593Smuzhiyun 	lcmd_pkt.dseg_count = cpu_to_le16(tot_dsds);
3116*4882a593Smuzhiyun 	lcmd_pkt.tgt_idx = cpu_to_le16(sp->fcport->tgt_id);
3117*4882a593Smuzhiyun 
3118*4882a593Smuzhiyun 	int_to_scsilun(cmd->device->lun, &llun);
3119*4882a593Smuzhiyun 	host_to_adap((uint8_t *)&llun, (uint8_t *)&lcmd_pkt.lun,
3120*4882a593Smuzhiyun 	    sizeof(lcmd_pkt.lun));
3121*4882a593Smuzhiyun 
3122*4882a593Smuzhiyun 	/* Load SCSI command packet. */
3123*4882a593Smuzhiyun 	host_to_adap(cmd->cmnd, lcmd_pkt.fcp_cdb, sizeof(lcmd_pkt.fcp_cdb));
3124*4882a593Smuzhiyun 	lcmd_pkt.byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
3125*4882a593Smuzhiyun 
3126*4882a593Smuzhiyun 	/* Build IOCB segments */
3127*4882a593Smuzhiyun 	qlafx00_build_scsi_iocbs(sp, cmd_pkt, tot_dsds, &lcmd_pkt);
3128*4882a593Smuzhiyun 
3129*4882a593Smuzhiyun 	/* Set total data segment count. */
3130*4882a593Smuzhiyun 	lcmd_pkt.entry_count = (uint8_t)req_cnt;
3131*4882a593Smuzhiyun 
3132*4882a593Smuzhiyun 	/* Specify response queue number where completion should happen */
3133*4882a593Smuzhiyun 	lcmd_pkt.entry_status = (uint8_t) rsp->id;
3134*4882a593Smuzhiyun 
3135*4882a593Smuzhiyun 	ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302e,
3136*4882a593Smuzhiyun 	    cmd->cmnd, cmd->cmd_len);
3137*4882a593Smuzhiyun 	ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3032,
3138*4882a593Smuzhiyun 	    &lcmd_pkt, sizeof(lcmd_pkt));
3139*4882a593Smuzhiyun 
3140*4882a593Smuzhiyun 	memcpy_toio((void __iomem *)cmd_pkt, &lcmd_pkt, REQUEST_ENTRY_SIZE);
3141*4882a593Smuzhiyun 	wmb();
3142*4882a593Smuzhiyun 
3143*4882a593Smuzhiyun 	/* Adjust ring index. */
3144*4882a593Smuzhiyun 	req->ring_index++;
3145*4882a593Smuzhiyun 	if (req->ring_index == req->length) {
3146*4882a593Smuzhiyun 		req->ring_index = 0;
3147*4882a593Smuzhiyun 		req->ring_ptr = req->ring;
3148*4882a593Smuzhiyun 	} else
3149*4882a593Smuzhiyun 		req->ring_ptr++;
3150*4882a593Smuzhiyun 
3151*4882a593Smuzhiyun 	sp->flags |= SRB_DMA_VALID;
3152*4882a593Smuzhiyun 
3153*4882a593Smuzhiyun 	/* Set chip new ring index. */
3154*4882a593Smuzhiyun 	wrt_reg_dword(req->req_q_in, req->ring_index);
3155*4882a593Smuzhiyun 	QLAFX00_SET_HST_INTR(ha, ha->rqstq_intr_code);
3156*4882a593Smuzhiyun 
3157*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
3158*4882a593Smuzhiyun 	return QLA_SUCCESS;
3159*4882a593Smuzhiyun 
3160*4882a593Smuzhiyun queuing_error:
3161*4882a593Smuzhiyun 	if (tot_dsds)
3162*4882a593Smuzhiyun 		scsi_dma_unmap(cmd);
3163*4882a593Smuzhiyun 
3164*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
3165*4882a593Smuzhiyun 
3166*4882a593Smuzhiyun 	return QLA_FUNCTION_FAILED;
3167*4882a593Smuzhiyun }
3168*4882a593Smuzhiyun 
3169*4882a593Smuzhiyun void
qlafx00_tm_iocb(srb_t * sp,struct tsk_mgmt_entry_fx00 * ptm_iocb)3170*4882a593Smuzhiyun qlafx00_tm_iocb(srb_t *sp, struct tsk_mgmt_entry_fx00 *ptm_iocb)
3171*4882a593Smuzhiyun {
3172*4882a593Smuzhiyun 	struct srb_iocb *fxio = &sp->u.iocb_cmd;
3173*4882a593Smuzhiyun 	scsi_qla_host_t *vha = sp->vha;
3174*4882a593Smuzhiyun 	struct req_que *req = vha->req;
3175*4882a593Smuzhiyun 	struct tsk_mgmt_entry_fx00 tm_iocb;
3176*4882a593Smuzhiyun 	struct scsi_lun llun;
3177*4882a593Smuzhiyun 
3178*4882a593Smuzhiyun 	memset(&tm_iocb, 0, sizeof(struct tsk_mgmt_entry_fx00));
3179*4882a593Smuzhiyun 	tm_iocb.entry_type = TSK_MGMT_IOCB_TYPE_FX00;
3180*4882a593Smuzhiyun 	tm_iocb.entry_count = 1;
3181*4882a593Smuzhiyun 	tm_iocb.handle = make_handle(req->id, sp->handle);
3182*4882a593Smuzhiyun 	tm_iocb.reserved_0 = 0;
3183*4882a593Smuzhiyun 	tm_iocb.tgt_id = cpu_to_le16(sp->fcport->tgt_id);
3184*4882a593Smuzhiyun 	tm_iocb.control_flags = cpu_to_le32(fxio->u.tmf.flags);
3185*4882a593Smuzhiyun 	if (tm_iocb.control_flags == cpu_to_le32((uint32_t)TCF_LUN_RESET)) {
3186*4882a593Smuzhiyun 		int_to_scsilun(fxio->u.tmf.lun, &llun);
3187*4882a593Smuzhiyun 		host_to_adap((uint8_t *)&llun, (uint8_t *)&tm_iocb.lun,
3188*4882a593Smuzhiyun 		    sizeof(struct scsi_lun));
3189*4882a593Smuzhiyun 	}
3190*4882a593Smuzhiyun 
3191*4882a593Smuzhiyun 	memcpy(ptm_iocb, &tm_iocb,
3192*4882a593Smuzhiyun 	    sizeof(struct tsk_mgmt_entry_fx00));
3193*4882a593Smuzhiyun 	wmb();
3194*4882a593Smuzhiyun }
3195*4882a593Smuzhiyun 
3196*4882a593Smuzhiyun void
qlafx00_abort_iocb(srb_t * sp,struct abort_iocb_entry_fx00 * pabt_iocb)3197*4882a593Smuzhiyun qlafx00_abort_iocb(srb_t *sp, struct abort_iocb_entry_fx00 *pabt_iocb)
3198*4882a593Smuzhiyun {
3199*4882a593Smuzhiyun 	struct srb_iocb *fxio = &sp->u.iocb_cmd;
3200*4882a593Smuzhiyun 	scsi_qla_host_t *vha = sp->vha;
3201*4882a593Smuzhiyun 	struct req_que *req = vha->req;
3202*4882a593Smuzhiyun 	struct abort_iocb_entry_fx00 abt_iocb;
3203*4882a593Smuzhiyun 
3204*4882a593Smuzhiyun 	memset(&abt_iocb, 0, sizeof(struct abort_iocb_entry_fx00));
3205*4882a593Smuzhiyun 	abt_iocb.entry_type = ABORT_IOCB_TYPE_FX00;
3206*4882a593Smuzhiyun 	abt_iocb.entry_count = 1;
3207*4882a593Smuzhiyun 	abt_iocb.handle = make_handle(req->id, sp->handle);
3208*4882a593Smuzhiyun 	abt_iocb.abort_handle = make_handle(req->id, fxio->u.abt.cmd_hndl);
3209*4882a593Smuzhiyun 	abt_iocb.tgt_id_sts = cpu_to_le16(sp->fcport->tgt_id);
3210*4882a593Smuzhiyun 	abt_iocb.req_que_no = cpu_to_le16(req->id);
3211*4882a593Smuzhiyun 
3212*4882a593Smuzhiyun 	memcpy(pabt_iocb, &abt_iocb,
3213*4882a593Smuzhiyun 	    sizeof(struct abort_iocb_entry_fx00));
3214*4882a593Smuzhiyun 	wmb();
3215*4882a593Smuzhiyun }
3216*4882a593Smuzhiyun 
3217*4882a593Smuzhiyun void
qlafx00_fxdisc_iocb(srb_t * sp,struct fxdisc_entry_fx00 * pfxiocb)3218*4882a593Smuzhiyun qlafx00_fxdisc_iocb(srb_t *sp, struct fxdisc_entry_fx00 *pfxiocb)
3219*4882a593Smuzhiyun {
3220*4882a593Smuzhiyun 	struct srb_iocb *fxio = &sp->u.iocb_cmd;
3221*4882a593Smuzhiyun 	struct qla_mt_iocb_rqst_fx00 *piocb_rqst;
3222*4882a593Smuzhiyun 	struct bsg_job *bsg_job;
3223*4882a593Smuzhiyun 	struct fc_bsg_request *bsg_request;
3224*4882a593Smuzhiyun 	struct fxdisc_entry_fx00 fx_iocb;
3225*4882a593Smuzhiyun 	uint8_t entry_cnt = 1;
3226*4882a593Smuzhiyun 
3227*4882a593Smuzhiyun 	memset(&fx_iocb, 0, sizeof(struct fxdisc_entry_fx00));
3228*4882a593Smuzhiyun 	fx_iocb.entry_type = FX00_IOCB_TYPE;
3229*4882a593Smuzhiyun 	fx_iocb.handle = sp->handle;
3230*4882a593Smuzhiyun 	fx_iocb.entry_count = entry_cnt;
3231*4882a593Smuzhiyun 
3232*4882a593Smuzhiyun 	if (sp->type == SRB_FXIOCB_DCMD) {
3233*4882a593Smuzhiyun 		fx_iocb.func_num =
3234*4882a593Smuzhiyun 		    sp->u.iocb_cmd.u.fxiocb.req_func_type;
3235*4882a593Smuzhiyun 		fx_iocb.adapid = fxio->u.fxiocb.adapter_id;
3236*4882a593Smuzhiyun 		fx_iocb.adapid_hi = fxio->u.fxiocb.adapter_id_hi;
3237*4882a593Smuzhiyun 		fx_iocb.reserved_0 = fxio->u.fxiocb.reserved_0;
3238*4882a593Smuzhiyun 		fx_iocb.reserved_1 = fxio->u.fxiocb.reserved_1;
3239*4882a593Smuzhiyun 		fx_iocb.dataword_extra = fxio->u.fxiocb.req_data_extra;
3240*4882a593Smuzhiyun 
3241*4882a593Smuzhiyun 		if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
3242*4882a593Smuzhiyun 			fx_iocb.req_dsdcnt = cpu_to_le16(1);
3243*4882a593Smuzhiyun 			fx_iocb.req_xfrcnt =
3244*4882a593Smuzhiyun 			    cpu_to_le16(fxio->u.fxiocb.req_len);
3245*4882a593Smuzhiyun 			put_unaligned_le64(fxio->u.fxiocb.req_dma_handle,
3246*4882a593Smuzhiyun 					   &fx_iocb.dseg_rq.address);
3247*4882a593Smuzhiyun 			fx_iocb.dseg_rq.length =
3248*4882a593Smuzhiyun 			    cpu_to_le32(fxio->u.fxiocb.req_len);
3249*4882a593Smuzhiyun 		}
3250*4882a593Smuzhiyun 
3251*4882a593Smuzhiyun 		if (fxio->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
3252*4882a593Smuzhiyun 			fx_iocb.rsp_dsdcnt = cpu_to_le16(1);
3253*4882a593Smuzhiyun 			fx_iocb.rsp_xfrcnt =
3254*4882a593Smuzhiyun 			    cpu_to_le16(fxio->u.fxiocb.rsp_len);
3255*4882a593Smuzhiyun 			put_unaligned_le64(fxio->u.fxiocb.rsp_dma_handle,
3256*4882a593Smuzhiyun 					   &fx_iocb.dseg_rsp.address);
3257*4882a593Smuzhiyun 			fx_iocb.dseg_rsp.length =
3258*4882a593Smuzhiyun 			    cpu_to_le32(fxio->u.fxiocb.rsp_len);
3259*4882a593Smuzhiyun 		}
3260*4882a593Smuzhiyun 
3261*4882a593Smuzhiyun 		if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DWRD_VALID) {
3262*4882a593Smuzhiyun 			fx_iocb.dataword = fxio->u.fxiocb.req_data;
3263*4882a593Smuzhiyun 		}
3264*4882a593Smuzhiyun 		fx_iocb.flags = fxio->u.fxiocb.flags;
3265*4882a593Smuzhiyun 	} else {
3266*4882a593Smuzhiyun 		struct scatterlist *sg;
3267*4882a593Smuzhiyun 
3268*4882a593Smuzhiyun 		bsg_job = sp->u.bsg_job;
3269*4882a593Smuzhiyun 		bsg_request = bsg_job->request;
3270*4882a593Smuzhiyun 		piocb_rqst = (struct qla_mt_iocb_rqst_fx00 *)
3271*4882a593Smuzhiyun 			&bsg_request->rqst_data.h_vendor.vendor_cmd[1];
3272*4882a593Smuzhiyun 
3273*4882a593Smuzhiyun 		fx_iocb.func_num = piocb_rqst->func_type;
3274*4882a593Smuzhiyun 		fx_iocb.adapid = piocb_rqst->adapid;
3275*4882a593Smuzhiyun 		fx_iocb.adapid_hi = piocb_rqst->adapid_hi;
3276*4882a593Smuzhiyun 		fx_iocb.reserved_0 = piocb_rqst->reserved_0;
3277*4882a593Smuzhiyun 		fx_iocb.reserved_1 = piocb_rqst->reserved_1;
3278*4882a593Smuzhiyun 		fx_iocb.dataword_extra = piocb_rqst->dataword_extra;
3279*4882a593Smuzhiyun 		fx_iocb.dataword = piocb_rqst->dataword;
3280*4882a593Smuzhiyun 		fx_iocb.req_xfrcnt = piocb_rqst->req_len;
3281*4882a593Smuzhiyun 		fx_iocb.rsp_xfrcnt = piocb_rqst->rsp_len;
3282*4882a593Smuzhiyun 
3283*4882a593Smuzhiyun 		if (piocb_rqst->flags & SRB_FXDISC_REQ_DMA_VALID) {
3284*4882a593Smuzhiyun 			int avail_dsds, tot_dsds;
3285*4882a593Smuzhiyun 			cont_a64_entry_t lcont_pkt;
3286*4882a593Smuzhiyun 			cont_a64_entry_t *cont_pkt = NULL;
3287*4882a593Smuzhiyun 			struct dsd64 *cur_dsd;
3288*4882a593Smuzhiyun 			int index = 0, cont = 0;
3289*4882a593Smuzhiyun 
3290*4882a593Smuzhiyun 			fx_iocb.req_dsdcnt =
3291*4882a593Smuzhiyun 			    cpu_to_le16(bsg_job->request_payload.sg_cnt);
3292*4882a593Smuzhiyun 			tot_dsds =
3293*4882a593Smuzhiyun 			    bsg_job->request_payload.sg_cnt;
3294*4882a593Smuzhiyun 			cur_dsd = &fx_iocb.dseg_rq;
3295*4882a593Smuzhiyun 			avail_dsds = 1;
3296*4882a593Smuzhiyun 			for_each_sg(bsg_job->request_payload.sg_list, sg,
3297*4882a593Smuzhiyun 			    tot_dsds, index) {
3298*4882a593Smuzhiyun 				/* Allocate additional continuation packets? */
3299*4882a593Smuzhiyun 				if (avail_dsds == 0) {
3300*4882a593Smuzhiyun 					/*
3301*4882a593Smuzhiyun 					 * Five DSDs are available in the Cont.
3302*4882a593Smuzhiyun 					 * Type 1 IOCB.
3303*4882a593Smuzhiyun 					 */
3304*4882a593Smuzhiyun 					memset(&lcont_pkt, 0,
3305*4882a593Smuzhiyun 					    REQUEST_ENTRY_SIZE);
3306*4882a593Smuzhiyun 					cont_pkt =
3307*4882a593Smuzhiyun 					    qlafx00_prep_cont_type1_iocb(
3308*4882a593Smuzhiyun 						sp->vha->req, &lcont_pkt);
3309*4882a593Smuzhiyun 					cur_dsd = lcont_pkt.dsd;
3310*4882a593Smuzhiyun 					avail_dsds = 5;
3311*4882a593Smuzhiyun 					cont = 1;
3312*4882a593Smuzhiyun 					entry_cnt++;
3313*4882a593Smuzhiyun 				}
3314*4882a593Smuzhiyun 
3315*4882a593Smuzhiyun 				append_dsd64(&cur_dsd, sg);
3316*4882a593Smuzhiyun 				avail_dsds--;
3317*4882a593Smuzhiyun 
3318*4882a593Smuzhiyun 				if (avail_dsds == 0 && cont == 1) {
3319*4882a593Smuzhiyun 					cont = 0;
3320*4882a593Smuzhiyun 					memcpy_toio(
3321*4882a593Smuzhiyun 					    (void __iomem *)cont_pkt,
3322*4882a593Smuzhiyun 					    &lcont_pkt, REQUEST_ENTRY_SIZE);
3323*4882a593Smuzhiyun 					ql_dump_buffer(
3324*4882a593Smuzhiyun 					    ql_dbg_user + ql_dbg_verbose,
3325*4882a593Smuzhiyun 					    sp->vha, 0x3042,
3326*4882a593Smuzhiyun 					    (uint8_t *)&lcont_pkt,
3327*4882a593Smuzhiyun 					     REQUEST_ENTRY_SIZE);
3328*4882a593Smuzhiyun 				}
3329*4882a593Smuzhiyun 			}
3330*4882a593Smuzhiyun 			if (avail_dsds != 0 && cont == 1) {
3331*4882a593Smuzhiyun 				memcpy_toio((void __iomem *)cont_pkt,
3332*4882a593Smuzhiyun 				    &lcont_pkt, REQUEST_ENTRY_SIZE);
3333*4882a593Smuzhiyun 				ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
3334*4882a593Smuzhiyun 				    sp->vha, 0x3043,
3335*4882a593Smuzhiyun 				    (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
3336*4882a593Smuzhiyun 			}
3337*4882a593Smuzhiyun 		}
3338*4882a593Smuzhiyun 
3339*4882a593Smuzhiyun 		if (piocb_rqst->flags & SRB_FXDISC_RESP_DMA_VALID) {
3340*4882a593Smuzhiyun 			int avail_dsds, tot_dsds;
3341*4882a593Smuzhiyun 			cont_a64_entry_t lcont_pkt;
3342*4882a593Smuzhiyun 			cont_a64_entry_t *cont_pkt = NULL;
3343*4882a593Smuzhiyun 			struct dsd64 *cur_dsd;
3344*4882a593Smuzhiyun 			int index = 0, cont = 0;
3345*4882a593Smuzhiyun 
3346*4882a593Smuzhiyun 			fx_iocb.rsp_dsdcnt =
3347*4882a593Smuzhiyun 			   cpu_to_le16(bsg_job->reply_payload.sg_cnt);
3348*4882a593Smuzhiyun 			tot_dsds = bsg_job->reply_payload.sg_cnt;
3349*4882a593Smuzhiyun 			cur_dsd = &fx_iocb.dseg_rsp;
3350*4882a593Smuzhiyun 			avail_dsds = 1;
3351*4882a593Smuzhiyun 
3352*4882a593Smuzhiyun 			for_each_sg(bsg_job->reply_payload.sg_list, sg,
3353*4882a593Smuzhiyun 			    tot_dsds, index) {
3354*4882a593Smuzhiyun 				/* Allocate additional continuation packets? */
3355*4882a593Smuzhiyun 				if (avail_dsds == 0) {
3356*4882a593Smuzhiyun 					/*
3357*4882a593Smuzhiyun 					* Five DSDs are available in the Cont.
3358*4882a593Smuzhiyun 					* Type 1 IOCB.
3359*4882a593Smuzhiyun 					*/
3360*4882a593Smuzhiyun 					memset(&lcont_pkt, 0,
3361*4882a593Smuzhiyun 					    REQUEST_ENTRY_SIZE);
3362*4882a593Smuzhiyun 					cont_pkt =
3363*4882a593Smuzhiyun 					    qlafx00_prep_cont_type1_iocb(
3364*4882a593Smuzhiyun 						sp->vha->req, &lcont_pkt);
3365*4882a593Smuzhiyun 					cur_dsd = lcont_pkt.dsd;
3366*4882a593Smuzhiyun 					avail_dsds = 5;
3367*4882a593Smuzhiyun 					cont = 1;
3368*4882a593Smuzhiyun 					entry_cnt++;
3369*4882a593Smuzhiyun 				}
3370*4882a593Smuzhiyun 
3371*4882a593Smuzhiyun 				append_dsd64(&cur_dsd, sg);
3372*4882a593Smuzhiyun 				avail_dsds--;
3373*4882a593Smuzhiyun 
3374*4882a593Smuzhiyun 				if (avail_dsds == 0 && cont == 1) {
3375*4882a593Smuzhiyun 					cont = 0;
3376*4882a593Smuzhiyun 					memcpy_toio((void __iomem *)cont_pkt,
3377*4882a593Smuzhiyun 					    &lcont_pkt,
3378*4882a593Smuzhiyun 					    REQUEST_ENTRY_SIZE);
3379*4882a593Smuzhiyun 					ql_dump_buffer(
3380*4882a593Smuzhiyun 					    ql_dbg_user + ql_dbg_verbose,
3381*4882a593Smuzhiyun 					    sp->vha, 0x3045,
3382*4882a593Smuzhiyun 					    (uint8_t *)&lcont_pkt,
3383*4882a593Smuzhiyun 					    REQUEST_ENTRY_SIZE);
3384*4882a593Smuzhiyun 				}
3385*4882a593Smuzhiyun 			}
3386*4882a593Smuzhiyun 			if (avail_dsds != 0 && cont == 1) {
3387*4882a593Smuzhiyun 				memcpy_toio((void __iomem *)cont_pkt,
3388*4882a593Smuzhiyun 				    &lcont_pkt, REQUEST_ENTRY_SIZE);
3389*4882a593Smuzhiyun 				ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
3390*4882a593Smuzhiyun 				    sp->vha, 0x3046,
3391*4882a593Smuzhiyun 				    (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
3392*4882a593Smuzhiyun 			}
3393*4882a593Smuzhiyun 		}
3394*4882a593Smuzhiyun 
3395*4882a593Smuzhiyun 		if (piocb_rqst->flags & SRB_FXDISC_REQ_DWRD_VALID)
3396*4882a593Smuzhiyun 			fx_iocb.dataword = piocb_rqst->dataword;
3397*4882a593Smuzhiyun 		fx_iocb.flags = piocb_rqst->flags;
3398*4882a593Smuzhiyun 		fx_iocb.entry_count = entry_cnt;
3399*4882a593Smuzhiyun 	}
3400*4882a593Smuzhiyun 
3401*4882a593Smuzhiyun 	ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
3402*4882a593Smuzhiyun 	    sp->vha, 0x3047, &fx_iocb, sizeof(fx_iocb));
3403*4882a593Smuzhiyun 
3404*4882a593Smuzhiyun 	memcpy_toio((void __iomem *)pfxiocb, &fx_iocb, sizeof(fx_iocb));
3405*4882a593Smuzhiyun 	wmb();
3406*4882a593Smuzhiyun }
3407