1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * QLogic Fibre Channel HBA Driver
4*4882a593Smuzhiyun * Copyright (c) 2003-2014 QLogic Corporation
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun #include "qla_def.h"
7*4882a593Smuzhiyun #include "qla_gbl.h"
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/slab.h>
11*4882a593Smuzhiyun #include <linux/vmalloc.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include "qla_devtbl.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #ifdef CONFIG_SPARC
16*4882a593Smuzhiyun #include <asm/prom.h>
17*4882a593Smuzhiyun #endif
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include "qla_target.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /*
22*4882a593Smuzhiyun * QLogic ISP2x00 Hardware Support Function Prototypes.
23*4882a593Smuzhiyun */
24*4882a593Smuzhiyun static int qla2x00_isp_firmware(scsi_qla_host_t *);
25*4882a593Smuzhiyun static int qla2x00_setup_chip(scsi_qla_host_t *);
26*4882a593Smuzhiyun static int qla2x00_fw_ready(scsi_qla_host_t *);
27*4882a593Smuzhiyun static int qla2x00_configure_hba(scsi_qla_host_t *);
28*4882a593Smuzhiyun static int qla2x00_configure_loop(scsi_qla_host_t *);
29*4882a593Smuzhiyun static int qla2x00_configure_local_loop(scsi_qla_host_t *);
30*4882a593Smuzhiyun static int qla2x00_configure_fabric(scsi_qla_host_t *);
31*4882a593Smuzhiyun static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *);
32*4882a593Smuzhiyun static int qla2x00_restart_isp(scsi_qla_host_t *);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
35*4882a593Smuzhiyun static int qla84xx_init_chip(scsi_qla_host_t *);
36*4882a593Smuzhiyun static int qla25xx_init_queues(struct qla_hw_data *);
37*4882a593Smuzhiyun static int qla24xx_post_prli_work(struct scsi_qla_host*, fc_port_t *);
38*4882a593Smuzhiyun static void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha,
39*4882a593Smuzhiyun struct event_arg *ea);
40*4882a593Smuzhiyun static void qla24xx_handle_prli_done_event(struct scsi_qla_host *,
41*4882a593Smuzhiyun struct event_arg *);
42*4882a593Smuzhiyun static void __qla24xx_handle_gpdb_event(scsi_qla_host_t *, struct event_arg *);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* SRB Extensions ---------------------------------------------------------- */
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun void
qla2x00_sp_timeout(struct timer_list * t)47*4882a593Smuzhiyun qla2x00_sp_timeout(struct timer_list *t)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun srb_t *sp = from_timer(sp, t, u.iocb_cmd.timer);
50*4882a593Smuzhiyun struct srb_iocb *iocb;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun WARN_ON(irqs_disabled());
53*4882a593Smuzhiyun iocb = &sp->u.iocb_cmd;
54*4882a593Smuzhiyun iocb->timeout(sp);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
qla2x00_sp_free(srb_t * sp)57*4882a593Smuzhiyun void qla2x00_sp_free(srb_t *sp)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun struct srb_iocb *iocb = &sp->u.iocb_cmd;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun del_timer(&iocb->timer);
62*4882a593Smuzhiyun qla2x00_rel_sp(sp);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
qla2xxx_rel_done_warning(srb_t * sp,int res)65*4882a593Smuzhiyun void qla2xxx_rel_done_warning(srb_t *sp, int res)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun WARN_ONCE(1, "Calling done() of an already freed srb %p object\n", sp);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
qla2xxx_rel_free_warning(srb_t * sp)70*4882a593Smuzhiyun void qla2xxx_rel_free_warning(srb_t *sp)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun WARN_ONCE(1, "Calling free() of an already freed srb %p object\n", sp);
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Asynchronous Login/Logout Routines -------------------------------------- */
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun unsigned long
qla2x00_get_async_timeout(struct scsi_qla_host * vha)78*4882a593Smuzhiyun qla2x00_get_async_timeout(struct scsi_qla_host *vha)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun unsigned long tmo;
81*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /* Firmware should use switch negotiated r_a_tov for timeout. */
84*4882a593Smuzhiyun tmo = ha->r_a_tov / 10 * 2;
85*4882a593Smuzhiyun if (IS_QLAFX00(ha)) {
86*4882a593Smuzhiyun tmo = FX00_DEF_RATOV * 2;
87*4882a593Smuzhiyun } else if (!IS_FWI2_CAPABLE(ha)) {
88*4882a593Smuzhiyun /*
89*4882a593Smuzhiyun * Except for earlier ISPs where the timeout is seeded from the
90*4882a593Smuzhiyun * initialization control block.
91*4882a593Smuzhiyun */
92*4882a593Smuzhiyun tmo = ha->login_timeout;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun return tmo;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
qla24xx_abort_iocb_timeout(void * data)97*4882a593Smuzhiyun static void qla24xx_abort_iocb_timeout(void *data)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun srb_t *sp = data;
100*4882a593Smuzhiyun struct srb_iocb *abt = &sp->u.iocb_cmd;
101*4882a593Smuzhiyun struct qla_qpair *qpair = sp->qpair;
102*4882a593Smuzhiyun u32 handle;
103*4882a593Smuzhiyun unsigned long flags;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun if (sp->cmd_sp)
106*4882a593Smuzhiyun ql_dbg(ql_dbg_async, sp->vha, 0x507c,
107*4882a593Smuzhiyun "Abort timeout - cmd hdl=%x, cmd type=%x hdl=%x, type=%x\n",
108*4882a593Smuzhiyun sp->cmd_sp->handle, sp->cmd_sp->type,
109*4882a593Smuzhiyun sp->handle, sp->type);
110*4882a593Smuzhiyun else
111*4882a593Smuzhiyun ql_dbg(ql_dbg_async, sp->vha, 0x507c,
112*4882a593Smuzhiyun "Abort timeout 2 - hdl=%x, type=%x\n",
113*4882a593Smuzhiyun sp->handle, sp->type);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun spin_lock_irqsave(qpair->qp_lock_ptr, flags);
116*4882a593Smuzhiyun for (handle = 1; handle < qpair->req->num_outstanding_cmds; handle++) {
117*4882a593Smuzhiyun if (sp->cmd_sp && (qpair->req->outstanding_cmds[handle] ==
118*4882a593Smuzhiyun sp->cmd_sp))
119*4882a593Smuzhiyun qpair->req->outstanding_cmds[handle] = NULL;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /* removing the abort */
122*4882a593Smuzhiyun if (qpair->req->outstanding_cmds[handle] == sp) {
123*4882a593Smuzhiyun qpair->req->outstanding_cmds[handle] = NULL;
124*4882a593Smuzhiyun break;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun if (sp->cmd_sp)
130*4882a593Smuzhiyun sp->cmd_sp->done(sp->cmd_sp, QLA_OS_TIMER_EXPIRED);
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun abt->u.abt.comp_status = cpu_to_le16(CS_TIMEOUT);
133*4882a593Smuzhiyun sp->done(sp, QLA_OS_TIMER_EXPIRED);
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
qla24xx_abort_sp_done(srb_t * sp,int res)136*4882a593Smuzhiyun static void qla24xx_abort_sp_done(srb_t *sp, int res)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun struct srb_iocb *abt = &sp->u.iocb_cmd;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun del_timer(&sp->u.iocb_cmd.timer);
141*4882a593Smuzhiyun if (sp->flags & SRB_WAKEUP_ON_COMP)
142*4882a593Smuzhiyun complete(&abt->u.abt.comp);
143*4882a593Smuzhiyun else
144*4882a593Smuzhiyun sp->free(sp);
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
qla24xx_async_abort_cmd(srb_t * cmd_sp,bool wait)147*4882a593Smuzhiyun int qla24xx_async_abort_cmd(srb_t *cmd_sp, bool wait)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun scsi_qla_host_t *vha = cmd_sp->vha;
150*4882a593Smuzhiyun struct srb_iocb *abt_iocb;
151*4882a593Smuzhiyun srb_t *sp;
152*4882a593Smuzhiyun int rval = QLA_FUNCTION_FAILED;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun sp = qla2xxx_get_qpair_sp(cmd_sp->vha, cmd_sp->qpair, cmd_sp->fcport,
155*4882a593Smuzhiyun GFP_ATOMIC);
156*4882a593Smuzhiyun if (!sp)
157*4882a593Smuzhiyun return rval;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun abt_iocb = &sp->u.iocb_cmd;
160*4882a593Smuzhiyun sp->type = SRB_ABT_CMD;
161*4882a593Smuzhiyun sp->name = "abort";
162*4882a593Smuzhiyun sp->qpair = cmd_sp->qpair;
163*4882a593Smuzhiyun sp->cmd_sp = cmd_sp;
164*4882a593Smuzhiyun if (wait)
165*4882a593Smuzhiyun sp->flags = SRB_WAKEUP_ON_COMP;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun abt_iocb->timeout = qla24xx_abort_iocb_timeout;
168*4882a593Smuzhiyun init_completion(&abt_iocb->u.abt.comp);
169*4882a593Smuzhiyun /* FW can send 2 x ABTS's timeout/20s */
170*4882a593Smuzhiyun qla2x00_init_timer(sp, 42);
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
173*4882a593Smuzhiyun abt_iocb->u.abt.req_que_no = cpu_to_le16(cmd_sp->qpair->req->id);
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun sp->done = qla24xx_abort_sp_done;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun ql_dbg(ql_dbg_async, vha, 0x507c,
178*4882a593Smuzhiyun "Abort command issued - hdl=%x, type=%x\n", cmd_sp->handle,
179*4882a593Smuzhiyun cmd_sp->type);
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun rval = qla2x00_start_sp(sp);
182*4882a593Smuzhiyun if (rval != QLA_SUCCESS) {
183*4882a593Smuzhiyun sp->free(sp);
184*4882a593Smuzhiyun return rval;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun if (wait) {
188*4882a593Smuzhiyun wait_for_completion(&abt_iocb->u.abt.comp);
189*4882a593Smuzhiyun rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
190*4882a593Smuzhiyun QLA_SUCCESS : QLA_FUNCTION_FAILED;
191*4882a593Smuzhiyun sp->free(sp);
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun return rval;
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun void
qla2x00_async_iocb_timeout(void * data)198*4882a593Smuzhiyun qla2x00_async_iocb_timeout(void *data)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun srb_t *sp = data;
201*4882a593Smuzhiyun fc_port_t *fcport = sp->fcport;
202*4882a593Smuzhiyun struct srb_iocb *lio = &sp->u.iocb_cmd;
203*4882a593Smuzhiyun int rc, h;
204*4882a593Smuzhiyun unsigned long flags;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun if (fcport) {
207*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
208*4882a593Smuzhiyun "Async-%s timeout - hdl=%x portid=%06x %8phC.\n",
209*4882a593Smuzhiyun sp->name, sp->handle, fcport->d_id.b24, fcport->port_name);
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
212*4882a593Smuzhiyun } else {
213*4882a593Smuzhiyun pr_info("Async-%s timeout - hdl=%x.\n",
214*4882a593Smuzhiyun sp->name, sp->handle);
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun switch (sp->type) {
218*4882a593Smuzhiyun case SRB_LOGIN_CMD:
219*4882a593Smuzhiyun rc = qla24xx_async_abort_cmd(sp, false);
220*4882a593Smuzhiyun if (rc) {
221*4882a593Smuzhiyun /* Retry as needed. */
222*4882a593Smuzhiyun lio->u.logio.data[0] = MBS_COMMAND_ERROR;
223*4882a593Smuzhiyun lio->u.logio.data[1] =
224*4882a593Smuzhiyun lio->u.logio.flags & SRB_LOGIN_RETRIED ?
225*4882a593Smuzhiyun QLA_LOGIO_LOGIN_RETRIED : 0;
226*4882a593Smuzhiyun spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags);
227*4882a593Smuzhiyun for (h = 1; h < sp->qpair->req->num_outstanding_cmds;
228*4882a593Smuzhiyun h++) {
229*4882a593Smuzhiyun if (sp->qpair->req->outstanding_cmds[h] ==
230*4882a593Smuzhiyun sp) {
231*4882a593Smuzhiyun sp->qpair->req->outstanding_cmds[h] =
232*4882a593Smuzhiyun NULL;
233*4882a593Smuzhiyun break;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags);
237*4882a593Smuzhiyun sp->done(sp, QLA_FUNCTION_TIMEOUT);
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun break;
240*4882a593Smuzhiyun case SRB_LOGOUT_CMD:
241*4882a593Smuzhiyun case SRB_CT_PTHRU_CMD:
242*4882a593Smuzhiyun case SRB_MB_IOCB:
243*4882a593Smuzhiyun case SRB_NACK_PLOGI:
244*4882a593Smuzhiyun case SRB_NACK_PRLI:
245*4882a593Smuzhiyun case SRB_NACK_LOGO:
246*4882a593Smuzhiyun case SRB_CTRL_VP:
247*4882a593Smuzhiyun default:
248*4882a593Smuzhiyun rc = qla24xx_async_abort_cmd(sp, false);
249*4882a593Smuzhiyun if (rc) {
250*4882a593Smuzhiyun spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags);
251*4882a593Smuzhiyun for (h = 1; h < sp->qpair->req->num_outstanding_cmds;
252*4882a593Smuzhiyun h++) {
253*4882a593Smuzhiyun if (sp->qpair->req->outstanding_cmds[h] ==
254*4882a593Smuzhiyun sp) {
255*4882a593Smuzhiyun sp->qpair->req->outstanding_cmds[h] =
256*4882a593Smuzhiyun NULL;
257*4882a593Smuzhiyun break;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags);
261*4882a593Smuzhiyun sp->done(sp, QLA_FUNCTION_TIMEOUT);
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun break;
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun
qla2x00_async_login_sp_done(srb_t * sp,int res)267*4882a593Smuzhiyun static void qla2x00_async_login_sp_done(srb_t *sp, int res)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun struct scsi_qla_host *vha = sp->vha;
270*4882a593Smuzhiyun struct srb_iocb *lio = &sp->u.iocb_cmd;
271*4882a593Smuzhiyun struct event_arg ea;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20dd,
274*4882a593Smuzhiyun "%s %8phC res %d \n", __func__, sp->fcport->port_name, res);
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun if (!test_bit(UNLOADING, &vha->dpc_flags)) {
279*4882a593Smuzhiyun memset(&ea, 0, sizeof(ea));
280*4882a593Smuzhiyun ea.fcport = sp->fcport;
281*4882a593Smuzhiyun ea.data[0] = lio->u.logio.data[0];
282*4882a593Smuzhiyun ea.data[1] = lio->u.logio.data[1];
283*4882a593Smuzhiyun ea.iop[0] = lio->u.logio.iop[0];
284*4882a593Smuzhiyun ea.iop[1] = lio->u.logio.iop[1];
285*4882a593Smuzhiyun ea.sp = sp;
286*4882a593Smuzhiyun qla24xx_handle_plogi_done_event(vha, &ea);
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun sp->free(sp);
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun static inline bool
fcport_is_smaller(fc_port_t * fcport)293*4882a593Smuzhiyun fcport_is_smaller(fc_port_t *fcport)
294*4882a593Smuzhiyun {
295*4882a593Smuzhiyun if (wwn_to_u64(fcport->port_name) <
296*4882a593Smuzhiyun wwn_to_u64(fcport->vha->port_name))
297*4882a593Smuzhiyun return true;
298*4882a593Smuzhiyun else
299*4882a593Smuzhiyun return false;
300*4882a593Smuzhiyun }
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun static inline bool
fcport_is_bigger(fc_port_t * fcport)303*4882a593Smuzhiyun fcport_is_bigger(fc_port_t *fcport)
304*4882a593Smuzhiyun {
305*4882a593Smuzhiyun return !fcport_is_smaller(fcport);
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun int
qla2x00_async_login(struct scsi_qla_host * vha,fc_port_t * fcport,uint16_t * data)309*4882a593Smuzhiyun qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
310*4882a593Smuzhiyun uint16_t *data)
311*4882a593Smuzhiyun {
312*4882a593Smuzhiyun srb_t *sp;
313*4882a593Smuzhiyun struct srb_iocb *lio;
314*4882a593Smuzhiyun int rval = QLA_FUNCTION_FAILED;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT) ||
317*4882a593Smuzhiyun fcport->loop_id == FC_NO_LOOP_ID) {
318*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0xffff,
319*4882a593Smuzhiyun "%s: %8phC - not sending command.\n",
320*4882a593Smuzhiyun __func__, fcport->port_name);
321*4882a593Smuzhiyun return rval;
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
325*4882a593Smuzhiyun if (!sp)
326*4882a593Smuzhiyun goto done;
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_PEND);
329*4882a593Smuzhiyun fcport->flags |= FCF_ASYNC_SENT;
330*4882a593Smuzhiyun fcport->logout_completed = 0;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun sp->type = SRB_LOGIN_CMD;
333*4882a593Smuzhiyun sp->name = "login";
334*4882a593Smuzhiyun sp->gen1 = fcport->rscn_gen;
335*4882a593Smuzhiyun sp->gen2 = fcport->login_gen;
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun lio = &sp->u.iocb_cmd;
338*4882a593Smuzhiyun lio->timeout = qla2x00_async_iocb_timeout;
339*4882a593Smuzhiyun qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun sp->done = qla2x00_async_login_sp_done;
342*4882a593Smuzhiyun if (N2N_TOPO(fcport->vha->hw) && fcport_is_bigger(fcport))
343*4882a593Smuzhiyun lio->u.logio.flags |= SRB_LOGIN_PRLI_ONLY;
344*4882a593Smuzhiyun else
345*4882a593Smuzhiyun lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun if (NVME_TARGET(vha->hw, fcport))
348*4882a593Smuzhiyun lio->u.logio.flags |= SRB_LOGIN_SKIP_PRLI;
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2072,
351*4882a593Smuzhiyun "Async-login - %8phC hdl=%x, loopid=%x portid=%02x%02x%02x "
352*4882a593Smuzhiyun "retries=%d.\n", fcport->port_name, sp->handle, fcport->loop_id,
353*4882a593Smuzhiyun fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
354*4882a593Smuzhiyun fcport->login_retry);
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun rval = qla2x00_start_sp(sp);
357*4882a593Smuzhiyun if (rval != QLA_SUCCESS) {
358*4882a593Smuzhiyun fcport->flags |= FCF_LOGIN_NEEDED;
359*4882a593Smuzhiyun set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
360*4882a593Smuzhiyun goto done_free_sp;
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun return rval;
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun done_free_sp:
366*4882a593Smuzhiyun sp->free(sp);
367*4882a593Smuzhiyun fcport->flags &= ~FCF_ASYNC_SENT;
368*4882a593Smuzhiyun done:
369*4882a593Smuzhiyun fcport->flags &= ~FCF_ASYNC_ACTIVE;
370*4882a593Smuzhiyun return rval;
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun
qla2x00_async_logout_sp_done(srb_t * sp,int res)373*4882a593Smuzhiyun static void qla2x00_async_logout_sp_done(srb_t *sp, int res)
374*4882a593Smuzhiyun {
375*4882a593Smuzhiyun sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
376*4882a593Smuzhiyun sp->fcport->login_gen++;
377*4882a593Smuzhiyun qlt_logo_completion_handler(sp->fcport, res);
378*4882a593Smuzhiyun sp->free(sp);
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun int
qla2x00_async_logout(struct scsi_qla_host * vha,fc_port_t * fcport)382*4882a593Smuzhiyun qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
383*4882a593Smuzhiyun {
384*4882a593Smuzhiyun srb_t *sp;
385*4882a593Smuzhiyun struct srb_iocb *lio;
386*4882a593Smuzhiyun int rval = QLA_FUNCTION_FAILED;
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun fcport->flags |= FCF_ASYNC_SENT;
389*4882a593Smuzhiyun sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
390*4882a593Smuzhiyun if (!sp)
391*4882a593Smuzhiyun goto done;
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun sp->type = SRB_LOGOUT_CMD;
394*4882a593Smuzhiyun sp->name = "logout";
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun lio = &sp->u.iocb_cmd;
397*4882a593Smuzhiyun lio->timeout = qla2x00_async_iocb_timeout;
398*4882a593Smuzhiyun qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun sp->done = qla2x00_async_logout_sp_done;
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2070,
403*4882a593Smuzhiyun "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC.\n",
404*4882a593Smuzhiyun sp->handle, fcport->loop_id, fcport->d_id.b.domain,
405*4882a593Smuzhiyun fcport->d_id.b.area, fcport->d_id.b.al_pa,
406*4882a593Smuzhiyun fcport->port_name);
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun rval = qla2x00_start_sp(sp);
409*4882a593Smuzhiyun if (rval != QLA_SUCCESS)
410*4882a593Smuzhiyun goto done_free_sp;
411*4882a593Smuzhiyun return rval;
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun done_free_sp:
414*4882a593Smuzhiyun sp->free(sp);
415*4882a593Smuzhiyun done:
416*4882a593Smuzhiyun fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
417*4882a593Smuzhiyun return rval;
418*4882a593Smuzhiyun }
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun void
qla2x00_async_prlo_done(struct scsi_qla_host * vha,fc_port_t * fcport,uint16_t * data)421*4882a593Smuzhiyun qla2x00_async_prlo_done(struct scsi_qla_host *vha, fc_port_t *fcport,
422*4882a593Smuzhiyun uint16_t *data)
423*4882a593Smuzhiyun {
424*4882a593Smuzhiyun fcport->flags &= ~FCF_ASYNC_ACTIVE;
425*4882a593Smuzhiyun /* Don't re-login in target mode */
426*4882a593Smuzhiyun if (!fcport->tgt_session)
427*4882a593Smuzhiyun qla2x00_mark_device_lost(vha, fcport, 1);
428*4882a593Smuzhiyun qlt_logo_completion_handler(fcport, data[0]);
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun
qla2x00_async_prlo_sp_done(srb_t * sp,int res)431*4882a593Smuzhiyun static void qla2x00_async_prlo_sp_done(srb_t *sp, int res)
432*4882a593Smuzhiyun {
433*4882a593Smuzhiyun struct srb_iocb *lio = &sp->u.iocb_cmd;
434*4882a593Smuzhiyun struct scsi_qla_host *vha = sp->vha;
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun sp->fcport->flags &= ~FCF_ASYNC_ACTIVE;
437*4882a593Smuzhiyun if (!test_bit(UNLOADING, &vha->dpc_flags))
438*4882a593Smuzhiyun qla2x00_post_async_prlo_done_work(sp->fcport->vha, sp->fcport,
439*4882a593Smuzhiyun lio->u.logio.data);
440*4882a593Smuzhiyun sp->free(sp);
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun int
qla2x00_async_prlo(struct scsi_qla_host * vha,fc_port_t * fcport)444*4882a593Smuzhiyun qla2x00_async_prlo(struct scsi_qla_host *vha, fc_port_t *fcport)
445*4882a593Smuzhiyun {
446*4882a593Smuzhiyun srb_t *sp;
447*4882a593Smuzhiyun struct srb_iocb *lio;
448*4882a593Smuzhiyun int rval;
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun rval = QLA_FUNCTION_FAILED;
451*4882a593Smuzhiyun sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
452*4882a593Smuzhiyun if (!sp)
453*4882a593Smuzhiyun goto done;
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun sp->type = SRB_PRLO_CMD;
456*4882a593Smuzhiyun sp->name = "prlo";
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun lio = &sp->u.iocb_cmd;
459*4882a593Smuzhiyun lio->timeout = qla2x00_async_iocb_timeout;
460*4882a593Smuzhiyun qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun sp->done = qla2x00_async_prlo_sp_done;
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2070,
465*4882a593Smuzhiyun "Async-prlo - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
466*4882a593Smuzhiyun sp->handle, fcport->loop_id, fcport->d_id.b.domain,
467*4882a593Smuzhiyun fcport->d_id.b.area, fcport->d_id.b.al_pa);
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun rval = qla2x00_start_sp(sp);
470*4882a593Smuzhiyun if (rval != QLA_SUCCESS)
471*4882a593Smuzhiyun goto done_free_sp;
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun return rval;
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun done_free_sp:
476*4882a593Smuzhiyun sp->free(sp);
477*4882a593Smuzhiyun done:
478*4882a593Smuzhiyun fcport->flags &= ~FCF_ASYNC_ACTIVE;
479*4882a593Smuzhiyun return rval;
480*4882a593Smuzhiyun }
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun static
qla24xx_handle_adisc_event(scsi_qla_host_t * vha,struct event_arg * ea)483*4882a593Smuzhiyun void qla24xx_handle_adisc_event(scsi_qla_host_t *vha, struct event_arg *ea)
484*4882a593Smuzhiyun {
485*4882a593Smuzhiyun struct fc_port *fcport = ea->fcport;
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20d2,
488*4882a593Smuzhiyun "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d lid %d\n",
489*4882a593Smuzhiyun __func__, fcport->port_name, fcport->disc_state,
490*4882a593Smuzhiyun fcport->fw_login_state, ea->rc, fcport->login_gen, ea->sp->gen2,
491*4882a593Smuzhiyun fcport->rscn_gen, ea->sp->gen1, fcport->loop_id);
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n",
494*4882a593Smuzhiyun ea->data[0]);
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun if (ea->data[0] != MBS_COMMAND_COMPLETE) {
497*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2066,
498*4882a593Smuzhiyun "%s %8phC: adisc fail: post delete\n",
499*4882a593Smuzhiyun __func__, ea->fcport->port_name);
500*4882a593Smuzhiyun /* deleted = 0 & logout_on_delete = force fw cleanup */
501*4882a593Smuzhiyun fcport->deleted = 0;
502*4882a593Smuzhiyun fcport->logout_on_delete = 1;
503*4882a593Smuzhiyun qlt_schedule_sess_for_deletion(ea->fcport);
504*4882a593Smuzhiyun return;
505*4882a593Smuzhiyun }
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun if (ea->fcport->disc_state == DSC_DELETE_PEND)
508*4882a593Smuzhiyun return;
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun if (ea->sp->gen2 != ea->fcport->login_gen) {
511*4882a593Smuzhiyun /* target side must have changed it. */
512*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20d3,
513*4882a593Smuzhiyun "%s %8phC generation changed\n",
514*4882a593Smuzhiyun __func__, ea->fcport->port_name);
515*4882a593Smuzhiyun return;
516*4882a593Smuzhiyun } else if (ea->sp->gen1 != ea->fcport->rscn_gen) {
517*4882a593Smuzhiyun qla_rscn_replay(fcport);
518*4882a593Smuzhiyun qlt_schedule_sess_for_deletion(fcport);
519*4882a593Smuzhiyun return;
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun __qla24xx_handle_gpdb_event(vha, ea);
523*4882a593Smuzhiyun }
524*4882a593Smuzhiyun
qla_post_els_plogi_work(struct scsi_qla_host * vha,fc_port_t * fcport)525*4882a593Smuzhiyun static int qla_post_els_plogi_work(struct scsi_qla_host *vha, fc_port_t *fcport)
526*4882a593Smuzhiyun {
527*4882a593Smuzhiyun struct qla_work_evt *e;
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun e = qla2x00_alloc_work(vha, QLA_EVT_ELS_PLOGI);
530*4882a593Smuzhiyun if (!e)
531*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun e->u.fcport.fcport = fcport;
534*4882a593Smuzhiyun fcport->flags |= FCF_ASYNC_ACTIVE;
535*4882a593Smuzhiyun qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_PEND);
536*4882a593Smuzhiyun return qla2x00_post_work(vha, e);
537*4882a593Smuzhiyun }
538*4882a593Smuzhiyun
qla2x00_async_adisc_sp_done(srb_t * sp,int res)539*4882a593Smuzhiyun static void qla2x00_async_adisc_sp_done(srb_t *sp, int res)
540*4882a593Smuzhiyun {
541*4882a593Smuzhiyun struct scsi_qla_host *vha = sp->vha;
542*4882a593Smuzhiyun struct event_arg ea;
543*4882a593Smuzhiyun struct srb_iocb *lio = &sp->u.iocb_cmd;
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2066,
546*4882a593Smuzhiyun "Async done-%s res %x %8phC\n",
547*4882a593Smuzhiyun sp->name, res, sp->fcport->port_name);
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun memset(&ea, 0, sizeof(ea));
552*4882a593Smuzhiyun ea.rc = res;
553*4882a593Smuzhiyun ea.data[0] = lio->u.logio.data[0];
554*4882a593Smuzhiyun ea.data[1] = lio->u.logio.data[1];
555*4882a593Smuzhiyun ea.iop[0] = lio->u.logio.iop[0];
556*4882a593Smuzhiyun ea.iop[1] = lio->u.logio.iop[1];
557*4882a593Smuzhiyun ea.fcport = sp->fcport;
558*4882a593Smuzhiyun ea.sp = sp;
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun qla24xx_handle_adisc_event(vha, &ea);
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun sp->free(sp);
563*4882a593Smuzhiyun }
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun int
qla2x00_async_adisc(struct scsi_qla_host * vha,fc_port_t * fcport,uint16_t * data)566*4882a593Smuzhiyun qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
567*4882a593Smuzhiyun uint16_t *data)
568*4882a593Smuzhiyun {
569*4882a593Smuzhiyun srb_t *sp;
570*4882a593Smuzhiyun struct srb_iocb *lio;
571*4882a593Smuzhiyun int rval = QLA_FUNCTION_FAILED;
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun if (IS_SESSION_DELETED(fcport)) {
574*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0xffff,
575*4882a593Smuzhiyun "%s: %8phC is being delete - not sending command.\n",
576*4882a593Smuzhiyun __func__, fcport->port_name);
577*4882a593Smuzhiyun fcport->flags &= ~FCF_ASYNC_ACTIVE;
578*4882a593Smuzhiyun return rval;
579*4882a593Smuzhiyun }
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
582*4882a593Smuzhiyun return rval;
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun fcport->flags |= FCF_ASYNC_SENT;
585*4882a593Smuzhiyun sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
586*4882a593Smuzhiyun if (!sp)
587*4882a593Smuzhiyun goto done;
588*4882a593Smuzhiyun
589*4882a593Smuzhiyun sp->type = SRB_ADISC_CMD;
590*4882a593Smuzhiyun sp->name = "adisc";
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun lio = &sp->u.iocb_cmd;
593*4882a593Smuzhiyun lio->timeout = qla2x00_async_iocb_timeout;
594*4882a593Smuzhiyun sp->gen1 = fcport->rscn_gen;
595*4882a593Smuzhiyun sp->gen2 = fcport->login_gen;
596*4882a593Smuzhiyun qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun sp->done = qla2x00_async_adisc_sp_done;
599*4882a593Smuzhiyun if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
600*4882a593Smuzhiyun lio->u.logio.flags |= SRB_LOGIN_RETRIED;
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x206f,
603*4882a593Smuzhiyun "Async-adisc - hdl=%x loopid=%x portid=%06x %8phC.\n",
604*4882a593Smuzhiyun sp->handle, fcport->loop_id, fcport->d_id.b24, fcport->port_name);
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun rval = qla2x00_start_sp(sp);
607*4882a593Smuzhiyun if (rval != QLA_SUCCESS)
608*4882a593Smuzhiyun goto done_free_sp;
609*4882a593Smuzhiyun
610*4882a593Smuzhiyun return rval;
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun done_free_sp:
613*4882a593Smuzhiyun sp->free(sp);
614*4882a593Smuzhiyun done:
615*4882a593Smuzhiyun fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
616*4882a593Smuzhiyun qla2x00_post_async_adisc_work(vha, fcport, data);
617*4882a593Smuzhiyun return rval;
618*4882a593Smuzhiyun }
619*4882a593Smuzhiyun
qla2x00_is_reserved_id(scsi_qla_host_t * vha,uint16_t loop_id)620*4882a593Smuzhiyun static bool qla2x00_is_reserved_id(scsi_qla_host_t *vha, uint16_t loop_id)
621*4882a593Smuzhiyun {
622*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun if (IS_FWI2_CAPABLE(ha))
625*4882a593Smuzhiyun return loop_id > NPH_LAST_HANDLE;
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun return (loop_id > ha->max_loop_id && loop_id < SNS_FIRST_LOOP_ID) ||
628*4882a593Smuzhiyun loop_id == MANAGEMENT_SERVER || loop_id == BROADCAST;
629*4882a593Smuzhiyun }
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun /**
632*4882a593Smuzhiyun * qla2x00_find_new_loop_id - scan through our port list and find a new usable loop ID
633*4882a593Smuzhiyun * @vha: adapter state pointer.
634*4882a593Smuzhiyun * @dev: port structure pointer.
635*4882a593Smuzhiyun *
636*4882a593Smuzhiyun * Returns:
637*4882a593Smuzhiyun * qla2x00 local function return status code.
638*4882a593Smuzhiyun *
639*4882a593Smuzhiyun * Context:
640*4882a593Smuzhiyun * Kernel context.
641*4882a593Smuzhiyun */
qla2x00_find_new_loop_id(scsi_qla_host_t * vha,fc_port_t * dev)642*4882a593Smuzhiyun static int qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
643*4882a593Smuzhiyun {
644*4882a593Smuzhiyun int rval;
645*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
646*4882a593Smuzhiyun unsigned long flags = 0;
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun rval = QLA_SUCCESS;
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun spin_lock_irqsave(&ha->vport_slock, flags);
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun dev->loop_id = find_first_zero_bit(ha->loop_id_map, LOOPID_MAP_SIZE);
653*4882a593Smuzhiyun if (dev->loop_id >= LOOPID_MAP_SIZE ||
654*4882a593Smuzhiyun qla2x00_is_reserved_id(vha, dev->loop_id)) {
655*4882a593Smuzhiyun dev->loop_id = FC_NO_LOOP_ID;
656*4882a593Smuzhiyun rval = QLA_FUNCTION_FAILED;
657*4882a593Smuzhiyun } else {
658*4882a593Smuzhiyun set_bit(dev->loop_id, ha->loop_id_map);
659*4882a593Smuzhiyun }
660*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->vport_slock, flags);
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun if (rval == QLA_SUCCESS)
663*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
664*4882a593Smuzhiyun "Assigning new loopid=%x, portid=%x.\n",
665*4882a593Smuzhiyun dev->loop_id, dev->d_id.b24);
666*4882a593Smuzhiyun else
667*4882a593Smuzhiyun ql_log(ql_log_warn, dev->vha, 0x2087,
668*4882a593Smuzhiyun "No loop_id's available, portid=%x.\n",
669*4882a593Smuzhiyun dev->d_id.b24);
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun return rval;
672*4882a593Smuzhiyun }
673*4882a593Smuzhiyun
qla2x00_clear_loop_id(fc_port_t * fcport)674*4882a593Smuzhiyun void qla2x00_clear_loop_id(fc_port_t *fcport)
675*4882a593Smuzhiyun {
676*4882a593Smuzhiyun struct qla_hw_data *ha = fcport->vha->hw;
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun if (fcport->loop_id == FC_NO_LOOP_ID ||
679*4882a593Smuzhiyun qla2x00_is_reserved_id(fcport->vha, fcport->loop_id))
680*4882a593Smuzhiyun return;
681*4882a593Smuzhiyun
682*4882a593Smuzhiyun clear_bit(fcport->loop_id, ha->loop_id_map);
683*4882a593Smuzhiyun fcport->loop_id = FC_NO_LOOP_ID;
684*4882a593Smuzhiyun }
685*4882a593Smuzhiyun
qla24xx_handle_gnl_done_event(scsi_qla_host_t * vha,struct event_arg * ea)686*4882a593Smuzhiyun static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha,
687*4882a593Smuzhiyun struct event_arg *ea)
688*4882a593Smuzhiyun {
689*4882a593Smuzhiyun fc_port_t *fcport, *conflict_fcport;
690*4882a593Smuzhiyun struct get_name_list_extended *e;
691*4882a593Smuzhiyun u16 i, n, found = 0, loop_id;
692*4882a593Smuzhiyun port_id_t id;
693*4882a593Smuzhiyun u64 wwn;
694*4882a593Smuzhiyun u16 data[2];
695*4882a593Smuzhiyun u8 current_login_state, nvme_cls;
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun fcport = ea->fcport;
698*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0xffff,
699*4882a593Smuzhiyun "%s %8phC DS %d LS rc %d %d login %d|%d rscn %d|%d lid %d\n",
700*4882a593Smuzhiyun __func__, fcport->port_name, fcport->disc_state,
701*4882a593Smuzhiyun fcport->fw_login_state, ea->rc,
702*4882a593Smuzhiyun fcport->login_gen, fcport->last_login_gen,
703*4882a593Smuzhiyun fcport->rscn_gen, fcport->last_rscn_gen, vha->loop_id);
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun if (fcport->disc_state == DSC_DELETE_PEND)
706*4882a593Smuzhiyun return;
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun if (ea->rc) { /* rval */
709*4882a593Smuzhiyun if (fcport->login_retry == 0) {
710*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20de,
711*4882a593Smuzhiyun "GNL failed Port login retry %8phN, retry cnt=%d.\n",
712*4882a593Smuzhiyun fcport->port_name, fcport->login_retry);
713*4882a593Smuzhiyun }
714*4882a593Smuzhiyun return;
715*4882a593Smuzhiyun }
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun if (fcport->last_rscn_gen != fcport->rscn_gen) {
718*4882a593Smuzhiyun qla_rscn_replay(fcport);
719*4882a593Smuzhiyun qlt_schedule_sess_for_deletion(fcport);
720*4882a593Smuzhiyun return;
721*4882a593Smuzhiyun } else if (fcport->last_login_gen != fcport->login_gen) {
722*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20e0,
723*4882a593Smuzhiyun "%s %8phC login gen changed\n",
724*4882a593Smuzhiyun __func__, fcport->port_name);
725*4882a593Smuzhiyun return;
726*4882a593Smuzhiyun }
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun n = ea->data[0] / sizeof(struct get_name_list_extended);
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20e1,
731*4882a593Smuzhiyun "%s %d %8phC n %d %02x%02x%02x lid %d \n",
732*4882a593Smuzhiyun __func__, __LINE__, fcport->port_name, n,
733*4882a593Smuzhiyun fcport->d_id.b.domain, fcport->d_id.b.area,
734*4882a593Smuzhiyun fcport->d_id.b.al_pa, fcport->loop_id);
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun for (i = 0; i < n; i++) {
737*4882a593Smuzhiyun e = &vha->gnl.l[i];
738*4882a593Smuzhiyun wwn = wwn_to_u64(e->port_name);
739*4882a593Smuzhiyun id.b.domain = e->port_id[2];
740*4882a593Smuzhiyun id.b.area = e->port_id[1];
741*4882a593Smuzhiyun id.b.al_pa = e->port_id[0];
742*4882a593Smuzhiyun id.b.rsvd_1 = 0;
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE))
745*4882a593Smuzhiyun continue;
746*4882a593Smuzhiyun
747*4882a593Smuzhiyun if (IS_SW_RESV_ADDR(id))
748*4882a593Smuzhiyun continue;
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun found = 1;
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun loop_id = le16_to_cpu(e->nport_handle);
753*4882a593Smuzhiyun loop_id = (loop_id & 0x7fff);
754*4882a593Smuzhiyun nvme_cls = e->current_login_state >> 4;
755*4882a593Smuzhiyun current_login_state = e->current_login_state & 0xf;
756*4882a593Smuzhiyun
757*4882a593Smuzhiyun if (PRLI_PHASE(nvme_cls)) {
758*4882a593Smuzhiyun current_login_state = nvme_cls;
759*4882a593Smuzhiyun fcport->fc4_type &= ~FS_FC4TYPE_FCP;
760*4882a593Smuzhiyun fcport->fc4_type |= FS_FC4TYPE_NVME;
761*4882a593Smuzhiyun } else if (PRLI_PHASE(current_login_state)) {
762*4882a593Smuzhiyun fcport->fc4_type |= FS_FC4TYPE_FCP;
763*4882a593Smuzhiyun fcport->fc4_type &= ~FS_FC4TYPE_NVME;
764*4882a593Smuzhiyun }
765*4882a593Smuzhiyun
766*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20e2,
767*4882a593Smuzhiyun "%s found %8phC CLS [%x|%x] fc4_type %d ID[%06x|%06x] lid[%d|%d]\n",
768*4882a593Smuzhiyun __func__, fcport->port_name,
769*4882a593Smuzhiyun e->current_login_state, fcport->fw_login_state,
770*4882a593Smuzhiyun fcport->fc4_type, id.b24, fcport->d_id.b24,
771*4882a593Smuzhiyun loop_id, fcport->loop_id);
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun switch (fcport->disc_state) {
774*4882a593Smuzhiyun case DSC_DELETE_PEND:
775*4882a593Smuzhiyun case DSC_DELETED:
776*4882a593Smuzhiyun break;
777*4882a593Smuzhiyun default:
778*4882a593Smuzhiyun if ((id.b24 != fcport->d_id.b24 &&
779*4882a593Smuzhiyun fcport->d_id.b24 &&
780*4882a593Smuzhiyun fcport->loop_id != FC_NO_LOOP_ID) ||
781*4882a593Smuzhiyun (fcport->loop_id != FC_NO_LOOP_ID &&
782*4882a593Smuzhiyun fcport->loop_id != loop_id)) {
783*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20e3,
784*4882a593Smuzhiyun "%s %d %8phC post del sess\n",
785*4882a593Smuzhiyun __func__, __LINE__, fcport->port_name);
786*4882a593Smuzhiyun if (fcport->n2n_flag)
787*4882a593Smuzhiyun fcport->d_id.b24 = 0;
788*4882a593Smuzhiyun qlt_schedule_sess_for_deletion(fcport);
789*4882a593Smuzhiyun return;
790*4882a593Smuzhiyun }
791*4882a593Smuzhiyun break;
792*4882a593Smuzhiyun }
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun fcport->loop_id = loop_id;
795*4882a593Smuzhiyun if (fcport->n2n_flag)
796*4882a593Smuzhiyun fcport->d_id.b24 = id.b24;
797*4882a593Smuzhiyun
798*4882a593Smuzhiyun wwn = wwn_to_u64(fcport->port_name);
799*4882a593Smuzhiyun qlt_find_sess_invalidate_other(vha, wwn,
800*4882a593Smuzhiyun id, loop_id, &conflict_fcport);
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun if (conflict_fcport) {
803*4882a593Smuzhiyun /*
804*4882a593Smuzhiyun * Another share fcport share the same loop_id &
805*4882a593Smuzhiyun * nport id. Conflict fcport needs to finish
806*4882a593Smuzhiyun * cleanup before this fcport can proceed to login.
807*4882a593Smuzhiyun */
808*4882a593Smuzhiyun conflict_fcport->conflict = fcport;
809*4882a593Smuzhiyun fcport->login_pause = 1;
810*4882a593Smuzhiyun }
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun switch (vha->hw->current_topology) {
813*4882a593Smuzhiyun default:
814*4882a593Smuzhiyun switch (current_login_state) {
815*4882a593Smuzhiyun case DSC_LS_PRLI_COMP:
816*4882a593Smuzhiyun ql_dbg(ql_dbg_disc + ql_dbg_verbose,
817*4882a593Smuzhiyun vha, 0x20e4, "%s %d %8phC post gpdb\n",
818*4882a593Smuzhiyun __func__, __LINE__, fcport->port_name);
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun if ((e->prli_svc_param_word_3[0] & BIT_4) == 0)
821*4882a593Smuzhiyun fcport->port_type = FCT_INITIATOR;
822*4882a593Smuzhiyun else
823*4882a593Smuzhiyun fcport->port_type = FCT_TARGET;
824*4882a593Smuzhiyun data[0] = data[1] = 0;
825*4882a593Smuzhiyun qla2x00_post_async_adisc_work(vha, fcport,
826*4882a593Smuzhiyun data);
827*4882a593Smuzhiyun break;
828*4882a593Smuzhiyun case DSC_LS_PORT_UNAVAIL:
829*4882a593Smuzhiyun default:
830*4882a593Smuzhiyun if (fcport->loop_id == FC_NO_LOOP_ID) {
831*4882a593Smuzhiyun qla2x00_find_new_loop_id(vha, fcport);
832*4882a593Smuzhiyun fcport->fw_login_state =
833*4882a593Smuzhiyun DSC_LS_PORT_UNAVAIL;
834*4882a593Smuzhiyun }
835*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20e5,
836*4882a593Smuzhiyun "%s %d %8phC\n", __func__, __LINE__,
837*4882a593Smuzhiyun fcport->port_name);
838*4882a593Smuzhiyun qla24xx_fcport_handle_login(vha, fcport);
839*4882a593Smuzhiyun break;
840*4882a593Smuzhiyun }
841*4882a593Smuzhiyun break;
842*4882a593Smuzhiyun case ISP_CFG_N:
843*4882a593Smuzhiyun fcport->fw_login_state = current_login_state;
844*4882a593Smuzhiyun fcport->d_id = id;
845*4882a593Smuzhiyun switch (current_login_state) {
846*4882a593Smuzhiyun case DSC_LS_PRLI_PEND:
847*4882a593Smuzhiyun /*
848*4882a593Smuzhiyun * In the middle of PRLI. Let it finish.
849*4882a593Smuzhiyun * Allow relogin code to recheck state again
850*4882a593Smuzhiyun * with GNL. Push disc_state back to DELETED
851*4882a593Smuzhiyun * so GNL can go out again
852*4882a593Smuzhiyun */
853*4882a593Smuzhiyun qla2x00_set_fcport_disc_state(fcport,
854*4882a593Smuzhiyun DSC_DELETED);
855*4882a593Smuzhiyun break;
856*4882a593Smuzhiyun case DSC_LS_PRLI_COMP:
857*4882a593Smuzhiyun if ((e->prli_svc_param_word_3[0] & BIT_4) == 0)
858*4882a593Smuzhiyun fcport->port_type = FCT_INITIATOR;
859*4882a593Smuzhiyun else
860*4882a593Smuzhiyun fcport->port_type = FCT_TARGET;
861*4882a593Smuzhiyun
862*4882a593Smuzhiyun data[0] = data[1] = 0;
863*4882a593Smuzhiyun qla2x00_post_async_adisc_work(vha, fcport,
864*4882a593Smuzhiyun data);
865*4882a593Smuzhiyun break;
866*4882a593Smuzhiyun case DSC_LS_PLOGI_COMP:
867*4882a593Smuzhiyun if (fcport_is_bigger(fcport)) {
868*4882a593Smuzhiyun /* local adapter is smaller */
869*4882a593Smuzhiyun if (fcport->loop_id != FC_NO_LOOP_ID)
870*4882a593Smuzhiyun qla2x00_clear_loop_id(fcport);
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun fcport->loop_id = loop_id;
873*4882a593Smuzhiyun qla24xx_fcport_handle_login(vha,
874*4882a593Smuzhiyun fcport);
875*4882a593Smuzhiyun break;
876*4882a593Smuzhiyun }
877*4882a593Smuzhiyun fallthrough;
878*4882a593Smuzhiyun default:
879*4882a593Smuzhiyun if (fcport_is_smaller(fcport)) {
880*4882a593Smuzhiyun /* local adapter is bigger */
881*4882a593Smuzhiyun if (fcport->loop_id != FC_NO_LOOP_ID)
882*4882a593Smuzhiyun qla2x00_clear_loop_id(fcport);
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun fcport->loop_id = loop_id;
885*4882a593Smuzhiyun qla24xx_fcport_handle_login(vha,
886*4882a593Smuzhiyun fcport);
887*4882a593Smuzhiyun }
888*4882a593Smuzhiyun break;
889*4882a593Smuzhiyun }
890*4882a593Smuzhiyun break;
891*4882a593Smuzhiyun } /* switch (ha->current_topology) */
892*4882a593Smuzhiyun }
893*4882a593Smuzhiyun
894*4882a593Smuzhiyun if (!found) {
895*4882a593Smuzhiyun switch (vha->hw->current_topology) {
896*4882a593Smuzhiyun case ISP_CFG_F:
897*4882a593Smuzhiyun case ISP_CFG_FL:
898*4882a593Smuzhiyun for (i = 0; i < n; i++) {
899*4882a593Smuzhiyun e = &vha->gnl.l[i];
900*4882a593Smuzhiyun id.b.domain = e->port_id[0];
901*4882a593Smuzhiyun id.b.area = e->port_id[1];
902*4882a593Smuzhiyun id.b.al_pa = e->port_id[2];
903*4882a593Smuzhiyun id.b.rsvd_1 = 0;
904*4882a593Smuzhiyun loop_id = le16_to_cpu(e->nport_handle);
905*4882a593Smuzhiyun
906*4882a593Smuzhiyun if (fcport->d_id.b24 == id.b24) {
907*4882a593Smuzhiyun conflict_fcport =
908*4882a593Smuzhiyun qla2x00_find_fcport_by_wwpn(vha,
909*4882a593Smuzhiyun e->port_name, 0);
910*4882a593Smuzhiyun if (conflict_fcport) {
911*4882a593Smuzhiyun ql_dbg(ql_dbg_disc + ql_dbg_verbose,
912*4882a593Smuzhiyun vha, 0x20e5,
913*4882a593Smuzhiyun "%s %d %8phC post del sess\n",
914*4882a593Smuzhiyun __func__, __LINE__,
915*4882a593Smuzhiyun conflict_fcport->port_name);
916*4882a593Smuzhiyun qlt_schedule_sess_for_deletion
917*4882a593Smuzhiyun (conflict_fcport);
918*4882a593Smuzhiyun }
919*4882a593Smuzhiyun }
920*4882a593Smuzhiyun /*
921*4882a593Smuzhiyun * FW already picked this loop id for
922*4882a593Smuzhiyun * another fcport
923*4882a593Smuzhiyun */
924*4882a593Smuzhiyun if (fcport->loop_id == loop_id)
925*4882a593Smuzhiyun fcport->loop_id = FC_NO_LOOP_ID;
926*4882a593Smuzhiyun }
927*4882a593Smuzhiyun qla24xx_fcport_handle_login(vha, fcport);
928*4882a593Smuzhiyun break;
929*4882a593Smuzhiyun case ISP_CFG_N:
930*4882a593Smuzhiyun qla2x00_set_fcport_disc_state(fcport, DSC_DELETED);
931*4882a593Smuzhiyun if (time_after_eq(jiffies, fcport->dm_login_expire)) {
932*4882a593Smuzhiyun if (fcport->n2n_link_reset_cnt < 2) {
933*4882a593Smuzhiyun fcport->n2n_link_reset_cnt++;
934*4882a593Smuzhiyun /*
935*4882a593Smuzhiyun * remote port is not sending PLOGI.
936*4882a593Smuzhiyun * Reset link to kick start his state
937*4882a593Smuzhiyun * machine
938*4882a593Smuzhiyun */
939*4882a593Smuzhiyun set_bit(N2N_LINK_RESET,
940*4882a593Smuzhiyun &vha->dpc_flags);
941*4882a593Smuzhiyun } else {
942*4882a593Smuzhiyun if (fcport->n2n_chip_reset < 1) {
943*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x705d,
944*4882a593Smuzhiyun "Chip reset to bring laser down");
945*4882a593Smuzhiyun set_bit(ISP_ABORT_NEEDED,
946*4882a593Smuzhiyun &vha->dpc_flags);
947*4882a593Smuzhiyun fcport->n2n_chip_reset++;
948*4882a593Smuzhiyun } else {
949*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x705d,
950*4882a593Smuzhiyun "Remote port %8ph is not coming back\n",
951*4882a593Smuzhiyun fcport->port_name);
952*4882a593Smuzhiyun fcport->scan_state = 0;
953*4882a593Smuzhiyun }
954*4882a593Smuzhiyun }
955*4882a593Smuzhiyun qla2xxx_wake_dpc(vha);
956*4882a593Smuzhiyun } else {
957*4882a593Smuzhiyun /*
958*4882a593Smuzhiyun * report port suppose to do PLOGI. Give him
959*4882a593Smuzhiyun * more time. FW will catch it.
960*4882a593Smuzhiyun */
961*4882a593Smuzhiyun set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
962*4882a593Smuzhiyun }
963*4882a593Smuzhiyun break;
964*4882a593Smuzhiyun case ISP_CFG_NL:
965*4882a593Smuzhiyun qla24xx_fcport_handle_login(vha, fcport);
966*4882a593Smuzhiyun break;
967*4882a593Smuzhiyun default:
968*4882a593Smuzhiyun break;
969*4882a593Smuzhiyun }
970*4882a593Smuzhiyun }
971*4882a593Smuzhiyun } /* gnl_event */
972*4882a593Smuzhiyun
qla24xx_async_gnl_sp_done(srb_t * sp,int res)973*4882a593Smuzhiyun static void qla24xx_async_gnl_sp_done(srb_t *sp, int res)
974*4882a593Smuzhiyun {
975*4882a593Smuzhiyun struct scsi_qla_host *vha = sp->vha;
976*4882a593Smuzhiyun unsigned long flags;
977*4882a593Smuzhiyun struct fc_port *fcport = NULL, *tf;
978*4882a593Smuzhiyun u16 i, n = 0, loop_id;
979*4882a593Smuzhiyun struct event_arg ea;
980*4882a593Smuzhiyun struct get_name_list_extended *e;
981*4882a593Smuzhiyun u64 wwn;
982*4882a593Smuzhiyun struct list_head h;
983*4882a593Smuzhiyun bool found = false;
984*4882a593Smuzhiyun
985*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20e7,
986*4882a593Smuzhiyun "Async done-%s res %x mb[1]=%x mb[2]=%x \n",
987*4882a593Smuzhiyun sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1],
988*4882a593Smuzhiyun sp->u.iocb_cmd.u.mbx.in_mb[2]);
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun sp->fcport->flags &= ~(FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE);
992*4882a593Smuzhiyun memset(&ea, 0, sizeof(ea));
993*4882a593Smuzhiyun ea.sp = sp;
994*4882a593Smuzhiyun ea.rc = res;
995*4882a593Smuzhiyun
996*4882a593Smuzhiyun if (sp->u.iocb_cmd.u.mbx.in_mb[1] >=
997*4882a593Smuzhiyun sizeof(struct get_name_list_extended)) {
998*4882a593Smuzhiyun n = sp->u.iocb_cmd.u.mbx.in_mb[1] /
999*4882a593Smuzhiyun sizeof(struct get_name_list_extended);
1000*4882a593Smuzhiyun ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */
1001*4882a593Smuzhiyun }
1002*4882a593Smuzhiyun
1003*4882a593Smuzhiyun for (i = 0; i < n; i++) {
1004*4882a593Smuzhiyun e = &vha->gnl.l[i];
1005*4882a593Smuzhiyun loop_id = le16_to_cpu(e->nport_handle);
1006*4882a593Smuzhiyun /* mask out reserve bit */
1007*4882a593Smuzhiyun loop_id = (loop_id & 0x7fff);
1008*4882a593Smuzhiyun set_bit(loop_id, vha->hw->loop_id_map);
1009*4882a593Smuzhiyun wwn = wwn_to_u64(e->port_name);
1010*4882a593Smuzhiyun
1011*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20e8,
1012*4882a593Smuzhiyun "%s %8phC %02x:%02x:%02x CLS %x/%x lid %x \n",
1013*4882a593Smuzhiyun __func__, &wwn, e->port_id[2], e->port_id[1],
1014*4882a593Smuzhiyun e->port_id[0], e->current_login_state, e->last_login_state,
1015*4882a593Smuzhiyun (loop_id & 0x7fff));
1016*4882a593Smuzhiyun }
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1019*4882a593Smuzhiyun
1020*4882a593Smuzhiyun INIT_LIST_HEAD(&h);
1021*4882a593Smuzhiyun fcport = tf = NULL;
1022*4882a593Smuzhiyun if (!list_empty(&vha->gnl.fcports))
1023*4882a593Smuzhiyun list_splice_init(&vha->gnl.fcports, &h);
1024*4882a593Smuzhiyun spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1025*4882a593Smuzhiyun
1026*4882a593Smuzhiyun list_for_each_entry_safe(fcport, tf, &h, gnl_entry) {
1027*4882a593Smuzhiyun spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1028*4882a593Smuzhiyun list_del_init(&fcport->gnl_entry);
1029*4882a593Smuzhiyun fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
1030*4882a593Smuzhiyun spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1031*4882a593Smuzhiyun ea.fcport = fcport;
1032*4882a593Smuzhiyun
1033*4882a593Smuzhiyun qla24xx_handle_gnl_done_event(vha, &ea);
1034*4882a593Smuzhiyun }
1035*4882a593Smuzhiyun
1036*4882a593Smuzhiyun /* create new fcport if fw has knowledge of new sessions */
1037*4882a593Smuzhiyun for (i = 0; i < n; i++) {
1038*4882a593Smuzhiyun port_id_t id;
1039*4882a593Smuzhiyun u64 wwnn;
1040*4882a593Smuzhiyun
1041*4882a593Smuzhiyun e = &vha->gnl.l[i];
1042*4882a593Smuzhiyun wwn = wwn_to_u64(e->port_name);
1043*4882a593Smuzhiyun
1044*4882a593Smuzhiyun found = false;
1045*4882a593Smuzhiyun list_for_each_entry_safe(fcport, tf, &vha->vp_fcports, list) {
1046*4882a593Smuzhiyun if (!memcmp((u8 *)&wwn, fcport->port_name,
1047*4882a593Smuzhiyun WWN_SIZE)) {
1048*4882a593Smuzhiyun found = true;
1049*4882a593Smuzhiyun break;
1050*4882a593Smuzhiyun }
1051*4882a593Smuzhiyun }
1052*4882a593Smuzhiyun
1053*4882a593Smuzhiyun id.b.domain = e->port_id[2];
1054*4882a593Smuzhiyun id.b.area = e->port_id[1];
1055*4882a593Smuzhiyun id.b.al_pa = e->port_id[0];
1056*4882a593Smuzhiyun id.b.rsvd_1 = 0;
1057*4882a593Smuzhiyun
1058*4882a593Smuzhiyun if (!found && wwn && !IS_SW_RESV_ADDR(id)) {
1059*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2065,
1060*4882a593Smuzhiyun "%s %d %8phC %06x post new sess\n",
1061*4882a593Smuzhiyun __func__, __LINE__, (u8 *)&wwn, id.b24);
1062*4882a593Smuzhiyun wwnn = wwn_to_u64(e->node_name);
1063*4882a593Smuzhiyun qla24xx_post_newsess_work(vha, &id, (u8 *)&wwn,
1064*4882a593Smuzhiyun (u8 *)&wwnn, NULL, 0);
1065*4882a593Smuzhiyun }
1066*4882a593Smuzhiyun }
1067*4882a593Smuzhiyun
1068*4882a593Smuzhiyun spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1069*4882a593Smuzhiyun vha->gnl.sent = 0;
1070*4882a593Smuzhiyun if (!list_empty(&vha->gnl.fcports)) {
1071*4882a593Smuzhiyun /* retrigger gnl */
1072*4882a593Smuzhiyun list_for_each_entry_safe(fcport, tf, &vha->gnl.fcports,
1073*4882a593Smuzhiyun gnl_entry) {
1074*4882a593Smuzhiyun list_del_init(&fcport->gnl_entry);
1075*4882a593Smuzhiyun fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
1076*4882a593Smuzhiyun if (qla24xx_post_gnl_work(vha, fcport) == QLA_SUCCESS)
1077*4882a593Smuzhiyun break;
1078*4882a593Smuzhiyun }
1079*4882a593Smuzhiyun }
1080*4882a593Smuzhiyun spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1081*4882a593Smuzhiyun
1082*4882a593Smuzhiyun sp->free(sp);
1083*4882a593Smuzhiyun }
1084*4882a593Smuzhiyun
qla24xx_async_gnl(struct scsi_qla_host * vha,fc_port_t * fcport)1085*4882a593Smuzhiyun int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport)
1086*4882a593Smuzhiyun {
1087*4882a593Smuzhiyun srb_t *sp;
1088*4882a593Smuzhiyun struct srb_iocb *mbx;
1089*4882a593Smuzhiyun int rval = QLA_FUNCTION_FAILED;
1090*4882a593Smuzhiyun unsigned long flags;
1091*4882a593Smuzhiyun u16 *mb;
1092*4882a593Smuzhiyun
1093*4882a593Smuzhiyun if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
1094*4882a593Smuzhiyun return rval;
1095*4882a593Smuzhiyun
1096*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20d9,
1097*4882a593Smuzhiyun "Async-gnlist WWPN %8phC \n", fcport->port_name);
1098*4882a593Smuzhiyun
1099*4882a593Smuzhiyun spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1100*4882a593Smuzhiyun fcport->flags |= FCF_ASYNC_SENT;
1101*4882a593Smuzhiyun qla2x00_set_fcport_disc_state(fcport, DSC_GNL);
1102*4882a593Smuzhiyun fcport->last_rscn_gen = fcport->rscn_gen;
1103*4882a593Smuzhiyun fcport->last_login_gen = fcport->login_gen;
1104*4882a593Smuzhiyun
1105*4882a593Smuzhiyun list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports);
1106*4882a593Smuzhiyun if (vha->gnl.sent) {
1107*4882a593Smuzhiyun spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1108*4882a593Smuzhiyun return QLA_SUCCESS;
1109*4882a593Smuzhiyun }
1110*4882a593Smuzhiyun vha->gnl.sent = 1;
1111*4882a593Smuzhiyun spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1112*4882a593Smuzhiyun
1113*4882a593Smuzhiyun sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1114*4882a593Smuzhiyun if (!sp)
1115*4882a593Smuzhiyun goto done;
1116*4882a593Smuzhiyun
1117*4882a593Smuzhiyun sp->type = SRB_MB_IOCB;
1118*4882a593Smuzhiyun sp->name = "gnlist";
1119*4882a593Smuzhiyun sp->gen1 = fcport->rscn_gen;
1120*4882a593Smuzhiyun sp->gen2 = fcport->login_gen;
1121*4882a593Smuzhiyun
1122*4882a593Smuzhiyun mbx = &sp->u.iocb_cmd;
1123*4882a593Smuzhiyun mbx->timeout = qla2x00_async_iocb_timeout;
1124*4882a593Smuzhiyun qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)+2);
1125*4882a593Smuzhiyun
1126*4882a593Smuzhiyun mb = sp->u.iocb_cmd.u.mbx.out_mb;
1127*4882a593Smuzhiyun mb[0] = MBC_PORT_NODE_NAME_LIST;
1128*4882a593Smuzhiyun mb[1] = BIT_2 | BIT_3;
1129*4882a593Smuzhiyun mb[2] = MSW(vha->gnl.ldma);
1130*4882a593Smuzhiyun mb[3] = LSW(vha->gnl.ldma);
1131*4882a593Smuzhiyun mb[6] = MSW(MSD(vha->gnl.ldma));
1132*4882a593Smuzhiyun mb[7] = LSW(MSD(vha->gnl.ldma));
1133*4882a593Smuzhiyun mb[8] = vha->gnl.size;
1134*4882a593Smuzhiyun mb[9] = vha->vp_idx;
1135*4882a593Smuzhiyun
1136*4882a593Smuzhiyun sp->done = qla24xx_async_gnl_sp_done;
1137*4882a593Smuzhiyun
1138*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20da,
1139*4882a593Smuzhiyun "Async-%s - OUT WWPN %8phC hndl %x\n",
1140*4882a593Smuzhiyun sp->name, fcport->port_name, sp->handle);
1141*4882a593Smuzhiyun
1142*4882a593Smuzhiyun rval = qla2x00_start_sp(sp);
1143*4882a593Smuzhiyun if (rval != QLA_SUCCESS)
1144*4882a593Smuzhiyun goto done_free_sp;
1145*4882a593Smuzhiyun
1146*4882a593Smuzhiyun return rval;
1147*4882a593Smuzhiyun
1148*4882a593Smuzhiyun done_free_sp:
1149*4882a593Smuzhiyun sp->free(sp);
1150*4882a593Smuzhiyun done:
1151*4882a593Smuzhiyun fcport->flags &= ~(FCF_ASYNC_ACTIVE | FCF_ASYNC_SENT);
1152*4882a593Smuzhiyun return rval;
1153*4882a593Smuzhiyun }
1154*4882a593Smuzhiyun
qla24xx_post_gnl_work(struct scsi_qla_host * vha,fc_port_t * fcport)1155*4882a593Smuzhiyun int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport)
1156*4882a593Smuzhiyun {
1157*4882a593Smuzhiyun struct qla_work_evt *e;
1158*4882a593Smuzhiyun
1159*4882a593Smuzhiyun e = qla2x00_alloc_work(vha, QLA_EVT_GNL);
1160*4882a593Smuzhiyun if (!e)
1161*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
1162*4882a593Smuzhiyun
1163*4882a593Smuzhiyun e->u.fcport.fcport = fcport;
1164*4882a593Smuzhiyun fcport->flags |= FCF_ASYNC_ACTIVE;
1165*4882a593Smuzhiyun return qla2x00_post_work(vha, e);
1166*4882a593Smuzhiyun }
1167*4882a593Smuzhiyun
qla24xx_async_gpdb_sp_done(srb_t * sp,int res)1168*4882a593Smuzhiyun static void qla24xx_async_gpdb_sp_done(srb_t *sp, int res)
1169*4882a593Smuzhiyun {
1170*4882a593Smuzhiyun struct scsi_qla_host *vha = sp->vha;
1171*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
1172*4882a593Smuzhiyun fc_port_t *fcport = sp->fcport;
1173*4882a593Smuzhiyun u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb;
1174*4882a593Smuzhiyun struct event_arg ea;
1175*4882a593Smuzhiyun
1176*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20db,
1177*4882a593Smuzhiyun "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n",
1178*4882a593Smuzhiyun sp->name, res, fcport->port_name, mb[1], mb[2]);
1179*4882a593Smuzhiyun
1180*4882a593Smuzhiyun fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
1181*4882a593Smuzhiyun
1182*4882a593Smuzhiyun if (res == QLA_FUNCTION_TIMEOUT)
1183*4882a593Smuzhiyun goto done;
1184*4882a593Smuzhiyun
1185*4882a593Smuzhiyun memset(&ea, 0, sizeof(ea));
1186*4882a593Smuzhiyun ea.fcport = fcport;
1187*4882a593Smuzhiyun ea.sp = sp;
1188*4882a593Smuzhiyun
1189*4882a593Smuzhiyun qla24xx_handle_gpdb_event(vha, &ea);
1190*4882a593Smuzhiyun
1191*4882a593Smuzhiyun done:
1192*4882a593Smuzhiyun dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in,
1193*4882a593Smuzhiyun sp->u.iocb_cmd.u.mbx.in_dma);
1194*4882a593Smuzhiyun
1195*4882a593Smuzhiyun sp->free(sp);
1196*4882a593Smuzhiyun }
1197*4882a593Smuzhiyun
qla24xx_post_prli_work(struct scsi_qla_host * vha,fc_port_t * fcport)1198*4882a593Smuzhiyun static int qla24xx_post_prli_work(struct scsi_qla_host *vha, fc_port_t *fcport)
1199*4882a593Smuzhiyun {
1200*4882a593Smuzhiyun struct qla_work_evt *e;
1201*4882a593Smuzhiyun
1202*4882a593Smuzhiyun if (vha->host->active_mode == MODE_TARGET)
1203*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
1204*4882a593Smuzhiyun
1205*4882a593Smuzhiyun e = qla2x00_alloc_work(vha, QLA_EVT_PRLI);
1206*4882a593Smuzhiyun if (!e)
1207*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
1208*4882a593Smuzhiyun
1209*4882a593Smuzhiyun e->u.fcport.fcport = fcport;
1210*4882a593Smuzhiyun
1211*4882a593Smuzhiyun return qla2x00_post_work(vha, e);
1212*4882a593Smuzhiyun }
1213*4882a593Smuzhiyun
qla2x00_async_prli_sp_done(srb_t * sp,int res)1214*4882a593Smuzhiyun static void qla2x00_async_prli_sp_done(srb_t *sp, int res)
1215*4882a593Smuzhiyun {
1216*4882a593Smuzhiyun struct scsi_qla_host *vha = sp->vha;
1217*4882a593Smuzhiyun struct srb_iocb *lio = &sp->u.iocb_cmd;
1218*4882a593Smuzhiyun struct event_arg ea;
1219*4882a593Smuzhiyun
1220*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2129,
1221*4882a593Smuzhiyun "%s %8phC res %d \n", __func__,
1222*4882a593Smuzhiyun sp->fcport->port_name, res);
1223*4882a593Smuzhiyun
1224*4882a593Smuzhiyun sp->fcport->flags &= ~FCF_ASYNC_SENT;
1225*4882a593Smuzhiyun
1226*4882a593Smuzhiyun if (!test_bit(UNLOADING, &vha->dpc_flags)) {
1227*4882a593Smuzhiyun memset(&ea, 0, sizeof(ea));
1228*4882a593Smuzhiyun ea.fcport = sp->fcport;
1229*4882a593Smuzhiyun ea.data[0] = lio->u.logio.data[0];
1230*4882a593Smuzhiyun ea.data[1] = lio->u.logio.data[1];
1231*4882a593Smuzhiyun ea.iop[0] = lio->u.logio.iop[0];
1232*4882a593Smuzhiyun ea.iop[1] = lio->u.logio.iop[1];
1233*4882a593Smuzhiyun ea.sp = sp;
1234*4882a593Smuzhiyun
1235*4882a593Smuzhiyun qla24xx_handle_prli_done_event(vha, &ea);
1236*4882a593Smuzhiyun }
1237*4882a593Smuzhiyun
1238*4882a593Smuzhiyun sp->free(sp);
1239*4882a593Smuzhiyun }
1240*4882a593Smuzhiyun
1241*4882a593Smuzhiyun int
qla24xx_async_prli(struct scsi_qla_host * vha,fc_port_t * fcport)1242*4882a593Smuzhiyun qla24xx_async_prli(struct scsi_qla_host *vha, fc_port_t *fcport)
1243*4882a593Smuzhiyun {
1244*4882a593Smuzhiyun srb_t *sp;
1245*4882a593Smuzhiyun struct srb_iocb *lio;
1246*4882a593Smuzhiyun int rval = QLA_FUNCTION_FAILED;
1247*4882a593Smuzhiyun
1248*4882a593Smuzhiyun if (!vha->flags.online) {
1249*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC exit\n",
1250*4882a593Smuzhiyun __func__, __LINE__, fcport->port_name);
1251*4882a593Smuzhiyun return rval;
1252*4882a593Smuzhiyun }
1253*4882a593Smuzhiyun
1254*4882a593Smuzhiyun if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND ||
1255*4882a593Smuzhiyun fcport->fw_login_state == DSC_LS_PRLI_PEND) &&
1256*4882a593Smuzhiyun qla_dual_mode_enabled(vha)) {
1257*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC exit\n",
1258*4882a593Smuzhiyun __func__, __LINE__, fcport->port_name);
1259*4882a593Smuzhiyun return rval;
1260*4882a593Smuzhiyun }
1261*4882a593Smuzhiyun
1262*4882a593Smuzhiyun sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1263*4882a593Smuzhiyun if (!sp)
1264*4882a593Smuzhiyun return rval;
1265*4882a593Smuzhiyun
1266*4882a593Smuzhiyun fcport->flags |= FCF_ASYNC_SENT;
1267*4882a593Smuzhiyun fcport->logout_completed = 0;
1268*4882a593Smuzhiyun
1269*4882a593Smuzhiyun sp->type = SRB_PRLI_CMD;
1270*4882a593Smuzhiyun sp->name = "prli";
1271*4882a593Smuzhiyun
1272*4882a593Smuzhiyun lio = &sp->u.iocb_cmd;
1273*4882a593Smuzhiyun lio->timeout = qla2x00_async_iocb_timeout;
1274*4882a593Smuzhiyun qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
1275*4882a593Smuzhiyun
1276*4882a593Smuzhiyun sp->done = qla2x00_async_prli_sp_done;
1277*4882a593Smuzhiyun lio->u.logio.flags = 0;
1278*4882a593Smuzhiyun
1279*4882a593Smuzhiyun if (NVME_TARGET(vha->hw, fcport))
1280*4882a593Smuzhiyun lio->u.logio.flags |= SRB_LOGIN_NVME_PRLI;
1281*4882a593Smuzhiyun
1282*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x211b,
1283*4882a593Smuzhiyun "Async-prli - %8phC hdl=%x, loopid=%x portid=%06x retries=%d fc4type %x priority %x %s.\n",
1284*4882a593Smuzhiyun fcport->port_name, sp->handle, fcport->loop_id, fcport->d_id.b24,
1285*4882a593Smuzhiyun fcport->login_retry, fcport->fc4_type, vha->hw->fc4_type_priority,
1286*4882a593Smuzhiyun NVME_TARGET(vha->hw, fcport) ? "nvme" : "fcp");
1287*4882a593Smuzhiyun
1288*4882a593Smuzhiyun rval = qla2x00_start_sp(sp);
1289*4882a593Smuzhiyun if (rval != QLA_SUCCESS) {
1290*4882a593Smuzhiyun fcport->flags |= FCF_LOGIN_NEEDED;
1291*4882a593Smuzhiyun set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1292*4882a593Smuzhiyun goto done_free_sp;
1293*4882a593Smuzhiyun }
1294*4882a593Smuzhiyun
1295*4882a593Smuzhiyun return rval;
1296*4882a593Smuzhiyun
1297*4882a593Smuzhiyun done_free_sp:
1298*4882a593Smuzhiyun sp->free(sp);
1299*4882a593Smuzhiyun fcport->flags &= ~FCF_ASYNC_SENT;
1300*4882a593Smuzhiyun return rval;
1301*4882a593Smuzhiyun }
1302*4882a593Smuzhiyun
qla24xx_post_gpdb_work(struct scsi_qla_host * vha,fc_port_t * fcport,u8 opt)1303*4882a593Smuzhiyun int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
1304*4882a593Smuzhiyun {
1305*4882a593Smuzhiyun struct qla_work_evt *e;
1306*4882a593Smuzhiyun
1307*4882a593Smuzhiyun e = qla2x00_alloc_work(vha, QLA_EVT_GPDB);
1308*4882a593Smuzhiyun if (!e)
1309*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
1310*4882a593Smuzhiyun
1311*4882a593Smuzhiyun e->u.fcport.fcport = fcport;
1312*4882a593Smuzhiyun e->u.fcport.opt = opt;
1313*4882a593Smuzhiyun fcport->flags |= FCF_ASYNC_ACTIVE;
1314*4882a593Smuzhiyun return qla2x00_post_work(vha, e);
1315*4882a593Smuzhiyun }
1316*4882a593Smuzhiyun
qla24xx_async_gpdb(struct scsi_qla_host * vha,fc_port_t * fcport,u8 opt)1317*4882a593Smuzhiyun int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
1318*4882a593Smuzhiyun {
1319*4882a593Smuzhiyun srb_t *sp;
1320*4882a593Smuzhiyun struct srb_iocb *mbx;
1321*4882a593Smuzhiyun int rval = QLA_FUNCTION_FAILED;
1322*4882a593Smuzhiyun u16 *mb;
1323*4882a593Smuzhiyun dma_addr_t pd_dma;
1324*4882a593Smuzhiyun struct port_database_24xx *pd;
1325*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
1326*4882a593Smuzhiyun
1327*4882a593Smuzhiyun if (IS_SESSION_DELETED(fcport)) {
1328*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0xffff,
1329*4882a593Smuzhiyun "%s: %8phC is being delete - not sending command.\n",
1330*4882a593Smuzhiyun __func__, fcport->port_name);
1331*4882a593Smuzhiyun fcport->flags &= ~FCF_ASYNC_ACTIVE;
1332*4882a593Smuzhiyun return rval;
1333*4882a593Smuzhiyun }
1334*4882a593Smuzhiyun
1335*4882a593Smuzhiyun if (!vha->flags.online || fcport->flags & FCF_ASYNC_SENT) {
1336*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0xffff,
1337*4882a593Smuzhiyun "%s: %8phC online %d flags %x - not sending command.\n",
1338*4882a593Smuzhiyun __func__, fcport->port_name, vha->flags.online, fcport->flags);
1339*4882a593Smuzhiyun goto done;
1340*4882a593Smuzhiyun }
1341*4882a593Smuzhiyun
1342*4882a593Smuzhiyun sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1343*4882a593Smuzhiyun if (!sp)
1344*4882a593Smuzhiyun goto done;
1345*4882a593Smuzhiyun
1346*4882a593Smuzhiyun qla2x00_set_fcport_disc_state(fcport, DSC_GPDB);
1347*4882a593Smuzhiyun
1348*4882a593Smuzhiyun fcport->flags |= FCF_ASYNC_SENT;
1349*4882a593Smuzhiyun sp->type = SRB_MB_IOCB;
1350*4882a593Smuzhiyun sp->name = "gpdb";
1351*4882a593Smuzhiyun sp->gen1 = fcport->rscn_gen;
1352*4882a593Smuzhiyun sp->gen2 = fcport->login_gen;
1353*4882a593Smuzhiyun
1354*4882a593Smuzhiyun mbx = &sp->u.iocb_cmd;
1355*4882a593Smuzhiyun mbx->timeout = qla2x00_async_iocb_timeout;
1356*4882a593Smuzhiyun qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
1357*4882a593Smuzhiyun
1358*4882a593Smuzhiyun pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
1359*4882a593Smuzhiyun if (pd == NULL) {
1360*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0xd043,
1361*4882a593Smuzhiyun "Failed to allocate port database structure.\n");
1362*4882a593Smuzhiyun goto done_free_sp;
1363*4882a593Smuzhiyun }
1364*4882a593Smuzhiyun
1365*4882a593Smuzhiyun mb = sp->u.iocb_cmd.u.mbx.out_mb;
1366*4882a593Smuzhiyun mb[0] = MBC_GET_PORT_DATABASE;
1367*4882a593Smuzhiyun mb[1] = fcport->loop_id;
1368*4882a593Smuzhiyun mb[2] = MSW(pd_dma);
1369*4882a593Smuzhiyun mb[3] = LSW(pd_dma);
1370*4882a593Smuzhiyun mb[6] = MSW(MSD(pd_dma));
1371*4882a593Smuzhiyun mb[7] = LSW(MSD(pd_dma));
1372*4882a593Smuzhiyun mb[9] = vha->vp_idx;
1373*4882a593Smuzhiyun mb[10] = opt;
1374*4882a593Smuzhiyun
1375*4882a593Smuzhiyun mbx->u.mbx.in = pd;
1376*4882a593Smuzhiyun mbx->u.mbx.in_dma = pd_dma;
1377*4882a593Smuzhiyun
1378*4882a593Smuzhiyun sp->done = qla24xx_async_gpdb_sp_done;
1379*4882a593Smuzhiyun
1380*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20dc,
1381*4882a593Smuzhiyun "Async-%s %8phC hndl %x opt %x\n",
1382*4882a593Smuzhiyun sp->name, fcport->port_name, sp->handle, opt);
1383*4882a593Smuzhiyun
1384*4882a593Smuzhiyun rval = qla2x00_start_sp(sp);
1385*4882a593Smuzhiyun if (rval != QLA_SUCCESS)
1386*4882a593Smuzhiyun goto done_free_sp;
1387*4882a593Smuzhiyun return rval;
1388*4882a593Smuzhiyun
1389*4882a593Smuzhiyun done_free_sp:
1390*4882a593Smuzhiyun if (pd)
1391*4882a593Smuzhiyun dma_pool_free(ha->s_dma_pool, pd, pd_dma);
1392*4882a593Smuzhiyun
1393*4882a593Smuzhiyun sp->free(sp);
1394*4882a593Smuzhiyun fcport->flags &= ~FCF_ASYNC_SENT;
1395*4882a593Smuzhiyun done:
1396*4882a593Smuzhiyun fcport->flags &= ~FCF_ASYNC_ACTIVE;
1397*4882a593Smuzhiyun qla24xx_post_gpdb_work(vha, fcport, opt);
1398*4882a593Smuzhiyun return rval;
1399*4882a593Smuzhiyun }
1400*4882a593Smuzhiyun
1401*4882a593Smuzhiyun static
__qla24xx_handle_gpdb_event(scsi_qla_host_t * vha,struct event_arg * ea)1402*4882a593Smuzhiyun void __qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
1403*4882a593Smuzhiyun {
1404*4882a593Smuzhiyun unsigned long flags;
1405*4882a593Smuzhiyun
1406*4882a593Smuzhiyun spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1407*4882a593Smuzhiyun ea->fcport->login_gen++;
1408*4882a593Smuzhiyun ea->fcport->deleted = 0;
1409*4882a593Smuzhiyun ea->fcport->logout_on_delete = 1;
1410*4882a593Smuzhiyun
1411*4882a593Smuzhiyun if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) {
1412*4882a593Smuzhiyun vha->fcport_count++;
1413*4882a593Smuzhiyun ea->fcport->login_succ = 1;
1414*4882a593Smuzhiyun
1415*4882a593Smuzhiyun spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1416*4882a593Smuzhiyun qla24xx_sched_upd_fcport(ea->fcport);
1417*4882a593Smuzhiyun spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1418*4882a593Smuzhiyun } else if (ea->fcport->login_succ) {
1419*4882a593Smuzhiyun /*
1420*4882a593Smuzhiyun * We have an existing session. A late RSCN delivery
1421*4882a593Smuzhiyun * must have triggered the session to be re-validate.
1422*4882a593Smuzhiyun * Session is still valid.
1423*4882a593Smuzhiyun */
1424*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20d6,
1425*4882a593Smuzhiyun "%s %d %8phC session revalidate success\n",
1426*4882a593Smuzhiyun __func__, __LINE__, ea->fcport->port_name);
1427*4882a593Smuzhiyun qla2x00_set_fcport_disc_state(ea->fcport, DSC_LOGIN_COMPLETE);
1428*4882a593Smuzhiyun }
1429*4882a593Smuzhiyun spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1430*4882a593Smuzhiyun }
1431*4882a593Smuzhiyun
1432*4882a593Smuzhiyun static
qla24xx_handle_gpdb_event(scsi_qla_host_t * vha,struct event_arg * ea)1433*4882a593Smuzhiyun void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
1434*4882a593Smuzhiyun {
1435*4882a593Smuzhiyun fc_port_t *fcport = ea->fcport;
1436*4882a593Smuzhiyun struct port_database_24xx *pd;
1437*4882a593Smuzhiyun struct srb *sp = ea->sp;
1438*4882a593Smuzhiyun uint8_t ls;
1439*4882a593Smuzhiyun
1440*4882a593Smuzhiyun pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in;
1441*4882a593Smuzhiyun
1442*4882a593Smuzhiyun fcport->flags &= ~FCF_ASYNC_SENT;
1443*4882a593Smuzhiyun
1444*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20d2,
1445*4882a593Smuzhiyun "%s %8phC DS %d LS %d fc4_type %x rc %d\n", __func__,
1446*4882a593Smuzhiyun fcport->port_name, fcport->disc_state, pd->current_login_state,
1447*4882a593Smuzhiyun fcport->fc4_type, ea->rc);
1448*4882a593Smuzhiyun
1449*4882a593Smuzhiyun if (fcport->disc_state == DSC_DELETE_PEND)
1450*4882a593Smuzhiyun return;
1451*4882a593Smuzhiyun
1452*4882a593Smuzhiyun if (NVME_TARGET(vha->hw, fcport))
1453*4882a593Smuzhiyun ls = pd->current_login_state >> 4;
1454*4882a593Smuzhiyun else
1455*4882a593Smuzhiyun ls = pd->current_login_state & 0xf;
1456*4882a593Smuzhiyun
1457*4882a593Smuzhiyun if (ea->sp->gen2 != fcport->login_gen) {
1458*4882a593Smuzhiyun /* target side must have changed it. */
1459*4882a593Smuzhiyun
1460*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20d3,
1461*4882a593Smuzhiyun "%s %8phC generation changed\n",
1462*4882a593Smuzhiyun __func__, fcport->port_name);
1463*4882a593Smuzhiyun return;
1464*4882a593Smuzhiyun } else if (ea->sp->gen1 != fcport->rscn_gen) {
1465*4882a593Smuzhiyun qla_rscn_replay(fcport);
1466*4882a593Smuzhiyun qlt_schedule_sess_for_deletion(fcport);
1467*4882a593Smuzhiyun return;
1468*4882a593Smuzhiyun }
1469*4882a593Smuzhiyun
1470*4882a593Smuzhiyun switch (ls) {
1471*4882a593Smuzhiyun case PDS_PRLI_COMPLETE:
1472*4882a593Smuzhiyun __qla24xx_parse_gpdb(vha, fcport, pd);
1473*4882a593Smuzhiyun break;
1474*4882a593Smuzhiyun case PDS_PLOGI_PENDING:
1475*4882a593Smuzhiyun case PDS_PLOGI_COMPLETE:
1476*4882a593Smuzhiyun case PDS_PRLI_PENDING:
1477*4882a593Smuzhiyun case PDS_PRLI2_PENDING:
1478*4882a593Smuzhiyun /* Set discovery state back to GNL to Relogin attempt */
1479*4882a593Smuzhiyun if (qla_dual_mode_enabled(vha) ||
1480*4882a593Smuzhiyun qla_ini_mode_enabled(vha)) {
1481*4882a593Smuzhiyun qla2x00_set_fcport_disc_state(fcport, DSC_GNL);
1482*4882a593Smuzhiyun set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1483*4882a593Smuzhiyun }
1484*4882a593Smuzhiyun return;
1485*4882a593Smuzhiyun case PDS_LOGO_PENDING:
1486*4882a593Smuzhiyun case PDS_PORT_UNAVAILABLE:
1487*4882a593Smuzhiyun default:
1488*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC post del sess\n",
1489*4882a593Smuzhiyun __func__, __LINE__, fcport->port_name);
1490*4882a593Smuzhiyun qlt_schedule_sess_for_deletion(fcport);
1491*4882a593Smuzhiyun return;
1492*4882a593Smuzhiyun }
1493*4882a593Smuzhiyun __qla24xx_handle_gpdb_event(vha, ea);
1494*4882a593Smuzhiyun } /* gpdb event */
1495*4882a593Smuzhiyun
qla_chk_n2n_b4_login(struct scsi_qla_host * vha,fc_port_t * fcport)1496*4882a593Smuzhiyun static void qla_chk_n2n_b4_login(struct scsi_qla_host *vha, fc_port_t *fcport)
1497*4882a593Smuzhiyun {
1498*4882a593Smuzhiyun u8 login = 0;
1499*4882a593Smuzhiyun int rc;
1500*4882a593Smuzhiyun
1501*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x307b,
1502*4882a593Smuzhiyun "%s %8phC DS %d LS %d lid %d retries=%d\n",
1503*4882a593Smuzhiyun __func__, fcport->port_name, fcport->disc_state,
1504*4882a593Smuzhiyun fcport->fw_login_state, fcport->loop_id, fcport->login_retry);
1505*4882a593Smuzhiyun
1506*4882a593Smuzhiyun if (qla_tgt_mode_enabled(vha))
1507*4882a593Smuzhiyun return;
1508*4882a593Smuzhiyun
1509*4882a593Smuzhiyun if (qla_dual_mode_enabled(vha)) {
1510*4882a593Smuzhiyun if (N2N_TOPO(vha->hw)) {
1511*4882a593Smuzhiyun u64 mywwn, wwn;
1512*4882a593Smuzhiyun
1513*4882a593Smuzhiyun mywwn = wwn_to_u64(vha->port_name);
1514*4882a593Smuzhiyun wwn = wwn_to_u64(fcport->port_name);
1515*4882a593Smuzhiyun if (mywwn > wwn)
1516*4882a593Smuzhiyun login = 1;
1517*4882a593Smuzhiyun else if ((fcport->fw_login_state == DSC_LS_PLOGI_COMP)
1518*4882a593Smuzhiyun && time_after_eq(jiffies,
1519*4882a593Smuzhiyun fcport->plogi_nack_done_deadline))
1520*4882a593Smuzhiyun login = 1;
1521*4882a593Smuzhiyun } else {
1522*4882a593Smuzhiyun login = 1;
1523*4882a593Smuzhiyun }
1524*4882a593Smuzhiyun } else {
1525*4882a593Smuzhiyun /* initiator mode */
1526*4882a593Smuzhiyun login = 1;
1527*4882a593Smuzhiyun }
1528*4882a593Smuzhiyun
1529*4882a593Smuzhiyun if (login && fcport->login_retry) {
1530*4882a593Smuzhiyun fcport->login_retry--;
1531*4882a593Smuzhiyun if (fcport->loop_id == FC_NO_LOOP_ID) {
1532*4882a593Smuzhiyun fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
1533*4882a593Smuzhiyun rc = qla2x00_find_new_loop_id(vha, fcport);
1534*4882a593Smuzhiyun if (rc) {
1535*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20e6,
1536*4882a593Smuzhiyun "%s %d %8phC post del sess - out of loopid\n",
1537*4882a593Smuzhiyun __func__, __LINE__, fcport->port_name);
1538*4882a593Smuzhiyun fcport->scan_state = 0;
1539*4882a593Smuzhiyun qlt_schedule_sess_for_deletion(fcport);
1540*4882a593Smuzhiyun return;
1541*4882a593Smuzhiyun }
1542*4882a593Smuzhiyun }
1543*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20bf,
1544*4882a593Smuzhiyun "%s %d %8phC post login\n",
1545*4882a593Smuzhiyun __func__, __LINE__, fcport->port_name);
1546*4882a593Smuzhiyun qla2x00_post_async_login_work(vha, fcport, NULL);
1547*4882a593Smuzhiyun }
1548*4882a593Smuzhiyun }
1549*4882a593Smuzhiyun
qla24xx_fcport_handle_login(struct scsi_qla_host * vha,fc_port_t * fcport)1550*4882a593Smuzhiyun int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport)
1551*4882a593Smuzhiyun {
1552*4882a593Smuzhiyun u16 data[2];
1553*4882a593Smuzhiyun u64 wwn;
1554*4882a593Smuzhiyun u16 sec;
1555*4882a593Smuzhiyun
1556*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20d8,
1557*4882a593Smuzhiyun "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d lid %d scan %d\n",
1558*4882a593Smuzhiyun __func__, fcport->port_name, fcport->disc_state,
1559*4882a593Smuzhiyun fcport->fw_login_state, fcport->login_pause, fcport->flags,
1560*4882a593Smuzhiyun fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen,
1561*4882a593Smuzhiyun fcport->login_gen, fcport->loop_id, fcport->scan_state);
1562*4882a593Smuzhiyun
1563*4882a593Smuzhiyun if (fcport->scan_state != QLA_FCPORT_FOUND ||
1564*4882a593Smuzhiyun fcport->disc_state == DSC_DELETE_PEND)
1565*4882a593Smuzhiyun return 0;
1566*4882a593Smuzhiyun
1567*4882a593Smuzhiyun if ((fcport->loop_id != FC_NO_LOOP_ID) &&
1568*4882a593Smuzhiyun qla_dual_mode_enabled(vha) &&
1569*4882a593Smuzhiyun ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
1570*4882a593Smuzhiyun (fcport->fw_login_state == DSC_LS_PRLI_PEND)))
1571*4882a593Smuzhiyun return 0;
1572*4882a593Smuzhiyun
1573*4882a593Smuzhiyun if (fcport->fw_login_state == DSC_LS_PLOGI_COMP &&
1574*4882a593Smuzhiyun !N2N_TOPO(vha->hw)) {
1575*4882a593Smuzhiyun if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) {
1576*4882a593Smuzhiyun set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1577*4882a593Smuzhiyun return 0;
1578*4882a593Smuzhiyun }
1579*4882a593Smuzhiyun }
1580*4882a593Smuzhiyun
1581*4882a593Smuzhiyun /* Target won't initiate port login if fabric is present */
1582*4882a593Smuzhiyun if (vha->host->active_mode == MODE_TARGET && !N2N_TOPO(vha->hw))
1583*4882a593Smuzhiyun return 0;
1584*4882a593Smuzhiyun
1585*4882a593Smuzhiyun if (fcport->flags & (FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE)) {
1586*4882a593Smuzhiyun set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1587*4882a593Smuzhiyun return 0;
1588*4882a593Smuzhiyun }
1589*4882a593Smuzhiyun
1590*4882a593Smuzhiyun switch (fcport->disc_state) {
1591*4882a593Smuzhiyun case DSC_DELETED:
1592*4882a593Smuzhiyun wwn = wwn_to_u64(fcport->node_name);
1593*4882a593Smuzhiyun switch (vha->hw->current_topology) {
1594*4882a593Smuzhiyun case ISP_CFG_N:
1595*4882a593Smuzhiyun if (fcport_is_smaller(fcport)) {
1596*4882a593Smuzhiyun /* this adapter is bigger */
1597*4882a593Smuzhiyun if (fcport->login_retry) {
1598*4882a593Smuzhiyun if (fcport->loop_id == FC_NO_LOOP_ID) {
1599*4882a593Smuzhiyun qla2x00_find_new_loop_id(vha,
1600*4882a593Smuzhiyun fcport);
1601*4882a593Smuzhiyun fcport->fw_login_state =
1602*4882a593Smuzhiyun DSC_LS_PORT_UNAVAIL;
1603*4882a593Smuzhiyun }
1604*4882a593Smuzhiyun fcport->login_retry--;
1605*4882a593Smuzhiyun qla_post_els_plogi_work(vha, fcport);
1606*4882a593Smuzhiyun } else {
1607*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x705d,
1608*4882a593Smuzhiyun "Unable to reach remote port %8phC",
1609*4882a593Smuzhiyun fcport->port_name);
1610*4882a593Smuzhiyun }
1611*4882a593Smuzhiyun } else {
1612*4882a593Smuzhiyun qla24xx_post_gnl_work(vha, fcport);
1613*4882a593Smuzhiyun }
1614*4882a593Smuzhiyun break;
1615*4882a593Smuzhiyun default:
1616*4882a593Smuzhiyun if (wwn == 0) {
1617*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0xffff,
1618*4882a593Smuzhiyun "%s %d %8phC post GNNID\n",
1619*4882a593Smuzhiyun __func__, __LINE__, fcport->port_name);
1620*4882a593Smuzhiyun qla24xx_post_gnnid_work(vha, fcport);
1621*4882a593Smuzhiyun } else if (fcport->loop_id == FC_NO_LOOP_ID) {
1622*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20bd,
1623*4882a593Smuzhiyun "%s %d %8phC post gnl\n",
1624*4882a593Smuzhiyun __func__, __LINE__, fcport->port_name);
1625*4882a593Smuzhiyun qla24xx_post_gnl_work(vha, fcport);
1626*4882a593Smuzhiyun } else {
1627*4882a593Smuzhiyun qla_chk_n2n_b4_login(vha, fcport);
1628*4882a593Smuzhiyun }
1629*4882a593Smuzhiyun break;
1630*4882a593Smuzhiyun }
1631*4882a593Smuzhiyun break;
1632*4882a593Smuzhiyun
1633*4882a593Smuzhiyun case DSC_GNL:
1634*4882a593Smuzhiyun switch (vha->hw->current_topology) {
1635*4882a593Smuzhiyun case ISP_CFG_N:
1636*4882a593Smuzhiyun if ((fcport->current_login_state & 0xf) == 0x6) {
1637*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2118,
1638*4882a593Smuzhiyun "%s %d %8phC post GPDB work\n",
1639*4882a593Smuzhiyun __func__, __LINE__, fcport->port_name);
1640*4882a593Smuzhiyun fcport->chip_reset =
1641*4882a593Smuzhiyun vha->hw->base_qpair->chip_reset;
1642*4882a593Smuzhiyun qla24xx_post_gpdb_work(vha, fcport, 0);
1643*4882a593Smuzhiyun } else {
1644*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2118,
1645*4882a593Smuzhiyun "%s %d %8phC post %s PRLI\n",
1646*4882a593Smuzhiyun __func__, __LINE__, fcport->port_name,
1647*4882a593Smuzhiyun NVME_TARGET(vha->hw, fcport) ? "NVME" :
1648*4882a593Smuzhiyun "FC");
1649*4882a593Smuzhiyun qla24xx_post_prli_work(vha, fcport);
1650*4882a593Smuzhiyun }
1651*4882a593Smuzhiyun break;
1652*4882a593Smuzhiyun default:
1653*4882a593Smuzhiyun if (fcport->login_pause) {
1654*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20d8,
1655*4882a593Smuzhiyun "%s %d %8phC exit\n",
1656*4882a593Smuzhiyun __func__, __LINE__,
1657*4882a593Smuzhiyun fcport->port_name);
1658*4882a593Smuzhiyun fcport->last_rscn_gen = fcport->rscn_gen;
1659*4882a593Smuzhiyun fcport->last_login_gen = fcport->login_gen;
1660*4882a593Smuzhiyun set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1661*4882a593Smuzhiyun break;
1662*4882a593Smuzhiyun }
1663*4882a593Smuzhiyun qla_chk_n2n_b4_login(vha, fcport);
1664*4882a593Smuzhiyun break;
1665*4882a593Smuzhiyun }
1666*4882a593Smuzhiyun break;
1667*4882a593Smuzhiyun
1668*4882a593Smuzhiyun case DSC_LOGIN_FAILED:
1669*4882a593Smuzhiyun if (N2N_TOPO(vha->hw))
1670*4882a593Smuzhiyun qla_chk_n2n_b4_login(vha, fcport);
1671*4882a593Smuzhiyun else
1672*4882a593Smuzhiyun qlt_schedule_sess_for_deletion(fcport);
1673*4882a593Smuzhiyun break;
1674*4882a593Smuzhiyun
1675*4882a593Smuzhiyun case DSC_LOGIN_COMPLETE:
1676*4882a593Smuzhiyun /* recheck login state */
1677*4882a593Smuzhiyun data[0] = data[1] = 0;
1678*4882a593Smuzhiyun qla2x00_post_async_adisc_work(vha, fcport, data);
1679*4882a593Smuzhiyun break;
1680*4882a593Smuzhiyun
1681*4882a593Smuzhiyun case DSC_LOGIN_PEND:
1682*4882a593Smuzhiyun if (fcport->fw_login_state == DSC_LS_PLOGI_COMP)
1683*4882a593Smuzhiyun qla24xx_post_prli_work(vha, fcport);
1684*4882a593Smuzhiyun break;
1685*4882a593Smuzhiyun
1686*4882a593Smuzhiyun case DSC_UPD_FCPORT:
1687*4882a593Smuzhiyun sec = jiffies_to_msecs(jiffies -
1688*4882a593Smuzhiyun fcport->jiffies_at_registration)/1000;
1689*4882a593Smuzhiyun if (fcport->sec_since_registration < sec && sec &&
1690*4882a593Smuzhiyun !(sec % 60)) {
1691*4882a593Smuzhiyun fcport->sec_since_registration = sec;
1692*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
1693*4882a593Smuzhiyun "%s %8phC - Slow Rport registration(%d Sec)\n",
1694*4882a593Smuzhiyun __func__, fcport->port_name, sec);
1695*4882a593Smuzhiyun }
1696*4882a593Smuzhiyun
1697*4882a593Smuzhiyun if (fcport->next_disc_state != DSC_DELETE_PEND)
1698*4882a593Smuzhiyun fcport->next_disc_state = DSC_ADISC;
1699*4882a593Smuzhiyun set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1700*4882a593Smuzhiyun break;
1701*4882a593Smuzhiyun
1702*4882a593Smuzhiyun default:
1703*4882a593Smuzhiyun break;
1704*4882a593Smuzhiyun }
1705*4882a593Smuzhiyun
1706*4882a593Smuzhiyun return 0;
1707*4882a593Smuzhiyun }
1708*4882a593Smuzhiyun
qla24xx_post_newsess_work(struct scsi_qla_host * vha,port_id_t * id,u8 * port_name,u8 * node_name,void * pla,u8 fc4_type)1709*4882a593Smuzhiyun int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id,
1710*4882a593Smuzhiyun u8 *port_name, u8 *node_name, void *pla, u8 fc4_type)
1711*4882a593Smuzhiyun {
1712*4882a593Smuzhiyun struct qla_work_evt *e;
1713*4882a593Smuzhiyun
1714*4882a593Smuzhiyun e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS);
1715*4882a593Smuzhiyun if (!e)
1716*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
1717*4882a593Smuzhiyun
1718*4882a593Smuzhiyun e->u.new_sess.id = *id;
1719*4882a593Smuzhiyun e->u.new_sess.pla = pla;
1720*4882a593Smuzhiyun e->u.new_sess.fc4_type = fc4_type;
1721*4882a593Smuzhiyun memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE);
1722*4882a593Smuzhiyun if (node_name)
1723*4882a593Smuzhiyun memcpy(e->u.new_sess.node_name, node_name, WWN_SIZE);
1724*4882a593Smuzhiyun
1725*4882a593Smuzhiyun return qla2x00_post_work(vha, e);
1726*4882a593Smuzhiyun }
1727*4882a593Smuzhiyun
qla2x00_handle_rscn(scsi_qla_host_t * vha,struct event_arg * ea)1728*4882a593Smuzhiyun void qla2x00_handle_rscn(scsi_qla_host_t *vha, struct event_arg *ea)
1729*4882a593Smuzhiyun {
1730*4882a593Smuzhiyun fc_port_t *fcport;
1731*4882a593Smuzhiyun unsigned long flags;
1732*4882a593Smuzhiyun
1733*4882a593Smuzhiyun switch (ea->id.b.rsvd_1) {
1734*4882a593Smuzhiyun case RSCN_PORT_ADDR:
1735*4882a593Smuzhiyun fcport = qla2x00_find_fcport_by_nportid(vha, &ea->id, 1);
1736*4882a593Smuzhiyun if (fcport) {
1737*4882a593Smuzhiyun if (fcport->flags & FCF_FCP2_DEVICE &&
1738*4882a593Smuzhiyun atomic_read(&fcport->state) == FCS_ONLINE) {
1739*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2115,
1740*4882a593Smuzhiyun "Delaying session delete for FCP2 portid=%06x %8phC ",
1741*4882a593Smuzhiyun fcport->d_id.b24, fcport->port_name);
1742*4882a593Smuzhiyun return;
1743*4882a593Smuzhiyun }
1744*4882a593Smuzhiyun fcport->scan_needed = 1;
1745*4882a593Smuzhiyun fcport->rscn_gen++;
1746*4882a593Smuzhiyun }
1747*4882a593Smuzhiyun break;
1748*4882a593Smuzhiyun case RSCN_AREA_ADDR:
1749*4882a593Smuzhiyun list_for_each_entry(fcport, &vha->vp_fcports, list) {
1750*4882a593Smuzhiyun if (fcport->flags & FCF_FCP2_DEVICE &&
1751*4882a593Smuzhiyun atomic_read(&fcport->state) == FCS_ONLINE)
1752*4882a593Smuzhiyun continue;
1753*4882a593Smuzhiyun
1754*4882a593Smuzhiyun if ((ea->id.b24 & 0xffff00) == (fcport->d_id.b24 & 0xffff00)) {
1755*4882a593Smuzhiyun fcport->scan_needed = 1;
1756*4882a593Smuzhiyun fcport->rscn_gen++;
1757*4882a593Smuzhiyun }
1758*4882a593Smuzhiyun }
1759*4882a593Smuzhiyun break;
1760*4882a593Smuzhiyun case RSCN_DOM_ADDR:
1761*4882a593Smuzhiyun list_for_each_entry(fcport, &vha->vp_fcports, list) {
1762*4882a593Smuzhiyun if (fcport->flags & FCF_FCP2_DEVICE &&
1763*4882a593Smuzhiyun atomic_read(&fcport->state) == FCS_ONLINE)
1764*4882a593Smuzhiyun continue;
1765*4882a593Smuzhiyun
1766*4882a593Smuzhiyun if ((ea->id.b24 & 0xff0000) == (fcport->d_id.b24 & 0xff0000)) {
1767*4882a593Smuzhiyun fcport->scan_needed = 1;
1768*4882a593Smuzhiyun fcport->rscn_gen++;
1769*4882a593Smuzhiyun }
1770*4882a593Smuzhiyun }
1771*4882a593Smuzhiyun break;
1772*4882a593Smuzhiyun case RSCN_FAB_ADDR:
1773*4882a593Smuzhiyun default:
1774*4882a593Smuzhiyun list_for_each_entry(fcport, &vha->vp_fcports, list) {
1775*4882a593Smuzhiyun if (fcport->flags & FCF_FCP2_DEVICE &&
1776*4882a593Smuzhiyun atomic_read(&fcport->state) == FCS_ONLINE)
1777*4882a593Smuzhiyun continue;
1778*4882a593Smuzhiyun
1779*4882a593Smuzhiyun fcport->scan_needed = 1;
1780*4882a593Smuzhiyun fcport->rscn_gen++;
1781*4882a593Smuzhiyun }
1782*4882a593Smuzhiyun break;
1783*4882a593Smuzhiyun }
1784*4882a593Smuzhiyun
1785*4882a593Smuzhiyun spin_lock_irqsave(&vha->work_lock, flags);
1786*4882a593Smuzhiyun if (vha->scan.scan_flags == 0) {
1787*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0xffff, "%s: schedule\n", __func__);
1788*4882a593Smuzhiyun vha->scan.scan_flags |= SF_QUEUED;
1789*4882a593Smuzhiyun schedule_delayed_work(&vha->scan.scan_work, 5);
1790*4882a593Smuzhiyun }
1791*4882a593Smuzhiyun spin_unlock_irqrestore(&vha->work_lock, flags);
1792*4882a593Smuzhiyun }
1793*4882a593Smuzhiyun
qla24xx_handle_relogin_event(scsi_qla_host_t * vha,struct event_arg * ea)1794*4882a593Smuzhiyun void qla24xx_handle_relogin_event(scsi_qla_host_t *vha,
1795*4882a593Smuzhiyun struct event_arg *ea)
1796*4882a593Smuzhiyun {
1797*4882a593Smuzhiyun fc_port_t *fcport = ea->fcport;
1798*4882a593Smuzhiyun
1799*4882a593Smuzhiyun if (test_bit(UNLOADING, &vha->dpc_flags))
1800*4882a593Smuzhiyun return;
1801*4882a593Smuzhiyun
1802*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2102,
1803*4882a593Smuzhiyun "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n",
1804*4882a593Smuzhiyun __func__, fcport->port_name, fcport->disc_state,
1805*4882a593Smuzhiyun fcport->fw_login_state, fcport->login_pause,
1806*4882a593Smuzhiyun fcport->deleted, fcport->conflict,
1807*4882a593Smuzhiyun fcport->last_rscn_gen, fcport->rscn_gen,
1808*4882a593Smuzhiyun fcport->last_login_gen, fcport->login_gen,
1809*4882a593Smuzhiyun fcport->flags);
1810*4882a593Smuzhiyun
1811*4882a593Smuzhiyun if (fcport->last_rscn_gen != fcport->rscn_gen) {
1812*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20e9, "%s %d %8phC post gnl\n",
1813*4882a593Smuzhiyun __func__, __LINE__, fcport->port_name);
1814*4882a593Smuzhiyun qla24xx_post_gnl_work(vha, fcport);
1815*4882a593Smuzhiyun return;
1816*4882a593Smuzhiyun }
1817*4882a593Smuzhiyun
1818*4882a593Smuzhiyun qla24xx_fcport_handle_login(vha, fcport);
1819*4882a593Smuzhiyun }
1820*4882a593Smuzhiyun
qla_handle_els_plogi_done(scsi_qla_host_t * vha,struct event_arg * ea)1821*4882a593Smuzhiyun void qla_handle_els_plogi_done(scsi_qla_host_t *vha,
1822*4882a593Smuzhiyun struct event_arg *ea)
1823*4882a593Smuzhiyun {
1824*4882a593Smuzhiyun /* for pure Target Mode, PRLI will not be initiated */
1825*4882a593Smuzhiyun if (vha->host->active_mode == MODE_TARGET)
1826*4882a593Smuzhiyun return;
1827*4882a593Smuzhiyun
1828*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2118,
1829*4882a593Smuzhiyun "%s %d %8phC post PRLI\n",
1830*4882a593Smuzhiyun __func__, __LINE__, ea->fcport->port_name);
1831*4882a593Smuzhiyun qla24xx_post_prli_work(vha, ea->fcport);
1832*4882a593Smuzhiyun }
1833*4882a593Smuzhiyun
1834*4882a593Smuzhiyun /*
1835*4882a593Smuzhiyun * RSCN(s) came in for this fcport, but the RSCN(s) was not able
1836*4882a593Smuzhiyun * to be consumed by the fcport
1837*4882a593Smuzhiyun */
qla_rscn_replay(fc_port_t * fcport)1838*4882a593Smuzhiyun void qla_rscn_replay(fc_port_t *fcport)
1839*4882a593Smuzhiyun {
1840*4882a593Smuzhiyun struct event_arg ea;
1841*4882a593Smuzhiyun
1842*4882a593Smuzhiyun switch (fcport->disc_state) {
1843*4882a593Smuzhiyun case DSC_DELETE_PEND:
1844*4882a593Smuzhiyun return;
1845*4882a593Smuzhiyun default:
1846*4882a593Smuzhiyun break;
1847*4882a593Smuzhiyun }
1848*4882a593Smuzhiyun
1849*4882a593Smuzhiyun if (fcport->scan_needed) {
1850*4882a593Smuzhiyun memset(&ea, 0, sizeof(ea));
1851*4882a593Smuzhiyun ea.id = fcport->d_id;
1852*4882a593Smuzhiyun ea.id.b.rsvd_1 = RSCN_PORT_ADDR;
1853*4882a593Smuzhiyun qla2x00_handle_rscn(fcport->vha, &ea);
1854*4882a593Smuzhiyun }
1855*4882a593Smuzhiyun }
1856*4882a593Smuzhiyun
1857*4882a593Smuzhiyun static void
qla2x00_tmf_iocb_timeout(void * data)1858*4882a593Smuzhiyun qla2x00_tmf_iocb_timeout(void *data)
1859*4882a593Smuzhiyun {
1860*4882a593Smuzhiyun srb_t *sp = data;
1861*4882a593Smuzhiyun struct srb_iocb *tmf = &sp->u.iocb_cmd;
1862*4882a593Smuzhiyun int rc, h;
1863*4882a593Smuzhiyun unsigned long flags;
1864*4882a593Smuzhiyun
1865*4882a593Smuzhiyun rc = qla24xx_async_abort_cmd(sp, false);
1866*4882a593Smuzhiyun if (rc) {
1867*4882a593Smuzhiyun spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags);
1868*4882a593Smuzhiyun for (h = 1; h < sp->qpair->req->num_outstanding_cmds; h++) {
1869*4882a593Smuzhiyun if (sp->qpair->req->outstanding_cmds[h] == sp) {
1870*4882a593Smuzhiyun sp->qpair->req->outstanding_cmds[h] = NULL;
1871*4882a593Smuzhiyun break;
1872*4882a593Smuzhiyun }
1873*4882a593Smuzhiyun }
1874*4882a593Smuzhiyun spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags);
1875*4882a593Smuzhiyun tmf->u.tmf.comp_status = cpu_to_le16(CS_TIMEOUT);
1876*4882a593Smuzhiyun tmf->u.tmf.data = QLA_FUNCTION_FAILED;
1877*4882a593Smuzhiyun complete(&tmf->u.tmf.comp);
1878*4882a593Smuzhiyun }
1879*4882a593Smuzhiyun }
1880*4882a593Smuzhiyun
qla2x00_tmf_sp_done(srb_t * sp,int res)1881*4882a593Smuzhiyun static void qla2x00_tmf_sp_done(srb_t *sp, int res)
1882*4882a593Smuzhiyun {
1883*4882a593Smuzhiyun struct srb_iocb *tmf = &sp->u.iocb_cmd;
1884*4882a593Smuzhiyun
1885*4882a593Smuzhiyun complete(&tmf->u.tmf.comp);
1886*4882a593Smuzhiyun }
1887*4882a593Smuzhiyun
1888*4882a593Smuzhiyun int
qla2x00_async_tm_cmd(fc_port_t * fcport,uint32_t flags,uint32_t lun,uint32_t tag)1889*4882a593Smuzhiyun qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
1890*4882a593Smuzhiyun uint32_t tag)
1891*4882a593Smuzhiyun {
1892*4882a593Smuzhiyun struct scsi_qla_host *vha = fcport->vha;
1893*4882a593Smuzhiyun struct srb_iocb *tm_iocb;
1894*4882a593Smuzhiyun srb_t *sp;
1895*4882a593Smuzhiyun int rval = QLA_FUNCTION_FAILED;
1896*4882a593Smuzhiyun
1897*4882a593Smuzhiyun sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1898*4882a593Smuzhiyun if (!sp)
1899*4882a593Smuzhiyun goto done;
1900*4882a593Smuzhiyun
1901*4882a593Smuzhiyun tm_iocb = &sp->u.iocb_cmd;
1902*4882a593Smuzhiyun sp->type = SRB_TM_CMD;
1903*4882a593Smuzhiyun sp->name = "tmf";
1904*4882a593Smuzhiyun
1905*4882a593Smuzhiyun tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
1906*4882a593Smuzhiyun init_completion(&tm_iocb->u.tmf.comp);
1907*4882a593Smuzhiyun qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
1908*4882a593Smuzhiyun
1909*4882a593Smuzhiyun tm_iocb->u.tmf.flags = flags;
1910*4882a593Smuzhiyun tm_iocb->u.tmf.lun = lun;
1911*4882a593Smuzhiyun tm_iocb->u.tmf.data = tag;
1912*4882a593Smuzhiyun sp->done = qla2x00_tmf_sp_done;
1913*4882a593Smuzhiyun
1914*4882a593Smuzhiyun ql_dbg(ql_dbg_taskm, vha, 0x802f,
1915*4882a593Smuzhiyun "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
1916*4882a593Smuzhiyun sp->handle, fcport->loop_id, fcport->d_id.b.domain,
1917*4882a593Smuzhiyun fcport->d_id.b.area, fcport->d_id.b.al_pa);
1918*4882a593Smuzhiyun
1919*4882a593Smuzhiyun rval = qla2x00_start_sp(sp);
1920*4882a593Smuzhiyun if (rval != QLA_SUCCESS)
1921*4882a593Smuzhiyun goto done_free_sp;
1922*4882a593Smuzhiyun wait_for_completion(&tm_iocb->u.tmf.comp);
1923*4882a593Smuzhiyun
1924*4882a593Smuzhiyun rval = tm_iocb->u.tmf.data;
1925*4882a593Smuzhiyun
1926*4882a593Smuzhiyun if (rval != QLA_SUCCESS) {
1927*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x8030,
1928*4882a593Smuzhiyun "TM IOCB failed (%x).\n", rval);
1929*4882a593Smuzhiyun }
1930*4882a593Smuzhiyun
1931*4882a593Smuzhiyun if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
1932*4882a593Smuzhiyun flags = tm_iocb->u.tmf.flags;
1933*4882a593Smuzhiyun lun = (uint16_t)tm_iocb->u.tmf.lun;
1934*4882a593Smuzhiyun
1935*4882a593Smuzhiyun /* Issue Marker IOCB */
1936*4882a593Smuzhiyun qla2x00_marker(vha, vha->hw->base_qpair,
1937*4882a593Smuzhiyun fcport->loop_id, lun,
1938*4882a593Smuzhiyun flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
1939*4882a593Smuzhiyun }
1940*4882a593Smuzhiyun
1941*4882a593Smuzhiyun done_free_sp:
1942*4882a593Smuzhiyun sp->free(sp);
1943*4882a593Smuzhiyun fcport->flags &= ~FCF_ASYNC_SENT;
1944*4882a593Smuzhiyun done:
1945*4882a593Smuzhiyun return rval;
1946*4882a593Smuzhiyun }
1947*4882a593Smuzhiyun
1948*4882a593Smuzhiyun int
qla24xx_async_abort_command(srb_t * sp)1949*4882a593Smuzhiyun qla24xx_async_abort_command(srb_t *sp)
1950*4882a593Smuzhiyun {
1951*4882a593Smuzhiyun unsigned long flags = 0;
1952*4882a593Smuzhiyun
1953*4882a593Smuzhiyun uint32_t handle;
1954*4882a593Smuzhiyun fc_port_t *fcport = sp->fcport;
1955*4882a593Smuzhiyun struct qla_qpair *qpair = sp->qpair;
1956*4882a593Smuzhiyun struct scsi_qla_host *vha = fcport->vha;
1957*4882a593Smuzhiyun struct req_que *req = qpair->req;
1958*4882a593Smuzhiyun
1959*4882a593Smuzhiyun spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1960*4882a593Smuzhiyun for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
1961*4882a593Smuzhiyun if (req->outstanding_cmds[handle] == sp)
1962*4882a593Smuzhiyun break;
1963*4882a593Smuzhiyun }
1964*4882a593Smuzhiyun spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1965*4882a593Smuzhiyun
1966*4882a593Smuzhiyun if (handle == req->num_outstanding_cmds) {
1967*4882a593Smuzhiyun /* Command not found. */
1968*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
1969*4882a593Smuzhiyun }
1970*4882a593Smuzhiyun if (sp->type == SRB_FXIOCB_DCMD)
1971*4882a593Smuzhiyun return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1972*4882a593Smuzhiyun FXDISC_ABORT_IOCTL);
1973*4882a593Smuzhiyun
1974*4882a593Smuzhiyun return qla24xx_async_abort_cmd(sp, true);
1975*4882a593Smuzhiyun }
1976*4882a593Smuzhiyun
1977*4882a593Smuzhiyun static void
qla24xx_handle_prli_done_event(struct scsi_qla_host * vha,struct event_arg * ea)1978*4882a593Smuzhiyun qla24xx_handle_prli_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
1979*4882a593Smuzhiyun {
1980*4882a593Smuzhiyun WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n",
1981*4882a593Smuzhiyun ea->data[0]);
1982*4882a593Smuzhiyun
1983*4882a593Smuzhiyun switch (ea->data[0]) {
1984*4882a593Smuzhiyun case MBS_COMMAND_COMPLETE:
1985*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2118,
1986*4882a593Smuzhiyun "%s %d %8phC post gpdb\n",
1987*4882a593Smuzhiyun __func__, __LINE__, ea->fcport->port_name);
1988*4882a593Smuzhiyun
1989*4882a593Smuzhiyun ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
1990*4882a593Smuzhiyun ea->fcport->logout_on_delete = 1;
1991*4882a593Smuzhiyun ea->fcport->nvme_prli_service_param = ea->iop[0];
1992*4882a593Smuzhiyun if (ea->iop[0] & NVME_PRLI_SP_FIRST_BURST)
1993*4882a593Smuzhiyun ea->fcport->nvme_first_burst_size =
1994*4882a593Smuzhiyun (ea->iop[1] & 0xffff) * 512;
1995*4882a593Smuzhiyun else
1996*4882a593Smuzhiyun ea->fcport->nvme_first_burst_size = 0;
1997*4882a593Smuzhiyun qla24xx_post_gpdb_work(vha, ea->fcport, 0);
1998*4882a593Smuzhiyun break;
1999*4882a593Smuzhiyun default:
2000*4882a593Smuzhiyun if ((ea->iop[0] == LSC_SCODE_ELS_REJECT) &&
2001*4882a593Smuzhiyun (ea->iop[1] == 0x50000)) { /* reson 5=busy expl:0x0 */
2002*4882a593Smuzhiyun set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
2003*4882a593Smuzhiyun ea->fcport->fw_login_state = DSC_LS_PLOGI_COMP;
2004*4882a593Smuzhiyun break;
2005*4882a593Smuzhiyun }
2006*4882a593Smuzhiyun
2007*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2118,
2008*4882a593Smuzhiyun "%s %d %8phC priority %s, fc4type %x\n",
2009*4882a593Smuzhiyun __func__, __LINE__, ea->fcport->port_name,
2010*4882a593Smuzhiyun vha->hw->fc4_type_priority == FC4_PRIORITY_FCP ?
2011*4882a593Smuzhiyun "FCP" : "NVMe", ea->fcport->fc4_type);
2012*4882a593Smuzhiyun
2013*4882a593Smuzhiyun if (N2N_TOPO(vha->hw)) {
2014*4882a593Smuzhiyun if (vha->hw->fc4_type_priority == FC4_PRIORITY_NVME) {
2015*4882a593Smuzhiyun ea->fcport->fc4_type &= ~FS_FC4TYPE_NVME;
2016*4882a593Smuzhiyun ea->fcport->fc4_type |= FS_FC4TYPE_FCP;
2017*4882a593Smuzhiyun } else {
2018*4882a593Smuzhiyun ea->fcport->fc4_type &= ~FS_FC4TYPE_FCP;
2019*4882a593Smuzhiyun ea->fcport->fc4_type |= FS_FC4TYPE_NVME;
2020*4882a593Smuzhiyun }
2021*4882a593Smuzhiyun
2022*4882a593Smuzhiyun if (ea->fcport->n2n_link_reset_cnt < 3) {
2023*4882a593Smuzhiyun ea->fcport->n2n_link_reset_cnt++;
2024*4882a593Smuzhiyun vha->relogin_jif = jiffies + 2 * HZ;
2025*4882a593Smuzhiyun /*
2026*4882a593Smuzhiyun * PRLI failed. Reset link to kick start
2027*4882a593Smuzhiyun * state machine
2028*4882a593Smuzhiyun */
2029*4882a593Smuzhiyun set_bit(N2N_LINK_RESET, &vha->dpc_flags);
2030*4882a593Smuzhiyun } else {
2031*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x2119,
2032*4882a593Smuzhiyun "%s %d %8phC Unable to reconnect\n",
2033*4882a593Smuzhiyun __func__, __LINE__,
2034*4882a593Smuzhiyun ea->fcport->port_name);
2035*4882a593Smuzhiyun }
2036*4882a593Smuzhiyun } else {
2037*4882a593Smuzhiyun /*
2038*4882a593Smuzhiyun * switch connect. login failed. Take connection down
2039*4882a593Smuzhiyun * and allow relogin to retrigger
2040*4882a593Smuzhiyun */
2041*4882a593Smuzhiyun if (NVME_FCP_TARGET(ea->fcport)) {
2042*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2118,
2043*4882a593Smuzhiyun "%s %d %8phC post %s prli\n",
2044*4882a593Smuzhiyun __func__, __LINE__,
2045*4882a593Smuzhiyun ea->fcport->port_name,
2046*4882a593Smuzhiyun (ea->fcport->fc4_type & FS_FC4TYPE_NVME)
2047*4882a593Smuzhiyun ? "NVMe" : "FCP");
2048*4882a593Smuzhiyun if (vha->hw->fc4_type_priority == FC4_PRIORITY_NVME)
2049*4882a593Smuzhiyun ea->fcport->fc4_type &= ~FS_FC4TYPE_NVME;
2050*4882a593Smuzhiyun else
2051*4882a593Smuzhiyun ea->fcport->fc4_type &= ~FS_FC4TYPE_FCP;
2052*4882a593Smuzhiyun }
2053*4882a593Smuzhiyun
2054*4882a593Smuzhiyun ea->fcport->flags &= ~FCF_ASYNC_SENT;
2055*4882a593Smuzhiyun ea->fcport->keep_nport_handle = 0;
2056*4882a593Smuzhiyun ea->fcport->logout_on_delete = 1;
2057*4882a593Smuzhiyun qlt_schedule_sess_for_deletion(ea->fcport);
2058*4882a593Smuzhiyun }
2059*4882a593Smuzhiyun break;
2060*4882a593Smuzhiyun }
2061*4882a593Smuzhiyun }
2062*4882a593Smuzhiyun
2063*4882a593Smuzhiyun void
qla24xx_handle_plogi_done_event(struct scsi_qla_host * vha,struct event_arg * ea)2064*4882a593Smuzhiyun qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
2065*4882a593Smuzhiyun {
2066*4882a593Smuzhiyun port_id_t cid; /* conflict Nport id */
2067*4882a593Smuzhiyun u16 lid;
2068*4882a593Smuzhiyun struct fc_port *conflict_fcport;
2069*4882a593Smuzhiyun unsigned long flags;
2070*4882a593Smuzhiyun struct fc_port *fcport = ea->fcport;
2071*4882a593Smuzhiyun
2072*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0xffff,
2073*4882a593Smuzhiyun "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d data %x|%x iop %x|%x\n",
2074*4882a593Smuzhiyun __func__, fcport->port_name, fcport->disc_state,
2075*4882a593Smuzhiyun fcport->fw_login_state, ea->rc, ea->sp->gen2, fcport->login_gen,
2076*4882a593Smuzhiyun ea->sp->gen1, fcport->rscn_gen,
2077*4882a593Smuzhiyun ea->data[0], ea->data[1], ea->iop[0], ea->iop[1]);
2078*4882a593Smuzhiyun
2079*4882a593Smuzhiyun if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
2080*4882a593Smuzhiyun (fcport->fw_login_state == DSC_LS_PRLI_PEND)) {
2081*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20ea,
2082*4882a593Smuzhiyun "%s %d %8phC Remote is trying to login\n",
2083*4882a593Smuzhiyun __func__, __LINE__, fcport->port_name);
2084*4882a593Smuzhiyun return;
2085*4882a593Smuzhiyun }
2086*4882a593Smuzhiyun
2087*4882a593Smuzhiyun if ((fcport->disc_state == DSC_DELETE_PEND) ||
2088*4882a593Smuzhiyun (fcport->disc_state == DSC_DELETED)) {
2089*4882a593Smuzhiyun set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
2090*4882a593Smuzhiyun return;
2091*4882a593Smuzhiyun }
2092*4882a593Smuzhiyun
2093*4882a593Smuzhiyun if (ea->sp->gen2 != fcport->login_gen) {
2094*4882a593Smuzhiyun /* target side must have changed it. */
2095*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20d3,
2096*4882a593Smuzhiyun "%s %8phC generation changed\n",
2097*4882a593Smuzhiyun __func__, fcport->port_name);
2098*4882a593Smuzhiyun set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
2099*4882a593Smuzhiyun return;
2100*4882a593Smuzhiyun } else if (ea->sp->gen1 != fcport->rscn_gen) {
2101*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20d3,
2102*4882a593Smuzhiyun "%s %8phC RSCN generation changed\n",
2103*4882a593Smuzhiyun __func__, fcport->port_name);
2104*4882a593Smuzhiyun qla_rscn_replay(fcport);
2105*4882a593Smuzhiyun qlt_schedule_sess_for_deletion(fcport);
2106*4882a593Smuzhiyun return;
2107*4882a593Smuzhiyun }
2108*4882a593Smuzhiyun
2109*4882a593Smuzhiyun WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n",
2110*4882a593Smuzhiyun ea->data[0]);
2111*4882a593Smuzhiyun
2112*4882a593Smuzhiyun switch (ea->data[0]) {
2113*4882a593Smuzhiyun case MBS_COMMAND_COMPLETE:
2114*4882a593Smuzhiyun /*
2115*4882a593Smuzhiyun * Driver must validate login state - If PRLI not complete,
2116*4882a593Smuzhiyun * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
2117*4882a593Smuzhiyun * requests.
2118*4882a593Smuzhiyun */
2119*4882a593Smuzhiyun if (NVME_TARGET(vha->hw, ea->fcport)) {
2120*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2117,
2121*4882a593Smuzhiyun "%s %d %8phC post prli\n",
2122*4882a593Smuzhiyun __func__, __LINE__, ea->fcport->port_name);
2123*4882a593Smuzhiyun qla24xx_post_prli_work(vha, ea->fcport);
2124*4882a593Smuzhiyun } else {
2125*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20ea,
2126*4882a593Smuzhiyun "%s %d %8phC LoopID 0x%x in use with %06x. post gpdb\n",
2127*4882a593Smuzhiyun __func__, __LINE__, ea->fcport->port_name,
2128*4882a593Smuzhiyun ea->fcport->loop_id, ea->fcport->d_id.b24);
2129*4882a593Smuzhiyun
2130*4882a593Smuzhiyun set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
2131*4882a593Smuzhiyun spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
2132*4882a593Smuzhiyun ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
2133*4882a593Smuzhiyun ea->fcport->logout_on_delete = 1;
2134*4882a593Smuzhiyun ea->fcport->send_els_logo = 0;
2135*4882a593Smuzhiyun ea->fcport->fw_login_state = DSC_LS_PRLI_COMP;
2136*4882a593Smuzhiyun spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
2137*4882a593Smuzhiyun
2138*4882a593Smuzhiyun qla24xx_post_gpdb_work(vha, ea->fcport, 0);
2139*4882a593Smuzhiyun }
2140*4882a593Smuzhiyun break;
2141*4882a593Smuzhiyun case MBS_COMMAND_ERROR:
2142*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20eb, "%s %d %8phC cmd error %x\n",
2143*4882a593Smuzhiyun __func__, __LINE__, ea->fcport->port_name, ea->data[1]);
2144*4882a593Smuzhiyun
2145*4882a593Smuzhiyun qlt_schedule_sess_for_deletion(ea->fcport);
2146*4882a593Smuzhiyun break;
2147*4882a593Smuzhiyun case MBS_LOOP_ID_USED:
2148*4882a593Smuzhiyun /* data[1] = IO PARAM 1 = nport ID */
2149*4882a593Smuzhiyun cid.b.domain = (ea->iop[1] >> 16) & 0xff;
2150*4882a593Smuzhiyun cid.b.area = (ea->iop[1] >> 8) & 0xff;
2151*4882a593Smuzhiyun cid.b.al_pa = ea->iop[1] & 0xff;
2152*4882a593Smuzhiyun cid.b.rsvd_1 = 0;
2153*4882a593Smuzhiyun
2154*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20ec,
2155*4882a593Smuzhiyun "%s %d %8phC lid %#x in use with pid %06x post gnl\n",
2156*4882a593Smuzhiyun __func__, __LINE__, ea->fcport->port_name,
2157*4882a593Smuzhiyun ea->fcport->loop_id, cid.b24);
2158*4882a593Smuzhiyun
2159*4882a593Smuzhiyun set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
2160*4882a593Smuzhiyun ea->fcport->loop_id = FC_NO_LOOP_ID;
2161*4882a593Smuzhiyun qla24xx_post_gnl_work(vha, ea->fcport);
2162*4882a593Smuzhiyun break;
2163*4882a593Smuzhiyun case MBS_PORT_ID_USED:
2164*4882a593Smuzhiyun lid = ea->iop[1] & 0xffff;
2165*4882a593Smuzhiyun qlt_find_sess_invalidate_other(vha,
2166*4882a593Smuzhiyun wwn_to_u64(ea->fcport->port_name),
2167*4882a593Smuzhiyun ea->fcport->d_id, lid, &conflict_fcport);
2168*4882a593Smuzhiyun
2169*4882a593Smuzhiyun if (conflict_fcport) {
2170*4882a593Smuzhiyun /*
2171*4882a593Smuzhiyun * Another fcport share the same loop_id/nport id.
2172*4882a593Smuzhiyun * Conflict fcport needs to finish cleanup before this
2173*4882a593Smuzhiyun * fcport can proceed to login.
2174*4882a593Smuzhiyun */
2175*4882a593Smuzhiyun conflict_fcport->conflict = ea->fcport;
2176*4882a593Smuzhiyun ea->fcport->login_pause = 1;
2177*4882a593Smuzhiyun
2178*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20ed,
2179*4882a593Smuzhiyun "%s %d %8phC NPortId %06x inuse with loopid 0x%x. post gidpn\n",
2180*4882a593Smuzhiyun __func__, __LINE__, ea->fcport->port_name,
2181*4882a593Smuzhiyun ea->fcport->d_id.b24, lid);
2182*4882a593Smuzhiyun } else {
2183*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20ed,
2184*4882a593Smuzhiyun "%s %d %8phC NPortId %06x inuse with loopid 0x%x. sched delete\n",
2185*4882a593Smuzhiyun __func__, __LINE__, ea->fcport->port_name,
2186*4882a593Smuzhiyun ea->fcport->d_id.b24, lid);
2187*4882a593Smuzhiyun
2188*4882a593Smuzhiyun qla2x00_clear_loop_id(ea->fcport);
2189*4882a593Smuzhiyun set_bit(lid, vha->hw->loop_id_map);
2190*4882a593Smuzhiyun ea->fcport->loop_id = lid;
2191*4882a593Smuzhiyun ea->fcport->keep_nport_handle = 0;
2192*4882a593Smuzhiyun ea->fcport->logout_on_delete = 1;
2193*4882a593Smuzhiyun qlt_schedule_sess_for_deletion(ea->fcport);
2194*4882a593Smuzhiyun }
2195*4882a593Smuzhiyun break;
2196*4882a593Smuzhiyun }
2197*4882a593Smuzhiyun return;
2198*4882a593Smuzhiyun }
2199*4882a593Smuzhiyun
2200*4882a593Smuzhiyun /****************************************************************************/
2201*4882a593Smuzhiyun /* QLogic ISP2x00 Hardware Support Functions. */
2202*4882a593Smuzhiyun /****************************************************************************/
2203*4882a593Smuzhiyun
2204*4882a593Smuzhiyun static int
qla83xx_nic_core_fw_load(scsi_qla_host_t * vha)2205*4882a593Smuzhiyun qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
2206*4882a593Smuzhiyun {
2207*4882a593Smuzhiyun int rval = QLA_SUCCESS;
2208*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
2209*4882a593Smuzhiyun uint32_t idc_major_ver, idc_minor_ver;
2210*4882a593Smuzhiyun uint16_t config[4];
2211*4882a593Smuzhiyun
2212*4882a593Smuzhiyun qla83xx_idc_lock(vha, 0);
2213*4882a593Smuzhiyun
2214*4882a593Smuzhiyun /* SV: TODO: Assign initialization timeout from
2215*4882a593Smuzhiyun * flash-info / other param
2216*4882a593Smuzhiyun */
2217*4882a593Smuzhiyun ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
2218*4882a593Smuzhiyun ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
2219*4882a593Smuzhiyun
2220*4882a593Smuzhiyun /* Set our fcoe function presence */
2221*4882a593Smuzhiyun if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
2222*4882a593Smuzhiyun ql_dbg(ql_dbg_p3p, vha, 0xb077,
2223*4882a593Smuzhiyun "Error while setting DRV-Presence.\n");
2224*4882a593Smuzhiyun rval = QLA_FUNCTION_FAILED;
2225*4882a593Smuzhiyun goto exit;
2226*4882a593Smuzhiyun }
2227*4882a593Smuzhiyun
2228*4882a593Smuzhiyun /* Decide the reset ownership */
2229*4882a593Smuzhiyun qla83xx_reset_ownership(vha);
2230*4882a593Smuzhiyun
2231*4882a593Smuzhiyun /*
2232*4882a593Smuzhiyun * On first protocol driver load:
2233*4882a593Smuzhiyun * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
2234*4882a593Smuzhiyun * register.
2235*4882a593Smuzhiyun * Others: Check compatibility with current IDC Major version.
2236*4882a593Smuzhiyun */
2237*4882a593Smuzhiyun qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
2238*4882a593Smuzhiyun if (ha->flags.nic_core_reset_owner) {
2239*4882a593Smuzhiyun /* Set IDC Major version */
2240*4882a593Smuzhiyun idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
2241*4882a593Smuzhiyun qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
2242*4882a593Smuzhiyun
2243*4882a593Smuzhiyun /* Clearing IDC-Lock-Recovery register */
2244*4882a593Smuzhiyun qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
2245*4882a593Smuzhiyun } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
2246*4882a593Smuzhiyun /*
2247*4882a593Smuzhiyun * Clear further IDC participation if we are not compatible with
2248*4882a593Smuzhiyun * the current IDC Major Version.
2249*4882a593Smuzhiyun */
2250*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0xb07d,
2251*4882a593Smuzhiyun "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
2252*4882a593Smuzhiyun idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
2253*4882a593Smuzhiyun __qla83xx_clear_drv_presence(vha);
2254*4882a593Smuzhiyun rval = QLA_FUNCTION_FAILED;
2255*4882a593Smuzhiyun goto exit;
2256*4882a593Smuzhiyun }
2257*4882a593Smuzhiyun /* Each function sets its supported Minor version. */
2258*4882a593Smuzhiyun qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
2259*4882a593Smuzhiyun idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
2260*4882a593Smuzhiyun qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
2261*4882a593Smuzhiyun
2262*4882a593Smuzhiyun if (ha->flags.nic_core_reset_owner) {
2263*4882a593Smuzhiyun memset(config, 0, sizeof(config));
2264*4882a593Smuzhiyun if (!qla81xx_get_port_config(vha, config))
2265*4882a593Smuzhiyun qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
2266*4882a593Smuzhiyun QLA8XXX_DEV_READY);
2267*4882a593Smuzhiyun }
2268*4882a593Smuzhiyun
2269*4882a593Smuzhiyun rval = qla83xx_idc_state_handler(vha);
2270*4882a593Smuzhiyun
2271*4882a593Smuzhiyun exit:
2272*4882a593Smuzhiyun qla83xx_idc_unlock(vha, 0);
2273*4882a593Smuzhiyun
2274*4882a593Smuzhiyun return rval;
2275*4882a593Smuzhiyun }
2276*4882a593Smuzhiyun
2277*4882a593Smuzhiyun /*
2278*4882a593Smuzhiyun * qla2x00_initialize_adapter
2279*4882a593Smuzhiyun * Initialize board.
2280*4882a593Smuzhiyun *
2281*4882a593Smuzhiyun * Input:
2282*4882a593Smuzhiyun * ha = adapter block pointer.
2283*4882a593Smuzhiyun *
2284*4882a593Smuzhiyun * Returns:
2285*4882a593Smuzhiyun * 0 = success
2286*4882a593Smuzhiyun */
2287*4882a593Smuzhiyun int
qla2x00_initialize_adapter(scsi_qla_host_t * vha)2288*4882a593Smuzhiyun qla2x00_initialize_adapter(scsi_qla_host_t *vha)
2289*4882a593Smuzhiyun {
2290*4882a593Smuzhiyun int rval;
2291*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
2292*4882a593Smuzhiyun struct req_que *req = ha->req_q_map[0];
2293*4882a593Smuzhiyun struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2294*4882a593Smuzhiyun
2295*4882a593Smuzhiyun memset(&vha->qla_stats, 0, sizeof(vha->qla_stats));
2296*4882a593Smuzhiyun memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat));
2297*4882a593Smuzhiyun
2298*4882a593Smuzhiyun /* Clear adapter flags. */
2299*4882a593Smuzhiyun vha->flags.online = 0;
2300*4882a593Smuzhiyun ha->flags.chip_reset_done = 0;
2301*4882a593Smuzhiyun vha->flags.reset_active = 0;
2302*4882a593Smuzhiyun ha->flags.pci_channel_io_perm_failure = 0;
2303*4882a593Smuzhiyun ha->flags.eeh_busy = 0;
2304*4882a593Smuzhiyun vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
2305*4882a593Smuzhiyun atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
2306*4882a593Smuzhiyun atomic_set(&vha->loop_state, LOOP_DOWN);
2307*4882a593Smuzhiyun vha->device_flags = DFLG_NO_CABLE;
2308*4882a593Smuzhiyun vha->dpc_flags = 0;
2309*4882a593Smuzhiyun vha->flags.management_server_logged_in = 0;
2310*4882a593Smuzhiyun vha->marker_needed = 0;
2311*4882a593Smuzhiyun ha->isp_abort_cnt = 0;
2312*4882a593Smuzhiyun ha->beacon_blink_led = 0;
2313*4882a593Smuzhiyun
2314*4882a593Smuzhiyun set_bit(0, ha->req_qid_map);
2315*4882a593Smuzhiyun set_bit(0, ha->rsp_qid_map);
2316*4882a593Smuzhiyun
2317*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0040,
2318*4882a593Smuzhiyun "Configuring PCI space...\n");
2319*4882a593Smuzhiyun rval = ha->isp_ops->pci_config(vha);
2320*4882a593Smuzhiyun if (rval) {
2321*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0044,
2322*4882a593Smuzhiyun "Unable to configure PCI space.\n");
2323*4882a593Smuzhiyun return (rval);
2324*4882a593Smuzhiyun }
2325*4882a593Smuzhiyun
2326*4882a593Smuzhiyun ha->isp_ops->reset_chip(vha);
2327*4882a593Smuzhiyun
2328*4882a593Smuzhiyun /* Check for secure flash support */
2329*4882a593Smuzhiyun if (IS_QLA28XX(ha)) {
2330*4882a593Smuzhiyun if (rd_reg_word(®->mailbox12) & BIT_0)
2331*4882a593Smuzhiyun ha->flags.secure_adapter = 1;
2332*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0xffff, "Secure Adapter: %s\n",
2333*4882a593Smuzhiyun (ha->flags.secure_adapter) ? "Yes" : "No");
2334*4882a593Smuzhiyun }
2335*4882a593Smuzhiyun
2336*4882a593Smuzhiyun
2337*4882a593Smuzhiyun rval = qla2xxx_get_flash_info(vha);
2338*4882a593Smuzhiyun if (rval) {
2339*4882a593Smuzhiyun ql_log(ql_log_fatal, vha, 0x004f,
2340*4882a593Smuzhiyun "Unable to validate FLASH data.\n");
2341*4882a593Smuzhiyun return rval;
2342*4882a593Smuzhiyun }
2343*4882a593Smuzhiyun
2344*4882a593Smuzhiyun if (IS_QLA8044(ha)) {
2345*4882a593Smuzhiyun qla8044_read_reset_template(vha);
2346*4882a593Smuzhiyun
2347*4882a593Smuzhiyun /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
2348*4882a593Smuzhiyun * If DONRESET_BIT0 is set, drivers should not set dev_state
2349*4882a593Smuzhiyun * to NEED_RESET. But if NEED_RESET is set, drivers should
2350*4882a593Smuzhiyun * should honor the reset. */
2351*4882a593Smuzhiyun if (ql2xdontresethba == 1)
2352*4882a593Smuzhiyun qla8044_set_idc_dontreset(vha);
2353*4882a593Smuzhiyun }
2354*4882a593Smuzhiyun
2355*4882a593Smuzhiyun ha->isp_ops->get_flash_version(vha, req->ring);
2356*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0061,
2357*4882a593Smuzhiyun "Configure NVRAM parameters...\n");
2358*4882a593Smuzhiyun
2359*4882a593Smuzhiyun /* Let priority default to FCP, can be overridden by nvram_config */
2360*4882a593Smuzhiyun ha->fc4_type_priority = FC4_PRIORITY_FCP;
2361*4882a593Smuzhiyun
2362*4882a593Smuzhiyun ha->isp_ops->nvram_config(vha);
2363*4882a593Smuzhiyun
2364*4882a593Smuzhiyun if (ha->fc4_type_priority != FC4_PRIORITY_FCP &&
2365*4882a593Smuzhiyun ha->fc4_type_priority != FC4_PRIORITY_NVME)
2366*4882a593Smuzhiyun ha->fc4_type_priority = FC4_PRIORITY_FCP;
2367*4882a593Smuzhiyun
2368*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0xffff, "FC4 priority set to %s\n",
2369*4882a593Smuzhiyun ha->fc4_type_priority == FC4_PRIORITY_FCP ? "FCP" : "NVMe");
2370*4882a593Smuzhiyun
2371*4882a593Smuzhiyun if (ha->flags.disable_serdes) {
2372*4882a593Smuzhiyun /* Mask HBA via NVRAM settings? */
2373*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x0077,
2374*4882a593Smuzhiyun "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
2375*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
2376*4882a593Smuzhiyun }
2377*4882a593Smuzhiyun
2378*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0078,
2379*4882a593Smuzhiyun "Verifying loaded RISC code...\n");
2380*4882a593Smuzhiyun
2381*4882a593Smuzhiyun /* If smartsan enabled then require fdmi and rdp enabled */
2382*4882a593Smuzhiyun if (ql2xsmartsan) {
2383*4882a593Smuzhiyun ql2xfdmienable = 1;
2384*4882a593Smuzhiyun ql2xrdpenable = 1;
2385*4882a593Smuzhiyun }
2386*4882a593Smuzhiyun
2387*4882a593Smuzhiyun if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
2388*4882a593Smuzhiyun rval = ha->isp_ops->chip_diag(vha);
2389*4882a593Smuzhiyun if (rval)
2390*4882a593Smuzhiyun return (rval);
2391*4882a593Smuzhiyun rval = qla2x00_setup_chip(vha);
2392*4882a593Smuzhiyun if (rval)
2393*4882a593Smuzhiyun return (rval);
2394*4882a593Smuzhiyun }
2395*4882a593Smuzhiyun
2396*4882a593Smuzhiyun if (IS_QLA84XX(ha)) {
2397*4882a593Smuzhiyun ha->cs84xx = qla84xx_get_chip(vha);
2398*4882a593Smuzhiyun if (!ha->cs84xx) {
2399*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x00d0,
2400*4882a593Smuzhiyun "Unable to configure ISP84XX.\n");
2401*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
2402*4882a593Smuzhiyun }
2403*4882a593Smuzhiyun }
2404*4882a593Smuzhiyun
2405*4882a593Smuzhiyun if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha))
2406*4882a593Smuzhiyun rval = qla2x00_init_rings(vha);
2407*4882a593Smuzhiyun
2408*4882a593Smuzhiyun /* No point in continuing if firmware initialization failed. */
2409*4882a593Smuzhiyun if (rval != QLA_SUCCESS)
2410*4882a593Smuzhiyun return rval;
2411*4882a593Smuzhiyun
2412*4882a593Smuzhiyun ha->flags.chip_reset_done = 1;
2413*4882a593Smuzhiyun
2414*4882a593Smuzhiyun if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
2415*4882a593Smuzhiyun /* Issue verify 84xx FW IOCB to complete 84xx initialization */
2416*4882a593Smuzhiyun rval = qla84xx_init_chip(vha);
2417*4882a593Smuzhiyun if (rval != QLA_SUCCESS) {
2418*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x00d4,
2419*4882a593Smuzhiyun "Unable to initialize ISP84XX.\n");
2420*4882a593Smuzhiyun qla84xx_put_chip(vha);
2421*4882a593Smuzhiyun }
2422*4882a593Smuzhiyun }
2423*4882a593Smuzhiyun
2424*4882a593Smuzhiyun /* Load the NIC Core f/w if we are the first protocol driver. */
2425*4882a593Smuzhiyun if (IS_QLA8031(ha)) {
2426*4882a593Smuzhiyun rval = qla83xx_nic_core_fw_load(vha);
2427*4882a593Smuzhiyun if (rval)
2428*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0124,
2429*4882a593Smuzhiyun "Error in initializing NIC Core f/w.\n");
2430*4882a593Smuzhiyun }
2431*4882a593Smuzhiyun
2432*4882a593Smuzhiyun if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
2433*4882a593Smuzhiyun qla24xx_read_fcp_prio_cfg(vha);
2434*4882a593Smuzhiyun
2435*4882a593Smuzhiyun if (IS_P3P_TYPE(ha))
2436*4882a593Smuzhiyun qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
2437*4882a593Smuzhiyun else
2438*4882a593Smuzhiyun qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
2439*4882a593Smuzhiyun
2440*4882a593Smuzhiyun return (rval);
2441*4882a593Smuzhiyun }
2442*4882a593Smuzhiyun
2443*4882a593Smuzhiyun /**
2444*4882a593Smuzhiyun * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
2445*4882a593Smuzhiyun * @vha: HA context
2446*4882a593Smuzhiyun *
2447*4882a593Smuzhiyun * Returns 0 on success.
2448*4882a593Smuzhiyun */
2449*4882a593Smuzhiyun int
qla2100_pci_config(scsi_qla_host_t * vha)2450*4882a593Smuzhiyun qla2100_pci_config(scsi_qla_host_t *vha)
2451*4882a593Smuzhiyun {
2452*4882a593Smuzhiyun uint16_t w;
2453*4882a593Smuzhiyun unsigned long flags;
2454*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
2455*4882a593Smuzhiyun struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2456*4882a593Smuzhiyun
2457*4882a593Smuzhiyun pci_set_master(ha->pdev);
2458*4882a593Smuzhiyun pci_try_set_mwi(ha->pdev);
2459*4882a593Smuzhiyun
2460*4882a593Smuzhiyun pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
2461*4882a593Smuzhiyun w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
2462*4882a593Smuzhiyun pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2463*4882a593Smuzhiyun
2464*4882a593Smuzhiyun pci_disable_rom(ha->pdev);
2465*4882a593Smuzhiyun
2466*4882a593Smuzhiyun /* Get PCI bus information. */
2467*4882a593Smuzhiyun spin_lock_irqsave(&ha->hardware_lock, flags);
2468*4882a593Smuzhiyun ha->pci_attr = rd_reg_word(®->ctrl_status);
2469*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->hardware_lock, flags);
2470*4882a593Smuzhiyun
2471*4882a593Smuzhiyun return QLA_SUCCESS;
2472*4882a593Smuzhiyun }
2473*4882a593Smuzhiyun
2474*4882a593Smuzhiyun /**
2475*4882a593Smuzhiyun * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
2476*4882a593Smuzhiyun * @vha: HA context
2477*4882a593Smuzhiyun *
2478*4882a593Smuzhiyun * Returns 0 on success.
2479*4882a593Smuzhiyun */
2480*4882a593Smuzhiyun int
qla2300_pci_config(scsi_qla_host_t * vha)2481*4882a593Smuzhiyun qla2300_pci_config(scsi_qla_host_t *vha)
2482*4882a593Smuzhiyun {
2483*4882a593Smuzhiyun uint16_t w;
2484*4882a593Smuzhiyun unsigned long flags = 0;
2485*4882a593Smuzhiyun uint32_t cnt;
2486*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
2487*4882a593Smuzhiyun struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2488*4882a593Smuzhiyun
2489*4882a593Smuzhiyun pci_set_master(ha->pdev);
2490*4882a593Smuzhiyun pci_try_set_mwi(ha->pdev);
2491*4882a593Smuzhiyun
2492*4882a593Smuzhiyun pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
2493*4882a593Smuzhiyun w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
2494*4882a593Smuzhiyun
2495*4882a593Smuzhiyun if (IS_QLA2322(ha) || IS_QLA6322(ha))
2496*4882a593Smuzhiyun w &= ~PCI_COMMAND_INTX_DISABLE;
2497*4882a593Smuzhiyun pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2498*4882a593Smuzhiyun
2499*4882a593Smuzhiyun /*
2500*4882a593Smuzhiyun * If this is a 2300 card and not 2312, reset the
2501*4882a593Smuzhiyun * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
2502*4882a593Smuzhiyun * the 2310 also reports itself as a 2300 so we need to get the
2503*4882a593Smuzhiyun * fb revision level -- a 6 indicates it really is a 2300 and
2504*4882a593Smuzhiyun * not a 2310.
2505*4882a593Smuzhiyun */
2506*4882a593Smuzhiyun if (IS_QLA2300(ha)) {
2507*4882a593Smuzhiyun spin_lock_irqsave(&ha->hardware_lock, flags);
2508*4882a593Smuzhiyun
2509*4882a593Smuzhiyun /* Pause RISC. */
2510*4882a593Smuzhiyun wrt_reg_word(®->hccr, HCCR_PAUSE_RISC);
2511*4882a593Smuzhiyun for (cnt = 0; cnt < 30000; cnt++) {
2512*4882a593Smuzhiyun if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) != 0)
2513*4882a593Smuzhiyun break;
2514*4882a593Smuzhiyun
2515*4882a593Smuzhiyun udelay(10);
2516*4882a593Smuzhiyun }
2517*4882a593Smuzhiyun
2518*4882a593Smuzhiyun /* Select FPM registers. */
2519*4882a593Smuzhiyun wrt_reg_word(®->ctrl_status, 0x20);
2520*4882a593Smuzhiyun rd_reg_word(®->ctrl_status);
2521*4882a593Smuzhiyun
2522*4882a593Smuzhiyun /* Get the fb rev level */
2523*4882a593Smuzhiyun ha->fb_rev = RD_FB_CMD_REG(ha, reg);
2524*4882a593Smuzhiyun
2525*4882a593Smuzhiyun if (ha->fb_rev == FPM_2300)
2526*4882a593Smuzhiyun pci_clear_mwi(ha->pdev);
2527*4882a593Smuzhiyun
2528*4882a593Smuzhiyun /* Deselect FPM registers. */
2529*4882a593Smuzhiyun wrt_reg_word(®->ctrl_status, 0x0);
2530*4882a593Smuzhiyun rd_reg_word(®->ctrl_status);
2531*4882a593Smuzhiyun
2532*4882a593Smuzhiyun /* Release RISC module. */
2533*4882a593Smuzhiyun wrt_reg_word(®->hccr, HCCR_RELEASE_RISC);
2534*4882a593Smuzhiyun for (cnt = 0; cnt < 30000; cnt++) {
2535*4882a593Smuzhiyun if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) == 0)
2536*4882a593Smuzhiyun break;
2537*4882a593Smuzhiyun
2538*4882a593Smuzhiyun udelay(10);
2539*4882a593Smuzhiyun }
2540*4882a593Smuzhiyun
2541*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->hardware_lock, flags);
2542*4882a593Smuzhiyun }
2543*4882a593Smuzhiyun
2544*4882a593Smuzhiyun pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
2545*4882a593Smuzhiyun
2546*4882a593Smuzhiyun pci_disable_rom(ha->pdev);
2547*4882a593Smuzhiyun
2548*4882a593Smuzhiyun /* Get PCI bus information. */
2549*4882a593Smuzhiyun spin_lock_irqsave(&ha->hardware_lock, flags);
2550*4882a593Smuzhiyun ha->pci_attr = rd_reg_word(®->ctrl_status);
2551*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->hardware_lock, flags);
2552*4882a593Smuzhiyun
2553*4882a593Smuzhiyun return QLA_SUCCESS;
2554*4882a593Smuzhiyun }
2555*4882a593Smuzhiyun
2556*4882a593Smuzhiyun /**
2557*4882a593Smuzhiyun * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
2558*4882a593Smuzhiyun * @vha: HA context
2559*4882a593Smuzhiyun *
2560*4882a593Smuzhiyun * Returns 0 on success.
2561*4882a593Smuzhiyun */
2562*4882a593Smuzhiyun int
qla24xx_pci_config(scsi_qla_host_t * vha)2563*4882a593Smuzhiyun qla24xx_pci_config(scsi_qla_host_t *vha)
2564*4882a593Smuzhiyun {
2565*4882a593Smuzhiyun uint16_t w;
2566*4882a593Smuzhiyun unsigned long flags = 0;
2567*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
2568*4882a593Smuzhiyun struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2569*4882a593Smuzhiyun
2570*4882a593Smuzhiyun pci_set_master(ha->pdev);
2571*4882a593Smuzhiyun pci_try_set_mwi(ha->pdev);
2572*4882a593Smuzhiyun
2573*4882a593Smuzhiyun pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
2574*4882a593Smuzhiyun w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
2575*4882a593Smuzhiyun w &= ~PCI_COMMAND_INTX_DISABLE;
2576*4882a593Smuzhiyun pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2577*4882a593Smuzhiyun
2578*4882a593Smuzhiyun pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
2579*4882a593Smuzhiyun
2580*4882a593Smuzhiyun /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
2581*4882a593Smuzhiyun if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
2582*4882a593Smuzhiyun pcix_set_mmrbc(ha->pdev, 2048);
2583*4882a593Smuzhiyun
2584*4882a593Smuzhiyun /* PCIe -- adjust Maximum Read Request Size (2048). */
2585*4882a593Smuzhiyun if (pci_is_pcie(ha->pdev))
2586*4882a593Smuzhiyun pcie_set_readrq(ha->pdev, 4096);
2587*4882a593Smuzhiyun
2588*4882a593Smuzhiyun pci_disable_rom(ha->pdev);
2589*4882a593Smuzhiyun
2590*4882a593Smuzhiyun ha->chip_revision = ha->pdev->revision;
2591*4882a593Smuzhiyun
2592*4882a593Smuzhiyun /* Get PCI bus information. */
2593*4882a593Smuzhiyun spin_lock_irqsave(&ha->hardware_lock, flags);
2594*4882a593Smuzhiyun ha->pci_attr = rd_reg_dword(®->ctrl_status);
2595*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->hardware_lock, flags);
2596*4882a593Smuzhiyun
2597*4882a593Smuzhiyun return QLA_SUCCESS;
2598*4882a593Smuzhiyun }
2599*4882a593Smuzhiyun
2600*4882a593Smuzhiyun /**
2601*4882a593Smuzhiyun * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
2602*4882a593Smuzhiyun * @vha: HA context
2603*4882a593Smuzhiyun *
2604*4882a593Smuzhiyun * Returns 0 on success.
2605*4882a593Smuzhiyun */
2606*4882a593Smuzhiyun int
qla25xx_pci_config(scsi_qla_host_t * vha)2607*4882a593Smuzhiyun qla25xx_pci_config(scsi_qla_host_t *vha)
2608*4882a593Smuzhiyun {
2609*4882a593Smuzhiyun uint16_t w;
2610*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
2611*4882a593Smuzhiyun
2612*4882a593Smuzhiyun pci_set_master(ha->pdev);
2613*4882a593Smuzhiyun pci_try_set_mwi(ha->pdev);
2614*4882a593Smuzhiyun
2615*4882a593Smuzhiyun pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
2616*4882a593Smuzhiyun w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
2617*4882a593Smuzhiyun w &= ~PCI_COMMAND_INTX_DISABLE;
2618*4882a593Smuzhiyun pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2619*4882a593Smuzhiyun
2620*4882a593Smuzhiyun /* PCIe -- adjust Maximum Read Request Size (2048). */
2621*4882a593Smuzhiyun if (pci_is_pcie(ha->pdev))
2622*4882a593Smuzhiyun pcie_set_readrq(ha->pdev, 4096);
2623*4882a593Smuzhiyun
2624*4882a593Smuzhiyun pci_disable_rom(ha->pdev);
2625*4882a593Smuzhiyun
2626*4882a593Smuzhiyun ha->chip_revision = ha->pdev->revision;
2627*4882a593Smuzhiyun
2628*4882a593Smuzhiyun return QLA_SUCCESS;
2629*4882a593Smuzhiyun }
2630*4882a593Smuzhiyun
2631*4882a593Smuzhiyun /**
2632*4882a593Smuzhiyun * qla2x00_isp_firmware() - Choose firmware image.
2633*4882a593Smuzhiyun * @vha: HA context
2634*4882a593Smuzhiyun *
2635*4882a593Smuzhiyun * Returns 0 on success.
2636*4882a593Smuzhiyun */
2637*4882a593Smuzhiyun static int
qla2x00_isp_firmware(scsi_qla_host_t * vha)2638*4882a593Smuzhiyun qla2x00_isp_firmware(scsi_qla_host_t *vha)
2639*4882a593Smuzhiyun {
2640*4882a593Smuzhiyun int rval;
2641*4882a593Smuzhiyun uint16_t loop_id, topo, sw_cap;
2642*4882a593Smuzhiyun uint8_t domain, area, al_pa;
2643*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
2644*4882a593Smuzhiyun
2645*4882a593Smuzhiyun /* Assume loading risc code */
2646*4882a593Smuzhiyun rval = QLA_FUNCTION_FAILED;
2647*4882a593Smuzhiyun
2648*4882a593Smuzhiyun if (ha->flags.disable_risc_code_load) {
2649*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
2650*4882a593Smuzhiyun
2651*4882a593Smuzhiyun /* Verify checksum of loaded RISC code. */
2652*4882a593Smuzhiyun rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
2653*4882a593Smuzhiyun if (rval == QLA_SUCCESS) {
2654*4882a593Smuzhiyun /* And, verify we are not in ROM code. */
2655*4882a593Smuzhiyun rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
2656*4882a593Smuzhiyun &area, &domain, &topo, &sw_cap);
2657*4882a593Smuzhiyun }
2658*4882a593Smuzhiyun }
2659*4882a593Smuzhiyun
2660*4882a593Smuzhiyun if (rval)
2661*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x007a,
2662*4882a593Smuzhiyun "**** Load RISC code ****.\n");
2663*4882a593Smuzhiyun
2664*4882a593Smuzhiyun return (rval);
2665*4882a593Smuzhiyun }
2666*4882a593Smuzhiyun
2667*4882a593Smuzhiyun /**
2668*4882a593Smuzhiyun * qla2x00_reset_chip() - Reset ISP chip.
2669*4882a593Smuzhiyun * @vha: HA context
2670*4882a593Smuzhiyun *
2671*4882a593Smuzhiyun * Returns 0 on success.
2672*4882a593Smuzhiyun */
2673*4882a593Smuzhiyun int
qla2x00_reset_chip(scsi_qla_host_t * vha)2674*4882a593Smuzhiyun qla2x00_reset_chip(scsi_qla_host_t *vha)
2675*4882a593Smuzhiyun {
2676*4882a593Smuzhiyun unsigned long flags = 0;
2677*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
2678*4882a593Smuzhiyun struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2679*4882a593Smuzhiyun uint32_t cnt;
2680*4882a593Smuzhiyun uint16_t cmd;
2681*4882a593Smuzhiyun int rval = QLA_FUNCTION_FAILED;
2682*4882a593Smuzhiyun
2683*4882a593Smuzhiyun if (unlikely(pci_channel_offline(ha->pdev)))
2684*4882a593Smuzhiyun return rval;
2685*4882a593Smuzhiyun
2686*4882a593Smuzhiyun ha->isp_ops->disable_intrs(ha);
2687*4882a593Smuzhiyun
2688*4882a593Smuzhiyun spin_lock_irqsave(&ha->hardware_lock, flags);
2689*4882a593Smuzhiyun
2690*4882a593Smuzhiyun /* Turn off master enable */
2691*4882a593Smuzhiyun cmd = 0;
2692*4882a593Smuzhiyun pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
2693*4882a593Smuzhiyun cmd &= ~PCI_COMMAND_MASTER;
2694*4882a593Smuzhiyun pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2695*4882a593Smuzhiyun
2696*4882a593Smuzhiyun if (!IS_QLA2100(ha)) {
2697*4882a593Smuzhiyun /* Pause RISC. */
2698*4882a593Smuzhiyun wrt_reg_word(®->hccr, HCCR_PAUSE_RISC);
2699*4882a593Smuzhiyun if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
2700*4882a593Smuzhiyun for (cnt = 0; cnt < 30000; cnt++) {
2701*4882a593Smuzhiyun if ((rd_reg_word(®->hccr) &
2702*4882a593Smuzhiyun HCCR_RISC_PAUSE) != 0)
2703*4882a593Smuzhiyun break;
2704*4882a593Smuzhiyun udelay(100);
2705*4882a593Smuzhiyun }
2706*4882a593Smuzhiyun } else {
2707*4882a593Smuzhiyun rd_reg_word(®->hccr); /* PCI Posting. */
2708*4882a593Smuzhiyun udelay(10);
2709*4882a593Smuzhiyun }
2710*4882a593Smuzhiyun
2711*4882a593Smuzhiyun /* Select FPM registers. */
2712*4882a593Smuzhiyun wrt_reg_word(®->ctrl_status, 0x20);
2713*4882a593Smuzhiyun rd_reg_word(®->ctrl_status); /* PCI Posting. */
2714*4882a593Smuzhiyun
2715*4882a593Smuzhiyun /* FPM Soft Reset. */
2716*4882a593Smuzhiyun wrt_reg_word(®->fpm_diag_config, 0x100);
2717*4882a593Smuzhiyun rd_reg_word(®->fpm_diag_config); /* PCI Posting. */
2718*4882a593Smuzhiyun
2719*4882a593Smuzhiyun /* Toggle Fpm Reset. */
2720*4882a593Smuzhiyun if (!IS_QLA2200(ha)) {
2721*4882a593Smuzhiyun wrt_reg_word(®->fpm_diag_config, 0x0);
2722*4882a593Smuzhiyun rd_reg_word(®->fpm_diag_config); /* PCI Posting. */
2723*4882a593Smuzhiyun }
2724*4882a593Smuzhiyun
2725*4882a593Smuzhiyun /* Select frame buffer registers. */
2726*4882a593Smuzhiyun wrt_reg_word(®->ctrl_status, 0x10);
2727*4882a593Smuzhiyun rd_reg_word(®->ctrl_status); /* PCI Posting. */
2728*4882a593Smuzhiyun
2729*4882a593Smuzhiyun /* Reset frame buffer FIFOs. */
2730*4882a593Smuzhiyun if (IS_QLA2200(ha)) {
2731*4882a593Smuzhiyun WRT_FB_CMD_REG(ha, reg, 0xa000);
2732*4882a593Smuzhiyun RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
2733*4882a593Smuzhiyun } else {
2734*4882a593Smuzhiyun WRT_FB_CMD_REG(ha, reg, 0x00fc);
2735*4882a593Smuzhiyun
2736*4882a593Smuzhiyun /* Read back fb_cmd until zero or 3 seconds max */
2737*4882a593Smuzhiyun for (cnt = 0; cnt < 3000; cnt++) {
2738*4882a593Smuzhiyun if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
2739*4882a593Smuzhiyun break;
2740*4882a593Smuzhiyun udelay(100);
2741*4882a593Smuzhiyun }
2742*4882a593Smuzhiyun }
2743*4882a593Smuzhiyun
2744*4882a593Smuzhiyun /* Select RISC module registers. */
2745*4882a593Smuzhiyun wrt_reg_word(®->ctrl_status, 0);
2746*4882a593Smuzhiyun rd_reg_word(®->ctrl_status); /* PCI Posting. */
2747*4882a593Smuzhiyun
2748*4882a593Smuzhiyun /* Reset RISC processor. */
2749*4882a593Smuzhiyun wrt_reg_word(®->hccr, HCCR_RESET_RISC);
2750*4882a593Smuzhiyun rd_reg_word(®->hccr); /* PCI Posting. */
2751*4882a593Smuzhiyun
2752*4882a593Smuzhiyun /* Release RISC processor. */
2753*4882a593Smuzhiyun wrt_reg_word(®->hccr, HCCR_RELEASE_RISC);
2754*4882a593Smuzhiyun rd_reg_word(®->hccr); /* PCI Posting. */
2755*4882a593Smuzhiyun }
2756*4882a593Smuzhiyun
2757*4882a593Smuzhiyun wrt_reg_word(®->hccr, HCCR_CLR_RISC_INT);
2758*4882a593Smuzhiyun wrt_reg_word(®->hccr, HCCR_CLR_HOST_INT);
2759*4882a593Smuzhiyun
2760*4882a593Smuzhiyun /* Reset ISP chip. */
2761*4882a593Smuzhiyun wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET);
2762*4882a593Smuzhiyun
2763*4882a593Smuzhiyun /* Wait for RISC to recover from reset. */
2764*4882a593Smuzhiyun if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2765*4882a593Smuzhiyun /*
2766*4882a593Smuzhiyun * It is necessary to for a delay here since the card doesn't
2767*4882a593Smuzhiyun * respond to PCI reads during a reset. On some architectures
2768*4882a593Smuzhiyun * this will result in an MCA.
2769*4882a593Smuzhiyun */
2770*4882a593Smuzhiyun udelay(20);
2771*4882a593Smuzhiyun for (cnt = 30000; cnt; cnt--) {
2772*4882a593Smuzhiyun if ((rd_reg_word(®->ctrl_status) &
2773*4882a593Smuzhiyun CSR_ISP_SOFT_RESET) == 0)
2774*4882a593Smuzhiyun break;
2775*4882a593Smuzhiyun udelay(100);
2776*4882a593Smuzhiyun }
2777*4882a593Smuzhiyun } else
2778*4882a593Smuzhiyun udelay(10);
2779*4882a593Smuzhiyun
2780*4882a593Smuzhiyun /* Reset RISC processor. */
2781*4882a593Smuzhiyun wrt_reg_word(®->hccr, HCCR_RESET_RISC);
2782*4882a593Smuzhiyun
2783*4882a593Smuzhiyun wrt_reg_word(®->semaphore, 0);
2784*4882a593Smuzhiyun
2785*4882a593Smuzhiyun /* Release RISC processor. */
2786*4882a593Smuzhiyun wrt_reg_word(®->hccr, HCCR_RELEASE_RISC);
2787*4882a593Smuzhiyun rd_reg_word(®->hccr); /* PCI Posting. */
2788*4882a593Smuzhiyun
2789*4882a593Smuzhiyun if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2790*4882a593Smuzhiyun for (cnt = 0; cnt < 30000; cnt++) {
2791*4882a593Smuzhiyun if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
2792*4882a593Smuzhiyun break;
2793*4882a593Smuzhiyun
2794*4882a593Smuzhiyun udelay(100);
2795*4882a593Smuzhiyun }
2796*4882a593Smuzhiyun } else
2797*4882a593Smuzhiyun udelay(100);
2798*4882a593Smuzhiyun
2799*4882a593Smuzhiyun /* Turn on master enable */
2800*4882a593Smuzhiyun cmd |= PCI_COMMAND_MASTER;
2801*4882a593Smuzhiyun pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2802*4882a593Smuzhiyun
2803*4882a593Smuzhiyun /* Disable RISC pause on FPM parity error. */
2804*4882a593Smuzhiyun if (!IS_QLA2100(ha)) {
2805*4882a593Smuzhiyun wrt_reg_word(®->hccr, HCCR_DISABLE_PARITY_PAUSE);
2806*4882a593Smuzhiyun rd_reg_word(®->hccr); /* PCI Posting. */
2807*4882a593Smuzhiyun }
2808*4882a593Smuzhiyun
2809*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->hardware_lock, flags);
2810*4882a593Smuzhiyun
2811*4882a593Smuzhiyun return QLA_SUCCESS;
2812*4882a593Smuzhiyun }
2813*4882a593Smuzhiyun
2814*4882a593Smuzhiyun /**
2815*4882a593Smuzhiyun * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
2816*4882a593Smuzhiyun * @vha: HA context
2817*4882a593Smuzhiyun *
2818*4882a593Smuzhiyun * Returns 0 on success.
2819*4882a593Smuzhiyun */
2820*4882a593Smuzhiyun static int
qla81xx_reset_mpi(scsi_qla_host_t * vha)2821*4882a593Smuzhiyun qla81xx_reset_mpi(scsi_qla_host_t *vha)
2822*4882a593Smuzhiyun {
2823*4882a593Smuzhiyun uint16_t mb[4] = {0x1010, 0, 1, 0};
2824*4882a593Smuzhiyun
2825*4882a593Smuzhiyun if (!IS_QLA81XX(vha->hw))
2826*4882a593Smuzhiyun return QLA_SUCCESS;
2827*4882a593Smuzhiyun
2828*4882a593Smuzhiyun return qla81xx_write_mpi_register(vha, mb);
2829*4882a593Smuzhiyun }
2830*4882a593Smuzhiyun
2831*4882a593Smuzhiyun /**
2832*4882a593Smuzhiyun * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
2833*4882a593Smuzhiyun * @vha: HA context
2834*4882a593Smuzhiyun *
2835*4882a593Smuzhiyun * Returns 0 on success.
2836*4882a593Smuzhiyun */
2837*4882a593Smuzhiyun static inline int
qla24xx_reset_risc(scsi_qla_host_t * vha)2838*4882a593Smuzhiyun qla24xx_reset_risc(scsi_qla_host_t *vha)
2839*4882a593Smuzhiyun {
2840*4882a593Smuzhiyun unsigned long flags = 0;
2841*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
2842*4882a593Smuzhiyun struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2843*4882a593Smuzhiyun uint32_t cnt;
2844*4882a593Smuzhiyun uint16_t wd;
2845*4882a593Smuzhiyun static int abts_cnt; /* ISP abort retry counts */
2846*4882a593Smuzhiyun int rval = QLA_SUCCESS;
2847*4882a593Smuzhiyun
2848*4882a593Smuzhiyun spin_lock_irqsave(&ha->hardware_lock, flags);
2849*4882a593Smuzhiyun
2850*4882a593Smuzhiyun /* Reset RISC. */
2851*4882a593Smuzhiyun wrt_reg_dword(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
2852*4882a593Smuzhiyun for (cnt = 0; cnt < 30000; cnt++) {
2853*4882a593Smuzhiyun if ((rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
2854*4882a593Smuzhiyun break;
2855*4882a593Smuzhiyun
2856*4882a593Smuzhiyun udelay(10);
2857*4882a593Smuzhiyun }
2858*4882a593Smuzhiyun
2859*4882a593Smuzhiyun if (!(rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE))
2860*4882a593Smuzhiyun set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
2861*4882a593Smuzhiyun
2862*4882a593Smuzhiyun ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
2863*4882a593Smuzhiyun "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
2864*4882a593Smuzhiyun rd_reg_dword(®->hccr),
2865*4882a593Smuzhiyun rd_reg_dword(®->ctrl_status),
2866*4882a593Smuzhiyun (rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE));
2867*4882a593Smuzhiyun
2868*4882a593Smuzhiyun wrt_reg_dword(®->ctrl_status,
2869*4882a593Smuzhiyun CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
2870*4882a593Smuzhiyun pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2871*4882a593Smuzhiyun
2872*4882a593Smuzhiyun udelay(100);
2873*4882a593Smuzhiyun
2874*4882a593Smuzhiyun /* Wait for firmware to complete NVRAM accesses. */
2875*4882a593Smuzhiyun rd_reg_word(®->mailbox0);
2876*4882a593Smuzhiyun for (cnt = 10000; rd_reg_word(®->mailbox0) != 0 &&
2877*4882a593Smuzhiyun rval == QLA_SUCCESS; cnt--) {
2878*4882a593Smuzhiyun barrier();
2879*4882a593Smuzhiyun if (cnt)
2880*4882a593Smuzhiyun udelay(5);
2881*4882a593Smuzhiyun else
2882*4882a593Smuzhiyun rval = QLA_FUNCTION_TIMEOUT;
2883*4882a593Smuzhiyun }
2884*4882a593Smuzhiyun
2885*4882a593Smuzhiyun if (rval == QLA_SUCCESS)
2886*4882a593Smuzhiyun set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
2887*4882a593Smuzhiyun
2888*4882a593Smuzhiyun ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
2889*4882a593Smuzhiyun "HCCR: 0x%x, MailBox0 Status 0x%x\n",
2890*4882a593Smuzhiyun rd_reg_dword(®->hccr),
2891*4882a593Smuzhiyun rd_reg_word(®->mailbox0));
2892*4882a593Smuzhiyun
2893*4882a593Smuzhiyun /* Wait for soft-reset to complete. */
2894*4882a593Smuzhiyun rd_reg_dword(®->ctrl_status);
2895*4882a593Smuzhiyun for (cnt = 0; cnt < 60; cnt++) {
2896*4882a593Smuzhiyun barrier();
2897*4882a593Smuzhiyun if ((rd_reg_dword(®->ctrl_status) &
2898*4882a593Smuzhiyun CSRX_ISP_SOFT_RESET) == 0)
2899*4882a593Smuzhiyun break;
2900*4882a593Smuzhiyun
2901*4882a593Smuzhiyun udelay(5);
2902*4882a593Smuzhiyun }
2903*4882a593Smuzhiyun if (!(rd_reg_dword(®->ctrl_status) & CSRX_ISP_SOFT_RESET))
2904*4882a593Smuzhiyun set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
2905*4882a593Smuzhiyun
2906*4882a593Smuzhiyun ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
2907*4882a593Smuzhiyun "HCCR: 0x%x, Soft Reset status: 0x%x\n",
2908*4882a593Smuzhiyun rd_reg_dword(®->hccr),
2909*4882a593Smuzhiyun rd_reg_dword(®->ctrl_status));
2910*4882a593Smuzhiyun
2911*4882a593Smuzhiyun /* If required, do an MPI FW reset now */
2912*4882a593Smuzhiyun if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
2913*4882a593Smuzhiyun if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
2914*4882a593Smuzhiyun if (++abts_cnt < 5) {
2915*4882a593Smuzhiyun set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2916*4882a593Smuzhiyun set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
2917*4882a593Smuzhiyun } else {
2918*4882a593Smuzhiyun /*
2919*4882a593Smuzhiyun * We exhausted the ISP abort retries. We have to
2920*4882a593Smuzhiyun * set the board offline.
2921*4882a593Smuzhiyun */
2922*4882a593Smuzhiyun abts_cnt = 0;
2923*4882a593Smuzhiyun vha->flags.online = 0;
2924*4882a593Smuzhiyun }
2925*4882a593Smuzhiyun }
2926*4882a593Smuzhiyun }
2927*4882a593Smuzhiyun
2928*4882a593Smuzhiyun wrt_reg_dword(®->hccr, HCCRX_SET_RISC_RESET);
2929*4882a593Smuzhiyun rd_reg_dword(®->hccr);
2930*4882a593Smuzhiyun
2931*4882a593Smuzhiyun wrt_reg_dword(®->hccr, HCCRX_REL_RISC_PAUSE);
2932*4882a593Smuzhiyun rd_reg_dword(®->hccr);
2933*4882a593Smuzhiyun
2934*4882a593Smuzhiyun wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_RESET);
2935*4882a593Smuzhiyun rd_reg_dword(®->hccr);
2936*4882a593Smuzhiyun
2937*4882a593Smuzhiyun rd_reg_word(®->mailbox0);
2938*4882a593Smuzhiyun for (cnt = 60; rd_reg_word(®->mailbox0) != 0 &&
2939*4882a593Smuzhiyun rval == QLA_SUCCESS; cnt--) {
2940*4882a593Smuzhiyun barrier();
2941*4882a593Smuzhiyun if (cnt)
2942*4882a593Smuzhiyun udelay(5);
2943*4882a593Smuzhiyun else
2944*4882a593Smuzhiyun rval = QLA_FUNCTION_TIMEOUT;
2945*4882a593Smuzhiyun }
2946*4882a593Smuzhiyun if (rval == QLA_SUCCESS)
2947*4882a593Smuzhiyun set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
2948*4882a593Smuzhiyun
2949*4882a593Smuzhiyun ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
2950*4882a593Smuzhiyun "Host Risc 0x%x, mailbox0 0x%x\n",
2951*4882a593Smuzhiyun rd_reg_dword(®->hccr),
2952*4882a593Smuzhiyun rd_reg_word(®->mailbox0));
2953*4882a593Smuzhiyun
2954*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->hardware_lock, flags);
2955*4882a593Smuzhiyun
2956*4882a593Smuzhiyun ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
2957*4882a593Smuzhiyun "Driver in %s mode\n",
2958*4882a593Smuzhiyun IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
2959*4882a593Smuzhiyun
2960*4882a593Smuzhiyun if (IS_NOPOLLING_TYPE(ha))
2961*4882a593Smuzhiyun ha->isp_ops->enable_intrs(ha);
2962*4882a593Smuzhiyun
2963*4882a593Smuzhiyun return rval;
2964*4882a593Smuzhiyun }
2965*4882a593Smuzhiyun
2966*4882a593Smuzhiyun static void
qla25xx_read_risc_sema_reg(scsi_qla_host_t * vha,uint32_t * data)2967*4882a593Smuzhiyun qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
2968*4882a593Smuzhiyun {
2969*4882a593Smuzhiyun struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2970*4882a593Smuzhiyun
2971*4882a593Smuzhiyun wrt_reg_dword(®->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2972*4882a593Smuzhiyun *data = rd_reg_dword(®->iobase_window + RISC_REGISTER_WINDOW_OFFSET);
2973*4882a593Smuzhiyun }
2974*4882a593Smuzhiyun
2975*4882a593Smuzhiyun static void
qla25xx_write_risc_sema_reg(scsi_qla_host_t * vha,uint32_t data)2976*4882a593Smuzhiyun qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
2977*4882a593Smuzhiyun {
2978*4882a593Smuzhiyun struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2979*4882a593Smuzhiyun
2980*4882a593Smuzhiyun wrt_reg_dword(®->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2981*4882a593Smuzhiyun wrt_reg_dword(®->iobase_window + RISC_REGISTER_WINDOW_OFFSET, data);
2982*4882a593Smuzhiyun }
2983*4882a593Smuzhiyun
2984*4882a593Smuzhiyun static void
qla25xx_manipulate_risc_semaphore(scsi_qla_host_t * vha)2985*4882a593Smuzhiyun qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
2986*4882a593Smuzhiyun {
2987*4882a593Smuzhiyun uint32_t wd32 = 0;
2988*4882a593Smuzhiyun uint delta_msec = 100;
2989*4882a593Smuzhiyun uint elapsed_msec = 0;
2990*4882a593Smuzhiyun uint timeout_msec;
2991*4882a593Smuzhiyun ulong n;
2992*4882a593Smuzhiyun
2993*4882a593Smuzhiyun if (vha->hw->pdev->subsystem_device != 0x0175 &&
2994*4882a593Smuzhiyun vha->hw->pdev->subsystem_device != 0x0240)
2995*4882a593Smuzhiyun return;
2996*4882a593Smuzhiyun
2997*4882a593Smuzhiyun wrt_reg_dword(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);
2998*4882a593Smuzhiyun udelay(100);
2999*4882a593Smuzhiyun
3000*4882a593Smuzhiyun attempt:
3001*4882a593Smuzhiyun timeout_msec = TIMEOUT_SEMAPHORE;
3002*4882a593Smuzhiyun n = timeout_msec / delta_msec;
3003*4882a593Smuzhiyun while (n--) {
3004*4882a593Smuzhiyun qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
3005*4882a593Smuzhiyun qla25xx_read_risc_sema_reg(vha, &wd32);
3006*4882a593Smuzhiyun if (wd32 & RISC_SEMAPHORE)
3007*4882a593Smuzhiyun break;
3008*4882a593Smuzhiyun msleep(delta_msec);
3009*4882a593Smuzhiyun elapsed_msec += delta_msec;
3010*4882a593Smuzhiyun if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
3011*4882a593Smuzhiyun goto force;
3012*4882a593Smuzhiyun }
3013*4882a593Smuzhiyun
3014*4882a593Smuzhiyun if (!(wd32 & RISC_SEMAPHORE))
3015*4882a593Smuzhiyun goto force;
3016*4882a593Smuzhiyun
3017*4882a593Smuzhiyun if (!(wd32 & RISC_SEMAPHORE_FORCE))
3018*4882a593Smuzhiyun goto acquired;
3019*4882a593Smuzhiyun
3020*4882a593Smuzhiyun qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
3021*4882a593Smuzhiyun timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
3022*4882a593Smuzhiyun n = timeout_msec / delta_msec;
3023*4882a593Smuzhiyun while (n--) {
3024*4882a593Smuzhiyun qla25xx_read_risc_sema_reg(vha, &wd32);
3025*4882a593Smuzhiyun if (!(wd32 & RISC_SEMAPHORE_FORCE))
3026*4882a593Smuzhiyun break;
3027*4882a593Smuzhiyun msleep(delta_msec);
3028*4882a593Smuzhiyun elapsed_msec += delta_msec;
3029*4882a593Smuzhiyun if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
3030*4882a593Smuzhiyun goto force;
3031*4882a593Smuzhiyun }
3032*4882a593Smuzhiyun
3033*4882a593Smuzhiyun if (wd32 & RISC_SEMAPHORE_FORCE)
3034*4882a593Smuzhiyun qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
3035*4882a593Smuzhiyun
3036*4882a593Smuzhiyun goto attempt;
3037*4882a593Smuzhiyun
3038*4882a593Smuzhiyun force:
3039*4882a593Smuzhiyun qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
3040*4882a593Smuzhiyun
3041*4882a593Smuzhiyun acquired:
3042*4882a593Smuzhiyun return;
3043*4882a593Smuzhiyun }
3044*4882a593Smuzhiyun
3045*4882a593Smuzhiyun /**
3046*4882a593Smuzhiyun * qla24xx_reset_chip() - Reset ISP24xx chip.
3047*4882a593Smuzhiyun * @vha: HA context
3048*4882a593Smuzhiyun *
3049*4882a593Smuzhiyun * Returns 0 on success.
3050*4882a593Smuzhiyun */
3051*4882a593Smuzhiyun int
qla24xx_reset_chip(scsi_qla_host_t * vha)3052*4882a593Smuzhiyun qla24xx_reset_chip(scsi_qla_host_t *vha)
3053*4882a593Smuzhiyun {
3054*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
3055*4882a593Smuzhiyun int rval = QLA_FUNCTION_FAILED;
3056*4882a593Smuzhiyun
3057*4882a593Smuzhiyun if (pci_channel_offline(ha->pdev) &&
3058*4882a593Smuzhiyun ha->flags.pci_channel_io_perm_failure) {
3059*4882a593Smuzhiyun return rval;
3060*4882a593Smuzhiyun }
3061*4882a593Smuzhiyun
3062*4882a593Smuzhiyun ha->isp_ops->disable_intrs(ha);
3063*4882a593Smuzhiyun
3064*4882a593Smuzhiyun qla25xx_manipulate_risc_semaphore(vha);
3065*4882a593Smuzhiyun
3066*4882a593Smuzhiyun /* Perform RISC reset. */
3067*4882a593Smuzhiyun rval = qla24xx_reset_risc(vha);
3068*4882a593Smuzhiyun
3069*4882a593Smuzhiyun return rval;
3070*4882a593Smuzhiyun }
3071*4882a593Smuzhiyun
3072*4882a593Smuzhiyun /**
3073*4882a593Smuzhiyun * qla2x00_chip_diag() - Test chip for proper operation.
3074*4882a593Smuzhiyun * @vha: HA context
3075*4882a593Smuzhiyun *
3076*4882a593Smuzhiyun * Returns 0 on success.
3077*4882a593Smuzhiyun */
3078*4882a593Smuzhiyun int
qla2x00_chip_diag(scsi_qla_host_t * vha)3079*4882a593Smuzhiyun qla2x00_chip_diag(scsi_qla_host_t *vha)
3080*4882a593Smuzhiyun {
3081*4882a593Smuzhiyun int rval;
3082*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
3083*4882a593Smuzhiyun struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
3084*4882a593Smuzhiyun unsigned long flags = 0;
3085*4882a593Smuzhiyun uint16_t data;
3086*4882a593Smuzhiyun uint32_t cnt;
3087*4882a593Smuzhiyun uint16_t mb[5];
3088*4882a593Smuzhiyun struct req_que *req = ha->req_q_map[0];
3089*4882a593Smuzhiyun
3090*4882a593Smuzhiyun /* Assume a failed state */
3091*4882a593Smuzhiyun rval = QLA_FUNCTION_FAILED;
3092*4882a593Smuzhiyun
3093*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x007b, "Testing device at %p.\n",
3094*4882a593Smuzhiyun ®->flash_address);
3095*4882a593Smuzhiyun
3096*4882a593Smuzhiyun spin_lock_irqsave(&ha->hardware_lock, flags);
3097*4882a593Smuzhiyun
3098*4882a593Smuzhiyun /* Reset ISP chip. */
3099*4882a593Smuzhiyun wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET);
3100*4882a593Smuzhiyun
3101*4882a593Smuzhiyun /*
3102*4882a593Smuzhiyun * We need to have a delay here since the card will not respond while
3103*4882a593Smuzhiyun * in reset causing an MCA on some architectures.
3104*4882a593Smuzhiyun */
3105*4882a593Smuzhiyun udelay(20);
3106*4882a593Smuzhiyun data = qla2x00_debounce_register(®->ctrl_status);
3107*4882a593Smuzhiyun for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
3108*4882a593Smuzhiyun udelay(5);
3109*4882a593Smuzhiyun data = rd_reg_word(®->ctrl_status);
3110*4882a593Smuzhiyun barrier();
3111*4882a593Smuzhiyun }
3112*4882a593Smuzhiyun
3113*4882a593Smuzhiyun if (!cnt)
3114*4882a593Smuzhiyun goto chip_diag_failed;
3115*4882a593Smuzhiyun
3116*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x007c,
3117*4882a593Smuzhiyun "Reset register cleared by chip reset.\n");
3118*4882a593Smuzhiyun
3119*4882a593Smuzhiyun /* Reset RISC processor. */
3120*4882a593Smuzhiyun wrt_reg_word(®->hccr, HCCR_RESET_RISC);
3121*4882a593Smuzhiyun wrt_reg_word(®->hccr, HCCR_RELEASE_RISC);
3122*4882a593Smuzhiyun
3123*4882a593Smuzhiyun /* Workaround for QLA2312 PCI parity error */
3124*4882a593Smuzhiyun if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
3125*4882a593Smuzhiyun data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
3126*4882a593Smuzhiyun for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
3127*4882a593Smuzhiyun udelay(5);
3128*4882a593Smuzhiyun data = RD_MAILBOX_REG(ha, reg, 0);
3129*4882a593Smuzhiyun barrier();
3130*4882a593Smuzhiyun }
3131*4882a593Smuzhiyun } else
3132*4882a593Smuzhiyun udelay(10);
3133*4882a593Smuzhiyun
3134*4882a593Smuzhiyun if (!cnt)
3135*4882a593Smuzhiyun goto chip_diag_failed;
3136*4882a593Smuzhiyun
3137*4882a593Smuzhiyun /* Check product ID of chip */
3138*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product ID of chip.\n");
3139*4882a593Smuzhiyun
3140*4882a593Smuzhiyun mb[1] = RD_MAILBOX_REG(ha, reg, 1);
3141*4882a593Smuzhiyun mb[2] = RD_MAILBOX_REG(ha, reg, 2);
3142*4882a593Smuzhiyun mb[3] = RD_MAILBOX_REG(ha, reg, 3);
3143*4882a593Smuzhiyun mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
3144*4882a593Smuzhiyun if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
3145*4882a593Smuzhiyun mb[3] != PROD_ID_3) {
3146*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0062,
3147*4882a593Smuzhiyun "Wrong product ID = 0x%x,0x%x,0x%x.\n",
3148*4882a593Smuzhiyun mb[1], mb[2], mb[3]);
3149*4882a593Smuzhiyun
3150*4882a593Smuzhiyun goto chip_diag_failed;
3151*4882a593Smuzhiyun }
3152*4882a593Smuzhiyun ha->product_id[0] = mb[1];
3153*4882a593Smuzhiyun ha->product_id[1] = mb[2];
3154*4882a593Smuzhiyun ha->product_id[2] = mb[3];
3155*4882a593Smuzhiyun ha->product_id[3] = mb[4];
3156*4882a593Smuzhiyun
3157*4882a593Smuzhiyun /* Adjust fw RISC transfer size */
3158*4882a593Smuzhiyun if (req->length > 1024)
3159*4882a593Smuzhiyun ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
3160*4882a593Smuzhiyun else
3161*4882a593Smuzhiyun ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
3162*4882a593Smuzhiyun req->length;
3163*4882a593Smuzhiyun
3164*4882a593Smuzhiyun if (IS_QLA2200(ha) &&
3165*4882a593Smuzhiyun RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
3166*4882a593Smuzhiyun /* Limit firmware transfer size with a 2200A */
3167*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
3168*4882a593Smuzhiyun
3169*4882a593Smuzhiyun ha->device_type |= DT_ISP2200A;
3170*4882a593Smuzhiyun ha->fw_transfer_size = 128;
3171*4882a593Smuzhiyun }
3172*4882a593Smuzhiyun
3173*4882a593Smuzhiyun /* Wrap Incoming Mailboxes Test. */
3174*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->hardware_lock, flags);
3175*4882a593Smuzhiyun
3176*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
3177*4882a593Smuzhiyun rval = qla2x00_mbx_reg_test(vha);
3178*4882a593Smuzhiyun if (rval)
3179*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0080,
3180*4882a593Smuzhiyun "Failed mailbox send register test.\n");
3181*4882a593Smuzhiyun else
3182*4882a593Smuzhiyun /* Flag a successful rval */
3183*4882a593Smuzhiyun rval = QLA_SUCCESS;
3184*4882a593Smuzhiyun spin_lock_irqsave(&ha->hardware_lock, flags);
3185*4882a593Smuzhiyun
3186*4882a593Smuzhiyun chip_diag_failed:
3187*4882a593Smuzhiyun if (rval)
3188*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x0081,
3189*4882a593Smuzhiyun "Chip diagnostics **** FAILED ****.\n");
3190*4882a593Smuzhiyun
3191*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->hardware_lock, flags);
3192*4882a593Smuzhiyun
3193*4882a593Smuzhiyun return (rval);
3194*4882a593Smuzhiyun }
3195*4882a593Smuzhiyun
3196*4882a593Smuzhiyun /**
3197*4882a593Smuzhiyun * qla24xx_chip_diag() - Test ISP24xx for proper operation.
3198*4882a593Smuzhiyun * @vha: HA context
3199*4882a593Smuzhiyun *
3200*4882a593Smuzhiyun * Returns 0 on success.
3201*4882a593Smuzhiyun */
3202*4882a593Smuzhiyun int
qla24xx_chip_diag(scsi_qla_host_t * vha)3203*4882a593Smuzhiyun qla24xx_chip_diag(scsi_qla_host_t *vha)
3204*4882a593Smuzhiyun {
3205*4882a593Smuzhiyun int rval;
3206*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
3207*4882a593Smuzhiyun struct req_que *req = ha->req_q_map[0];
3208*4882a593Smuzhiyun
3209*4882a593Smuzhiyun if (IS_P3P_TYPE(ha))
3210*4882a593Smuzhiyun return QLA_SUCCESS;
3211*4882a593Smuzhiyun
3212*4882a593Smuzhiyun ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
3213*4882a593Smuzhiyun
3214*4882a593Smuzhiyun rval = qla2x00_mbx_reg_test(vha);
3215*4882a593Smuzhiyun if (rval) {
3216*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0082,
3217*4882a593Smuzhiyun "Failed mailbox send register test.\n");
3218*4882a593Smuzhiyun } else {
3219*4882a593Smuzhiyun /* Flag a successful rval */
3220*4882a593Smuzhiyun rval = QLA_SUCCESS;
3221*4882a593Smuzhiyun }
3222*4882a593Smuzhiyun
3223*4882a593Smuzhiyun return rval;
3224*4882a593Smuzhiyun }
3225*4882a593Smuzhiyun
3226*4882a593Smuzhiyun static void
qla2x00_init_fce_trace(scsi_qla_host_t * vha)3227*4882a593Smuzhiyun qla2x00_init_fce_trace(scsi_qla_host_t *vha)
3228*4882a593Smuzhiyun {
3229*4882a593Smuzhiyun int rval;
3230*4882a593Smuzhiyun dma_addr_t tc_dma;
3231*4882a593Smuzhiyun void *tc;
3232*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
3233*4882a593Smuzhiyun
3234*4882a593Smuzhiyun if (!IS_FWI2_CAPABLE(ha))
3235*4882a593Smuzhiyun return;
3236*4882a593Smuzhiyun
3237*4882a593Smuzhiyun if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
3238*4882a593Smuzhiyun !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
3239*4882a593Smuzhiyun return;
3240*4882a593Smuzhiyun
3241*4882a593Smuzhiyun if (ha->fce) {
3242*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x00bd,
3243*4882a593Smuzhiyun "%s: FCE Mem is already allocated.\n",
3244*4882a593Smuzhiyun __func__);
3245*4882a593Smuzhiyun return;
3246*4882a593Smuzhiyun }
3247*4882a593Smuzhiyun
3248*4882a593Smuzhiyun /* Allocate memory for Fibre Channel Event Buffer. */
3249*4882a593Smuzhiyun tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
3250*4882a593Smuzhiyun GFP_KERNEL);
3251*4882a593Smuzhiyun if (!tc) {
3252*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x00be,
3253*4882a593Smuzhiyun "Unable to allocate (%d KB) for FCE.\n",
3254*4882a593Smuzhiyun FCE_SIZE / 1024);
3255*4882a593Smuzhiyun return;
3256*4882a593Smuzhiyun }
3257*4882a593Smuzhiyun
3258*4882a593Smuzhiyun rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
3259*4882a593Smuzhiyun ha->fce_mb, &ha->fce_bufs);
3260*4882a593Smuzhiyun if (rval) {
3261*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x00bf,
3262*4882a593Smuzhiyun "Unable to initialize FCE (%d).\n", rval);
3263*4882a593Smuzhiyun dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc, tc_dma);
3264*4882a593Smuzhiyun return;
3265*4882a593Smuzhiyun }
3266*4882a593Smuzhiyun
3267*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x00c0,
3268*4882a593Smuzhiyun "Allocated (%d KB) for FCE...\n", FCE_SIZE / 1024);
3269*4882a593Smuzhiyun
3270*4882a593Smuzhiyun ha->flags.fce_enabled = 1;
3271*4882a593Smuzhiyun ha->fce_dma = tc_dma;
3272*4882a593Smuzhiyun ha->fce = tc;
3273*4882a593Smuzhiyun }
3274*4882a593Smuzhiyun
3275*4882a593Smuzhiyun static void
qla2x00_init_eft_trace(scsi_qla_host_t * vha)3276*4882a593Smuzhiyun qla2x00_init_eft_trace(scsi_qla_host_t *vha)
3277*4882a593Smuzhiyun {
3278*4882a593Smuzhiyun int rval;
3279*4882a593Smuzhiyun dma_addr_t tc_dma;
3280*4882a593Smuzhiyun void *tc;
3281*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
3282*4882a593Smuzhiyun
3283*4882a593Smuzhiyun if (!IS_FWI2_CAPABLE(ha))
3284*4882a593Smuzhiyun return;
3285*4882a593Smuzhiyun
3286*4882a593Smuzhiyun if (ha->eft) {
3287*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x00bd,
3288*4882a593Smuzhiyun "%s: EFT Mem is already allocated.\n",
3289*4882a593Smuzhiyun __func__);
3290*4882a593Smuzhiyun return;
3291*4882a593Smuzhiyun }
3292*4882a593Smuzhiyun
3293*4882a593Smuzhiyun /* Allocate memory for Extended Trace Buffer. */
3294*4882a593Smuzhiyun tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
3295*4882a593Smuzhiyun GFP_KERNEL);
3296*4882a593Smuzhiyun if (!tc) {
3297*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x00c1,
3298*4882a593Smuzhiyun "Unable to allocate (%d KB) for EFT.\n",
3299*4882a593Smuzhiyun EFT_SIZE / 1024);
3300*4882a593Smuzhiyun return;
3301*4882a593Smuzhiyun }
3302*4882a593Smuzhiyun
3303*4882a593Smuzhiyun rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
3304*4882a593Smuzhiyun if (rval) {
3305*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x00c2,
3306*4882a593Smuzhiyun "Unable to initialize EFT (%d).\n", rval);
3307*4882a593Smuzhiyun dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc, tc_dma);
3308*4882a593Smuzhiyun return;
3309*4882a593Smuzhiyun }
3310*4882a593Smuzhiyun
3311*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x00c3,
3312*4882a593Smuzhiyun "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
3313*4882a593Smuzhiyun
3314*4882a593Smuzhiyun ha->eft_dma = tc_dma;
3315*4882a593Smuzhiyun ha->eft = tc;
3316*4882a593Smuzhiyun }
3317*4882a593Smuzhiyun
3318*4882a593Smuzhiyun static void
qla2x00_alloc_offload_mem(scsi_qla_host_t * vha)3319*4882a593Smuzhiyun qla2x00_alloc_offload_mem(scsi_qla_host_t *vha)
3320*4882a593Smuzhiyun {
3321*4882a593Smuzhiyun qla2x00_init_fce_trace(vha);
3322*4882a593Smuzhiyun qla2x00_init_eft_trace(vha);
3323*4882a593Smuzhiyun }
3324*4882a593Smuzhiyun
3325*4882a593Smuzhiyun void
qla2x00_alloc_fw_dump(scsi_qla_host_t * vha)3326*4882a593Smuzhiyun qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
3327*4882a593Smuzhiyun {
3328*4882a593Smuzhiyun uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
3329*4882a593Smuzhiyun eft_size, fce_size, mq_size;
3330*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
3331*4882a593Smuzhiyun struct req_que *req = ha->req_q_map[0];
3332*4882a593Smuzhiyun struct rsp_que *rsp = ha->rsp_q_map[0];
3333*4882a593Smuzhiyun struct qla2xxx_fw_dump *fw_dump;
3334*4882a593Smuzhiyun
3335*4882a593Smuzhiyun if (ha->fw_dump) {
3336*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x00bd,
3337*4882a593Smuzhiyun "Firmware dump already allocated.\n");
3338*4882a593Smuzhiyun return;
3339*4882a593Smuzhiyun }
3340*4882a593Smuzhiyun
3341*4882a593Smuzhiyun ha->fw_dumped = 0;
3342*4882a593Smuzhiyun ha->fw_dump_cap_flags = 0;
3343*4882a593Smuzhiyun dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
3344*4882a593Smuzhiyun req_q_size = rsp_q_size = 0;
3345*4882a593Smuzhiyun
3346*4882a593Smuzhiyun if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3347*4882a593Smuzhiyun fixed_size = sizeof(struct qla2100_fw_dump);
3348*4882a593Smuzhiyun } else if (IS_QLA23XX(ha)) {
3349*4882a593Smuzhiyun fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
3350*4882a593Smuzhiyun mem_size = (ha->fw_memory_size - 0x11000 + 1) *
3351*4882a593Smuzhiyun sizeof(uint16_t);
3352*4882a593Smuzhiyun } else if (IS_FWI2_CAPABLE(ha)) {
3353*4882a593Smuzhiyun if (IS_QLA83XX(ha))
3354*4882a593Smuzhiyun fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
3355*4882a593Smuzhiyun else if (IS_QLA81XX(ha))
3356*4882a593Smuzhiyun fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
3357*4882a593Smuzhiyun else if (IS_QLA25XX(ha))
3358*4882a593Smuzhiyun fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
3359*4882a593Smuzhiyun else
3360*4882a593Smuzhiyun fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
3361*4882a593Smuzhiyun
3362*4882a593Smuzhiyun mem_size = (ha->fw_memory_size - 0x100000 + 1) *
3363*4882a593Smuzhiyun sizeof(uint32_t);
3364*4882a593Smuzhiyun if (ha->mqenable) {
3365*4882a593Smuzhiyun if (!IS_QLA83XX(ha))
3366*4882a593Smuzhiyun mq_size = sizeof(struct qla2xxx_mq_chain);
3367*4882a593Smuzhiyun /*
3368*4882a593Smuzhiyun * Allocate maximum buffer size for all queues - Q0.
3369*4882a593Smuzhiyun * Resizing must be done at end-of-dump processing.
3370*4882a593Smuzhiyun */
3371*4882a593Smuzhiyun mq_size += (ha->max_req_queues - 1) *
3372*4882a593Smuzhiyun (req->length * sizeof(request_t));
3373*4882a593Smuzhiyun mq_size += (ha->max_rsp_queues - 1) *
3374*4882a593Smuzhiyun (rsp->length * sizeof(response_t));
3375*4882a593Smuzhiyun }
3376*4882a593Smuzhiyun if (ha->tgt.atio_ring)
3377*4882a593Smuzhiyun mq_size += ha->tgt.atio_q_length * sizeof(request_t);
3378*4882a593Smuzhiyun
3379*4882a593Smuzhiyun qla2x00_init_fce_trace(vha);
3380*4882a593Smuzhiyun if (ha->fce)
3381*4882a593Smuzhiyun fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
3382*4882a593Smuzhiyun qla2x00_init_eft_trace(vha);
3383*4882a593Smuzhiyun if (ha->eft)
3384*4882a593Smuzhiyun eft_size = EFT_SIZE;
3385*4882a593Smuzhiyun }
3386*4882a593Smuzhiyun
3387*4882a593Smuzhiyun if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
3388*4882a593Smuzhiyun struct fwdt *fwdt = ha->fwdt;
3389*4882a593Smuzhiyun uint j;
3390*4882a593Smuzhiyun
3391*4882a593Smuzhiyun for (j = 0; j < 2; j++, fwdt++) {
3392*4882a593Smuzhiyun if (!fwdt->template) {
3393*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x00ba,
3394*4882a593Smuzhiyun "-> fwdt%u no template\n", j);
3395*4882a593Smuzhiyun continue;
3396*4882a593Smuzhiyun }
3397*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x00fa,
3398*4882a593Smuzhiyun "-> fwdt%u calculating fwdump size...\n", j);
3399*4882a593Smuzhiyun fwdt->dump_size = qla27xx_fwdt_calculate_dump_size(
3400*4882a593Smuzhiyun vha, fwdt->template);
3401*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x00fa,
3402*4882a593Smuzhiyun "-> fwdt%u calculated fwdump size = %#lx bytes\n",
3403*4882a593Smuzhiyun j, fwdt->dump_size);
3404*4882a593Smuzhiyun dump_size += fwdt->dump_size;
3405*4882a593Smuzhiyun }
3406*4882a593Smuzhiyun /* Add space for spare MPI fw dump. */
3407*4882a593Smuzhiyun dump_size += ha->fwdt[1].dump_size;
3408*4882a593Smuzhiyun } else {
3409*4882a593Smuzhiyun req_q_size = req->length * sizeof(request_t);
3410*4882a593Smuzhiyun rsp_q_size = rsp->length * sizeof(response_t);
3411*4882a593Smuzhiyun dump_size = offsetof(struct qla2xxx_fw_dump, isp);
3412*4882a593Smuzhiyun dump_size += fixed_size + mem_size + req_q_size + rsp_q_size
3413*4882a593Smuzhiyun + eft_size;
3414*4882a593Smuzhiyun ha->chain_offset = dump_size;
3415*4882a593Smuzhiyun dump_size += mq_size + fce_size;
3416*4882a593Smuzhiyun if (ha->exchoffld_buf)
3417*4882a593Smuzhiyun dump_size += sizeof(struct qla2xxx_offld_chain) +
3418*4882a593Smuzhiyun ha->exchoffld_size;
3419*4882a593Smuzhiyun if (ha->exlogin_buf)
3420*4882a593Smuzhiyun dump_size += sizeof(struct qla2xxx_offld_chain) +
3421*4882a593Smuzhiyun ha->exlogin_size;
3422*4882a593Smuzhiyun }
3423*4882a593Smuzhiyun
3424*4882a593Smuzhiyun if (!ha->fw_dump_len || dump_size > ha->fw_dump_alloc_len) {
3425*4882a593Smuzhiyun
3426*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x00c5,
3427*4882a593Smuzhiyun "%s dump_size %d fw_dump_len %d fw_dump_alloc_len %d\n",
3428*4882a593Smuzhiyun __func__, dump_size, ha->fw_dump_len,
3429*4882a593Smuzhiyun ha->fw_dump_alloc_len);
3430*4882a593Smuzhiyun
3431*4882a593Smuzhiyun fw_dump = vmalloc(dump_size);
3432*4882a593Smuzhiyun if (!fw_dump) {
3433*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x00c4,
3434*4882a593Smuzhiyun "Unable to allocate (%d KB) for firmware dump.\n",
3435*4882a593Smuzhiyun dump_size / 1024);
3436*4882a593Smuzhiyun } else {
3437*4882a593Smuzhiyun mutex_lock(&ha->optrom_mutex);
3438*4882a593Smuzhiyun if (ha->fw_dumped) {
3439*4882a593Smuzhiyun memcpy(fw_dump, ha->fw_dump, ha->fw_dump_len);
3440*4882a593Smuzhiyun vfree(ha->fw_dump);
3441*4882a593Smuzhiyun ha->fw_dump = fw_dump;
3442*4882a593Smuzhiyun ha->fw_dump_alloc_len = dump_size;
3443*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x00c5,
3444*4882a593Smuzhiyun "Re-Allocated (%d KB) and save firmware dump.\n",
3445*4882a593Smuzhiyun dump_size / 1024);
3446*4882a593Smuzhiyun } else {
3447*4882a593Smuzhiyun if (ha->fw_dump)
3448*4882a593Smuzhiyun vfree(ha->fw_dump);
3449*4882a593Smuzhiyun ha->fw_dump = fw_dump;
3450*4882a593Smuzhiyun
3451*4882a593Smuzhiyun ha->fw_dump_len = ha->fw_dump_alloc_len =
3452*4882a593Smuzhiyun dump_size;
3453*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x00c5,
3454*4882a593Smuzhiyun "Allocated (%d KB) for firmware dump.\n",
3455*4882a593Smuzhiyun dump_size / 1024);
3456*4882a593Smuzhiyun
3457*4882a593Smuzhiyun if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
3458*4882a593Smuzhiyun ha->mpi_fw_dump = (char *)fw_dump +
3459*4882a593Smuzhiyun ha->fwdt[1].dump_size;
3460*4882a593Smuzhiyun mutex_unlock(&ha->optrom_mutex);
3461*4882a593Smuzhiyun return;
3462*4882a593Smuzhiyun }
3463*4882a593Smuzhiyun
3464*4882a593Smuzhiyun ha->fw_dump->signature[0] = 'Q';
3465*4882a593Smuzhiyun ha->fw_dump->signature[1] = 'L';
3466*4882a593Smuzhiyun ha->fw_dump->signature[2] = 'G';
3467*4882a593Smuzhiyun ha->fw_dump->signature[3] = 'C';
3468*4882a593Smuzhiyun ha->fw_dump->version = htonl(1);
3469*4882a593Smuzhiyun
3470*4882a593Smuzhiyun ha->fw_dump->fixed_size = htonl(fixed_size);
3471*4882a593Smuzhiyun ha->fw_dump->mem_size = htonl(mem_size);
3472*4882a593Smuzhiyun ha->fw_dump->req_q_size = htonl(req_q_size);
3473*4882a593Smuzhiyun ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
3474*4882a593Smuzhiyun
3475*4882a593Smuzhiyun ha->fw_dump->eft_size = htonl(eft_size);
3476*4882a593Smuzhiyun ha->fw_dump->eft_addr_l =
3477*4882a593Smuzhiyun htonl(LSD(ha->eft_dma));
3478*4882a593Smuzhiyun ha->fw_dump->eft_addr_h =
3479*4882a593Smuzhiyun htonl(MSD(ha->eft_dma));
3480*4882a593Smuzhiyun
3481*4882a593Smuzhiyun ha->fw_dump->header_size =
3482*4882a593Smuzhiyun htonl(offsetof
3483*4882a593Smuzhiyun (struct qla2xxx_fw_dump, isp));
3484*4882a593Smuzhiyun }
3485*4882a593Smuzhiyun mutex_unlock(&ha->optrom_mutex);
3486*4882a593Smuzhiyun }
3487*4882a593Smuzhiyun }
3488*4882a593Smuzhiyun }
3489*4882a593Smuzhiyun
3490*4882a593Smuzhiyun static int
qla81xx_mpi_sync(scsi_qla_host_t * vha)3491*4882a593Smuzhiyun qla81xx_mpi_sync(scsi_qla_host_t *vha)
3492*4882a593Smuzhiyun {
3493*4882a593Smuzhiyun #define MPS_MASK 0xe0
3494*4882a593Smuzhiyun int rval;
3495*4882a593Smuzhiyun uint16_t dc;
3496*4882a593Smuzhiyun uint32_t dw;
3497*4882a593Smuzhiyun
3498*4882a593Smuzhiyun if (!IS_QLA81XX(vha->hw))
3499*4882a593Smuzhiyun return QLA_SUCCESS;
3500*4882a593Smuzhiyun
3501*4882a593Smuzhiyun rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
3502*4882a593Smuzhiyun if (rval != QLA_SUCCESS) {
3503*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0105,
3504*4882a593Smuzhiyun "Unable to acquire semaphore.\n");
3505*4882a593Smuzhiyun goto done;
3506*4882a593Smuzhiyun }
3507*4882a593Smuzhiyun
3508*4882a593Smuzhiyun pci_read_config_word(vha->hw->pdev, 0x54, &dc);
3509*4882a593Smuzhiyun rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
3510*4882a593Smuzhiyun if (rval != QLA_SUCCESS) {
3511*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
3512*4882a593Smuzhiyun goto done_release;
3513*4882a593Smuzhiyun }
3514*4882a593Smuzhiyun
3515*4882a593Smuzhiyun dc &= MPS_MASK;
3516*4882a593Smuzhiyun if (dc == (dw & MPS_MASK))
3517*4882a593Smuzhiyun goto done_release;
3518*4882a593Smuzhiyun
3519*4882a593Smuzhiyun dw &= ~MPS_MASK;
3520*4882a593Smuzhiyun dw |= dc;
3521*4882a593Smuzhiyun rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
3522*4882a593Smuzhiyun if (rval != QLA_SUCCESS) {
3523*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
3524*4882a593Smuzhiyun }
3525*4882a593Smuzhiyun
3526*4882a593Smuzhiyun done_release:
3527*4882a593Smuzhiyun rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
3528*4882a593Smuzhiyun if (rval != QLA_SUCCESS) {
3529*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x006d,
3530*4882a593Smuzhiyun "Unable to release semaphore.\n");
3531*4882a593Smuzhiyun }
3532*4882a593Smuzhiyun
3533*4882a593Smuzhiyun done:
3534*4882a593Smuzhiyun return rval;
3535*4882a593Smuzhiyun }
3536*4882a593Smuzhiyun
3537*4882a593Smuzhiyun int
qla2x00_alloc_outstanding_cmds(struct qla_hw_data * ha,struct req_que * req)3538*4882a593Smuzhiyun qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
3539*4882a593Smuzhiyun {
3540*4882a593Smuzhiyun /* Don't try to reallocate the array */
3541*4882a593Smuzhiyun if (req->outstanding_cmds)
3542*4882a593Smuzhiyun return QLA_SUCCESS;
3543*4882a593Smuzhiyun
3544*4882a593Smuzhiyun if (!IS_FWI2_CAPABLE(ha))
3545*4882a593Smuzhiyun req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
3546*4882a593Smuzhiyun else {
3547*4882a593Smuzhiyun if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count)
3548*4882a593Smuzhiyun req->num_outstanding_cmds = ha->cur_fw_xcb_count;
3549*4882a593Smuzhiyun else
3550*4882a593Smuzhiyun req->num_outstanding_cmds = ha->cur_fw_iocb_count;
3551*4882a593Smuzhiyun }
3552*4882a593Smuzhiyun
3553*4882a593Smuzhiyun req->outstanding_cmds = kcalloc(req->num_outstanding_cmds,
3554*4882a593Smuzhiyun sizeof(srb_t *),
3555*4882a593Smuzhiyun GFP_KERNEL);
3556*4882a593Smuzhiyun
3557*4882a593Smuzhiyun if (!req->outstanding_cmds) {
3558*4882a593Smuzhiyun /*
3559*4882a593Smuzhiyun * Try to allocate a minimal size just so we can get through
3560*4882a593Smuzhiyun * initialization.
3561*4882a593Smuzhiyun */
3562*4882a593Smuzhiyun req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
3563*4882a593Smuzhiyun req->outstanding_cmds = kcalloc(req->num_outstanding_cmds,
3564*4882a593Smuzhiyun sizeof(srb_t *),
3565*4882a593Smuzhiyun GFP_KERNEL);
3566*4882a593Smuzhiyun
3567*4882a593Smuzhiyun if (!req->outstanding_cmds) {
3568*4882a593Smuzhiyun ql_log(ql_log_fatal, NULL, 0x0126,
3569*4882a593Smuzhiyun "Failed to allocate memory for "
3570*4882a593Smuzhiyun "outstanding_cmds for req_que %p.\n", req);
3571*4882a593Smuzhiyun req->num_outstanding_cmds = 0;
3572*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
3573*4882a593Smuzhiyun }
3574*4882a593Smuzhiyun }
3575*4882a593Smuzhiyun
3576*4882a593Smuzhiyun return QLA_SUCCESS;
3577*4882a593Smuzhiyun }
3578*4882a593Smuzhiyun
3579*4882a593Smuzhiyun #define PRINT_FIELD(_field, _flag, _str) { \
3580*4882a593Smuzhiyun if (a0->_field & _flag) {\
3581*4882a593Smuzhiyun if (p) {\
3582*4882a593Smuzhiyun strcat(ptr, "|");\
3583*4882a593Smuzhiyun ptr++;\
3584*4882a593Smuzhiyun leftover--;\
3585*4882a593Smuzhiyun } \
3586*4882a593Smuzhiyun len = snprintf(ptr, leftover, "%s", _str); \
3587*4882a593Smuzhiyun p = 1;\
3588*4882a593Smuzhiyun leftover -= len;\
3589*4882a593Smuzhiyun ptr += len; \
3590*4882a593Smuzhiyun } \
3591*4882a593Smuzhiyun }
3592*4882a593Smuzhiyun
qla2xxx_print_sfp_info(struct scsi_qla_host * vha)3593*4882a593Smuzhiyun static void qla2xxx_print_sfp_info(struct scsi_qla_host *vha)
3594*4882a593Smuzhiyun {
3595*4882a593Smuzhiyun #define STR_LEN 64
3596*4882a593Smuzhiyun struct sff_8247_a0 *a0 = (struct sff_8247_a0 *)vha->hw->sfp_data;
3597*4882a593Smuzhiyun u8 str[STR_LEN], *ptr, p;
3598*4882a593Smuzhiyun int leftover, len;
3599*4882a593Smuzhiyun
3600*4882a593Smuzhiyun memset(str, 0, STR_LEN);
3601*4882a593Smuzhiyun snprintf(str, SFF_VEN_NAME_LEN+1, a0->vendor_name);
3602*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x015a,
3603*4882a593Smuzhiyun "SFP MFG Name: %s\n", str);
3604*4882a593Smuzhiyun
3605*4882a593Smuzhiyun memset(str, 0, STR_LEN);
3606*4882a593Smuzhiyun snprintf(str, SFF_PART_NAME_LEN+1, a0->vendor_pn);
3607*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x015c,
3608*4882a593Smuzhiyun "SFP Part Name: %s\n", str);
3609*4882a593Smuzhiyun
3610*4882a593Smuzhiyun /* media */
3611*4882a593Smuzhiyun memset(str, 0, STR_LEN);
3612*4882a593Smuzhiyun ptr = str;
3613*4882a593Smuzhiyun leftover = STR_LEN;
3614*4882a593Smuzhiyun p = len = 0;
3615*4882a593Smuzhiyun PRINT_FIELD(fc_med_cc9, FC_MED_TW, "Twin AX");
3616*4882a593Smuzhiyun PRINT_FIELD(fc_med_cc9, FC_MED_TP, "Twisted Pair");
3617*4882a593Smuzhiyun PRINT_FIELD(fc_med_cc9, FC_MED_MI, "Min Coax");
3618*4882a593Smuzhiyun PRINT_FIELD(fc_med_cc9, FC_MED_TV, "Video Coax");
3619*4882a593Smuzhiyun PRINT_FIELD(fc_med_cc9, FC_MED_M6, "MultiMode 62.5um");
3620*4882a593Smuzhiyun PRINT_FIELD(fc_med_cc9, FC_MED_M5, "MultiMode 50um");
3621*4882a593Smuzhiyun PRINT_FIELD(fc_med_cc9, FC_MED_SM, "SingleMode");
3622*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0160,
3623*4882a593Smuzhiyun "SFP Media: %s\n", str);
3624*4882a593Smuzhiyun
3625*4882a593Smuzhiyun /* link length */
3626*4882a593Smuzhiyun memset(str, 0, STR_LEN);
3627*4882a593Smuzhiyun ptr = str;
3628*4882a593Smuzhiyun leftover = STR_LEN;
3629*4882a593Smuzhiyun p = len = 0;
3630*4882a593Smuzhiyun PRINT_FIELD(fc_ll_cc7, FC_LL_VL, "Very Long");
3631*4882a593Smuzhiyun PRINT_FIELD(fc_ll_cc7, FC_LL_S, "Short");
3632*4882a593Smuzhiyun PRINT_FIELD(fc_ll_cc7, FC_LL_I, "Intermediate");
3633*4882a593Smuzhiyun PRINT_FIELD(fc_ll_cc7, FC_LL_L, "Long");
3634*4882a593Smuzhiyun PRINT_FIELD(fc_ll_cc7, FC_LL_M, "Medium");
3635*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0196,
3636*4882a593Smuzhiyun "SFP Link Length: %s\n", str);
3637*4882a593Smuzhiyun
3638*4882a593Smuzhiyun memset(str, 0, STR_LEN);
3639*4882a593Smuzhiyun ptr = str;
3640*4882a593Smuzhiyun leftover = STR_LEN;
3641*4882a593Smuzhiyun p = len = 0;
3642*4882a593Smuzhiyun PRINT_FIELD(fc_ll_cc7, FC_LL_SA, "Short Wave (SA)");
3643*4882a593Smuzhiyun PRINT_FIELD(fc_ll_cc7, FC_LL_LC, "Long Wave(LC)");
3644*4882a593Smuzhiyun PRINT_FIELD(fc_tec_cc8, FC_TEC_SN, "Short Wave (SN)");
3645*4882a593Smuzhiyun PRINT_FIELD(fc_tec_cc8, FC_TEC_SL, "Short Wave (SL)");
3646*4882a593Smuzhiyun PRINT_FIELD(fc_tec_cc8, FC_TEC_LL, "Long Wave (LL)");
3647*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x016e,
3648*4882a593Smuzhiyun "SFP FC Link Tech: %s\n", str);
3649*4882a593Smuzhiyun
3650*4882a593Smuzhiyun if (a0->length_km)
3651*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x016f,
3652*4882a593Smuzhiyun "SFP Distant: %d km\n", a0->length_km);
3653*4882a593Smuzhiyun if (a0->length_100m)
3654*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0170,
3655*4882a593Smuzhiyun "SFP Distant: %d m\n", a0->length_100m*100);
3656*4882a593Smuzhiyun if (a0->length_50um_10m)
3657*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0189,
3658*4882a593Smuzhiyun "SFP Distant (WL=50um): %d m\n", a0->length_50um_10m * 10);
3659*4882a593Smuzhiyun if (a0->length_62um_10m)
3660*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x018a,
3661*4882a593Smuzhiyun "SFP Distant (WL=62.5um): %d m\n", a0->length_62um_10m * 10);
3662*4882a593Smuzhiyun if (a0->length_om4_10m)
3663*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0194,
3664*4882a593Smuzhiyun "SFP Distant (OM4): %d m\n", a0->length_om4_10m * 10);
3665*4882a593Smuzhiyun if (a0->length_om3_10m)
3666*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0195,
3667*4882a593Smuzhiyun "SFP Distant (OM3): %d m\n", a0->length_om3_10m * 10);
3668*4882a593Smuzhiyun }
3669*4882a593Smuzhiyun
3670*4882a593Smuzhiyun
3671*4882a593Smuzhiyun /**
3672*4882a593Smuzhiyun * qla24xx_detect_sfp()
3673*4882a593Smuzhiyun *
3674*4882a593Smuzhiyun * @vha: adapter state pointer.
3675*4882a593Smuzhiyun *
3676*4882a593Smuzhiyun * @return
3677*4882a593Smuzhiyun * 0 -- Configure firmware to use short-range settings -- normal
3678*4882a593Smuzhiyun * buffer-to-buffer credits.
3679*4882a593Smuzhiyun *
3680*4882a593Smuzhiyun * 1 -- Configure firmware to use long-range settings -- extra
3681*4882a593Smuzhiyun * buffer-to-buffer credits should be allocated with
3682*4882a593Smuzhiyun * ha->lr_distance containing distance settings from NVRAM or SFP
3683*4882a593Smuzhiyun * (if supported).
3684*4882a593Smuzhiyun */
3685*4882a593Smuzhiyun int
qla24xx_detect_sfp(scsi_qla_host_t * vha)3686*4882a593Smuzhiyun qla24xx_detect_sfp(scsi_qla_host_t *vha)
3687*4882a593Smuzhiyun {
3688*4882a593Smuzhiyun int rc, used_nvram;
3689*4882a593Smuzhiyun struct sff_8247_a0 *a;
3690*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
3691*4882a593Smuzhiyun struct nvram_81xx *nv = ha->nvram;
3692*4882a593Smuzhiyun #define LR_DISTANCE_UNKNOWN 2
3693*4882a593Smuzhiyun static const char * const types[] = { "Short", "Long" };
3694*4882a593Smuzhiyun static const char * const lengths[] = { "(10km)", "(5km)", "" };
3695*4882a593Smuzhiyun u8 ll = 0;
3696*4882a593Smuzhiyun
3697*4882a593Smuzhiyun /* Seed with NVRAM settings. */
3698*4882a593Smuzhiyun used_nvram = 0;
3699*4882a593Smuzhiyun ha->flags.lr_detected = 0;
3700*4882a593Smuzhiyun if (IS_BPM_RANGE_CAPABLE(ha) &&
3701*4882a593Smuzhiyun (nv->enhanced_features & NEF_LR_DIST_ENABLE)) {
3702*4882a593Smuzhiyun used_nvram = 1;
3703*4882a593Smuzhiyun ha->flags.lr_detected = 1;
3704*4882a593Smuzhiyun ha->lr_distance =
3705*4882a593Smuzhiyun (nv->enhanced_features >> LR_DIST_NV_POS)
3706*4882a593Smuzhiyun & LR_DIST_NV_MASK;
3707*4882a593Smuzhiyun }
3708*4882a593Smuzhiyun
3709*4882a593Smuzhiyun if (!IS_BPM_ENABLED(vha))
3710*4882a593Smuzhiyun goto out;
3711*4882a593Smuzhiyun /* Determine SR/LR capabilities of SFP/Transceiver. */
3712*4882a593Smuzhiyun rc = qla2x00_read_sfp_dev(vha, NULL, 0);
3713*4882a593Smuzhiyun if (rc)
3714*4882a593Smuzhiyun goto out;
3715*4882a593Smuzhiyun
3716*4882a593Smuzhiyun used_nvram = 0;
3717*4882a593Smuzhiyun a = (struct sff_8247_a0 *)vha->hw->sfp_data;
3718*4882a593Smuzhiyun qla2xxx_print_sfp_info(vha);
3719*4882a593Smuzhiyun
3720*4882a593Smuzhiyun ha->flags.lr_detected = 0;
3721*4882a593Smuzhiyun ll = a->fc_ll_cc7;
3722*4882a593Smuzhiyun if (ll & FC_LL_VL || ll & FC_LL_L) {
3723*4882a593Smuzhiyun /* Long range, track length. */
3724*4882a593Smuzhiyun ha->flags.lr_detected = 1;
3725*4882a593Smuzhiyun
3726*4882a593Smuzhiyun if (a->length_km > 5 || a->length_100m > 50)
3727*4882a593Smuzhiyun ha->lr_distance = LR_DISTANCE_10K;
3728*4882a593Smuzhiyun else
3729*4882a593Smuzhiyun ha->lr_distance = LR_DISTANCE_5K;
3730*4882a593Smuzhiyun }
3731*4882a593Smuzhiyun
3732*4882a593Smuzhiyun out:
3733*4882a593Smuzhiyun ql_dbg(ql_dbg_async, vha, 0x507b,
3734*4882a593Smuzhiyun "SFP detect: %s-Range SFP %s (nvr=%x ll=%x lr=%x lrd=%x).\n",
3735*4882a593Smuzhiyun types[ha->flags.lr_detected],
3736*4882a593Smuzhiyun ha->flags.lr_detected ? lengths[ha->lr_distance] :
3737*4882a593Smuzhiyun lengths[LR_DISTANCE_UNKNOWN],
3738*4882a593Smuzhiyun used_nvram, ll, ha->flags.lr_detected, ha->lr_distance);
3739*4882a593Smuzhiyun return ha->flags.lr_detected;
3740*4882a593Smuzhiyun }
3741*4882a593Smuzhiyun
qla_init_iocb_limit(scsi_qla_host_t * vha)3742*4882a593Smuzhiyun void qla_init_iocb_limit(scsi_qla_host_t *vha)
3743*4882a593Smuzhiyun {
3744*4882a593Smuzhiyun u16 i, num_qps;
3745*4882a593Smuzhiyun u32 limit;
3746*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
3747*4882a593Smuzhiyun
3748*4882a593Smuzhiyun num_qps = ha->num_qpairs + 1;
3749*4882a593Smuzhiyun limit = (ha->orig_fw_iocb_count * QLA_IOCB_PCT_LIMIT) / 100;
3750*4882a593Smuzhiyun
3751*4882a593Smuzhiyun ha->base_qpair->fwres.iocbs_total = ha->orig_fw_iocb_count;
3752*4882a593Smuzhiyun ha->base_qpair->fwres.iocbs_limit = limit;
3753*4882a593Smuzhiyun ha->base_qpair->fwres.iocbs_qp_limit = limit / num_qps;
3754*4882a593Smuzhiyun ha->base_qpair->fwres.iocbs_used = 0;
3755*4882a593Smuzhiyun for (i = 0; i < ha->max_qpairs; i++) {
3756*4882a593Smuzhiyun if (ha->queue_pair_map[i]) {
3757*4882a593Smuzhiyun ha->queue_pair_map[i]->fwres.iocbs_total =
3758*4882a593Smuzhiyun ha->orig_fw_iocb_count;
3759*4882a593Smuzhiyun ha->queue_pair_map[i]->fwres.iocbs_limit = limit;
3760*4882a593Smuzhiyun ha->queue_pair_map[i]->fwres.iocbs_qp_limit =
3761*4882a593Smuzhiyun limit / num_qps;
3762*4882a593Smuzhiyun ha->queue_pair_map[i]->fwres.iocbs_used = 0;
3763*4882a593Smuzhiyun }
3764*4882a593Smuzhiyun }
3765*4882a593Smuzhiyun }
3766*4882a593Smuzhiyun
3767*4882a593Smuzhiyun /**
3768*4882a593Smuzhiyun * qla2x00_setup_chip() - Load and start RISC firmware.
3769*4882a593Smuzhiyun * @vha: HA context
3770*4882a593Smuzhiyun *
3771*4882a593Smuzhiyun * Returns 0 on success.
3772*4882a593Smuzhiyun */
3773*4882a593Smuzhiyun static int
qla2x00_setup_chip(scsi_qla_host_t * vha)3774*4882a593Smuzhiyun qla2x00_setup_chip(scsi_qla_host_t *vha)
3775*4882a593Smuzhiyun {
3776*4882a593Smuzhiyun int rval;
3777*4882a593Smuzhiyun uint32_t srisc_address = 0;
3778*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
3779*4882a593Smuzhiyun struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
3780*4882a593Smuzhiyun unsigned long flags;
3781*4882a593Smuzhiyun uint16_t fw_major_version;
3782*4882a593Smuzhiyun int done_once = 0;
3783*4882a593Smuzhiyun
3784*4882a593Smuzhiyun if (IS_P3P_TYPE(ha)) {
3785*4882a593Smuzhiyun rval = ha->isp_ops->load_risc(vha, &srisc_address);
3786*4882a593Smuzhiyun if (rval == QLA_SUCCESS) {
3787*4882a593Smuzhiyun qla2x00_stop_firmware(vha);
3788*4882a593Smuzhiyun goto enable_82xx_npiv;
3789*4882a593Smuzhiyun } else
3790*4882a593Smuzhiyun goto failed;
3791*4882a593Smuzhiyun }
3792*4882a593Smuzhiyun
3793*4882a593Smuzhiyun if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3794*4882a593Smuzhiyun /* Disable SRAM, Instruction RAM and GP RAM parity. */
3795*4882a593Smuzhiyun spin_lock_irqsave(&ha->hardware_lock, flags);
3796*4882a593Smuzhiyun wrt_reg_word(®->hccr, (HCCR_ENABLE_PARITY + 0x0));
3797*4882a593Smuzhiyun rd_reg_word(®->hccr);
3798*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->hardware_lock, flags);
3799*4882a593Smuzhiyun }
3800*4882a593Smuzhiyun
3801*4882a593Smuzhiyun qla81xx_mpi_sync(vha);
3802*4882a593Smuzhiyun
3803*4882a593Smuzhiyun execute_fw_with_lr:
3804*4882a593Smuzhiyun /* Load firmware sequences */
3805*4882a593Smuzhiyun rval = ha->isp_ops->load_risc(vha, &srisc_address);
3806*4882a593Smuzhiyun if (rval == QLA_SUCCESS) {
3807*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x00c9,
3808*4882a593Smuzhiyun "Verifying Checksum of loaded RISC code.\n");
3809*4882a593Smuzhiyun
3810*4882a593Smuzhiyun rval = qla2x00_verify_checksum(vha, srisc_address);
3811*4882a593Smuzhiyun if (rval == QLA_SUCCESS) {
3812*4882a593Smuzhiyun /* Start firmware execution. */
3813*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x00ca,
3814*4882a593Smuzhiyun "Starting firmware.\n");
3815*4882a593Smuzhiyun
3816*4882a593Smuzhiyun if (ql2xexlogins)
3817*4882a593Smuzhiyun ha->flags.exlogins_enabled = 1;
3818*4882a593Smuzhiyun
3819*4882a593Smuzhiyun if (qla_is_exch_offld_enabled(vha))
3820*4882a593Smuzhiyun ha->flags.exchoffld_enabled = 1;
3821*4882a593Smuzhiyun
3822*4882a593Smuzhiyun rval = qla2x00_execute_fw(vha, srisc_address);
3823*4882a593Smuzhiyun /* Retrieve firmware information. */
3824*4882a593Smuzhiyun if (rval == QLA_SUCCESS) {
3825*4882a593Smuzhiyun /* Enable BPM support? */
3826*4882a593Smuzhiyun if (!done_once++ && qla24xx_detect_sfp(vha)) {
3827*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x00ca,
3828*4882a593Smuzhiyun "Re-starting firmware -- BPM.\n");
3829*4882a593Smuzhiyun /* Best-effort - re-init. */
3830*4882a593Smuzhiyun ha->isp_ops->reset_chip(vha);
3831*4882a593Smuzhiyun ha->isp_ops->chip_diag(vha);
3832*4882a593Smuzhiyun goto execute_fw_with_lr;
3833*4882a593Smuzhiyun }
3834*4882a593Smuzhiyun
3835*4882a593Smuzhiyun if (IS_ZIO_THRESHOLD_CAPABLE(ha))
3836*4882a593Smuzhiyun qla27xx_set_zio_threshold(vha,
3837*4882a593Smuzhiyun ha->last_zio_threshold);
3838*4882a593Smuzhiyun
3839*4882a593Smuzhiyun rval = qla2x00_set_exlogins_buffer(vha);
3840*4882a593Smuzhiyun if (rval != QLA_SUCCESS)
3841*4882a593Smuzhiyun goto failed;
3842*4882a593Smuzhiyun
3843*4882a593Smuzhiyun rval = qla2x00_set_exchoffld_buffer(vha);
3844*4882a593Smuzhiyun if (rval != QLA_SUCCESS)
3845*4882a593Smuzhiyun goto failed;
3846*4882a593Smuzhiyun
3847*4882a593Smuzhiyun enable_82xx_npiv:
3848*4882a593Smuzhiyun fw_major_version = ha->fw_major_version;
3849*4882a593Smuzhiyun if (IS_P3P_TYPE(ha))
3850*4882a593Smuzhiyun qla82xx_check_md_needed(vha);
3851*4882a593Smuzhiyun else
3852*4882a593Smuzhiyun rval = qla2x00_get_fw_version(vha);
3853*4882a593Smuzhiyun if (rval != QLA_SUCCESS)
3854*4882a593Smuzhiyun goto failed;
3855*4882a593Smuzhiyun ha->flags.npiv_supported = 0;
3856*4882a593Smuzhiyun if (IS_QLA2XXX_MIDTYPE(ha) &&
3857*4882a593Smuzhiyun (ha->fw_attributes & BIT_2)) {
3858*4882a593Smuzhiyun ha->flags.npiv_supported = 1;
3859*4882a593Smuzhiyun if ((!ha->max_npiv_vports) ||
3860*4882a593Smuzhiyun ((ha->max_npiv_vports + 1) %
3861*4882a593Smuzhiyun MIN_MULTI_ID_FABRIC))
3862*4882a593Smuzhiyun ha->max_npiv_vports =
3863*4882a593Smuzhiyun MIN_MULTI_ID_FABRIC - 1;
3864*4882a593Smuzhiyun }
3865*4882a593Smuzhiyun qla2x00_get_resource_cnts(vha);
3866*4882a593Smuzhiyun qla_init_iocb_limit(vha);
3867*4882a593Smuzhiyun
3868*4882a593Smuzhiyun /*
3869*4882a593Smuzhiyun * Allocate the array of outstanding commands
3870*4882a593Smuzhiyun * now that we know the firmware resources.
3871*4882a593Smuzhiyun */
3872*4882a593Smuzhiyun rval = qla2x00_alloc_outstanding_cmds(ha,
3873*4882a593Smuzhiyun vha->req);
3874*4882a593Smuzhiyun if (rval != QLA_SUCCESS)
3875*4882a593Smuzhiyun goto failed;
3876*4882a593Smuzhiyun
3877*4882a593Smuzhiyun if (!fw_major_version && !(IS_P3P_TYPE(ha)))
3878*4882a593Smuzhiyun qla2x00_alloc_offload_mem(vha);
3879*4882a593Smuzhiyun
3880*4882a593Smuzhiyun if (ql2xallocfwdump && !(IS_P3P_TYPE(ha)))
3881*4882a593Smuzhiyun qla2x00_alloc_fw_dump(vha);
3882*4882a593Smuzhiyun
3883*4882a593Smuzhiyun } else {
3884*4882a593Smuzhiyun goto failed;
3885*4882a593Smuzhiyun }
3886*4882a593Smuzhiyun } else {
3887*4882a593Smuzhiyun ql_log(ql_log_fatal, vha, 0x00cd,
3888*4882a593Smuzhiyun "ISP Firmware failed checksum.\n");
3889*4882a593Smuzhiyun goto failed;
3890*4882a593Smuzhiyun }
3891*4882a593Smuzhiyun
3892*4882a593Smuzhiyun /* Enable PUREX PASSTHRU */
3893*4882a593Smuzhiyun if (ql2xrdpenable || ha->flags.scm_supported_f)
3894*4882a593Smuzhiyun qla25xx_set_els_cmds_supported(vha);
3895*4882a593Smuzhiyun } else
3896*4882a593Smuzhiyun goto failed;
3897*4882a593Smuzhiyun
3898*4882a593Smuzhiyun if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3899*4882a593Smuzhiyun /* Enable proper parity. */
3900*4882a593Smuzhiyun spin_lock_irqsave(&ha->hardware_lock, flags);
3901*4882a593Smuzhiyun if (IS_QLA2300(ha))
3902*4882a593Smuzhiyun /* SRAM parity */
3903*4882a593Smuzhiyun wrt_reg_word(®->hccr, HCCR_ENABLE_PARITY + 0x1);
3904*4882a593Smuzhiyun else
3905*4882a593Smuzhiyun /* SRAM, Instruction RAM and GP RAM parity */
3906*4882a593Smuzhiyun wrt_reg_word(®->hccr, HCCR_ENABLE_PARITY + 0x7);
3907*4882a593Smuzhiyun rd_reg_word(®->hccr);
3908*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->hardware_lock, flags);
3909*4882a593Smuzhiyun }
3910*4882a593Smuzhiyun
3911*4882a593Smuzhiyun if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
3912*4882a593Smuzhiyun ha->flags.fac_supported = 1;
3913*4882a593Smuzhiyun else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
3914*4882a593Smuzhiyun uint32_t size;
3915*4882a593Smuzhiyun
3916*4882a593Smuzhiyun rval = qla81xx_fac_get_sector_size(vha, &size);
3917*4882a593Smuzhiyun if (rval == QLA_SUCCESS) {
3918*4882a593Smuzhiyun ha->flags.fac_supported = 1;
3919*4882a593Smuzhiyun ha->fdt_block_size = size << 2;
3920*4882a593Smuzhiyun } else {
3921*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x00ce,
3922*4882a593Smuzhiyun "Unsupported FAC firmware (%d.%02d.%02d).\n",
3923*4882a593Smuzhiyun ha->fw_major_version, ha->fw_minor_version,
3924*4882a593Smuzhiyun ha->fw_subminor_version);
3925*4882a593Smuzhiyun
3926*4882a593Smuzhiyun if (IS_QLA83XX(ha)) {
3927*4882a593Smuzhiyun ha->flags.fac_supported = 0;
3928*4882a593Smuzhiyun rval = QLA_SUCCESS;
3929*4882a593Smuzhiyun }
3930*4882a593Smuzhiyun }
3931*4882a593Smuzhiyun }
3932*4882a593Smuzhiyun failed:
3933*4882a593Smuzhiyun if (rval) {
3934*4882a593Smuzhiyun ql_log(ql_log_fatal, vha, 0x00cf,
3935*4882a593Smuzhiyun "Setup chip ****FAILED****.\n");
3936*4882a593Smuzhiyun }
3937*4882a593Smuzhiyun
3938*4882a593Smuzhiyun return (rval);
3939*4882a593Smuzhiyun }
3940*4882a593Smuzhiyun
3941*4882a593Smuzhiyun /**
3942*4882a593Smuzhiyun * qla2x00_init_response_q_entries() - Initializes response queue entries.
3943*4882a593Smuzhiyun * @rsp: response queue
3944*4882a593Smuzhiyun *
3945*4882a593Smuzhiyun * Beginning of request ring has initialization control block already built
3946*4882a593Smuzhiyun * by nvram config routine.
3947*4882a593Smuzhiyun *
3948*4882a593Smuzhiyun * Returns 0 on success.
3949*4882a593Smuzhiyun */
3950*4882a593Smuzhiyun void
qla2x00_init_response_q_entries(struct rsp_que * rsp)3951*4882a593Smuzhiyun qla2x00_init_response_q_entries(struct rsp_que *rsp)
3952*4882a593Smuzhiyun {
3953*4882a593Smuzhiyun uint16_t cnt;
3954*4882a593Smuzhiyun response_t *pkt;
3955*4882a593Smuzhiyun
3956*4882a593Smuzhiyun rsp->ring_ptr = rsp->ring;
3957*4882a593Smuzhiyun rsp->ring_index = 0;
3958*4882a593Smuzhiyun rsp->status_srb = NULL;
3959*4882a593Smuzhiyun pkt = rsp->ring_ptr;
3960*4882a593Smuzhiyun for (cnt = 0; cnt < rsp->length; cnt++) {
3961*4882a593Smuzhiyun pkt->signature = RESPONSE_PROCESSED;
3962*4882a593Smuzhiyun pkt++;
3963*4882a593Smuzhiyun }
3964*4882a593Smuzhiyun }
3965*4882a593Smuzhiyun
3966*4882a593Smuzhiyun /**
3967*4882a593Smuzhiyun * qla2x00_update_fw_options() - Read and process firmware options.
3968*4882a593Smuzhiyun * @vha: HA context
3969*4882a593Smuzhiyun *
3970*4882a593Smuzhiyun * Returns 0 on success.
3971*4882a593Smuzhiyun */
3972*4882a593Smuzhiyun void
qla2x00_update_fw_options(scsi_qla_host_t * vha)3973*4882a593Smuzhiyun qla2x00_update_fw_options(scsi_qla_host_t *vha)
3974*4882a593Smuzhiyun {
3975*4882a593Smuzhiyun uint16_t swing, emphasis, tx_sens, rx_sens;
3976*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
3977*4882a593Smuzhiyun
3978*4882a593Smuzhiyun memset(ha->fw_options, 0, sizeof(ha->fw_options));
3979*4882a593Smuzhiyun qla2x00_get_fw_options(vha, ha->fw_options);
3980*4882a593Smuzhiyun
3981*4882a593Smuzhiyun if (IS_QLA2100(ha) || IS_QLA2200(ha))
3982*4882a593Smuzhiyun return;
3983*4882a593Smuzhiyun
3984*4882a593Smuzhiyun /* Serial Link options. */
3985*4882a593Smuzhiyun ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
3986*4882a593Smuzhiyun "Serial link options.\n");
3987*4882a593Smuzhiyun ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
3988*4882a593Smuzhiyun ha->fw_seriallink_options, sizeof(ha->fw_seriallink_options));
3989*4882a593Smuzhiyun
3990*4882a593Smuzhiyun ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
3991*4882a593Smuzhiyun if (ha->fw_seriallink_options[3] & BIT_2) {
3992*4882a593Smuzhiyun ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
3993*4882a593Smuzhiyun
3994*4882a593Smuzhiyun /* 1G settings */
3995*4882a593Smuzhiyun swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
3996*4882a593Smuzhiyun emphasis = (ha->fw_seriallink_options[2] &
3997*4882a593Smuzhiyun (BIT_4 | BIT_3)) >> 3;
3998*4882a593Smuzhiyun tx_sens = ha->fw_seriallink_options[0] &
3999*4882a593Smuzhiyun (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4000*4882a593Smuzhiyun rx_sens = (ha->fw_seriallink_options[0] &
4001*4882a593Smuzhiyun (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
4002*4882a593Smuzhiyun ha->fw_options[10] = (emphasis << 14) | (swing << 8);
4003*4882a593Smuzhiyun if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
4004*4882a593Smuzhiyun if (rx_sens == 0x0)
4005*4882a593Smuzhiyun rx_sens = 0x3;
4006*4882a593Smuzhiyun ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
4007*4882a593Smuzhiyun } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
4008*4882a593Smuzhiyun ha->fw_options[10] |= BIT_5 |
4009*4882a593Smuzhiyun ((rx_sens & (BIT_1 | BIT_0)) << 2) |
4010*4882a593Smuzhiyun (tx_sens & (BIT_1 | BIT_0));
4011*4882a593Smuzhiyun
4012*4882a593Smuzhiyun /* 2G settings */
4013*4882a593Smuzhiyun swing = (ha->fw_seriallink_options[2] &
4014*4882a593Smuzhiyun (BIT_7 | BIT_6 | BIT_5)) >> 5;
4015*4882a593Smuzhiyun emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
4016*4882a593Smuzhiyun tx_sens = ha->fw_seriallink_options[1] &
4017*4882a593Smuzhiyun (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4018*4882a593Smuzhiyun rx_sens = (ha->fw_seriallink_options[1] &
4019*4882a593Smuzhiyun (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
4020*4882a593Smuzhiyun ha->fw_options[11] = (emphasis << 14) | (swing << 8);
4021*4882a593Smuzhiyun if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
4022*4882a593Smuzhiyun if (rx_sens == 0x0)
4023*4882a593Smuzhiyun rx_sens = 0x3;
4024*4882a593Smuzhiyun ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
4025*4882a593Smuzhiyun } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
4026*4882a593Smuzhiyun ha->fw_options[11] |= BIT_5 |
4027*4882a593Smuzhiyun ((rx_sens & (BIT_1 | BIT_0)) << 2) |
4028*4882a593Smuzhiyun (tx_sens & (BIT_1 | BIT_0));
4029*4882a593Smuzhiyun }
4030*4882a593Smuzhiyun
4031*4882a593Smuzhiyun /* FCP2 options. */
4032*4882a593Smuzhiyun /* Return command IOCBs without waiting for an ABTS to complete. */
4033*4882a593Smuzhiyun ha->fw_options[3] |= BIT_13;
4034*4882a593Smuzhiyun
4035*4882a593Smuzhiyun /* LED scheme. */
4036*4882a593Smuzhiyun if (ha->flags.enable_led_scheme)
4037*4882a593Smuzhiyun ha->fw_options[2] |= BIT_12;
4038*4882a593Smuzhiyun
4039*4882a593Smuzhiyun /* Detect ISP6312. */
4040*4882a593Smuzhiyun if (IS_QLA6312(ha))
4041*4882a593Smuzhiyun ha->fw_options[2] |= BIT_13;
4042*4882a593Smuzhiyun
4043*4882a593Smuzhiyun /* Set Retry FLOGI in case of P2P connection */
4044*4882a593Smuzhiyun if (ha->operating_mode == P2P) {
4045*4882a593Smuzhiyun ha->fw_options[2] |= BIT_3;
4046*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2100,
4047*4882a593Smuzhiyun "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
4048*4882a593Smuzhiyun __func__, ha->fw_options[2]);
4049*4882a593Smuzhiyun }
4050*4882a593Smuzhiyun
4051*4882a593Smuzhiyun /* Update firmware options. */
4052*4882a593Smuzhiyun qla2x00_set_fw_options(vha, ha->fw_options);
4053*4882a593Smuzhiyun }
4054*4882a593Smuzhiyun
4055*4882a593Smuzhiyun void
qla24xx_update_fw_options(scsi_qla_host_t * vha)4056*4882a593Smuzhiyun qla24xx_update_fw_options(scsi_qla_host_t *vha)
4057*4882a593Smuzhiyun {
4058*4882a593Smuzhiyun int rval;
4059*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
4060*4882a593Smuzhiyun
4061*4882a593Smuzhiyun if (IS_P3P_TYPE(ha))
4062*4882a593Smuzhiyun return;
4063*4882a593Smuzhiyun
4064*4882a593Smuzhiyun /* Hold status IOCBs until ABTS response received. */
4065*4882a593Smuzhiyun if (ql2xfwholdabts)
4066*4882a593Smuzhiyun ha->fw_options[3] |= BIT_12;
4067*4882a593Smuzhiyun
4068*4882a593Smuzhiyun /* Set Retry FLOGI in case of P2P connection */
4069*4882a593Smuzhiyun if (ha->operating_mode == P2P) {
4070*4882a593Smuzhiyun ha->fw_options[2] |= BIT_3;
4071*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2101,
4072*4882a593Smuzhiyun "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
4073*4882a593Smuzhiyun __func__, ha->fw_options[2]);
4074*4882a593Smuzhiyun }
4075*4882a593Smuzhiyun
4076*4882a593Smuzhiyun /* Move PUREX, ABTS RX & RIDA to ATIOQ */
4077*4882a593Smuzhiyun if (ql2xmvasynctoatio &&
4078*4882a593Smuzhiyun (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) {
4079*4882a593Smuzhiyun if (qla_tgt_mode_enabled(vha) ||
4080*4882a593Smuzhiyun qla_dual_mode_enabled(vha))
4081*4882a593Smuzhiyun ha->fw_options[2] |= BIT_11;
4082*4882a593Smuzhiyun else
4083*4882a593Smuzhiyun ha->fw_options[2] &= ~BIT_11;
4084*4882a593Smuzhiyun }
4085*4882a593Smuzhiyun
4086*4882a593Smuzhiyun if (IS_QLA25XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
4087*4882a593Smuzhiyun IS_QLA28XX(ha)) {
4088*4882a593Smuzhiyun /*
4089*4882a593Smuzhiyun * Tell FW to track each exchange to prevent
4090*4882a593Smuzhiyun * driver from using stale exchange.
4091*4882a593Smuzhiyun */
4092*4882a593Smuzhiyun if (qla_tgt_mode_enabled(vha) ||
4093*4882a593Smuzhiyun qla_dual_mode_enabled(vha))
4094*4882a593Smuzhiyun ha->fw_options[2] |= BIT_4;
4095*4882a593Smuzhiyun else
4096*4882a593Smuzhiyun ha->fw_options[2] &= ~BIT_4;
4097*4882a593Smuzhiyun
4098*4882a593Smuzhiyun /* Reserve 1/2 of emergency exchanges for ELS.*/
4099*4882a593Smuzhiyun if (qla2xuseresexchforels)
4100*4882a593Smuzhiyun ha->fw_options[2] |= BIT_8;
4101*4882a593Smuzhiyun else
4102*4882a593Smuzhiyun ha->fw_options[2] &= ~BIT_8;
4103*4882a593Smuzhiyun }
4104*4882a593Smuzhiyun
4105*4882a593Smuzhiyun if (ql2xrdpenable || ha->flags.scm_supported_f)
4106*4882a593Smuzhiyun ha->fw_options[1] |= ADD_FO1_ENABLE_PUREX_IOCB;
4107*4882a593Smuzhiyun
4108*4882a593Smuzhiyun /* Enable Async 8130/8131 events -- transceiver insertion/removal */
4109*4882a593Smuzhiyun if (IS_BPM_RANGE_CAPABLE(ha))
4110*4882a593Smuzhiyun ha->fw_options[3] |= BIT_10;
4111*4882a593Smuzhiyun
4112*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x00e8,
4113*4882a593Smuzhiyun "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
4114*4882a593Smuzhiyun __func__, ha->fw_options[1], ha->fw_options[2],
4115*4882a593Smuzhiyun ha->fw_options[3], vha->host->active_mode);
4116*4882a593Smuzhiyun
4117*4882a593Smuzhiyun if (ha->fw_options[1] || ha->fw_options[2] || ha->fw_options[3])
4118*4882a593Smuzhiyun qla2x00_set_fw_options(vha, ha->fw_options);
4119*4882a593Smuzhiyun
4120*4882a593Smuzhiyun /* Update Serial Link options. */
4121*4882a593Smuzhiyun if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
4122*4882a593Smuzhiyun return;
4123*4882a593Smuzhiyun
4124*4882a593Smuzhiyun rval = qla2x00_set_serdes_params(vha,
4125*4882a593Smuzhiyun le16_to_cpu(ha->fw_seriallink_options24[1]),
4126*4882a593Smuzhiyun le16_to_cpu(ha->fw_seriallink_options24[2]),
4127*4882a593Smuzhiyun le16_to_cpu(ha->fw_seriallink_options24[3]));
4128*4882a593Smuzhiyun if (rval != QLA_SUCCESS) {
4129*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0104,
4130*4882a593Smuzhiyun "Unable to update Serial Link options (%x).\n", rval);
4131*4882a593Smuzhiyun }
4132*4882a593Smuzhiyun }
4133*4882a593Smuzhiyun
4134*4882a593Smuzhiyun void
qla2x00_config_rings(struct scsi_qla_host * vha)4135*4882a593Smuzhiyun qla2x00_config_rings(struct scsi_qla_host *vha)
4136*4882a593Smuzhiyun {
4137*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
4138*4882a593Smuzhiyun struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4139*4882a593Smuzhiyun struct req_que *req = ha->req_q_map[0];
4140*4882a593Smuzhiyun struct rsp_que *rsp = ha->rsp_q_map[0];
4141*4882a593Smuzhiyun
4142*4882a593Smuzhiyun /* Setup ring parameters in initialization control block. */
4143*4882a593Smuzhiyun ha->init_cb->request_q_outpointer = cpu_to_le16(0);
4144*4882a593Smuzhiyun ha->init_cb->response_q_inpointer = cpu_to_le16(0);
4145*4882a593Smuzhiyun ha->init_cb->request_q_length = cpu_to_le16(req->length);
4146*4882a593Smuzhiyun ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
4147*4882a593Smuzhiyun put_unaligned_le64(req->dma, &ha->init_cb->request_q_address);
4148*4882a593Smuzhiyun put_unaligned_le64(rsp->dma, &ha->init_cb->response_q_address);
4149*4882a593Smuzhiyun
4150*4882a593Smuzhiyun wrt_reg_word(ISP_REQ_Q_IN(ha, reg), 0);
4151*4882a593Smuzhiyun wrt_reg_word(ISP_REQ_Q_OUT(ha, reg), 0);
4152*4882a593Smuzhiyun wrt_reg_word(ISP_RSP_Q_IN(ha, reg), 0);
4153*4882a593Smuzhiyun wrt_reg_word(ISP_RSP_Q_OUT(ha, reg), 0);
4154*4882a593Smuzhiyun rd_reg_word(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
4155*4882a593Smuzhiyun }
4156*4882a593Smuzhiyun
4157*4882a593Smuzhiyun void
qla24xx_config_rings(struct scsi_qla_host * vha)4158*4882a593Smuzhiyun qla24xx_config_rings(struct scsi_qla_host *vha)
4159*4882a593Smuzhiyun {
4160*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
4161*4882a593Smuzhiyun device_reg_t *reg = ISP_QUE_REG(ha, 0);
4162*4882a593Smuzhiyun struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
4163*4882a593Smuzhiyun struct qla_msix_entry *msix;
4164*4882a593Smuzhiyun struct init_cb_24xx *icb;
4165*4882a593Smuzhiyun uint16_t rid = 0;
4166*4882a593Smuzhiyun struct req_que *req = ha->req_q_map[0];
4167*4882a593Smuzhiyun struct rsp_que *rsp = ha->rsp_q_map[0];
4168*4882a593Smuzhiyun
4169*4882a593Smuzhiyun /* Setup ring parameters in initialization control block. */
4170*4882a593Smuzhiyun icb = (struct init_cb_24xx *)ha->init_cb;
4171*4882a593Smuzhiyun icb->request_q_outpointer = cpu_to_le16(0);
4172*4882a593Smuzhiyun icb->response_q_inpointer = cpu_to_le16(0);
4173*4882a593Smuzhiyun icb->request_q_length = cpu_to_le16(req->length);
4174*4882a593Smuzhiyun icb->response_q_length = cpu_to_le16(rsp->length);
4175*4882a593Smuzhiyun put_unaligned_le64(req->dma, &icb->request_q_address);
4176*4882a593Smuzhiyun put_unaligned_le64(rsp->dma, &icb->response_q_address);
4177*4882a593Smuzhiyun
4178*4882a593Smuzhiyun /* Setup ATIO queue dma pointers for target mode */
4179*4882a593Smuzhiyun icb->atio_q_inpointer = cpu_to_le16(0);
4180*4882a593Smuzhiyun icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
4181*4882a593Smuzhiyun put_unaligned_le64(ha->tgt.atio_dma, &icb->atio_q_address);
4182*4882a593Smuzhiyun
4183*4882a593Smuzhiyun if (IS_SHADOW_REG_CAPABLE(ha))
4184*4882a593Smuzhiyun icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29);
4185*4882a593Smuzhiyun
4186*4882a593Smuzhiyun if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
4187*4882a593Smuzhiyun IS_QLA28XX(ha)) {
4188*4882a593Smuzhiyun icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS);
4189*4882a593Smuzhiyun icb->rid = cpu_to_le16(rid);
4190*4882a593Smuzhiyun if (ha->flags.msix_enabled) {
4191*4882a593Smuzhiyun msix = &ha->msix_entries[1];
4192*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0019,
4193*4882a593Smuzhiyun "Registering vector 0x%x for base que.\n",
4194*4882a593Smuzhiyun msix->entry);
4195*4882a593Smuzhiyun icb->msix = cpu_to_le16(msix->entry);
4196*4882a593Smuzhiyun }
4197*4882a593Smuzhiyun /* Use alternate PCI bus number */
4198*4882a593Smuzhiyun if (MSB(rid))
4199*4882a593Smuzhiyun icb->firmware_options_2 |= cpu_to_le32(BIT_19);
4200*4882a593Smuzhiyun /* Use alternate PCI devfn */
4201*4882a593Smuzhiyun if (LSB(rid))
4202*4882a593Smuzhiyun icb->firmware_options_2 |= cpu_to_le32(BIT_18);
4203*4882a593Smuzhiyun
4204*4882a593Smuzhiyun /* Use Disable MSIX Handshake mode for capable adapters */
4205*4882a593Smuzhiyun if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
4206*4882a593Smuzhiyun (ha->flags.msix_enabled)) {
4207*4882a593Smuzhiyun icb->firmware_options_2 &= cpu_to_le32(~BIT_22);
4208*4882a593Smuzhiyun ha->flags.disable_msix_handshake = 1;
4209*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x00fe,
4210*4882a593Smuzhiyun "MSIX Handshake Disable Mode turned on.\n");
4211*4882a593Smuzhiyun } else {
4212*4882a593Smuzhiyun icb->firmware_options_2 |= cpu_to_le32(BIT_22);
4213*4882a593Smuzhiyun }
4214*4882a593Smuzhiyun icb->firmware_options_2 |= cpu_to_le32(BIT_23);
4215*4882a593Smuzhiyun
4216*4882a593Smuzhiyun wrt_reg_dword(®->isp25mq.req_q_in, 0);
4217*4882a593Smuzhiyun wrt_reg_dword(®->isp25mq.req_q_out, 0);
4218*4882a593Smuzhiyun wrt_reg_dword(®->isp25mq.rsp_q_in, 0);
4219*4882a593Smuzhiyun wrt_reg_dword(®->isp25mq.rsp_q_out, 0);
4220*4882a593Smuzhiyun } else {
4221*4882a593Smuzhiyun wrt_reg_dword(®->isp24.req_q_in, 0);
4222*4882a593Smuzhiyun wrt_reg_dword(®->isp24.req_q_out, 0);
4223*4882a593Smuzhiyun wrt_reg_dword(®->isp24.rsp_q_in, 0);
4224*4882a593Smuzhiyun wrt_reg_dword(®->isp24.rsp_q_out, 0);
4225*4882a593Smuzhiyun }
4226*4882a593Smuzhiyun
4227*4882a593Smuzhiyun qlt_24xx_config_rings(vha);
4228*4882a593Smuzhiyun
4229*4882a593Smuzhiyun /* If the user has configured the speed, set it here */
4230*4882a593Smuzhiyun if (ha->set_data_rate) {
4231*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x00fd,
4232*4882a593Smuzhiyun "Speed set by user : %s Gbps \n",
4233*4882a593Smuzhiyun qla2x00_get_link_speed_str(ha, ha->set_data_rate));
4234*4882a593Smuzhiyun icb->firmware_options_3 = cpu_to_le32(ha->set_data_rate << 13);
4235*4882a593Smuzhiyun }
4236*4882a593Smuzhiyun
4237*4882a593Smuzhiyun /* PCI posting */
4238*4882a593Smuzhiyun rd_reg_word(&ioreg->hccr);
4239*4882a593Smuzhiyun }
4240*4882a593Smuzhiyun
4241*4882a593Smuzhiyun /**
4242*4882a593Smuzhiyun * qla2x00_init_rings() - Initializes firmware.
4243*4882a593Smuzhiyun * @vha: HA context
4244*4882a593Smuzhiyun *
4245*4882a593Smuzhiyun * Beginning of request ring has initialization control block already built
4246*4882a593Smuzhiyun * by nvram config routine.
4247*4882a593Smuzhiyun *
4248*4882a593Smuzhiyun * Returns 0 on success.
4249*4882a593Smuzhiyun */
4250*4882a593Smuzhiyun int
qla2x00_init_rings(scsi_qla_host_t * vha)4251*4882a593Smuzhiyun qla2x00_init_rings(scsi_qla_host_t *vha)
4252*4882a593Smuzhiyun {
4253*4882a593Smuzhiyun int rval;
4254*4882a593Smuzhiyun unsigned long flags = 0;
4255*4882a593Smuzhiyun int cnt, que;
4256*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
4257*4882a593Smuzhiyun struct req_que *req;
4258*4882a593Smuzhiyun struct rsp_que *rsp;
4259*4882a593Smuzhiyun struct mid_init_cb_24xx *mid_init_cb =
4260*4882a593Smuzhiyun (struct mid_init_cb_24xx *) ha->init_cb;
4261*4882a593Smuzhiyun
4262*4882a593Smuzhiyun spin_lock_irqsave(&ha->hardware_lock, flags);
4263*4882a593Smuzhiyun
4264*4882a593Smuzhiyun /* Clear outstanding commands array. */
4265*4882a593Smuzhiyun for (que = 0; que < ha->max_req_queues; que++) {
4266*4882a593Smuzhiyun req = ha->req_q_map[que];
4267*4882a593Smuzhiyun if (!req || !test_bit(que, ha->req_qid_map))
4268*4882a593Smuzhiyun continue;
4269*4882a593Smuzhiyun req->out_ptr = (uint16_t *)(req->ring + req->length);
4270*4882a593Smuzhiyun *req->out_ptr = 0;
4271*4882a593Smuzhiyun for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
4272*4882a593Smuzhiyun req->outstanding_cmds[cnt] = NULL;
4273*4882a593Smuzhiyun
4274*4882a593Smuzhiyun req->current_outstanding_cmd = 1;
4275*4882a593Smuzhiyun
4276*4882a593Smuzhiyun /* Initialize firmware. */
4277*4882a593Smuzhiyun req->ring_ptr = req->ring;
4278*4882a593Smuzhiyun req->ring_index = 0;
4279*4882a593Smuzhiyun req->cnt = req->length;
4280*4882a593Smuzhiyun }
4281*4882a593Smuzhiyun
4282*4882a593Smuzhiyun for (que = 0; que < ha->max_rsp_queues; que++) {
4283*4882a593Smuzhiyun rsp = ha->rsp_q_map[que];
4284*4882a593Smuzhiyun if (!rsp || !test_bit(que, ha->rsp_qid_map))
4285*4882a593Smuzhiyun continue;
4286*4882a593Smuzhiyun rsp->in_ptr = (uint16_t *)(rsp->ring + rsp->length);
4287*4882a593Smuzhiyun *rsp->in_ptr = 0;
4288*4882a593Smuzhiyun /* Initialize response queue entries */
4289*4882a593Smuzhiyun if (IS_QLAFX00(ha))
4290*4882a593Smuzhiyun qlafx00_init_response_q_entries(rsp);
4291*4882a593Smuzhiyun else
4292*4882a593Smuzhiyun qla2x00_init_response_q_entries(rsp);
4293*4882a593Smuzhiyun }
4294*4882a593Smuzhiyun
4295*4882a593Smuzhiyun ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
4296*4882a593Smuzhiyun ha->tgt.atio_ring_index = 0;
4297*4882a593Smuzhiyun /* Initialize ATIO queue entries */
4298*4882a593Smuzhiyun qlt_init_atio_q_entries(vha);
4299*4882a593Smuzhiyun
4300*4882a593Smuzhiyun ha->isp_ops->config_rings(vha);
4301*4882a593Smuzhiyun
4302*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->hardware_lock, flags);
4303*4882a593Smuzhiyun
4304*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
4305*4882a593Smuzhiyun
4306*4882a593Smuzhiyun if (IS_QLAFX00(ha)) {
4307*4882a593Smuzhiyun rval = qlafx00_init_firmware(vha, ha->init_cb_size);
4308*4882a593Smuzhiyun goto next_check;
4309*4882a593Smuzhiyun }
4310*4882a593Smuzhiyun
4311*4882a593Smuzhiyun /* Update any ISP specific firmware options before initialization. */
4312*4882a593Smuzhiyun ha->isp_ops->update_fw_options(vha);
4313*4882a593Smuzhiyun
4314*4882a593Smuzhiyun if (ha->flags.npiv_supported) {
4315*4882a593Smuzhiyun if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
4316*4882a593Smuzhiyun ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
4317*4882a593Smuzhiyun mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
4318*4882a593Smuzhiyun }
4319*4882a593Smuzhiyun
4320*4882a593Smuzhiyun if (IS_FWI2_CAPABLE(ha)) {
4321*4882a593Smuzhiyun mid_init_cb->options = cpu_to_le16(BIT_1);
4322*4882a593Smuzhiyun mid_init_cb->init_cb.execution_throttle =
4323*4882a593Smuzhiyun cpu_to_le16(ha->cur_fw_xcb_count);
4324*4882a593Smuzhiyun ha->flags.dport_enabled =
4325*4882a593Smuzhiyun (le32_to_cpu(mid_init_cb->init_cb.firmware_options_1) &
4326*4882a593Smuzhiyun BIT_7) != 0;
4327*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n",
4328*4882a593Smuzhiyun (ha->flags.dport_enabled) ? "enabled" : "disabled");
4329*4882a593Smuzhiyun /* FA-WWPN Status */
4330*4882a593Smuzhiyun ha->flags.fawwpn_enabled =
4331*4882a593Smuzhiyun (le32_to_cpu(mid_init_cb->init_cb.firmware_options_1) &
4332*4882a593Smuzhiyun BIT_6) != 0;
4333*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x00bc, "FA-WWPN Support: %s.\n",
4334*4882a593Smuzhiyun (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
4335*4882a593Smuzhiyun /* Init_cb will be reused for other command(s). Save a backup copy of port_name */
4336*4882a593Smuzhiyun memcpy(ha->port_name, ha->init_cb->port_name, WWN_SIZE);
4337*4882a593Smuzhiyun }
4338*4882a593Smuzhiyun
4339*4882a593Smuzhiyun rval = qla2x00_init_firmware(vha, ha->init_cb_size);
4340*4882a593Smuzhiyun next_check:
4341*4882a593Smuzhiyun if (rval) {
4342*4882a593Smuzhiyun ql_log(ql_log_fatal, vha, 0x00d2,
4343*4882a593Smuzhiyun "Init Firmware **** FAILED ****.\n");
4344*4882a593Smuzhiyun } else {
4345*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x00d3,
4346*4882a593Smuzhiyun "Init Firmware -- success.\n");
4347*4882a593Smuzhiyun QLA_FW_STARTED(ha);
4348*4882a593Smuzhiyun vha->u_ql2xexchoffld = vha->u_ql2xiniexchg = 0;
4349*4882a593Smuzhiyun }
4350*4882a593Smuzhiyun
4351*4882a593Smuzhiyun return (rval);
4352*4882a593Smuzhiyun }
4353*4882a593Smuzhiyun
4354*4882a593Smuzhiyun /**
4355*4882a593Smuzhiyun * qla2x00_fw_ready() - Waits for firmware ready.
4356*4882a593Smuzhiyun * @vha: HA context
4357*4882a593Smuzhiyun *
4358*4882a593Smuzhiyun * Returns 0 on success.
4359*4882a593Smuzhiyun */
4360*4882a593Smuzhiyun static int
qla2x00_fw_ready(scsi_qla_host_t * vha)4361*4882a593Smuzhiyun qla2x00_fw_ready(scsi_qla_host_t *vha)
4362*4882a593Smuzhiyun {
4363*4882a593Smuzhiyun int rval;
4364*4882a593Smuzhiyun unsigned long wtime, mtime, cs84xx_time;
4365*4882a593Smuzhiyun uint16_t min_wait; /* Minimum wait time if loop is down */
4366*4882a593Smuzhiyun uint16_t wait_time; /* Wait time if loop is coming ready */
4367*4882a593Smuzhiyun uint16_t state[6];
4368*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
4369*4882a593Smuzhiyun
4370*4882a593Smuzhiyun if (IS_QLAFX00(vha->hw))
4371*4882a593Smuzhiyun return qlafx00_fw_ready(vha);
4372*4882a593Smuzhiyun
4373*4882a593Smuzhiyun rval = QLA_SUCCESS;
4374*4882a593Smuzhiyun
4375*4882a593Smuzhiyun /* Time to wait for loop down */
4376*4882a593Smuzhiyun if (IS_P3P_TYPE(ha))
4377*4882a593Smuzhiyun min_wait = 30;
4378*4882a593Smuzhiyun else
4379*4882a593Smuzhiyun min_wait = 20;
4380*4882a593Smuzhiyun
4381*4882a593Smuzhiyun /*
4382*4882a593Smuzhiyun * Firmware should take at most one RATOV to login, plus 5 seconds for
4383*4882a593Smuzhiyun * our own processing.
4384*4882a593Smuzhiyun */
4385*4882a593Smuzhiyun if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
4386*4882a593Smuzhiyun wait_time = min_wait;
4387*4882a593Smuzhiyun }
4388*4882a593Smuzhiyun
4389*4882a593Smuzhiyun /* Min wait time if loop down */
4390*4882a593Smuzhiyun mtime = jiffies + (min_wait * HZ);
4391*4882a593Smuzhiyun
4392*4882a593Smuzhiyun /* wait time before firmware ready */
4393*4882a593Smuzhiyun wtime = jiffies + (wait_time * HZ);
4394*4882a593Smuzhiyun
4395*4882a593Smuzhiyun /* Wait for ISP to finish LIP */
4396*4882a593Smuzhiyun if (!vha->flags.init_done)
4397*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x801e,
4398*4882a593Smuzhiyun "Waiting for LIP to complete.\n");
4399*4882a593Smuzhiyun
4400*4882a593Smuzhiyun do {
4401*4882a593Smuzhiyun memset(state, -1, sizeof(state));
4402*4882a593Smuzhiyun rval = qla2x00_get_firmware_state(vha, state);
4403*4882a593Smuzhiyun if (rval == QLA_SUCCESS) {
4404*4882a593Smuzhiyun if (state[0] < FSTATE_LOSS_OF_SYNC) {
4405*4882a593Smuzhiyun vha->device_flags &= ~DFLG_NO_CABLE;
4406*4882a593Smuzhiyun }
4407*4882a593Smuzhiyun if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
4408*4882a593Smuzhiyun ql_dbg(ql_dbg_taskm, vha, 0x801f,
4409*4882a593Smuzhiyun "fw_state=%x 84xx=%x.\n", state[0],
4410*4882a593Smuzhiyun state[2]);
4411*4882a593Smuzhiyun if ((state[2] & FSTATE_LOGGED_IN) &&
4412*4882a593Smuzhiyun (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
4413*4882a593Smuzhiyun ql_dbg(ql_dbg_taskm, vha, 0x8028,
4414*4882a593Smuzhiyun "Sending verify iocb.\n");
4415*4882a593Smuzhiyun
4416*4882a593Smuzhiyun cs84xx_time = jiffies;
4417*4882a593Smuzhiyun rval = qla84xx_init_chip(vha);
4418*4882a593Smuzhiyun if (rval != QLA_SUCCESS) {
4419*4882a593Smuzhiyun ql_log(ql_log_warn,
4420*4882a593Smuzhiyun vha, 0x8007,
4421*4882a593Smuzhiyun "Init chip failed.\n");
4422*4882a593Smuzhiyun break;
4423*4882a593Smuzhiyun }
4424*4882a593Smuzhiyun
4425*4882a593Smuzhiyun /* Add time taken to initialize. */
4426*4882a593Smuzhiyun cs84xx_time = jiffies - cs84xx_time;
4427*4882a593Smuzhiyun wtime += cs84xx_time;
4428*4882a593Smuzhiyun mtime += cs84xx_time;
4429*4882a593Smuzhiyun ql_dbg(ql_dbg_taskm, vha, 0x8008,
4430*4882a593Smuzhiyun "Increasing wait time by %ld. "
4431*4882a593Smuzhiyun "New time %ld.\n", cs84xx_time,
4432*4882a593Smuzhiyun wtime);
4433*4882a593Smuzhiyun }
4434*4882a593Smuzhiyun } else if (state[0] == FSTATE_READY) {
4435*4882a593Smuzhiyun ql_dbg(ql_dbg_taskm, vha, 0x8037,
4436*4882a593Smuzhiyun "F/W Ready - OK.\n");
4437*4882a593Smuzhiyun
4438*4882a593Smuzhiyun qla2x00_get_retry_cnt(vha, &ha->retry_count,
4439*4882a593Smuzhiyun &ha->login_timeout, &ha->r_a_tov);
4440*4882a593Smuzhiyun
4441*4882a593Smuzhiyun rval = QLA_SUCCESS;
4442*4882a593Smuzhiyun break;
4443*4882a593Smuzhiyun }
4444*4882a593Smuzhiyun
4445*4882a593Smuzhiyun rval = QLA_FUNCTION_FAILED;
4446*4882a593Smuzhiyun
4447*4882a593Smuzhiyun if (atomic_read(&vha->loop_down_timer) &&
4448*4882a593Smuzhiyun state[0] != FSTATE_READY) {
4449*4882a593Smuzhiyun /* Loop down. Timeout on min_wait for states
4450*4882a593Smuzhiyun * other than Wait for Login.
4451*4882a593Smuzhiyun */
4452*4882a593Smuzhiyun if (time_after_eq(jiffies, mtime)) {
4453*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x8038,
4454*4882a593Smuzhiyun "Cable is unplugged...\n");
4455*4882a593Smuzhiyun
4456*4882a593Smuzhiyun vha->device_flags |= DFLG_NO_CABLE;
4457*4882a593Smuzhiyun break;
4458*4882a593Smuzhiyun }
4459*4882a593Smuzhiyun }
4460*4882a593Smuzhiyun } else {
4461*4882a593Smuzhiyun /* Mailbox cmd failed. Timeout on min_wait. */
4462*4882a593Smuzhiyun if (time_after_eq(jiffies, mtime) ||
4463*4882a593Smuzhiyun ha->flags.isp82xx_fw_hung)
4464*4882a593Smuzhiyun break;
4465*4882a593Smuzhiyun }
4466*4882a593Smuzhiyun
4467*4882a593Smuzhiyun if (time_after_eq(jiffies, wtime))
4468*4882a593Smuzhiyun break;
4469*4882a593Smuzhiyun
4470*4882a593Smuzhiyun /* Delay for a while */
4471*4882a593Smuzhiyun msleep(500);
4472*4882a593Smuzhiyun } while (1);
4473*4882a593Smuzhiyun
4474*4882a593Smuzhiyun ql_dbg(ql_dbg_taskm, vha, 0x803a,
4475*4882a593Smuzhiyun "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
4476*4882a593Smuzhiyun state[1], state[2], state[3], state[4], state[5], jiffies);
4477*4882a593Smuzhiyun
4478*4882a593Smuzhiyun if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
4479*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x803b,
4480*4882a593Smuzhiyun "Firmware ready **** FAILED ****.\n");
4481*4882a593Smuzhiyun }
4482*4882a593Smuzhiyun
4483*4882a593Smuzhiyun return (rval);
4484*4882a593Smuzhiyun }
4485*4882a593Smuzhiyun
4486*4882a593Smuzhiyun /*
4487*4882a593Smuzhiyun * qla2x00_configure_hba
4488*4882a593Smuzhiyun * Setup adapter context.
4489*4882a593Smuzhiyun *
4490*4882a593Smuzhiyun * Input:
4491*4882a593Smuzhiyun * ha = adapter state pointer.
4492*4882a593Smuzhiyun *
4493*4882a593Smuzhiyun * Returns:
4494*4882a593Smuzhiyun * 0 = success
4495*4882a593Smuzhiyun *
4496*4882a593Smuzhiyun * Context:
4497*4882a593Smuzhiyun * Kernel context.
4498*4882a593Smuzhiyun */
4499*4882a593Smuzhiyun static int
qla2x00_configure_hba(scsi_qla_host_t * vha)4500*4882a593Smuzhiyun qla2x00_configure_hba(scsi_qla_host_t *vha)
4501*4882a593Smuzhiyun {
4502*4882a593Smuzhiyun int rval;
4503*4882a593Smuzhiyun uint16_t loop_id;
4504*4882a593Smuzhiyun uint16_t topo;
4505*4882a593Smuzhiyun uint16_t sw_cap;
4506*4882a593Smuzhiyun uint8_t al_pa;
4507*4882a593Smuzhiyun uint8_t area;
4508*4882a593Smuzhiyun uint8_t domain;
4509*4882a593Smuzhiyun char connect_type[22];
4510*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
4511*4882a593Smuzhiyun scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4512*4882a593Smuzhiyun port_id_t id;
4513*4882a593Smuzhiyun unsigned long flags;
4514*4882a593Smuzhiyun
4515*4882a593Smuzhiyun /* Get host addresses. */
4516*4882a593Smuzhiyun rval = qla2x00_get_adapter_id(vha,
4517*4882a593Smuzhiyun &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
4518*4882a593Smuzhiyun if (rval != QLA_SUCCESS) {
4519*4882a593Smuzhiyun if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
4520*4882a593Smuzhiyun IS_CNA_CAPABLE(ha) ||
4521*4882a593Smuzhiyun (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
4522*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2008,
4523*4882a593Smuzhiyun "Loop is in a transition state.\n");
4524*4882a593Smuzhiyun } else {
4525*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x2009,
4526*4882a593Smuzhiyun "Unable to get host loop ID.\n");
4527*4882a593Smuzhiyun if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
4528*4882a593Smuzhiyun (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
4529*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x1151,
4530*4882a593Smuzhiyun "Doing link init.\n");
4531*4882a593Smuzhiyun if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
4532*4882a593Smuzhiyun return rval;
4533*4882a593Smuzhiyun }
4534*4882a593Smuzhiyun set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
4535*4882a593Smuzhiyun }
4536*4882a593Smuzhiyun return (rval);
4537*4882a593Smuzhiyun }
4538*4882a593Smuzhiyun
4539*4882a593Smuzhiyun if (topo == 4) {
4540*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x200a,
4541*4882a593Smuzhiyun "Cannot get topology - retrying.\n");
4542*4882a593Smuzhiyun return (QLA_FUNCTION_FAILED);
4543*4882a593Smuzhiyun }
4544*4882a593Smuzhiyun
4545*4882a593Smuzhiyun vha->loop_id = loop_id;
4546*4882a593Smuzhiyun
4547*4882a593Smuzhiyun /* initialize */
4548*4882a593Smuzhiyun ha->min_external_loopid = SNS_FIRST_LOOP_ID;
4549*4882a593Smuzhiyun ha->operating_mode = LOOP;
4550*4882a593Smuzhiyun ha->switch_cap = 0;
4551*4882a593Smuzhiyun
4552*4882a593Smuzhiyun switch (topo) {
4553*4882a593Smuzhiyun case 0:
4554*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
4555*4882a593Smuzhiyun ha->current_topology = ISP_CFG_NL;
4556*4882a593Smuzhiyun strcpy(connect_type, "(Loop)");
4557*4882a593Smuzhiyun break;
4558*4882a593Smuzhiyun
4559*4882a593Smuzhiyun case 1:
4560*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
4561*4882a593Smuzhiyun ha->switch_cap = sw_cap;
4562*4882a593Smuzhiyun ha->current_topology = ISP_CFG_FL;
4563*4882a593Smuzhiyun strcpy(connect_type, "(FL_Port)");
4564*4882a593Smuzhiyun break;
4565*4882a593Smuzhiyun
4566*4882a593Smuzhiyun case 2:
4567*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
4568*4882a593Smuzhiyun ha->operating_mode = P2P;
4569*4882a593Smuzhiyun ha->current_topology = ISP_CFG_N;
4570*4882a593Smuzhiyun strcpy(connect_type, "(N_Port-to-N_Port)");
4571*4882a593Smuzhiyun break;
4572*4882a593Smuzhiyun
4573*4882a593Smuzhiyun case 3:
4574*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
4575*4882a593Smuzhiyun ha->switch_cap = sw_cap;
4576*4882a593Smuzhiyun ha->operating_mode = P2P;
4577*4882a593Smuzhiyun ha->current_topology = ISP_CFG_F;
4578*4882a593Smuzhiyun strcpy(connect_type, "(F_Port)");
4579*4882a593Smuzhiyun break;
4580*4882a593Smuzhiyun
4581*4882a593Smuzhiyun default:
4582*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x200f,
4583*4882a593Smuzhiyun "HBA in unknown topology %x, using NL.\n", topo);
4584*4882a593Smuzhiyun ha->current_topology = ISP_CFG_NL;
4585*4882a593Smuzhiyun strcpy(connect_type, "(Loop)");
4586*4882a593Smuzhiyun break;
4587*4882a593Smuzhiyun }
4588*4882a593Smuzhiyun
4589*4882a593Smuzhiyun /* Save Host port and loop ID. */
4590*4882a593Smuzhiyun /* byte order - Big Endian */
4591*4882a593Smuzhiyun id.b.domain = domain;
4592*4882a593Smuzhiyun id.b.area = area;
4593*4882a593Smuzhiyun id.b.al_pa = al_pa;
4594*4882a593Smuzhiyun id.b.rsvd_1 = 0;
4595*4882a593Smuzhiyun spin_lock_irqsave(&ha->hardware_lock, flags);
4596*4882a593Smuzhiyun if (!(topo == 2 && ha->flags.n2n_bigger))
4597*4882a593Smuzhiyun qlt_update_host_map(vha, id);
4598*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->hardware_lock, flags);
4599*4882a593Smuzhiyun
4600*4882a593Smuzhiyun if (!vha->flags.init_done)
4601*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x2010,
4602*4882a593Smuzhiyun "Topology - %s, Host Loop address 0x%x.\n",
4603*4882a593Smuzhiyun connect_type, vha->loop_id);
4604*4882a593Smuzhiyun
4605*4882a593Smuzhiyun return(rval);
4606*4882a593Smuzhiyun }
4607*4882a593Smuzhiyun
4608*4882a593Smuzhiyun inline void
qla2x00_set_model_info(scsi_qla_host_t * vha,uint8_t * model,size_t len,const char * def)4609*4882a593Smuzhiyun qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
4610*4882a593Smuzhiyun const char *def)
4611*4882a593Smuzhiyun {
4612*4882a593Smuzhiyun char *st, *en;
4613*4882a593Smuzhiyun uint16_t index;
4614*4882a593Smuzhiyun uint64_t zero[2] = { 0 };
4615*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
4616*4882a593Smuzhiyun int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
4617*4882a593Smuzhiyun !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
4618*4882a593Smuzhiyun
4619*4882a593Smuzhiyun if (len > sizeof(zero))
4620*4882a593Smuzhiyun len = sizeof(zero);
4621*4882a593Smuzhiyun if (memcmp(model, &zero, len) != 0) {
4622*4882a593Smuzhiyun memcpy(ha->model_number, model, len);
4623*4882a593Smuzhiyun st = en = ha->model_number;
4624*4882a593Smuzhiyun en += len - 1;
4625*4882a593Smuzhiyun while (en > st) {
4626*4882a593Smuzhiyun if (*en != 0x20 && *en != 0x00)
4627*4882a593Smuzhiyun break;
4628*4882a593Smuzhiyun *en-- = '\0';
4629*4882a593Smuzhiyun }
4630*4882a593Smuzhiyun
4631*4882a593Smuzhiyun index = (ha->pdev->subsystem_device & 0xff);
4632*4882a593Smuzhiyun if (use_tbl &&
4633*4882a593Smuzhiyun ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
4634*4882a593Smuzhiyun index < QLA_MODEL_NAMES)
4635*4882a593Smuzhiyun strlcpy(ha->model_desc,
4636*4882a593Smuzhiyun qla2x00_model_name[index * 2 + 1],
4637*4882a593Smuzhiyun sizeof(ha->model_desc));
4638*4882a593Smuzhiyun } else {
4639*4882a593Smuzhiyun index = (ha->pdev->subsystem_device & 0xff);
4640*4882a593Smuzhiyun if (use_tbl &&
4641*4882a593Smuzhiyun ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
4642*4882a593Smuzhiyun index < QLA_MODEL_NAMES) {
4643*4882a593Smuzhiyun strlcpy(ha->model_number,
4644*4882a593Smuzhiyun qla2x00_model_name[index * 2],
4645*4882a593Smuzhiyun sizeof(ha->model_number));
4646*4882a593Smuzhiyun strlcpy(ha->model_desc,
4647*4882a593Smuzhiyun qla2x00_model_name[index * 2 + 1],
4648*4882a593Smuzhiyun sizeof(ha->model_desc));
4649*4882a593Smuzhiyun } else {
4650*4882a593Smuzhiyun strlcpy(ha->model_number, def,
4651*4882a593Smuzhiyun sizeof(ha->model_number));
4652*4882a593Smuzhiyun }
4653*4882a593Smuzhiyun }
4654*4882a593Smuzhiyun if (IS_FWI2_CAPABLE(ha))
4655*4882a593Smuzhiyun qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
4656*4882a593Smuzhiyun sizeof(ha->model_desc));
4657*4882a593Smuzhiyun }
4658*4882a593Smuzhiyun
4659*4882a593Smuzhiyun /* On sparc systems, obtain port and node WWN from firmware
4660*4882a593Smuzhiyun * properties.
4661*4882a593Smuzhiyun */
qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t * vha,nvram_t * nv)4662*4882a593Smuzhiyun static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4663*4882a593Smuzhiyun {
4664*4882a593Smuzhiyun #ifdef CONFIG_SPARC
4665*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
4666*4882a593Smuzhiyun struct pci_dev *pdev = ha->pdev;
4667*4882a593Smuzhiyun struct device_node *dp = pci_device_to_OF_node(pdev);
4668*4882a593Smuzhiyun const u8 *val;
4669*4882a593Smuzhiyun int len;
4670*4882a593Smuzhiyun
4671*4882a593Smuzhiyun val = of_get_property(dp, "port-wwn", &len);
4672*4882a593Smuzhiyun if (val && len >= WWN_SIZE)
4673*4882a593Smuzhiyun memcpy(nv->port_name, val, WWN_SIZE);
4674*4882a593Smuzhiyun
4675*4882a593Smuzhiyun val = of_get_property(dp, "node-wwn", &len);
4676*4882a593Smuzhiyun if (val && len >= WWN_SIZE)
4677*4882a593Smuzhiyun memcpy(nv->node_name, val, WWN_SIZE);
4678*4882a593Smuzhiyun #endif
4679*4882a593Smuzhiyun }
4680*4882a593Smuzhiyun
4681*4882a593Smuzhiyun /*
4682*4882a593Smuzhiyun * NVRAM configuration for ISP 2xxx
4683*4882a593Smuzhiyun *
4684*4882a593Smuzhiyun * Input:
4685*4882a593Smuzhiyun * ha = adapter block pointer.
4686*4882a593Smuzhiyun *
4687*4882a593Smuzhiyun * Output:
4688*4882a593Smuzhiyun * initialization control block in response_ring
4689*4882a593Smuzhiyun * host adapters parameters in host adapter block
4690*4882a593Smuzhiyun *
4691*4882a593Smuzhiyun * Returns:
4692*4882a593Smuzhiyun * 0 = success.
4693*4882a593Smuzhiyun */
4694*4882a593Smuzhiyun int
qla2x00_nvram_config(scsi_qla_host_t * vha)4695*4882a593Smuzhiyun qla2x00_nvram_config(scsi_qla_host_t *vha)
4696*4882a593Smuzhiyun {
4697*4882a593Smuzhiyun int rval;
4698*4882a593Smuzhiyun uint8_t chksum = 0;
4699*4882a593Smuzhiyun uint16_t cnt;
4700*4882a593Smuzhiyun uint8_t *dptr1, *dptr2;
4701*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
4702*4882a593Smuzhiyun init_cb_t *icb = ha->init_cb;
4703*4882a593Smuzhiyun nvram_t *nv = ha->nvram;
4704*4882a593Smuzhiyun uint8_t *ptr = ha->nvram;
4705*4882a593Smuzhiyun struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4706*4882a593Smuzhiyun
4707*4882a593Smuzhiyun rval = QLA_SUCCESS;
4708*4882a593Smuzhiyun
4709*4882a593Smuzhiyun /* Determine NVRAM starting address. */
4710*4882a593Smuzhiyun ha->nvram_size = sizeof(*nv);
4711*4882a593Smuzhiyun ha->nvram_base = 0;
4712*4882a593Smuzhiyun if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
4713*4882a593Smuzhiyun if ((rd_reg_word(®->ctrl_status) >> 14) == 1)
4714*4882a593Smuzhiyun ha->nvram_base = 0x80;
4715*4882a593Smuzhiyun
4716*4882a593Smuzhiyun /* Get NVRAM data and calculate checksum. */
4717*4882a593Smuzhiyun ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
4718*4882a593Smuzhiyun for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
4719*4882a593Smuzhiyun chksum += *ptr++;
4720*4882a593Smuzhiyun
4721*4882a593Smuzhiyun ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
4722*4882a593Smuzhiyun "Contents of NVRAM.\n");
4723*4882a593Smuzhiyun ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
4724*4882a593Smuzhiyun nv, ha->nvram_size);
4725*4882a593Smuzhiyun
4726*4882a593Smuzhiyun /* Bad NVRAM data, set defaults parameters. */
4727*4882a593Smuzhiyun if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) ||
4728*4882a593Smuzhiyun nv->nvram_version < 1) {
4729*4882a593Smuzhiyun /* Reset NVRAM data. */
4730*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0064,
4731*4882a593Smuzhiyun "Inconsistent NVRAM detected: checksum=%#x id=%.4s version=%#x.\n",
4732*4882a593Smuzhiyun chksum, nv->id, nv->nvram_version);
4733*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0065,
4734*4882a593Smuzhiyun "Falling back to "
4735*4882a593Smuzhiyun "functioning (yet invalid -- WWPN) defaults.\n");
4736*4882a593Smuzhiyun
4737*4882a593Smuzhiyun /*
4738*4882a593Smuzhiyun * Set default initialization control block.
4739*4882a593Smuzhiyun */
4740*4882a593Smuzhiyun memset(nv, 0, ha->nvram_size);
4741*4882a593Smuzhiyun nv->parameter_block_version = ICB_VERSION;
4742*4882a593Smuzhiyun
4743*4882a593Smuzhiyun if (IS_QLA23XX(ha)) {
4744*4882a593Smuzhiyun nv->firmware_options[0] = BIT_2 | BIT_1;
4745*4882a593Smuzhiyun nv->firmware_options[1] = BIT_7 | BIT_5;
4746*4882a593Smuzhiyun nv->add_firmware_options[0] = BIT_5;
4747*4882a593Smuzhiyun nv->add_firmware_options[1] = BIT_5 | BIT_4;
4748*4882a593Smuzhiyun nv->frame_payload_size = cpu_to_le16(2048);
4749*4882a593Smuzhiyun nv->special_options[1] = BIT_7;
4750*4882a593Smuzhiyun } else if (IS_QLA2200(ha)) {
4751*4882a593Smuzhiyun nv->firmware_options[0] = BIT_2 | BIT_1;
4752*4882a593Smuzhiyun nv->firmware_options[1] = BIT_7 | BIT_5;
4753*4882a593Smuzhiyun nv->add_firmware_options[0] = BIT_5;
4754*4882a593Smuzhiyun nv->add_firmware_options[1] = BIT_5 | BIT_4;
4755*4882a593Smuzhiyun nv->frame_payload_size = cpu_to_le16(1024);
4756*4882a593Smuzhiyun } else if (IS_QLA2100(ha)) {
4757*4882a593Smuzhiyun nv->firmware_options[0] = BIT_3 | BIT_1;
4758*4882a593Smuzhiyun nv->firmware_options[1] = BIT_5;
4759*4882a593Smuzhiyun nv->frame_payload_size = cpu_to_le16(1024);
4760*4882a593Smuzhiyun }
4761*4882a593Smuzhiyun
4762*4882a593Smuzhiyun nv->max_iocb_allocation = cpu_to_le16(256);
4763*4882a593Smuzhiyun nv->execution_throttle = cpu_to_le16(16);
4764*4882a593Smuzhiyun nv->retry_count = 8;
4765*4882a593Smuzhiyun nv->retry_delay = 1;
4766*4882a593Smuzhiyun
4767*4882a593Smuzhiyun nv->port_name[0] = 33;
4768*4882a593Smuzhiyun nv->port_name[3] = 224;
4769*4882a593Smuzhiyun nv->port_name[4] = 139;
4770*4882a593Smuzhiyun
4771*4882a593Smuzhiyun qla2xxx_nvram_wwn_from_ofw(vha, nv);
4772*4882a593Smuzhiyun
4773*4882a593Smuzhiyun nv->login_timeout = 4;
4774*4882a593Smuzhiyun
4775*4882a593Smuzhiyun /*
4776*4882a593Smuzhiyun * Set default host adapter parameters
4777*4882a593Smuzhiyun */
4778*4882a593Smuzhiyun nv->host_p[1] = BIT_2;
4779*4882a593Smuzhiyun nv->reset_delay = 5;
4780*4882a593Smuzhiyun nv->port_down_retry_count = 8;
4781*4882a593Smuzhiyun nv->max_luns_per_target = cpu_to_le16(8);
4782*4882a593Smuzhiyun nv->link_down_timeout = 60;
4783*4882a593Smuzhiyun
4784*4882a593Smuzhiyun rval = 1;
4785*4882a593Smuzhiyun }
4786*4882a593Smuzhiyun
4787*4882a593Smuzhiyun /* Reset Initialization control block */
4788*4882a593Smuzhiyun memset(icb, 0, ha->init_cb_size);
4789*4882a593Smuzhiyun
4790*4882a593Smuzhiyun /*
4791*4882a593Smuzhiyun * Setup driver NVRAM options.
4792*4882a593Smuzhiyun */
4793*4882a593Smuzhiyun nv->firmware_options[0] |= (BIT_6 | BIT_1);
4794*4882a593Smuzhiyun nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
4795*4882a593Smuzhiyun nv->firmware_options[1] |= (BIT_5 | BIT_0);
4796*4882a593Smuzhiyun nv->firmware_options[1] &= ~BIT_4;
4797*4882a593Smuzhiyun
4798*4882a593Smuzhiyun if (IS_QLA23XX(ha)) {
4799*4882a593Smuzhiyun nv->firmware_options[0] |= BIT_2;
4800*4882a593Smuzhiyun nv->firmware_options[0] &= ~BIT_3;
4801*4882a593Smuzhiyun nv->special_options[0] &= ~BIT_6;
4802*4882a593Smuzhiyun nv->add_firmware_options[1] |= BIT_5 | BIT_4;
4803*4882a593Smuzhiyun
4804*4882a593Smuzhiyun if (IS_QLA2300(ha)) {
4805*4882a593Smuzhiyun if (ha->fb_rev == FPM_2310) {
4806*4882a593Smuzhiyun strcpy(ha->model_number, "QLA2310");
4807*4882a593Smuzhiyun } else {
4808*4882a593Smuzhiyun strcpy(ha->model_number, "QLA2300");
4809*4882a593Smuzhiyun }
4810*4882a593Smuzhiyun } else {
4811*4882a593Smuzhiyun qla2x00_set_model_info(vha, nv->model_number,
4812*4882a593Smuzhiyun sizeof(nv->model_number), "QLA23xx");
4813*4882a593Smuzhiyun }
4814*4882a593Smuzhiyun } else if (IS_QLA2200(ha)) {
4815*4882a593Smuzhiyun nv->firmware_options[0] |= BIT_2;
4816*4882a593Smuzhiyun /*
4817*4882a593Smuzhiyun * 'Point-to-point preferred, else loop' is not a safe
4818*4882a593Smuzhiyun * connection mode setting.
4819*4882a593Smuzhiyun */
4820*4882a593Smuzhiyun if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
4821*4882a593Smuzhiyun (BIT_5 | BIT_4)) {
4822*4882a593Smuzhiyun /* Force 'loop preferred, else point-to-point'. */
4823*4882a593Smuzhiyun nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
4824*4882a593Smuzhiyun nv->add_firmware_options[0] |= BIT_5;
4825*4882a593Smuzhiyun }
4826*4882a593Smuzhiyun strcpy(ha->model_number, "QLA22xx");
4827*4882a593Smuzhiyun } else /*if (IS_QLA2100(ha))*/ {
4828*4882a593Smuzhiyun strcpy(ha->model_number, "QLA2100");
4829*4882a593Smuzhiyun }
4830*4882a593Smuzhiyun
4831*4882a593Smuzhiyun /*
4832*4882a593Smuzhiyun * Copy over NVRAM RISC parameter block to initialization control block.
4833*4882a593Smuzhiyun */
4834*4882a593Smuzhiyun dptr1 = (uint8_t *)icb;
4835*4882a593Smuzhiyun dptr2 = (uint8_t *)&nv->parameter_block_version;
4836*4882a593Smuzhiyun cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
4837*4882a593Smuzhiyun while (cnt--)
4838*4882a593Smuzhiyun *dptr1++ = *dptr2++;
4839*4882a593Smuzhiyun
4840*4882a593Smuzhiyun /* Copy 2nd half. */
4841*4882a593Smuzhiyun dptr1 = (uint8_t *)icb->add_firmware_options;
4842*4882a593Smuzhiyun cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
4843*4882a593Smuzhiyun while (cnt--)
4844*4882a593Smuzhiyun *dptr1++ = *dptr2++;
4845*4882a593Smuzhiyun ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
4846*4882a593Smuzhiyun /* Use alternate WWN? */
4847*4882a593Smuzhiyun if (nv->host_p[1] & BIT_7) {
4848*4882a593Smuzhiyun memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4849*4882a593Smuzhiyun memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4850*4882a593Smuzhiyun }
4851*4882a593Smuzhiyun
4852*4882a593Smuzhiyun /* Prepare nodename */
4853*4882a593Smuzhiyun if ((icb->firmware_options[1] & BIT_6) == 0) {
4854*4882a593Smuzhiyun /*
4855*4882a593Smuzhiyun * Firmware will apply the following mask if the nodename was
4856*4882a593Smuzhiyun * not provided.
4857*4882a593Smuzhiyun */
4858*4882a593Smuzhiyun memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4859*4882a593Smuzhiyun icb->node_name[0] &= 0xF0;
4860*4882a593Smuzhiyun }
4861*4882a593Smuzhiyun
4862*4882a593Smuzhiyun /*
4863*4882a593Smuzhiyun * Set host adapter parameters.
4864*4882a593Smuzhiyun */
4865*4882a593Smuzhiyun
4866*4882a593Smuzhiyun /*
4867*4882a593Smuzhiyun * BIT_7 in the host-parameters section allows for modification to
4868*4882a593Smuzhiyun * internal driver logging.
4869*4882a593Smuzhiyun */
4870*4882a593Smuzhiyun if (nv->host_p[0] & BIT_7)
4871*4882a593Smuzhiyun ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
4872*4882a593Smuzhiyun ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
4873*4882a593Smuzhiyun /* Always load RISC code on non ISP2[12]00 chips. */
4874*4882a593Smuzhiyun if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
4875*4882a593Smuzhiyun ha->flags.disable_risc_code_load = 0;
4876*4882a593Smuzhiyun ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
4877*4882a593Smuzhiyun ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
4878*4882a593Smuzhiyun ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
4879*4882a593Smuzhiyun ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
4880*4882a593Smuzhiyun ha->flags.disable_serdes = 0;
4881*4882a593Smuzhiyun
4882*4882a593Smuzhiyun ha->operating_mode =
4883*4882a593Smuzhiyun (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
4884*4882a593Smuzhiyun
4885*4882a593Smuzhiyun memcpy(ha->fw_seriallink_options, nv->seriallink_options,
4886*4882a593Smuzhiyun sizeof(ha->fw_seriallink_options));
4887*4882a593Smuzhiyun
4888*4882a593Smuzhiyun /* save HBA serial number */
4889*4882a593Smuzhiyun ha->serial0 = icb->port_name[5];
4890*4882a593Smuzhiyun ha->serial1 = icb->port_name[6];
4891*4882a593Smuzhiyun ha->serial2 = icb->port_name[7];
4892*4882a593Smuzhiyun memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4893*4882a593Smuzhiyun memcpy(vha->port_name, icb->port_name, WWN_SIZE);
4894*4882a593Smuzhiyun
4895*4882a593Smuzhiyun icb->execution_throttle = cpu_to_le16(0xFFFF);
4896*4882a593Smuzhiyun
4897*4882a593Smuzhiyun ha->retry_count = nv->retry_count;
4898*4882a593Smuzhiyun
4899*4882a593Smuzhiyun /* Set minimum login_timeout to 4 seconds. */
4900*4882a593Smuzhiyun if (nv->login_timeout != ql2xlogintimeout)
4901*4882a593Smuzhiyun nv->login_timeout = ql2xlogintimeout;
4902*4882a593Smuzhiyun if (nv->login_timeout < 4)
4903*4882a593Smuzhiyun nv->login_timeout = 4;
4904*4882a593Smuzhiyun ha->login_timeout = nv->login_timeout;
4905*4882a593Smuzhiyun
4906*4882a593Smuzhiyun /* Set minimum RATOV to 100 tenths of a second. */
4907*4882a593Smuzhiyun ha->r_a_tov = 100;
4908*4882a593Smuzhiyun
4909*4882a593Smuzhiyun ha->loop_reset_delay = nv->reset_delay;
4910*4882a593Smuzhiyun
4911*4882a593Smuzhiyun /* Link Down Timeout = 0:
4912*4882a593Smuzhiyun *
4913*4882a593Smuzhiyun * When Port Down timer expires we will start returning
4914*4882a593Smuzhiyun * I/O's to OS with "DID_NO_CONNECT".
4915*4882a593Smuzhiyun *
4916*4882a593Smuzhiyun * Link Down Timeout != 0:
4917*4882a593Smuzhiyun *
4918*4882a593Smuzhiyun * The driver waits for the link to come up after link down
4919*4882a593Smuzhiyun * before returning I/Os to OS with "DID_NO_CONNECT".
4920*4882a593Smuzhiyun */
4921*4882a593Smuzhiyun if (nv->link_down_timeout == 0) {
4922*4882a593Smuzhiyun ha->loop_down_abort_time =
4923*4882a593Smuzhiyun (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
4924*4882a593Smuzhiyun } else {
4925*4882a593Smuzhiyun ha->link_down_timeout = nv->link_down_timeout;
4926*4882a593Smuzhiyun ha->loop_down_abort_time =
4927*4882a593Smuzhiyun (LOOP_DOWN_TIME - ha->link_down_timeout);
4928*4882a593Smuzhiyun }
4929*4882a593Smuzhiyun
4930*4882a593Smuzhiyun /*
4931*4882a593Smuzhiyun * Need enough time to try and get the port back.
4932*4882a593Smuzhiyun */
4933*4882a593Smuzhiyun ha->port_down_retry_count = nv->port_down_retry_count;
4934*4882a593Smuzhiyun if (qlport_down_retry)
4935*4882a593Smuzhiyun ha->port_down_retry_count = qlport_down_retry;
4936*4882a593Smuzhiyun /* Set login_retry_count */
4937*4882a593Smuzhiyun ha->login_retry_count = nv->retry_count;
4938*4882a593Smuzhiyun if (ha->port_down_retry_count == nv->port_down_retry_count &&
4939*4882a593Smuzhiyun ha->port_down_retry_count > 3)
4940*4882a593Smuzhiyun ha->login_retry_count = ha->port_down_retry_count;
4941*4882a593Smuzhiyun else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4942*4882a593Smuzhiyun ha->login_retry_count = ha->port_down_retry_count;
4943*4882a593Smuzhiyun if (ql2xloginretrycount)
4944*4882a593Smuzhiyun ha->login_retry_count = ql2xloginretrycount;
4945*4882a593Smuzhiyun
4946*4882a593Smuzhiyun icb->lun_enables = cpu_to_le16(0);
4947*4882a593Smuzhiyun icb->command_resource_count = 0;
4948*4882a593Smuzhiyun icb->immediate_notify_resource_count = 0;
4949*4882a593Smuzhiyun icb->timeout = cpu_to_le16(0);
4950*4882a593Smuzhiyun
4951*4882a593Smuzhiyun if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4952*4882a593Smuzhiyun /* Enable RIO */
4953*4882a593Smuzhiyun icb->firmware_options[0] &= ~BIT_3;
4954*4882a593Smuzhiyun icb->add_firmware_options[0] &=
4955*4882a593Smuzhiyun ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
4956*4882a593Smuzhiyun icb->add_firmware_options[0] |= BIT_2;
4957*4882a593Smuzhiyun icb->response_accumulation_timer = 3;
4958*4882a593Smuzhiyun icb->interrupt_delay_timer = 5;
4959*4882a593Smuzhiyun
4960*4882a593Smuzhiyun vha->flags.process_response_queue = 1;
4961*4882a593Smuzhiyun } else {
4962*4882a593Smuzhiyun /* Enable ZIO. */
4963*4882a593Smuzhiyun if (!vha->flags.init_done) {
4964*4882a593Smuzhiyun ha->zio_mode = icb->add_firmware_options[0] &
4965*4882a593Smuzhiyun (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4966*4882a593Smuzhiyun ha->zio_timer = icb->interrupt_delay_timer ?
4967*4882a593Smuzhiyun icb->interrupt_delay_timer : 2;
4968*4882a593Smuzhiyun }
4969*4882a593Smuzhiyun icb->add_firmware_options[0] &=
4970*4882a593Smuzhiyun ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
4971*4882a593Smuzhiyun vha->flags.process_response_queue = 0;
4972*4882a593Smuzhiyun if (ha->zio_mode != QLA_ZIO_DISABLED) {
4973*4882a593Smuzhiyun ha->zio_mode = QLA_ZIO_MODE_6;
4974*4882a593Smuzhiyun
4975*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x0068,
4976*4882a593Smuzhiyun "ZIO mode %d enabled; timer delay (%d us).\n",
4977*4882a593Smuzhiyun ha->zio_mode, ha->zio_timer * 100);
4978*4882a593Smuzhiyun
4979*4882a593Smuzhiyun icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
4980*4882a593Smuzhiyun icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
4981*4882a593Smuzhiyun vha->flags.process_response_queue = 1;
4982*4882a593Smuzhiyun }
4983*4882a593Smuzhiyun }
4984*4882a593Smuzhiyun
4985*4882a593Smuzhiyun if (rval) {
4986*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0069,
4987*4882a593Smuzhiyun "NVRAM configuration failed.\n");
4988*4882a593Smuzhiyun }
4989*4882a593Smuzhiyun return (rval);
4990*4882a593Smuzhiyun }
4991*4882a593Smuzhiyun
4992*4882a593Smuzhiyun static void
qla2x00_rport_del(void * data)4993*4882a593Smuzhiyun qla2x00_rport_del(void *data)
4994*4882a593Smuzhiyun {
4995*4882a593Smuzhiyun fc_port_t *fcport = data;
4996*4882a593Smuzhiyun struct fc_rport *rport;
4997*4882a593Smuzhiyun unsigned long flags;
4998*4882a593Smuzhiyun
4999*4882a593Smuzhiyun spin_lock_irqsave(fcport->vha->host->host_lock, flags);
5000*4882a593Smuzhiyun rport = fcport->drport ? fcport->drport : fcport->rport;
5001*4882a593Smuzhiyun fcport->drport = NULL;
5002*4882a593Smuzhiyun spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
5003*4882a593Smuzhiyun if (rport) {
5004*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, fcport->vha, 0x210b,
5005*4882a593Smuzhiyun "%s %8phN. rport %p roles %x\n",
5006*4882a593Smuzhiyun __func__, fcport->port_name, rport,
5007*4882a593Smuzhiyun rport->roles);
5008*4882a593Smuzhiyun
5009*4882a593Smuzhiyun fc_remote_port_delete(rport);
5010*4882a593Smuzhiyun }
5011*4882a593Smuzhiyun }
5012*4882a593Smuzhiyun
qla2x00_set_fcport_state(fc_port_t * fcport,int state)5013*4882a593Smuzhiyun void qla2x00_set_fcport_state(fc_port_t *fcport, int state)
5014*4882a593Smuzhiyun {
5015*4882a593Smuzhiyun int old_state;
5016*4882a593Smuzhiyun
5017*4882a593Smuzhiyun old_state = atomic_read(&fcport->state);
5018*4882a593Smuzhiyun atomic_set(&fcport->state, state);
5019*4882a593Smuzhiyun
5020*4882a593Smuzhiyun /* Don't print state transitions during initial allocation of fcport */
5021*4882a593Smuzhiyun if (old_state && old_state != state) {
5022*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, fcport->vha, 0x207d,
5023*4882a593Smuzhiyun "FCPort %8phC state transitioned from %s to %s - portid=%02x%02x%02x.\n",
5024*4882a593Smuzhiyun fcport->port_name, port_state_str[old_state],
5025*4882a593Smuzhiyun port_state_str[state], fcport->d_id.b.domain,
5026*4882a593Smuzhiyun fcport->d_id.b.area, fcport->d_id.b.al_pa);
5027*4882a593Smuzhiyun }
5028*4882a593Smuzhiyun }
5029*4882a593Smuzhiyun
5030*4882a593Smuzhiyun /**
5031*4882a593Smuzhiyun * qla2x00_alloc_fcport() - Allocate a generic fcport.
5032*4882a593Smuzhiyun * @vha: HA context
5033*4882a593Smuzhiyun * @flags: allocation flags
5034*4882a593Smuzhiyun *
5035*4882a593Smuzhiyun * Returns a pointer to the allocated fcport, or NULL, if none available.
5036*4882a593Smuzhiyun */
5037*4882a593Smuzhiyun fc_port_t *
qla2x00_alloc_fcport(scsi_qla_host_t * vha,gfp_t flags)5038*4882a593Smuzhiyun qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
5039*4882a593Smuzhiyun {
5040*4882a593Smuzhiyun fc_port_t *fcport;
5041*4882a593Smuzhiyun
5042*4882a593Smuzhiyun fcport = kzalloc(sizeof(fc_port_t), flags);
5043*4882a593Smuzhiyun if (!fcport)
5044*4882a593Smuzhiyun return NULL;
5045*4882a593Smuzhiyun
5046*4882a593Smuzhiyun fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev,
5047*4882a593Smuzhiyun sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma,
5048*4882a593Smuzhiyun flags);
5049*4882a593Smuzhiyun if (!fcport->ct_desc.ct_sns) {
5050*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0xd049,
5051*4882a593Smuzhiyun "Failed to allocate ct_sns request.\n");
5052*4882a593Smuzhiyun kfree(fcport);
5053*4882a593Smuzhiyun return NULL;
5054*4882a593Smuzhiyun }
5055*4882a593Smuzhiyun
5056*4882a593Smuzhiyun /* Setup fcport template structure. */
5057*4882a593Smuzhiyun fcport->vha = vha;
5058*4882a593Smuzhiyun fcport->port_type = FCT_UNKNOWN;
5059*4882a593Smuzhiyun fcport->loop_id = FC_NO_LOOP_ID;
5060*4882a593Smuzhiyun qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
5061*4882a593Smuzhiyun fcport->supported_classes = FC_COS_UNSPECIFIED;
5062*4882a593Smuzhiyun fcport->fp_speed = PORT_SPEED_UNKNOWN;
5063*4882a593Smuzhiyun
5064*4882a593Smuzhiyun fcport->disc_state = DSC_DELETED;
5065*4882a593Smuzhiyun fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
5066*4882a593Smuzhiyun fcport->deleted = QLA_SESS_DELETED;
5067*4882a593Smuzhiyun fcport->login_retry = vha->hw->login_retry_count;
5068*4882a593Smuzhiyun fcport->chip_reset = vha->hw->base_qpair->chip_reset;
5069*4882a593Smuzhiyun fcport->logout_on_delete = 1;
5070*4882a593Smuzhiyun
5071*4882a593Smuzhiyun if (!fcport->ct_desc.ct_sns) {
5072*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0xd049,
5073*4882a593Smuzhiyun "Failed to allocate ct_sns request.\n");
5074*4882a593Smuzhiyun kfree(fcport);
5075*4882a593Smuzhiyun return NULL;
5076*4882a593Smuzhiyun }
5077*4882a593Smuzhiyun
5078*4882a593Smuzhiyun INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn);
5079*4882a593Smuzhiyun INIT_WORK(&fcport->free_work, qlt_free_session_done);
5080*4882a593Smuzhiyun INIT_WORK(&fcport->reg_work, qla_register_fcport_fn);
5081*4882a593Smuzhiyun INIT_LIST_HEAD(&fcport->gnl_entry);
5082*4882a593Smuzhiyun INIT_LIST_HEAD(&fcport->list);
5083*4882a593Smuzhiyun
5084*4882a593Smuzhiyun return fcport;
5085*4882a593Smuzhiyun }
5086*4882a593Smuzhiyun
5087*4882a593Smuzhiyun void
qla2x00_free_fcport(fc_port_t * fcport)5088*4882a593Smuzhiyun qla2x00_free_fcport(fc_port_t *fcport)
5089*4882a593Smuzhiyun {
5090*4882a593Smuzhiyun if (fcport->ct_desc.ct_sns) {
5091*4882a593Smuzhiyun dma_free_coherent(&fcport->vha->hw->pdev->dev,
5092*4882a593Smuzhiyun sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns,
5093*4882a593Smuzhiyun fcport->ct_desc.ct_sns_dma);
5094*4882a593Smuzhiyun
5095*4882a593Smuzhiyun fcport->ct_desc.ct_sns = NULL;
5096*4882a593Smuzhiyun }
5097*4882a593Smuzhiyun list_del(&fcport->list);
5098*4882a593Smuzhiyun qla2x00_clear_loop_id(fcport);
5099*4882a593Smuzhiyun kfree(fcport);
5100*4882a593Smuzhiyun }
5101*4882a593Smuzhiyun
qla_get_login_template(scsi_qla_host_t * vha)5102*4882a593Smuzhiyun static void qla_get_login_template(scsi_qla_host_t *vha)
5103*4882a593Smuzhiyun {
5104*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
5105*4882a593Smuzhiyun int rval;
5106*4882a593Smuzhiyun u32 *bp, sz;
5107*4882a593Smuzhiyun __be32 *q;
5108*4882a593Smuzhiyun
5109*4882a593Smuzhiyun memset(ha->init_cb, 0, ha->init_cb_size);
5110*4882a593Smuzhiyun sz = min_t(int, sizeof(struct fc_els_flogi), ha->init_cb_size);
5111*4882a593Smuzhiyun rval = qla24xx_get_port_login_templ(vha, ha->init_cb_dma,
5112*4882a593Smuzhiyun ha->init_cb, sz);
5113*4882a593Smuzhiyun if (rval != QLA_SUCCESS) {
5114*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x00d1,
5115*4882a593Smuzhiyun "PLOGI ELS param read fail.\n");
5116*4882a593Smuzhiyun return;
5117*4882a593Smuzhiyun }
5118*4882a593Smuzhiyun q = (__be32 *)&ha->plogi_els_payld.fl_csp;
5119*4882a593Smuzhiyun
5120*4882a593Smuzhiyun bp = (uint32_t *)ha->init_cb;
5121*4882a593Smuzhiyun cpu_to_be32_array(q, bp, sz / 4);
5122*4882a593Smuzhiyun ha->flags.plogi_template_valid = 1;
5123*4882a593Smuzhiyun }
5124*4882a593Smuzhiyun
5125*4882a593Smuzhiyun /*
5126*4882a593Smuzhiyun * qla2x00_configure_loop
5127*4882a593Smuzhiyun * Updates Fibre Channel Device Database with what is actually on loop.
5128*4882a593Smuzhiyun *
5129*4882a593Smuzhiyun * Input:
5130*4882a593Smuzhiyun * ha = adapter block pointer.
5131*4882a593Smuzhiyun *
5132*4882a593Smuzhiyun * Returns:
5133*4882a593Smuzhiyun * 0 = success.
5134*4882a593Smuzhiyun * 1 = error.
5135*4882a593Smuzhiyun * 2 = database was full and device was not configured.
5136*4882a593Smuzhiyun */
5137*4882a593Smuzhiyun static int
qla2x00_configure_loop(scsi_qla_host_t * vha)5138*4882a593Smuzhiyun qla2x00_configure_loop(scsi_qla_host_t *vha)
5139*4882a593Smuzhiyun {
5140*4882a593Smuzhiyun int rval;
5141*4882a593Smuzhiyun unsigned long flags, save_flags;
5142*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
5143*4882a593Smuzhiyun
5144*4882a593Smuzhiyun rval = QLA_SUCCESS;
5145*4882a593Smuzhiyun
5146*4882a593Smuzhiyun /* Get Initiator ID */
5147*4882a593Smuzhiyun if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
5148*4882a593Smuzhiyun rval = qla2x00_configure_hba(vha);
5149*4882a593Smuzhiyun if (rval != QLA_SUCCESS) {
5150*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2013,
5151*4882a593Smuzhiyun "Unable to configure HBA.\n");
5152*4882a593Smuzhiyun return (rval);
5153*4882a593Smuzhiyun }
5154*4882a593Smuzhiyun }
5155*4882a593Smuzhiyun
5156*4882a593Smuzhiyun save_flags = flags = vha->dpc_flags;
5157*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2014,
5158*4882a593Smuzhiyun "Configure loop -- dpc flags = 0x%lx.\n", flags);
5159*4882a593Smuzhiyun
5160*4882a593Smuzhiyun /*
5161*4882a593Smuzhiyun * If we have both an RSCN and PORT UPDATE pending then handle them
5162*4882a593Smuzhiyun * both at the same time.
5163*4882a593Smuzhiyun */
5164*4882a593Smuzhiyun clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5165*4882a593Smuzhiyun clear_bit(RSCN_UPDATE, &vha->dpc_flags);
5166*4882a593Smuzhiyun
5167*4882a593Smuzhiyun qla2x00_get_data_rate(vha);
5168*4882a593Smuzhiyun qla_get_login_template(vha);
5169*4882a593Smuzhiyun
5170*4882a593Smuzhiyun /* Determine what we need to do */
5171*4882a593Smuzhiyun if ((ha->current_topology == ISP_CFG_FL ||
5172*4882a593Smuzhiyun ha->current_topology == ISP_CFG_F) &&
5173*4882a593Smuzhiyun (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
5174*4882a593Smuzhiyun
5175*4882a593Smuzhiyun set_bit(RSCN_UPDATE, &flags);
5176*4882a593Smuzhiyun clear_bit(LOCAL_LOOP_UPDATE, &flags);
5177*4882a593Smuzhiyun
5178*4882a593Smuzhiyun } else if (ha->current_topology == ISP_CFG_NL ||
5179*4882a593Smuzhiyun ha->current_topology == ISP_CFG_N) {
5180*4882a593Smuzhiyun clear_bit(RSCN_UPDATE, &flags);
5181*4882a593Smuzhiyun set_bit(LOCAL_LOOP_UPDATE, &flags);
5182*4882a593Smuzhiyun } else if (!vha->flags.online ||
5183*4882a593Smuzhiyun (test_bit(ABORT_ISP_ACTIVE, &flags))) {
5184*4882a593Smuzhiyun set_bit(RSCN_UPDATE, &flags);
5185*4882a593Smuzhiyun set_bit(LOCAL_LOOP_UPDATE, &flags);
5186*4882a593Smuzhiyun }
5187*4882a593Smuzhiyun
5188*4882a593Smuzhiyun if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
5189*4882a593Smuzhiyun if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
5190*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2015,
5191*4882a593Smuzhiyun "Loop resync needed, failing.\n");
5192*4882a593Smuzhiyun rval = QLA_FUNCTION_FAILED;
5193*4882a593Smuzhiyun } else
5194*4882a593Smuzhiyun rval = qla2x00_configure_local_loop(vha);
5195*4882a593Smuzhiyun }
5196*4882a593Smuzhiyun
5197*4882a593Smuzhiyun if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
5198*4882a593Smuzhiyun if (LOOP_TRANSITION(vha)) {
5199*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2099,
5200*4882a593Smuzhiyun "Needs RSCN update and loop transition.\n");
5201*4882a593Smuzhiyun rval = QLA_FUNCTION_FAILED;
5202*4882a593Smuzhiyun }
5203*4882a593Smuzhiyun else
5204*4882a593Smuzhiyun rval = qla2x00_configure_fabric(vha);
5205*4882a593Smuzhiyun }
5206*4882a593Smuzhiyun
5207*4882a593Smuzhiyun if (rval == QLA_SUCCESS) {
5208*4882a593Smuzhiyun if (atomic_read(&vha->loop_down_timer) ||
5209*4882a593Smuzhiyun test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
5210*4882a593Smuzhiyun rval = QLA_FUNCTION_FAILED;
5211*4882a593Smuzhiyun } else {
5212*4882a593Smuzhiyun atomic_set(&vha->loop_state, LOOP_READY);
5213*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2069,
5214*4882a593Smuzhiyun "LOOP READY.\n");
5215*4882a593Smuzhiyun ha->flags.fw_init_done = 1;
5216*4882a593Smuzhiyun
5217*4882a593Smuzhiyun /*
5218*4882a593Smuzhiyun * Process any ATIO queue entries that came in
5219*4882a593Smuzhiyun * while we weren't online.
5220*4882a593Smuzhiyun */
5221*4882a593Smuzhiyun if (qla_tgt_mode_enabled(vha) ||
5222*4882a593Smuzhiyun qla_dual_mode_enabled(vha)) {
5223*4882a593Smuzhiyun spin_lock_irqsave(&ha->tgt.atio_lock, flags);
5224*4882a593Smuzhiyun qlt_24xx_process_atio_queue(vha, 0);
5225*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->tgt.atio_lock,
5226*4882a593Smuzhiyun flags);
5227*4882a593Smuzhiyun }
5228*4882a593Smuzhiyun }
5229*4882a593Smuzhiyun }
5230*4882a593Smuzhiyun
5231*4882a593Smuzhiyun if (rval) {
5232*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x206a,
5233*4882a593Smuzhiyun "%s *** FAILED ***.\n", __func__);
5234*4882a593Smuzhiyun } else {
5235*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x206b,
5236*4882a593Smuzhiyun "%s: exiting normally.\n", __func__);
5237*4882a593Smuzhiyun }
5238*4882a593Smuzhiyun
5239*4882a593Smuzhiyun /* Restore state if a resync event occurred during processing */
5240*4882a593Smuzhiyun if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
5241*4882a593Smuzhiyun if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
5242*4882a593Smuzhiyun set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5243*4882a593Smuzhiyun if (test_bit(RSCN_UPDATE, &save_flags)) {
5244*4882a593Smuzhiyun set_bit(RSCN_UPDATE, &vha->dpc_flags);
5245*4882a593Smuzhiyun }
5246*4882a593Smuzhiyun }
5247*4882a593Smuzhiyun
5248*4882a593Smuzhiyun return (rval);
5249*4882a593Smuzhiyun }
5250*4882a593Smuzhiyun
qla2x00_configure_n2n_loop(scsi_qla_host_t * vha)5251*4882a593Smuzhiyun static int qla2x00_configure_n2n_loop(scsi_qla_host_t *vha)
5252*4882a593Smuzhiyun {
5253*4882a593Smuzhiyun unsigned long flags;
5254*4882a593Smuzhiyun fc_port_t *fcport;
5255*4882a593Smuzhiyun
5256*4882a593Smuzhiyun if (test_and_clear_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags))
5257*4882a593Smuzhiyun set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5258*4882a593Smuzhiyun
5259*4882a593Smuzhiyun list_for_each_entry(fcport, &vha->vp_fcports, list) {
5260*4882a593Smuzhiyun if (fcport->n2n_flag) {
5261*4882a593Smuzhiyun qla24xx_fcport_handle_login(vha, fcport);
5262*4882a593Smuzhiyun return QLA_SUCCESS;
5263*4882a593Smuzhiyun }
5264*4882a593Smuzhiyun }
5265*4882a593Smuzhiyun
5266*4882a593Smuzhiyun spin_lock_irqsave(&vha->work_lock, flags);
5267*4882a593Smuzhiyun vha->scan.scan_retry++;
5268*4882a593Smuzhiyun spin_unlock_irqrestore(&vha->work_lock, flags);
5269*4882a593Smuzhiyun
5270*4882a593Smuzhiyun if (vha->scan.scan_retry < MAX_SCAN_RETRIES) {
5271*4882a593Smuzhiyun set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5272*4882a593Smuzhiyun set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5273*4882a593Smuzhiyun }
5274*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
5275*4882a593Smuzhiyun }
5276*4882a593Smuzhiyun
5277*4882a593Smuzhiyun static void
qla_reinitialize_link(scsi_qla_host_t * vha)5278*4882a593Smuzhiyun qla_reinitialize_link(scsi_qla_host_t *vha)
5279*4882a593Smuzhiyun {
5280*4882a593Smuzhiyun int rval;
5281*4882a593Smuzhiyun
5282*4882a593Smuzhiyun atomic_set(&vha->loop_state, LOOP_DOWN);
5283*4882a593Smuzhiyun atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
5284*4882a593Smuzhiyun rval = qla2x00_full_login_lip(vha);
5285*4882a593Smuzhiyun if (rval == QLA_SUCCESS) {
5286*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0xd050, "Link reinitialized\n");
5287*4882a593Smuzhiyun } else {
5288*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0xd051,
5289*4882a593Smuzhiyun "Link reinitialization failed (%d)\n", rval);
5290*4882a593Smuzhiyun }
5291*4882a593Smuzhiyun }
5292*4882a593Smuzhiyun
5293*4882a593Smuzhiyun /*
5294*4882a593Smuzhiyun * qla2x00_configure_local_loop
5295*4882a593Smuzhiyun * Updates Fibre Channel Device Database with local loop devices.
5296*4882a593Smuzhiyun *
5297*4882a593Smuzhiyun * Input:
5298*4882a593Smuzhiyun * ha = adapter block pointer.
5299*4882a593Smuzhiyun *
5300*4882a593Smuzhiyun * Returns:
5301*4882a593Smuzhiyun * 0 = success.
5302*4882a593Smuzhiyun */
5303*4882a593Smuzhiyun static int
qla2x00_configure_local_loop(scsi_qla_host_t * vha)5304*4882a593Smuzhiyun qla2x00_configure_local_loop(scsi_qla_host_t *vha)
5305*4882a593Smuzhiyun {
5306*4882a593Smuzhiyun int rval, rval2;
5307*4882a593Smuzhiyun int found_devs;
5308*4882a593Smuzhiyun int found;
5309*4882a593Smuzhiyun fc_port_t *fcport, *new_fcport;
5310*4882a593Smuzhiyun uint16_t index;
5311*4882a593Smuzhiyun uint16_t entries;
5312*4882a593Smuzhiyun struct gid_list_info *gid;
5313*4882a593Smuzhiyun uint16_t loop_id;
5314*4882a593Smuzhiyun uint8_t domain, area, al_pa;
5315*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
5316*4882a593Smuzhiyun unsigned long flags;
5317*4882a593Smuzhiyun
5318*4882a593Smuzhiyun /* Inititae N2N login. */
5319*4882a593Smuzhiyun if (N2N_TOPO(ha))
5320*4882a593Smuzhiyun return qla2x00_configure_n2n_loop(vha);
5321*4882a593Smuzhiyun
5322*4882a593Smuzhiyun found_devs = 0;
5323*4882a593Smuzhiyun new_fcport = NULL;
5324*4882a593Smuzhiyun entries = MAX_FIBRE_DEVICES_LOOP;
5325*4882a593Smuzhiyun
5326*4882a593Smuzhiyun /* Get list of logged in devices. */
5327*4882a593Smuzhiyun memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
5328*4882a593Smuzhiyun rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
5329*4882a593Smuzhiyun &entries);
5330*4882a593Smuzhiyun if (rval != QLA_SUCCESS)
5331*4882a593Smuzhiyun goto err;
5332*4882a593Smuzhiyun
5333*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2011,
5334*4882a593Smuzhiyun "Entries in ID list (%d).\n", entries);
5335*4882a593Smuzhiyun ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
5336*4882a593Smuzhiyun ha->gid_list, entries * sizeof(*ha->gid_list));
5337*4882a593Smuzhiyun
5338*4882a593Smuzhiyun if (entries == 0) {
5339*4882a593Smuzhiyun spin_lock_irqsave(&vha->work_lock, flags);
5340*4882a593Smuzhiyun vha->scan.scan_retry++;
5341*4882a593Smuzhiyun spin_unlock_irqrestore(&vha->work_lock, flags);
5342*4882a593Smuzhiyun
5343*4882a593Smuzhiyun if (vha->scan.scan_retry < MAX_SCAN_RETRIES) {
5344*4882a593Smuzhiyun u8 loop_map_entries = 0;
5345*4882a593Smuzhiyun int rc;
5346*4882a593Smuzhiyun
5347*4882a593Smuzhiyun rc = qla2x00_get_fcal_position_map(vha, NULL,
5348*4882a593Smuzhiyun &loop_map_entries);
5349*4882a593Smuzhiyun if (rc == QLA_SUCCESS && loop_map_entries > 1) {
5350*4882a593Smuzhiyun /*
5351*4882a593Smuzhiyun * There are devices that are still not logged
5352*4882a593Smuzhiyun * in. Reinitialize to give them a chance.
5353*4882a593Smuzhiyun */
5354*4882a593Smuzhiyun qla_reinitialize_link(vha);
5355*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
5356*4882a593Smuzhiyun }
5357*4882a593Smuzhiyun set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5358*4882a593Smuzhiyun set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5359*4882a593Smuzhiyun }
5360*4882a593Smuzhiyun } else {
5361*4882a593Smuzhiyun vha->scan.scan_retry = 0;
5362*4882a593Smuzhiyun }
5363*4882a593Smuzhiyun
5364*4882a593Smuzhiyun list_for_each_entry(fcport, &vha->vp_fcports, list) {
5365*4882a593Smuzhiyun fcport->scan_state = QLA_FCPORT_SCAN;
5366*4882a593Smuzhiyun }
5367*4882a593Smuzhiyun
5368*4882a593Smuzhiyun /* Allocate temporary fcport for any new fcports discovered. */
5369*4882a593Smuzhiyun new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5370*4882a593Smuzhiyun if (new_fcport == NULL) {
5371*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x2012,
5372*4882a593Smuzhiyun "Memory allocation failed for fcport.\n");
5373*4882a593Smuzhiyun rval = QLA_MEMORY_ALLOC_FAILED;
5374*4882a593Smuzhiyun goto err;
5375*4882a593Smuzhiyun }
5376*4882a593Smuzhiyun new_fcport->flags &= ~FCF_FABRIC_DEVICE;
5377*4882a593Smuzhiyun
5378*4882a593Smuzhiyun /* Add devices to port list. */
5379*4882a593Smuzhiyun gid = ha->gid_list;
5380*4882a593Smuzhiyun for (index = 0; index < entries; index++) {
5381*4882a593Smuzhiyun domain = gid->domain;
5382*4882a593Smuzhiyun area = gid->area;
5383*4882a593Smuzhiyun al_pa = gid->al_pa;
5384*4882a593Smuzhiyun if (IS_QLA2100(ha) || IS_QLA2200(ha))
5385*4882a593Smuzhiyun loop_id = gid->loop_id_2100;
5386*4882a593Smuzhiyun else
5387*4882a593Smuzhiyun loop_id = le16_to_cpu(gid->loop_id);
5388*4882a593Smuzhiyun gid = (void *)gid + ha->gid_list_info_size;
5389*4882a593Smuzhiyun
5390*4882a593Smuzhiyun /* Bypass reserved domain fields. */
5391*4882a593Smuzhiyun if ((domain & 0xf0) == 0xf0)
5392*4882a593Smuzhiyun continue;
5393*4882a593Smuzhiyun
5394*4882a593Smuzhiyun /* Bypass if not same domain and area of adapter. */
5395*4882a593Smuzhiyun if (area && domain && ((area != vha->d_id.b.area) ||
5396*4882a593Smuzhiyun (domain != vha->d_id.b.domain)) &&
5397*4882a593Smuzhiyun (ha->current_topology == ISP_CFG_NL))
5398*4882a593Smuzhiyun continue;
5399*4882a593Smuzhiyun
5400*4882a593Smuzhiyun
5401*4882a593Smuzhiyun /* Bypass invalid local loop ID. */
5402*4882a593Smuzhiyun if (loop_id > LAST_LOCAL_LOOP_ID)
5403*4882a593Smuzhiyun continue;
5404*4882a593Smuzhiyun
5405*4882a593Smuzhiyun memset(new_fcport->port_name, 0, WWN_SIZE);
5406*4882a593Smuzhiyun
5407*4882a593Smuzhiyun /* Fill in member data. */
5408*4882a593Smuzhiyun new_fcport->d_id.b.domain = domain;
5409*4882a593Smuzhiyun new_fcport->d_id.b.area = area;
5410*4882a593Smuzhiyun new_fcport->d_id.b.al_pa = al_pa;
5411*4882a593Smuzhiyun new_fcport->loop_id = loop_id;
5412*4882a593Smuzhiyun new_fcport->scan_state = QLA_FCPORT_FOUND;
5413*4882a593Smuzhiyun
5414*4882a593Smuzhiyun rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
5415*4882a593Smuzhiyun if (rval2 != QLA_SUCCESS) {
5416*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2097,
5417*4882a593Smuzhiyun "Failed to retrieve fcport information "
5418*4882a593Smuzhiyun "-- get_port_database=%x, loop_id=0x%04x.\n",
5419*4882a593Smuzhiyun rval2, new_fcport->loop_id);
5420*4882a593Smuzhiyun /* Skip retry if N2N */
5421*4882a593Smuzhiyun if (ha->current_topology != ISP_CFG_N) {
5422*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2105,
5423*4882a593Smuzhiyun "Scheduling resync.\n");
5424*4882a593Smuzhiyun set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5425*4882a593Smuzhiyun continue;
5426*4882a593Smuzhiyun }
5427*4882a593Smuzhiyun }
5428*4882a593Smuzhiyun
5429*4882a593Smuzhiyun spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5430*4882a593Smuzhiyun /* Check for matching device in port list. */
5431*4882a593Smuzhiyun found = 0;
5432*4882a593Smuzhiyun fcport = NULL;
5433*4882a593Smuzhiyun list_for_each_entry(fcport, &vha->vp_fcports, list) {
5434*4882a593Smuzhiyun if (memcmp(new_fcport->port_name, fcport->port_name,
5435*4882a593Smuzhiyun WWN_SIZE))
5436*4882a593Smuzhiyun continue;
5437*4882a593Smuzhiyun
5438*4882a593Smuzhiyun fcport->flags &= ~FCF_FABRIC_DEVICE;
5439*4882a593Smuzhiyun fcport->loop_id = new_fcport->loop_id;
5440*4882a593Smuzhiyun fcport->port_type = new_fcport->port_type;
5441*4882a593Smuzhiyun fcport->d_id.b24 = new_fcport->d_id.b24;
5442*4882a593Smuzhiyun memcpy(fcport->node_name, new_fcport->node_name,
5443*4882a593Smuzhiyun WWN_SIZE);
5444*4882a593Smuzhiyun fcport->scan_state = QLA_FCPORT_FOUND;
5445*4882a593Smuzhiyun if (fcport->login_retry == 0) {
5446*4882a593Smuzhiyun fcport->login_retry = vha->hw->login_retry_count;
5447*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2135,
5448*4882a593Smuzhiyun "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n",
5449*4882a593Smuzhiyun fcport->port_name, fcport->loop_id,
5450*4882a593Smuzhiyun fcport->login_retry);
5451*4882a593Smuzhiyun }
5452*4882a593Smuzhiyun found++;
5453*4882a593Smuzhiyun break;
5454*4882a593Smuzhiyun }
5455*4882a593Smuzhiyun
5456*4882a593Smuzhiyun if (!found) {
5457*4882a593Smuzhiyun /* New device, add to fcports list. */
5458*4882a593Smuzhiyun list_add_tail(&new_fcport->list, &vha->vp_fcports);
5459*4882a593Smuzhiyun
5460*4882a593Smuzhiyun /* Allocate a new replacement fcport. */
5461*4882a593Smuzhiyun fcport = new_fcport;
5462*4882a593Smuzhiyun
5463*4882a593Smuzhiyun spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5464*4882a593Smuzhiyun
5465*4882a593Smuzhiyun new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5466*4882a593Smuzhiyun
5467*4882a593Smuzhiyun if (new_fcport == NULL) {
5468*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0xd031,
5469*4882a593Smuzhiyun "Failed to allocate memory for fcport.\n");
5470*4882a593Smuzhiyun rval = QLA_MEMORY_ALLOC_FAILED;
5471*4882a593Smuzhiyun goto err;
5472*4882a593Smuzhiyun }
5473*4882a593Smuzhiyun spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5474*4882a593Smuzhiyun new_fcport->flags &= ~FCF_FABRIC_DEVICE;
5475*4882a593Smuzhiyun }
5476*4882a593Smuzhiyun
5477*4882a593Smuzhiyun spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5478*4882a593Smuzhiyun
5479*4882a593Smuzhiyun /* Base iIDMA settings on HBA port speed. */
5480*4882a593Smuzhiyun fcport->fp_speed = ha->link_data_rate;
5481*4882a593Smuzhiyun
5482*4882a593Smuzhiyun found_devs++;
5483*4882a593Smuzhiyun }
5484*4882a593Smuzhiyun
5485*4882a593Smuzhiyun list_for_each_entry(fcport, &vha->vp_fcports, list) {
5486*4882a593Smuzhiyun if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5487*4882a593Smuzhiyun break;
5488*4882a593Smuzhiyun
5489*4882a593Smuzhiyun if (fcport->scan_state == QLA_FCPORT_SCAN) {
5490*4882a593Smuzhiyun if ((qla_dual_mode_enabled(vha) ||
5491*4882a593Smuzhiyun qla_ini_mode_enabled(vha)) &&
5492*4882a593Smuzhiyun atomic_read(&fcport->state) == FCS_ONLINE) {
5493*4882a593Smuzhiyun qla2x00_mark_device_lost(vha, fcport,
5494*4882a593Smuzhiyun ql2xplogiabsentdevice);
5495*4882a593Smuzhiyun if (fcport->loop_id != FC_NO_LOOP_ID &&
5496*4882a593Smuzhiyun (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
5497*4882a593Smuzhiyun fcport->port_type != FCT_INITIATOR &&
5498*4882a593Smuzhiyun fcport->port_type != FCT_BROADCAST) {
5499*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20f0,
5500*4882a593Smuzhiyun "%s %d %8phC post del sess\n",
5501*4882a593Smuzhiyun __func__, __LINE__,
5502*4882a593Smuzhiyun fcport->port_name);
5503*4882a593Smuzhiyun
5504*4882a593Smuzhiyun qlt_schedule_sess_for_deletion(fcport);
5505*4882a593Smuzhiyun continue;
5506*4882a593Smuzhiyun }
5507*4882a593Smuzhiyun }
5508*4882a593Smuzhiyun }
5509*4882a593Smuzhiyun
5510*4882a593Smuzhiyun if (fcport->scan_state == QLA_FCPORT_FOUND)
5511*4882a593Smuzhiyun qla24xx_fcport_handle_login(vha, fcport);
5512*4882a593Smuzhiyun }
5513*4882a593Smuzhiyun
5514*4882a593Smuzhiyun qla2x00_free_fcport(new_fcport);
5515*4882a593Smuzhiyun
5516*4882a593Smuzhiyun return rval;
5517*4882a593Smuzhiyun
5518*4882a593Smuzhiyun err:
5519*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2098,
5520*4882a593Smuzhiyun "Configure local loop error exit: rval=%x.\n", rval);
5521*4882a593Smuzhiyun return rval;
5522*4882a593Smuzhiyun }
5523*4882a593Smuzhiyun
5524*4882a593Smuzhiyun static void
qla2x00_iidma_fcport(scsi_qla_host_t * vha,fc_port_t * fcport)5525*4882a593Smuzhiyun qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
5526*4882a593Smuzhiyun {
5527*4882a593Smuzhiyun int rval;
5528*4882a593Smuzhiyun uint16_t mb[MAILBOX_REGISTER_COUNT];
5529*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
5530*4882a593Smuzhiyun
5531*4882a593Smuzhiyun if (!IS_IIDMA_CAPABLE(ha))
5532*4882a593Smuzhiyun return;
5533*4882a593Smuzhiyun
5534*4882a593Smuzhiyun if (atomic_read(&fcport->state) != FCS_ONLINE)
5535*4882a593Smuzhiyun return;
5536*4882a593Smuzhiyun
5537*4882a593Smuzhiyun if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
5538*4882a593Smuzhiyun fcport->fp_speed > ha->link_data_rate ||
5539*4882a593Smuzhiyun !ha->flags.gpsc_supported)
5540*4882a593Smuzhiyun return;
5541*4882a593Smuzhiyun
5542*4882a593Smuzhiyun rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
5543*4882a593Smuzhiyun mb);
5544*4882a593Smuzhiyun if (rval != QLA_SUCCESS) {
5545*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2004,
5546*4882a593Smuzhiyun "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
5547*4882a593Smuzhiyun fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
5548*4882a593Smuzhiyun } else {
5549*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2005,
5550*4882a593Smuzhiyun "iIDMA adjusted to %s GB/s (%X) on %8phN.\n",
5551*4882a593Smuzhiyun qla2x00_get_link_speed_str(ha, fcport->fp_speed),
5552*4882a593Smuzhiyun fcport->fp_speed, fcport->port_name);
5553*4882a593Smuzhiyun }
5554*4882a593Smuzhiyun }
5555*4882a593Smuzhiyun
qla_do_iidma_work(struct scsi_qla_host * vha,fc_port_t * fcport)5556*4882a593Smuzhiyun void qla_do_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport)
5557*4882a593Smuzhiyun {
5558*4882a593Smuzhiyun qla2x00_iidma_fcport(vha, fcport);
5559*4882a593Smuzhiyun qla24xx_update_fcport_fcp_prio(vha, fcport);
5560*4882a593Smuzhiyun }
5561*4882a593Smuzhiyun
qla_post_iidma_work(struct scsi_qla_host * vha,fc_port_t * fcport)5562*4882a593Smuzhiyun int qla_post_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport)
5563*4882a593Smuzhiyun {
5564*4882a593Smuzhiyun struct qla_work_evt *e;
5565*4882a593Smuzhiyun
5566*4882a593Smuzhiyun e = qla2x00_alloc_work(vha, QLA_EVT_IIDMA);
5567*4882a593Smuzhiyun if (!e)
5568*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
5569*4882a593Smuzhiyun
5570*4882a593Smuzhiyun e->u.fcport.fcport = fcport;
5571*4882a593Smuzhiyun return qla2x00_post_work(vha, e);
5572*4882a593Smuzhiyun }
5573*4882a593Smuzhiyun
5574*4882a593Smuzhiyun /* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/
5575*4882a593Smuzhiyun static void
qla2x00_reg_remote_port(scsi_qla_host_t * vha,fc_port_t * fcport)5576*4882a593Smuzhiyun qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
5577*4882a593Smuzhiyun {
5578*4882a593Smuzhiyun struct fc_rport_identifiers rport_ids;
5579*4882a593Smuzhiyun struct fc_rport *rport;
5580*4882a593Smuzhiyun unsigned long flags;
5581*4882a593Smuzhiyun
5582*4882a593Smuzhiyun if (atomic_read(&fcport->state) == FCS_ONLINE)
5583*4882a593Smuzhiyun return;
5584*4882a593Smuzhiyun
5585*4882a593Smuzhiyun rport_ids.node_name = wwn_to_u64(fcport->node_name);
5586*4882a593Smuzhiyun rport_ids.port_name = wwn_to_u64(fcport->port_name);
5587*4882a593Smuzhiyun rport_ids.port_id = fcport->d_id.b.domain << 16 |
5588*4882a593Smuzhiyun fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
5589*4882a593Smuzhiyun rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
5590*4882a593Smuzhiyun fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
5591*4882a593Smuzhiyun if (!rport) {
5592*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x2006,
5593*4882a593Smuzhiyun "Unable to allocate fc remote port.\n");
5594*4882a593Smuzhiyun return;
5595*4882a593Smuzhiyun }
5596*4882a593Smuzhiyun
5597*4882a593Smuzhiyun spin_lock_irqsave(fcport->vha->host->host_lock, flags);
5598*4882a593Smuzhiyun *((fc_port_t **)rport->dd_data) = fcport;
5599*4882a593Smuzhiyun spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
5600*4882a593Smuzhiyun
5601*4882a593Smuzhiyun rport->supported_classes = fcport->supported_classes;
5602*4882a593Smuzhiyun
5603*4882a593Smuzhiyun rport_ids.roles = FC_PORT_ROLE_UNKNOWN;
5604*4882a593Smuzhiyun if (fcport->port_type == FCT_INITIATOR)
5605*4882a593Smuzhiyun rport_ids.roles |= FC_PORT_ROLE_FCP_INITIATOR;
5606*4882a593Smuzhiyun if (fcport->port_type == FCT_TARGET)
5607*4882a593Smuzhiyun rport_ids.roles |= FC_PORT_ROLE_FCP_TARGET;
5608*4882a593Smuzhiyun if (fcport->port_type & FCT_NVME_INITIATOR)
5609*4882a593Smuzhiyun rport_ids.roles |= FC_PORT_ROLE_NVME_INITIATOR;
5610*4882a593Smuzhiyun if (fcport->port_type & FCT_NVME_TARGET)
5611*4882a593Smuzhiyun rport_ids.roles |= FC_PORT_ROLE_NVME_TARGET;
5612*4882a593Smuzhiyun if (fcport->port_type & FCT_NVME_DISCOVERY)
5613*4882a593Smuzhiyun rport_ids.roles |= FC_PORT_ROLE_NVME_DISCOVERY;
5614*4882a593Smuzhiyun
5615*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20ee,
5616*4882a593Smuzhiyun "%s %8phN. rport %p is %s mode\n",
5617*4882a593Smuzhiyun __func__, fcport->port_name, rport,
5618*4882a593Smuzhiyun (fcport->port_type == FCT_TARGET) ? "tgt" :
5619*4882a593Smuzhiyun ((fcport->port_type & FCT_NVME) ? "nvme" : "ini"));
5620*4882a593Smuzhiyun
5621*4882a593Smuzhiyun fc_remote_port_rolechg(rport, rport_ids.roles);
5622*4882a593Smuzhiyun }
5623*4882a593Smuzhiyun
5624*4882a593Smuzhiyun /*
5625*4882a593Smuzhiyun * qla2x00_update_fcport
5626*4882a593Smuzhiyun * Updates device on list.
5627*4882a593Smuzhiyun *
5628*4882a593Smuzhiyun * Input:
5629*4882a593Smuzhiyun * ha = adapter block pointer.
5630*4882a593Smuzhiyun * fcport = port structure pointer.
5631*4882a593Smuzhiyun *
5632*4882a593Smuzhiyun * Return:
5633*4882a593Smuzhiyun * 0 - Success
5634*4882a593Smuzhiyun * BIT_0 - error
5635*4882a593Smuzhiyun *
5636*4882a593Smuzhiyun * Context:
5637*4882a593Smuzhiyun * Kernel context.
5638*4882a593Smuzhiyun */
5639*4882a593Smuzhiyun void
qla2x00_update_fcport(scsi_qla_host_t * vha,fc_port_t * fcport)5640*4882a593Smuzhiyun qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
5641*4882a593Smuzhiyun {
5642*4882a593Smuzhiyun if (IS_SW_RESV_ADDR(fcport->d_id))
5643*4882a593Smuzhiyun return;
5644*4882a593Smuzhiyun
5645*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20ef, "%s %8phC\n",
5646*4882a593Smuzhiyun __func__, fcport->port_name);
5647*4882a593Smuzhiyun
5648*4882a593Smuzhiyun qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT);
5649*4882a593Smuzhiyun fcport->login_retry = vha->hw->login_retry_count;
5650*4882a593Smuzhiyun fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
5651*4882a593Smuzhiyun fcport->deleted = 0;
5652*4882a593Smuzhiyun if (vha->hw->current_topology == ISP_CFG_NL)
5653*4882a593Smuzhiyun fcport->logout_on_delete = 0;
5654*4882a593Smuzhiyun else
5655*4882a593Smuzhiyun fcport->logout_on_delete = 1;
5656*4882a593Smuzhiyun fcport->n2n_chip_reset = fcport->n2n_link_reset_cnt = 0;
5657*4882a593Smuzhiyun
5658*4882a593Smuzhiyun switch (vha->hw->current_topology) {
5659*4882a593Smuzhiyun case ISP_CFG_N:
5660*4882a593Smuzhiyun case ISP_CFG_NL:
5661*4882a593Smuzhiyun fcport->keep_nport_handle = 1;
5662*4882a593Smuzhiyun break;
5663*4882a593Smuzhiyun default:
5664*4882a593Smuzhiyun break;
5665*4882a593Smuzhiyun }
5666*4882a593Smuzhiyun
5667*4882a593Smuzhiyun qla2x00_iidma_fcport(vha, fcport);
5668*4882a593Smuzhiyun
5669*4882a593Smuzhiyun qla2x00_dfs_create_rport(vha, fcport);
5670*4882a593Smuzhiyun
5671*4882a593Smuzhiyun if (NVME_TARGET(vha->hw, fcport)) {
5672*4882a593Smuzhiyun qla_nvme_register_remote(vha, fcport);
5673*4882a593Smuzhiyun qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_COMPLETE);
5674*4882a593Smuzhiyun qla2x00_set_fcport_state(fcport, FCS_ONLINE);
5675*4882a593Smuzhiyun return;
5676*4882a593Smuzhiyun }
5677*4882a593Smuzhiyun
5678*4882a593Smuzhiyun qla24xx_update_fcport_fcp_prio(vha, fcport);
5679*4882a593Smuzhiyun
5680*4882a593Smuzhiyun switch (vha->host->active_mode) {
5681*4882a593Smuzhiyun case MODE_INITIATOR:
5682*4882a593Smuzhiyun qla2x00_reg_remote_port(vha, fcport);
5683*4882a593Smuzhiyun break;
5684*4882a593Smuzhiyun case MODE_TARGET:
5685*4882a593Smuzhiyun if (!vha->vha_tgt.qla_tgt->tgt_stop &&
5686*4882a593Smuzhiyun !vha->vha_tgt.qla_tgt->tgt_stopped)
5687*4882a593Smuzhiyun qlt_fc_port_added(vha, fcport);
5688*4882a593Smuzhiyun break;
5689*4882a593Smuzhiyun case MODE_DUAL:
5690*4882a593Smuzhiyun qla2x00_reg_remote_port(vha, fcport);
5691*4882a593Smuzhiyun if (!vha->vha_tgt.qla_tgt->tgt_stop &&
5692*4882a593Smuzhiyun !vha->vha_tgt.qla_tgt->tgt_stopped)
5693*4882a593Smuzhiyun qlt_fc_port_added(vha, fcport);
5694*4882a593Smuzhiyun break;
5695*4882a593Smuzhiyun default:
5696*4882a593Smuzhiyun break;
5697*4882a593Smuzhiyun }
5698*4882a593Smuzhiyun
5699*4882a593Smuzhiyun qla2x00_set_fcport_state(fcport, FCS_ONLINE);
5700*4882a593Smuzhiyun
5701*4882a593Smuzhiyun if (IS_IIDMA_CAPABLE(vha->hw) && vha->hw->flags.gpsc_supported) {
5702*4882a593Smuzhiyun if (fcport->id_changed) {
5703*4882a593Smuzhiyun fcport->id_changed = 0;
5704*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20d7,
5705*4882a593Smuzhiyun "%s %d %8phC post gfpnid fcp_cnt %d\n",
5706*4882a593Smuzhiyun __func__, __LINE__, fcport->port_name,
5707*4882a593Smuzhiyun vha->fcport_count);
5708*4882a593Smuzhiyun qla24xx_post_gfpnid_work(vha, fcport);
5709*4882a593Smuzhiyun } else {
5710*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20d7,
5711*4882a593Smuzhiyun "%s %d %8phC post gpsc fcp_cnt %d\n",
5712*4882a593Smuzhiyun __func__, __LINE__, fcport->port_name,
5713*4882a593Smuzhiyun vha->fcport_count);
5714*4882a593Smuzhiyun qla24xx_post_gpsc_work(vha, fcport);
5715*4882a593Smuzhiyun }
5716*4882a593Smuzhiyun }
5717*4882a593Smuzhiyun
5718*4882a593Smuzhiyun qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_COMPLETE);
5719*4882a593Smuzhiyun }
5720*4882a593Smuzhiyun
qla_register_fcport_fn(struct work_struct * work)5721*4882a593Smuzhiyun void qla_register_fcport_fn(struct work_struct *work)
5722*4882a593Smuzhiyun {
5723*4882a593Smuzhiyun fc_port_t *fcport = container_of(work, struct fc_port, reg_work);
5724*4882a593Smuzhiyun u32 rscn_gen = fcport->rscn_gen;
5725*4882a593Smuzhiyun u16 data[2];
5726*4882a593Smuzhiyun
5727*4882a593Smuzhiyun if (IS_SW_RESV_ADDR(fcport->d_id))
5728*4882a593Smuzhiyun return;
5729*4882a593Smuzhiyun
5730*4882a593Smuzhiyun qla2x00_update_fcport(fcport->vha, fcport);
5731*4882a593Smuzhiyun
5732*4882a593Smuzhiyun if (rscn_gen != fcport->rscn_gen) {
5733*4882a593Smuzhiyun /* RSCN(s) came in while registration */
5734*4882a593Smuzhiyun switch (fcport->next_disc_state) {
5735*4882a593Smuzhiyun case DSC_DELETE_PEND:
5736*4882a593Smuzhiyun qlt_schedule_sess_for_deletion(fcport);
5737*4882a593Smuzhiyun break;
5738*4882a593Smuzhiyun case DSC_ADISC:
5739*4882a593Smuzhiyun data[0] = data[1] = 0;
5740*4882a593Smuzhiyun qla2x00_post_async_adisc_work(fcport->vha, fcport,
5741*4882a593Smuzhiyun data);
5742*4882a593Smuzhiyun break;
5743*4882a593Smuzhiyun default:
5744*4882a593Smuzhiyun break;
5745*4882a593Smuzhiyun }
5746*4882a593Smuzhiyun }
5747*4882a593Smuzhiyun }
5748*4882a593Smuzhiyun
5749*4882a593Smuzhiyun /*
5750*4882a593Smuzhiyun * qla2x00_configure_fabric
5751*4882a593Smuzhiyun * Setup SNS devices with loop ID's.
5752*4882a593Smuzhiyun *
5753*4882a593Smuzhiyun * Input:
5754*4882a593Smuzhiyun * ha = adapter block pointer.
5755*4882a593Smuzhiyun *
5756*4882a593Smuzhiyun * Returns:
5757*4882a593Smuzhiyun * 0 = success.
5758*4882a593Smuzhiyun * BIT_0 = error
5759*4882a593Smuzhiyun */
5760*4882a593Smuzhiyun static int
qla2x00_configure_fabric(scsi_qla_host_t * vha)5761*4882a593Smuzhiyun qla2x00_configure_fabric(scsi_qla_host_t *vha)
5762*4882a593Smuzhiyun {
5763*4882a593Smuzhiyun int rval;
5764*4882a593Smuzhiyun fc_port_t *fcport;
5765*4882a593Smuzhiyun uint16_t mb[MAILBOX_REGISTER_COUNT];
5766*4882a593Smuzhiyun uint16_t loop_id;
5767*4882a593Smuzhiyun LIST_HEAD(new_fcports);
5768*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
5769*4882a593Smuzhiyun int discovery_gen;
5770*4882a593Smuzhiyun
5771*4882a593Smuzhiyun /* If FL port exists, then SNS is present */
5772*4882a593Smuzhiyun if (IS_FWI2_CAPABLE(ha))
5773*4882a593Smuzhiyun loop_id = NPH_F_PORT;
5774*4882a593Smuzhiyun else
5775*4882a593Smuzhiyun loop_id = SNS_FL_PORT;
5776*4882a593Smuzhiyun rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
5777*4882a593Smuzhiyun if (rval != QLA_SUCCESS) {
5778*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20a0,
5779*4882a593Smuzhiyun "MBX_GET_PORT_NAME failed, No FL Port.\n");
5780*4882a593Smuzhiyun
5781*4882a593Smuzhiyun vha->device_flags &= ~SWITCH_FOUND;
5782*4882a593Smuzhiyun return (QLA_SUCCESS);
5783*4882a593Smuzhiyun }
5784*4882a593Smuzhiyun vha->device_flags |= SWITCH_FOUND;
5785*4882a593Smuzhiyun
5786*4882a593Smuzhiyun rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_port_name, 0);
5787*4882a593Smuzhiyun if (rval != QLA_SUCCESS)
5788*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20ff,
5789*4882a593Smuzhiyun "Failed to get Fabric Port Name\n");
5790*4882a593Smuzhiyun
5791*4882a593Smuzhiyun if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) {
5792*4882a593Smuzhiyun rval = qla2x00_send_change_request(vha, 0x3, 0);
5793*4882a593Smuzhiyun if (rval != QLA_SUCCESS)
5794*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x121,
5795*4882a593Smuzhiyun "Failed to enable receiving of RSCN requests: 0x%x.\n",
5796*4882a593Smuzhiyun rval);
5797*4882a593Smuzhiyun }
5798*4882a593Smuzhiyun
5799*4882a593Smuzhiyun do {
5800*4882a593Smuzhiyun qla2x00_mgmt_svr_login(vha);
5801*4882a593Smuzhiyun
5802*4882a593Smuzhiyun /* Ensure we are logged into the SNS. */
5803*4882a593Smuzhiyun loop_id = NPH_SNS_LID(ha);
5804*4882a593Smuzhiyun rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
5805*4882a593Smuzhiyun 0xfc, mb, BIT_1|BIT_0);
5806*4882a593Smuzhiyun if (rval != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5807*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20a1,
5808*4882a593Smuzhiyun "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[6]=%x mb[7]=%x (%x).\n",
5809*4882a593Smuzhiyun loop_id, mb[0], mb[1], mb[2], mb[6], mb[7], rval);
5810*4882a593Smuzhiyun set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5811*4882a593Smuzhiyun return rval;
5812*4882a593Smuzhiyun }
5813*4882a593Smuzhiyun
5814*4882a593Smuzhiyun /* FDMI support. */
5815*4882a593Smuzhiyun if (ql2xfdmienable &&
5816*4882a593Smuzhiyun test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
5817*4882a593Smuzhiyun qla2x00_fdmi_register(vha);
5818*4882a593Smuzhiyun
5819*4882a593Smuzhiyun if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
5820*4882a593Smuzhiyun if (qla2x00_rft_id(vha)) {
5821*4882a593Smuzhiyun /* EMPTY */
5822*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20a2,
5823*4882a593Smuzhiyun "Register FC-4 TYPE failed.\n");
5824*4882a593Smuzhiyun if (test_bit(LOOP_RESYNC_NEEDED,
5825*4882a593Smuzhiyun &vha->dpc_flags))
5826*4882a593Smuzhiyun break;
5827*4882a593Smuzhiyun }
5828*4882a593Smuzhiyun if (qla2x00_rff_id(vha, FC4_TYPE_FCP_SCSI)) {
5829*4882a593Smuzhiyun /* EMPTY */
5830*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x209a,
5831*4882a593Smuzhiyun "Register FC-4 Features failed.\n");
5832*4882a593Smuzhiyun if (test_bit(LOOP_RESYNC_NEEDED,
5833*4882a593Smuzhiyun &vha->dpc_flags))
5834*4882a593Smuzhiyun break;
5835*4882a593Smuzhiyun }
5836*4882a593Smuzhiyun if (vha->flags.nvme_enabled) {
5837*4882a593Smuzhiyun if (qla2x00_rff_id(vha, FC_TYPE_NVME)) {
5838*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2049,
5839*4882a593Smuzhiyun "Register NVME FC Type Features failed.\n");
5840*4882a593Smuzhiyun }
5841*4882a593Smuzhiyun }
5842*4882a593Smuzhiyun if (qla2x00_rnn_id(vha)) {
5843*4882a593Smuzhiyun /* EMPTY */
5844*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2104,
5845*4882a593Smuzhiyun "Register Node Name failed.\n");
5846*4882a593Smuzhiyun if (test_bit(LOOP_RESYNC_NEEDED,
5847*4882a593Smuzhiyun &vha->dpc_flags))
5848*4882a593Smuzhiyun break;
5849*4882a593Smuzhiyun } else if (qla2x00_rsnn_nn(vha)) {
5850*4882a593Smuzhiyun /* EMPTY */
5851*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x209b,
5852*4882a593Smuzhiyun "Register Symbolic Node Name failed.\n");
5853*4882a593Smuzhiyun if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5854*4882a593Smuzhiyun break;
5855*4882a593Smuzhiyun }
5856*4882a593Smuzhiyun }
5857*4882a593Smuzhiyun
5858*4882a593Smuzhiyun
5859*4882a593Smuzhiyun /* Mark the time right before querying FW for connected ports.
5860*4882a593Smuzhiyun * This process is long, asynchronous and by the time it's done,
5861*4882a593Smuzhiyun * collected information might not be accurate anymore. E.g.
5862*4882a593Smuzhiyun * disconnected port might have re-connected and a brand new
5863*4882a593Smuzhiyun * session has been created. In this case session's generation
5864*4882a593Smuzhiyun * will be newer than discovery_gen. */
5865*4882a593Smuzhiyun qlt_do_generation_tick(vha, &discovery_gen);
5866*4882a593Smuzhiyun
5867*4882a593Smuzhiyun if (USE_ASYNC_SCAN(ha)) {
5868*4882a593Smuzhiyun rval = qla24xx_async_gpnft(vha, FC4_TYPE_FCP_SCSI,
5869*4882a593Smuzhiyun NULL);
5870*4882a593Smuzhiyun if (rval)
5871*4882a593Smuzhiyun set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5872*4882a593Smuzhiyun } else {
5873*4882a593Smuzhiyun list_for_each_entry(fcport, &vha->vp_fcports, list)
5874*4882a593Smuzhiyun fcport->scan_state = QLA_FCPORT_SCAN;
5875*4882a593Smuzhiyun
5876*4882a593Smuzhiyun rval = qla2x00_find_all_fabric_devs(vha);
5877*4882a593Smuzhiyun }
5878*4882a593Smuzhiyun if (rval != QLA_SUCCESS)
5879*4882a593Smuzhiyun break;
5880*4882a593Smuzhiyun } while (0);
5881*4882a593Smuzhiyun
5882*4882a593Smuzhiyun if (!vha->nvme_local_port && vha->flags.nvme_enabled)
5883*4882a593Smuzhiyun qla_nvme_register_hba(vha);
5884*4882a593Smuzhiyun
5885*4882a593Smuzhiyun if (rval)
5886*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2068,
5887*4882a593Smuzhiyun "Configure fabric error exit rval=%d.\n", rval);
5888*4882a593Smuzhiyun
5889*4882a593Smuzhiyun return (rval);
5890*4882a593Smuzhiyun }
5891*4882a593Smuzhiyun
5892*4882a593Smuzhiyun /*
5893*4882a593Smuzhiyun * qla2x00_find_all_fabric_devs
5894*4882a593Smuzhiyun *
5895*4882a593Smuzhiyun * Input:
5896*4882a593Smuzhiyun * ha = adapter block pointer.
5897*4882a593Smuzhiyun * dev = database device entry pointer.
5898*4882a593Smuzhiyun *
5899*4882a593Smuzhiyun * Returns:
5900*4882a593Smuzhiyun * 0 = success.
5901*4882a593Smuzhiyun *
5902*4882a593Smuzhiyun * Context:
5903*4882a593Smuzhiyun * Kernel context.
5904*4882a593Smuzhiyun */
5905*4882a593Smuzhiyun static int
qla2x00_find_all_fabric_devs(scsi_qla_host_t * vha)5906*4882a593Smuzhiyun qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha)
5907*4882a593Smuzhiyun {
5908*4882a593Smuzhiyun int rval;
5909*4882a593Smuzhiyun uint16_t loop_id;
5910*4882a593Smuzhiyun fc_port_t *fcport, *new_fcport;
5911*4882a593Smuzhiyun int found;
5912*4882a593Smuzhiyun
5913*4882a593Smuzhiyun sw_info_t *swl;
5914*4882a593Smuzhiyun int swl_idx;
5915*4882a593Smuzhiyun int first_dev, last_dev;
5916*4882a593Smuzhiyun port_id_t wrap = {}, nxt_d_id;
5917*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
5918*4882a593Smuzhiyun struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
5919*4882a593Smuzhiyun unsigned long flags;
5920*4882a593Smuzhiyun
5921*4882a593Smuzhiyun rval = QLA_SUCCESS;
5922*4882a593Smuzhiyun
5923*4882a593Smuzhiyun /* Try GID_PT to get device list, else GAN. */
5924*4882a593Smuzhiyun if (!ha->swl)
5925*4882a593Smuzhiyun ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
5926*4882a593Smuzhiyun GFP_KERNEL);
5927*4882a593Smuzhiyun swl = ha->swl;
5928*4882a593Smuzhiyun if (!swl) {
5929*4882a593Smuzhiyun /*EMPTY*/
5930*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x209c,
5931*4882a593Smuzhiyun "GID_PT allocations failed, fallback on GA_NXT.\n");
5932*4882a593Smuzhiyun } else {
5933*4882a593Smuzhiyun memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
5934*4882a593Smuzhiyun if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
5935*4882a593Smuzhiyun swl = NULL;
5936*4882a593Smuzhiyun if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5937*4882a593Smuzhiyun return rval;
5938*4882a593Smuzhiyun } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
5939*4882a593Smuzhiyun swl = NULL;
5940*4882a593Smuzhiyun if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5941*4882a593Smuzhiyun return rval;
5942*4882a593Smuzhiyun } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
5943*4882a593Smuzhiyun swl = NULL;
5944*4882a593Smuzhiyun if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5945*4882a593Smuzhiyun return rval;
5946*4882a593Smuzhiyun } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) {
5947*4882a593Smuzhiyun swl = NULL;
5948*4882a593Smuzhiyun if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5949*4882a593Smuzhiyun return rval;
5950*4882a593Smuzhiyun }
5951*4882a593Smuzhiyun
5952*4882a593Smuzhiyun /* If other queries succeeded probe for FC-4 type */
5953*4882a593Smuzhiyun if (swl) {
5954*4882a593Smuzhiyun qla2x00_gff_id(vha, swl);
5955*4882a593Smuzhiyun if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5956*4882a593Smuzhiyun return rval;
5957*4882a593Smuzhiyun }
5958*4882a593Smuzhiyun }
5959*4882a593Smuzhiyun swl_idx = 0;
5960*4882a593Smuzhiyun
5961*4882a593Smuzhiyun /* Allocate temporary fcport for any new fcports discovered. */
5962*4882a593Smuzhiyun new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5963*4882a593Smuzhiyun if (new_fcport == NULL) {
5964*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x209d,
5965*4882a593Smuzhiyun "Failed to allocate memory for fcport.\n");
5966*4882a593Smuzhiyun return (QLA_MEMORY_ALLOC_FAILED);
5967*4882a593Smuzhiyun }
5968*4882a593Smuzhiyun new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
5969*4882a593Smuzhiyun /* Set start port ID scan at adapter ID. */
5970*4882a593Smuzhiyun first_dev = 1;
5971*4882a593Smuzhiyun last_dev = 0;
5972*4882a593Smuzhiyun
5973*4882a593Smuzhiyun /* Starting free loop ID. */
5974*4882a593Smuzhiyun loop_id = ha->min_external_loopid;
5975*4882a593Smuzhiyun for (; loop_id <= ha->max_loop_id; loop_id++) {
5976*4882a593Smuzhiyun if (qla2x00_is_reserved_id(vha, loop_id))
5977*4882a593Smuzhiyun continue;
5978*4882a593Smuzhiyun
5979*4882a593Smuzhiyun if (ha->current_topology == ISP_CFG_FL &&
5980*4882a593Smuzhiyun (atomic_read(&vha->loop_down_timer) ||
5981*4882a593Smuzhiyun LOOP_TRANSITION(vha))) {
5982*4882a593Smuzhiyun atomic_set(&vha->loop_down_timer, 0);
5983*4882a593Smuzhiyun set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5984*4882a593Smuzhiyun set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5985*4882a593Smuzhiyun break;
5986*4882a593Smuzhiyun }
5987*4882a593Smuzhiyun
5988*4882a593Smuzhiyun if (swl != NULL) {
5989*4882a593Smuzhiyun if (last_dev) {
5990*4882a593Smuzhiyun wrap.b24 = new_fcport->d_id.b24;
5991*4882a593Smuzhiyun } else {
5992*4882a593Smuzhiyun new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
5993*4882a593Smuzhiyun memcpy(new_fcport->node_name,
5994*4882a593Smuzhiyun swl[swl_idx].node_name, WWN_SIZE);
5995*4882a593Smuzhiyun memcpy(new_fcport->port_name,
5996*4882a593Smuzhiyun swl[swl_idx].port_name, WWN_SIZE);
5997*4882a593Smuzhiyun memcpy(new_fcport->fabric_port_name,
5998*4882a593Smuzhiyun swl[swl_idx].fabric_port_name, WWN_SIZE);
5999*4882a593Smuzhiyun new_fcport->fp_speed = swl[swl_idx].fp_speed;
6000*4882a593Smuzhiyun new_fcport->fc4_type = swl[swl_idx].fc4_type;
6001*4882a593Smuzhiyun
6002*4882a593Smuzhiyun new_fcport->nvme_flag = 0;
6003*4882a593Smuzhiyun if (vha->flags.nvme_enabled &&
6004*4882a593Smuzhiyun swl[swl_idx].fc4_type & FS_FC4TYPE_NVME) {
6005*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x2131,
6006*4882a593Smuzhiyun "FOUND: NVME port %8phC as FC Type 28h\n",
6007*4882a593Smuzhiyun new_fcport->port_name);
6008*4882a593Smuzhiyun }
6009*4882a593Smuzhiyun
6010*4882a593Smuzhiyun if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
6011*4882a593Smuzhiyun last_dev = 1;
6012*4882a593Smuzhiyun }
6013*4882a593Smuzhiyun swl_idx++;
6014*4882a593Smuzhiyun }
6015*4882a593Smuzhiyun } else {
6016*4882a593Smuzhiyun /* Send GA_NXT to the switch */
6017*4882a593Smuzhiyun rval = qla2x00_ga_nxt(vha, new_fcport);
6018*4882a593Smuzhiyun if (rval != QLA_SUCCESS) {
6019*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x209e,
6020*4882a593Smuzhiyun "SNS scan failed -- assuming "
6021*4882a593Smuzhiyun "zero-entry result.\n");
6022*4882a593Smuzhiyun rval = QLA_SUCCESS;
6023*4882a593Smuzhiyun break;
6024*4882a593Smuzhiyun }
6025*4882a593Smuzhiyun }
6026*4882a593Smuzhiyun
6027*4882a593Smuzhiyun /* If wrap on switch device list, exit. */
6028*4882a593Smuzhiyun if (first_dev) {
6029*4882a593Smuzhiyun wrap.b24 = new_fcport->d_id.b24;
6030*4882a593Smuzhiyun first_dev = 0;
6031*4882a593Smuzhiyun } else if (new_fcport->d_id.b24 == wrap.b24) {
6032*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x209f,
6033*4882a593Smuzhiyun "Device wrap (%02x%02x%02x).\n",
6034*4882a593Smuzhiyun new_fcport->d_id.b.domain,
6035*4882a593Smuzhiyun new_fcport->d_id.b.area,
6036*4882a593Smuzhiyun new_fcport->d_id.b.al_pa);
6037*4882a593Smuzhiyun break;
6038*4882a593Smuzhiyun }
6039*4882a593Smuzhiyun
6040*4882a593Smuzhiyun /* Bypass if same physical adapter. */
6041*4882a593Smuzhiyun if (new_fcport->d_id.b24 == base_vha->d_id.b24)
6042*4882a593Smuzhiyun continue;
6043*4882a593Smuzhiyun
6044*4882a593Smuzhiyun /* Bypass virtual ports of the same host. */
6045*4882a593Smuzhiyun if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
6046*4882a593Smuzhiyun continue;
6047*4882a593Smuzhiyun
6048*4882a593Smuzhiyun /* Bypass if same domain and area of adapter. */
6049*4882a593Smuzhiyun if (((new_fcport->d_id.b24 & 0xffff00) ==
6050*4882a593Smuzhiyun (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
6051*4882a593Smuzhiyun ISP_CFG_FL)
6052*4882a593Smuzhiyun continue;
6053*4882a593Smuzhiyun
6054*4882a593Smuzhiyun /* Bypass reserved domain fields. */
6055*4882a593Smuzhiyun if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
6056*4882a593Smuzhiyun continue;
6057*4882a593Smuzhiyun
6058*4882a593Smuzhiyun /* Bypass ports whose FCP-4 type is not FCP_SCSI */
6059*4882a593Smuzhiyun if (ql2xgffidenable &&
6060*4882a593Smuzhiyun (!(new_fcport->fc4_type & FS_FC4TYPE_FCP) &&
6061*4882a593Smuzhiyun new_fcport->fc4_type != 0))
6062*4882a593Smuzhiyun continue;
6063*4882a593Smuzhiyun
6064*4882a593Smuzhiyun spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
6065*4882a593Smuzhiyun
6066*4882a593Smuzhiyun /* Locate matching device in database. */
6067*4882a593Smuzhiyun found = 0;
6068*4882a593Smuzhiyun list_for_each_entry(fcport, &vha->vp_fcports, list) {
6069*4882a593Smuzhiyun if (memcmp(new_fcport->port_name, fcport->port_name,
6070*4882a593Smuzhiyun WWN_SIZE))
6071*4882a593Smuzhiyun continue;
6072*4882a593Smuzhiyun
6073*4882a593Smuzhiyun fcport->scan_state = QLA_FCPORT_FOUND;
6074*4882a593Smuzhiyun
6075*4882a593Smuzhiyun found++;
6076*4882a593Smuzhiyun
6077*4882a593Smuzhiyun /* Update port state. */
6078*4882a593Smuzhiyun memcpy(fcport->fabric_port_name,
6079*4882a593Smuzhiyun new_fcport->fabric_port_name, WWN_SIZE);
6080*4882a593Smuzhiyun fcport->fp_speed = new_fcport->fp_speed;
6081*4882a593Smuzhiyun
6082*4882a593Smuzhiyun /*
6083*4882a593Smuzhiyun * If address the same and state FCS_ONLINE
6084*4882a593Smuzhiyun * (or in target mode), nothing changed.
6085*4882a593Smuzhiyun */
6086*4882a593Smuzhiyun if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
6087*4882a593Smuzhiyun (atomic_read(&fcport->state) == FCS_ONLINE ||
6088*4882a593Smuzhiyun (vha->host->active_mode == MODE_TARGET))) {
6089*4882a593Smuzhiyun break;
6090*4882a593Smuzhiyun }
6091*4882a593Smuzhiyun
6092*4882a593Smuzhiyun /*
6093*4882a593Smuzhiyun * If device was not a fabric device before.
6094*4882a593Smuzhiyun */
6095*4882a593Smuzhiyun if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
6096*4882a593Smuzhiyun fcport->d_id.b24 = new_fcport->d_id.b24;
6097*4882a593Smuzhiyun qla2x00_clear_loop_id(fcport);
6098*4882a593Smuzhiyun fcport->flags |= (FCF_FABRIC_DEVICE |
6099*4882a593Smuzhiyun FCF_LOGIN_NEEDED);
6100*4882a593Smuzhiyun break;
6101*4882a593Smuzhiyun }
6102*4882a593Smuzhiyun
6103*4882a593Smuzhiyun /*
6104*4882a593Smuzhiyun * Port ID changed or device was marked to be updated;
6105*4882a593Smuzhiyun * Log it out if still logged in and mark it for
6106*4882a593Smuzhiyun * relogin later.
6107*4882a593Smuzhiyun */
6108*4882a593Smuzhiyun if (qla_tgt_mode_enabled(base_vha)) {
6109*4882a593Smuzhiyun ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080,
6110*4882a593Smuzhiyun "port changed FC ID, %8phC"
6111*4882a593Smuzhiyun " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n",
6112*4882a593Smuzhiyun fcport->port_name,
6113*4882a593Smuzhiyun fcport->d_id.b.domain,
6114*4882a593Smuzhiyun fcport->d_id.b.area,
6115*4882a593Smuzhiyun fcport->d_id.b.al_pa,
6116*4882a593Smuzhiyun fcport->loop_id,
6117*4882a593Smuzhiyun new_fcport->d_id.b.domain,
6118*4882a593Smuzhiyun new_fcport->d_id.b.area,
6119*4882a593Smuzhiyun new_fcport->d_id.b.al_pa);
6120*4882a593Smuzhiyun fcport->d_id.b24 = new_fcport->d_id.b24;
6121*4882a593Smuzhiyun break;
6122*4882a593Smuzhiyun }
6123*4882a593Smuzhiyun
6124*4882a593Smuzhiyun fcport->d_id.b24 = new_fcport->d_id.b24;
6125*4882a593Smuzhiyun fcport->flags |= FCF_LOGIN_NEEDED;
6126*4882a593Smuzhiyun break;
6127*4882a593Smuzhiyun }
6128*4882a593Smuzhiyun
6129*4882a593Smuzhiyun if (found && NVME_TARGET(vha->hw, fcport)) {
6130*4882a593Smuzhiyun if (fcport->disc_state == DSC_DELETE_PEND) {
6131*4882a593Smuzhiyun qla2x00_set_fcport_disc_state(fcport, DSC_GNL);
6132*4882a593Smuzhiyun vha->fcport_count--;
6133*4882a593Smuzhiyun fcport->login_succ = 0;
6134*4882a593Smuzhiyun }
6135*4882a593Smuzhiyun }
6136*4882a593Smuzhiyun
6137*4882a593Smuzhiyun if (found) {
6138*4882a593Smuzhiyun spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
6139*4882a593Smuzhiyun continue;
6140*4882a593Smuzhiyun }
6141*4882a593Smuzhiyun /* If device was not in our fcports list, then add it. */
6142*4882a593Smuzhiyun new_fcport->scan_state = QLA_FCPORT_FOUND;
6143*4882a593Smuzhiyun list_add_tail(&new_fcport->list, &vha->vp_fcports);
6144*4882a593Smuzhiyun
6145*4882a593Smuzhiyun spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
6146*4882a593Smuzhiyun
6147*4882a593Smuzhiyun
6148*4882a593Smuzhiyun /* Allocate a new replacement fcport. */
6149*4882a593Smuzhiyun nxt_d_id.b24 = new_fcport->d_id.b24;
6150*4882a593Smuzhiyun new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
6151*4882a593Smuzhiyun if (new_fcport == NULL) {
6152*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0xd032,
6153*4882a593Smuzhiyun "Memory allocation failed for fcport.\n");
6154*4882a593Smuzhiyun return (QLA_MEMORY_ALLOC_FAILED);
6155*4882a593Smuzhiyun }
6156*4882a593Smuzhiyun new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
6157*4882a593Smuzhiyun new_fcport->d_id.b24 = nxt_d_id.b24;
6158*4882a593Smuzhiyun }
6159*4882a593Smuzhiyun
6160*4882a593Smuzhiyun qla2x00_free_fcport(new_fcport);
6161*4882a593Smuzhiyun
6162*4882a593Smuzhiyun /*
6163*4882a593Smuzhiyun * Logout all previous fabric dev marked lost, except FCP2 devices.
6164*4882a593Smuzhiyun */
6165*4882a593Smuzhiyun list_for_each_entry(fcport, &vha->vp_fcports, list) {
6166*4882a593Smuzhiyun if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
6167*4882a593Smuzhiyun break;
6168*4882a593Smuzhiyun
6169*4882a593Smuzhiyun if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
6170*4882a593Smuzhiyun continue;
6171*4882a593Smuzhiyun
6172*4882a593Smuzhiyun if (fcport->scan_state == QLA_FCPORT_SCAN) {
6173*4882a593Smuzhiyun if ((qla_dual_mode_enabled(vha) ||
6174*4882a593Smuzhiyun qla_ini_mode_enabled(vha)) &&
6175*4882a593Smuzhiyun atomic_read(&fcport->state) == FCS_ONLINE) {
6176*4882a593Smuzhiyun qla2x00_mark_device_lost(vha, fcport,
6177*4882a593Smuzhiyun ql2xplogiabsentdevice);
6178*4882a593Smuzhiyun if (fcport->loop_id != FC_NO_LOOP_ID &&
6179*4882a593Smuzhiyun (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
6180*4882a593Smuzhiyun fcport->port_type != FCT_INITIATOR &&
6181*4882a593Smuzhiyun fcport->port_type != FCT_BROADCAST) {
6182*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x20f0,
6183*4882a593Smuzhiyun "%s %d %8phC post del sess\n",
6184*4882a593Smuzhiyun __func__, __LINE__,
6185*4882a593Smuzhiyun fcport->port_name);
6186*4882a593Smuzhiyun qlt_schedule_sess_for_deletion(fcport);
6187*4882a593Smuzhiyun continue;
6188*4882a593Smuzhiyun }
6189*4882a593Smuzhiyun }
6190*4882a593Smuzhiyun }
6191*4882a593Smuzhiyun
6192*4882a593Smuzhiyun if (fcport->scan_state == QLA_FCPORT_FOUND &&
6193*4882a593Smuzhiyun (fcport->flags & FCF_LOGIN_NEEDED) != 0)
6194*4882a593Smuzhiyun qla24xx_fcport_handle_login(vha, fcport);
6195*4882a593Smuzhiyun }
6196*4882a593Smuzhiyun return (rval);
6197*4882a593Smuzhiyun }
6198*4882a593Smuzhiyun
6199*4882a593Smuzhiyun /* FW does not set aside Loop id for MGMT Server/FFFFFAh */
6200*4882a593Smuzhiyun int
qla2x00_reserve_mgmt_server_loop_id(scsi_qla_host_t * vha)6201*4882a593Smuzhiyun qla2x00_reserve_mgmt_server_loop_id(scsi_qla_host_t *vha)
6202*4882a593Smuzhiyun {
6203*4882a593Smuzhiyun int loop_id = FC_NO_LOOP_ID;
6204*4882a593Smuzhiyun int lid = NPH_MGMT_SERVER - vha->vp_idx;
6205*4882a593Smuzhiyun unsigned long flags;
6206*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
6207*4882a593Smuzhiyun
6208*4882a593Smuzhiyun if (vha->vp_idx == 0) {
6209*4882a593Smuzhiyun set_bit(NPH_MGMT_SERVER, ha->loop_id_map);
6210*4882a593Smuzhiyun return NPH_MGMT_SERVER;
6211*4882a593Smuzhiyun }
6212*4882a593Smuzhiyun
6213*4882a593Smuzhiyun /* pick id from high and work down to low */
6214*4882a593Smuzhiyun spin_lock_irqsave(&ha->vport_slock, flags);
6215*4882a593Smuzhiyun for (; lid > 0; lid--) {
6216*4882a593Smuzhiyun if (!test_bit(lid, vha->hw->loop_id_map)) {
6217*4882a593Smuzhiyun set_bit(lid, vha->hw->loop_id_map);
6218*4882a593Smuzhiyun loop_id = lid;
6219*4882a593Smuzhiyun break;
6220*4882a593Smuzhiyun }
6221*4882a593Smuzhiyun }
6222*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->vport_slock, flags);
6223*4882a593Smuzhiyun
6224*4882a593Smuzhiyun return loop_id;
6225*4882a593Smuzhiyun }
6226*4882a593Smuzhiyun
6227*4882a593Smuzhiyun /*
6228*4882a593Smuzhiyun * qla2x00_fabric_login
6229*4882a593Smuzhiyun * Issue fabric login command.
6230*4882a593Smuzhiyun *
6231*4882a593Smuzhiyun * Input:
6232*4882a593Smuzhiyun * ha = adapter block pointer.
6233*4882a593Smuzhiyun * device = pointer to FC device type structure.
6234*4882a593Smuzhiyun *
6235*4882a593Smuzhiyun * Returns:
6236*4882a593Smuzhiyun * 0 - Login successfully
6237*4882a593Smuzhiyun * 1 - Login failed
6238*4882a593Smuzhiyun * 2 - Initiator device
6239*4882a593Smuzhiyun * 3 - Fatal error
6240*4882a593Smuzhiyun */
6241*4882a593Smuzhiyun int
qla2x00_fabric_login(scsi_qla_host_t * vha,fc_port_t * fcport,uint16_t * next_loopid)6242*4882a593Smuzhiyun qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
6243*4882a593Smuzhiyun uint16_t *next_loopid)
6244*4882a593Smuzhiyun {
6245*4882a593Smuzhiyun int rval;
6246*4882a593Smuzhiyun int retry;
6247*4882a593Smuzhiyun uint16_t tmp_loopid;
6248*4882a593Smuzhiyun uint16_t mb[MAILBOX_REGISTER_COUNT];
6249*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
6250*4882a593Smuzhiyun
6251*4882a593Smuzhiyun retry = 0;
6252*4882a593Smuzhiyun tmp_loopid = 0;
6253*4882a593Smuzhiyun
6254*4882a593Smuzhiyun for (;;) {
6255*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2000,
6256*4882a593Smuzhiyun "Trying Fabric Login w/loop id 0x%04x for port "
6257*4882a593Smuzhiyun "%02x%02x%02x.\n",
6258*4882a593Smuzhiyun fcport->loop_id, fcport->d_id.b.domain,
6259*4882a593Smuzhiyun fcport->d_id.b.area, fcport->d_id.b.al_pa);
6260*4882a593Smuzhiyun
6261*4882a593Smuzhiyun /* Login fcport on switch. */
6262*4882a593Smuzhiyun rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
6263*4882a593Smuzhiyun fcport->d_id.b.domain, fcport->d_id.b.area,
6264*4882a593Smuzhiyun fcport->d_id.b.al_pa, mb, BIT_0);
6265*4882a593Smuzhiyun if (rval != QLA_SUCCESS) {
6266*4882a593Smuzhiyun return rval;
6267*4882a593Smuzhiyun }
6268*4882a593Smuzhiyun if (mb[0] == MBS_PORT_ID_USED) {
6269*4882a593Smuzhiyun /*
6270*4882a593Smuzhiyun * Device has another loop ID. The firmware team
6271*4882a593Smuzhiyun * recommends the driver perform an implicit login with
6272*4882a593Smuzhiyun * the specified ID again. The ID we just used is save
6273*4882a593Smuzhiyun * here so we return with an ID that can be tried by
6274*4882a593Smuzhiyun * the next login.
6275*4882a593Smuzhiyun */
6276*4882a593Smuzhiyun retry++;
6277*4882a593Smuzhiyun tmp_loopid = fcport->loop_id;
6278*4882a593Smuzhiyun fcport->loop_id = mb[1];
6279*4882a593Smuzhiyun
6280*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2001,
6281*4882a593Smuzhiyun "Fabric Login: port in use - next loop "
6282*4882a593Smuzhiyun "id=0x%04x, port id= %02x%02x%02x.\n",
6283*4882a593Smuzhiyun fcport->loop_id, fcport->d_id.b.domain,
6284*4882a593Smuzhiyun fcport->d_id.b.area, fcport->d_id.b.al_pa);
6285*4882a593Smuzhiyun
6286*4882a593Smuzhiyun } else if (mb[0] == MBS_COMMAND_COMPLETE) {
6287*4882a593Smuzhiyun /*
6288*4882a593Smuzhiyun * Login succeeded.
6289*4882a593Smuzhiyun */
6290*4882a593Smuzhiyun if (retry) {
6291*4882a593Smuzhiyun /* A retry occurred before. */
6292*4882a593Smuzhiyun *next_loopid = tmp_loopid;
6293*4882a593Smuzhiyun } else {
6294*4882a593Smuzhiyun /*
6295*4882a593Smuzhiyun * No retry occurred before. Just increment the
6296*4882a593Smuzhiyun * ID value for next login.
6297*4882a593Smuzhiyun */
6298*4882a593Smuzhiyun *next_loopid = (fcport->loop_id + 1);
6299*4882a593Smuzhiyun }
6300*4882a593Smuzhiyun
6301*4882a593Smuzhiyun if (mb[1] & BIT_0) {
6302*4882a593Smuzhiyun fcport->port_type = FCT_INITIATOR;
6303*4882a593Smuzhiyun } else {
6304*4882a593Smuzhiyun fcport->port_type = FCT_TARGET;
6305*4882a593Smuzhiyun if (mb[1] & BIT_1) {
6306*4882a593Smuzhiyun fcport->flags |= FCF_FCP2_DEVICE;
6307*4882a593Smuzhiyun }
6308*4882a593Smuzhiyun }
6309*4882a593Smuzhiyun
6310*4882a593Smuzhiyun if (mb[10] & BIT_0)
6311*4882a593Smuzhiyun fcport->supported_classes |= FC_COS_CLASS2;
6312*4882a593Smuzhiyun if (mb[10] & BIT_1)
6313*4882a593Smuzhiyun fcport->supported_classes |= FC_COS_CLASS3;
6314*4882a593Smuzhiyun
6315*4882a593Smuzhiyun if (IS_FWI2_CAPABLE(ha)) {
6316*4882a593Smuzhiyun if (mb[10] & BIT_7)
6317*4882a593Smuzhiyun fcport->flags |=
6318*4882a593Smuzhiyun FCF_CONF_COMP_SUPPORTED;
6319*4882a593Smuzhiyun }
6320*4882a593Smuzhiyun
6321*4882a593Smuzhiyun rval = QLA_SUCCESS;
6322*4882a593Smuzhiyun break;
6323*4882a593Smuzhiyun } else if (mb[0] == MBS_LOOP_ID_USED) {
6324*4882a593Smuzhiyun /*
6325*4882a593Smuzhiyun * Loop ID already used, try next loop ID.
6326*4882a593Smuzhiyun */
6327*4882a593Smuzhiyun fcport->loop_id++;
6328*4882a593Smuzhiyun rval = qla2x00_find_new_loop_id(vha, fcport);
6329*4882a593Smuzhiyun if (rval != QLA_SUCCESS) {
6330*4882a593Smuzhiyun /* Ran out of loop IDs to use */
6331*4882a593Smuzhiyun break;
6332*4882a593Smuzhiyun }
6333*4882a593Smuzhiyun } else if (mb[0] == MBS_COMMAND_ERROR) {
6334*4882a593Smuzhiyun /*
6335*4882a593Smuzhiyun * Firmware possibly timed out during login. If NO
6336*4882a593Smuzhiyun * retries are left to do then the device is declared
6337*4882a593Smuzhiyun * dead.
6338*4882a593Smuzhiyun */
6339*4882a593Smuzhiyun *next_loopid = fcport->loop_id;
6340*4882a593Smuzhiyun ha->isp_ops->fabric_logout(vha, fcport->loop_id,
6341*4882a593Smuzhiyun fcport->d_id.b.domain, fcport->d_id.b.area,
6342*4882a593Smuzhiyun fcport->d_id.b.al_pa);
6343*4882a593Smuzhiyun qla2x00_mark_device_lost(vha, fcport, 1);
6344*4882a593Smuzhiyun
6345*4882a593Smuzhiyun rval = 1;
6346*4882a593Smuzhiyun break;
6347*4882a593Smuzhiyun } else {
6348*4882a593Smuzhiyun /*
6349*4882a593Smuzhiyun * unrecoverable / not handled error
6350*4882a593Smuzhiyun */
6351*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x2002,
6352*4882a593Smuzhiyun "Failed=%x port_id=%02x%02x%02x loop_id=%x "
6353*4882a593Smuzhiyun "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
6354*4882a593Smuzhiyun fcport->d_id.b.area, fcport->d_id.b.al_pa,
6355*4882a593Smuzhiyun fcport->loop_id, jiffies);
6356*4882a593Smuzhiyun
6357*4882a593Smuzhiyun *next_loopid = fcport->loop_id;
6358*4882a593Smuzhiyun ha->isp_ops->fabric_logout(vha, fcport->loop_id,
6359*4882a593Smuzhiyun fcport->d_id.b.domain, fcport->d_id.b.area,
6360*4882a593Smuzhiyun fcport->d_id.b.al_pa);
6361*4882a593Smuzhiyun qla2x00_clear_loop_id(fcport);
6362*4882a593Smuzhiyun fcport->login_retry = 0;
6363*4882a593Smuzhiyun
6364*4882a593Smuzhiyun rval = 3;
6365*4882a593Smuzhiyun break;
6366*4882a593Smuzhiyun }
6367*4882a593Smuzhiyun }
6368*4882a593Smuzhiyun
6369*4882a593Smuzhiyun return (rval);
6370*4882a593Smuzhiyun }
6371*4882a593Smuzhiyun
6372*4882a593Smuzhiyun /*
6373*4882a593Smuzhiyun * qla2x00_local_device_login
6374*4882a593Smuzhiyun * Issue local device login command.
6375*4882a593Smuzhiyun *
6376*4882a593Smuzhiyun * Input:
6377*4882a593Smuzhiyun * ha = adapter block pointer.
6378*4882a593Smuzhiyun * loop_id = loop id of device to login to.
6379*4882a593Smuzhiyun *
6380*4882a593Smuzhiyun * Returns (Where's the #define!!!!):
6381*4882a593Smuzhiyun * 0 - Login successfully
6382*4882a593Smuzhiyun * 1 - Login failed
6383*4882a593Smuzhiyun * 3 - Fatal error
6384*4882a593Smuzhiyun */
6385*4882a593Smuzhiyun int
qla2x00_local_device_login(scsi_qla_host_t * vha,fc_port_t * fcport)6386*4882a593Smuzhiyun qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
6387*4882a593Smuzhiyun {
6388*4882a593Smuzhiyun int rval;
6389*4882a593Smuzhiyun uint16_t mb[MAILBOX_REGISTER_COUNT];
6390*4882a593Smuzhiyun
6391*4882a593Smuzhiyun memset(mb, 0, sizeof(mb));
6392*4882a593Smuzhiyun rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
6393*4882a593Smuzhiyun if (rval == QLA_SUCCESS) {
6394*4882a593Smuzhiyun /* Interrogate mailbox registers for any errors */
6395*4882a593Smuzhiyun if (mb[0] == MBS_COMMAND_ERROR)
6396*4882a593Smuzhiyun rval = 1;
6397*4882a593Smuzhiyun else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
6398*4882a593Smuzhiyun /* device not in PCB table */
6399*4882a593Smuzhiyun rval = 3;
6400*4882a593Smuzhiyun }
6401*4882a593Smuzhiyun
6402*4882a593Smuzhiyun return (rval);
6403*4882a593Smuzhiyun }
6404*4882a593Smuzhiyun
6405*4882a593Smuzhiyun /*
6406*4882a593Smuzhiyun * qla2x00_loop_resync
6407*4882a593Smuzhiyun * Resync with fibre channel devices.
6408*4882a593Smuzhiyun *
6409*4882a593Smuzhiyun * Input:
6410*4882a593Smuzhiyun * ha = adapter block pointer.
6411*4882a593Smuzhiyun *
6412*4882a593Smuzhiyun * Returns:
6413*4882a593Smuzhiyun * 0 = success
6414*4882a593Smuzhiyun */
6415*4882a593Smuzhiyun int
qla2x00_loop_resync(scsi_qla_host_t * vha)6416*4882a593Smuzhiyun qla2x00_loop_resync(scsi_qla_host_t *vha)
6417*4882a593Smuzhiyun {
6418*4882a593Smuzhiyun int rval = QLA_SUCCESS;
6419*4882a593Smuzhiyun uint32_t wait_time;
6420*4882a593Smuzhiyun
6421*4882a593Smuzhiyun clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6422*4882a593Smuzhiyun if (vha->flags.online) {
6423*4882a593Smuzhiyun if (!(rval = qla2x00_fw_ready(vha))) {
6424*4882a593Smuzhiyun /* Wait at most MAX_TARGET RSCNs for a stable link. */
6425*4882a593Smuzhiyun wait_time = 256;
6426*4882a593Smuzhiyun do {
6427*4882a593Smuzhiyun if (!IS_QLAFX00(vha->hw)) {
6428*4882a593Smuzhiyun /*
6429*4882a593Smuzhiyun * Issue a marker after FW becomes
6430*4882a593Smuzhiyun * ready.
6431*4882a593Smuzhiyun */
6432*4882a593Smuzhiyun qla2x00_marker(vha, vha->hw->base_qpair,
6433*4882a593Smuzhiyun 0, 0, MK_SYNC_ALL);
6434*4882a593Smuzhiyun vha->marker_needed = 0;
6435*4882a593Smuzhiyun }
6436*4882a593Smuzhiyun
6437*4882a593Smuzhiyun /* Remap devices on Loop. */
6438*4882a593Smuzhiyun clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
6439*4882a593Smuzhiyun
6440*4882a593Smuzhiyun if (IS_QLAFX00(vha->hw))
6441*4882a593Smuzhiyun qlafx00_configure_devices(vha);
6442*4882a593Smuzhiyun else
6443*4882a593Smuzhiyun qla2x00_configure_loop(vha);
6444*4882a593Smuzhiyun
6445*4882a593Smuzhiyun wait_time--;
6446*4882a593Smuzhiyun } while (!atomic_read(&vha->loop_down_timer) &&
6447*4882a593Smuzhiyun !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
6448*4882a593Smuzhiyun && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
6449*4882a593Smuzhiyun &vha->dpc_flags)));
6450*4882a593Smuzhiyun }
6451*4882a593Smuzhiyun }
6452*4882a593Smuzhiyun
6453*4882a593Smuzhiyun if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
6454*4882a593Smuzhiyun return (QLA_FUNCTION_FAILED);
6455*4882a593Smuzhiyun
6456*4882a593Smuzhiyun if (rval)
6457*4882a593Smuzhiyun ql_dbg(ql_dbg_disc, vha, 0x206c,
6458*4882a593Smuzhiyun "%s *** FAILED ***.\n", __func__);
6459*4882a593Smuzhiyun
6460*4882a593Smuzhiyun return (rval);
6461*4882a593Smuzhiyun }
6462*4882a593Smuzhiyun
6463*4882a593Smuzhiyun /*
6464*4882a593Smuzhiyun * qla2x00_perform_loop_resync
6465*4882a593Smuzhiyun * Description: This function will set the appropriate flags and call
6466*4882a593Smuzhiyun * qla2x00_loop_resync. If successful loop will be resynced
6467*4882a593Smuzhiyun * Arguments : scsi_qla_host_t pointer
6468*4882a593Smuzhiyun * returm : Success or Failure
6469*4882a593Smuzhiyun */
6470*4882a593Smuzhiyun
qla2x00_perform_loop_resync(scsi_qla_host_t * ha)6471*4882a593Smuzhiyun int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
6472*4882a593Smuzhiyun {
6473*4882a593Smuzhiyun int32_t rval = 0;
6474*4882a593Smuzhiyun
6475*4882a593Smuzhiyun if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
6476*4882a593Smuzhiyun /*Configure the flags so that resync happens properly*/
6477*4882a593Smuzhiyun atomic_set(&ha->loop_down_timer, 0);
6478*4882a593Smuzhiyun if (!(ha->device_flags & DFLG_NO_CABLE)) {
6479*4882a593Smuzhiyun atomic_set(&ha->loop_state, LOOP_UP);
6480*4882a593Smuzhiyun set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
6481*4882a593Smuzhiyun set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
6482*4882a593Smuzhiyun set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
6483*4882a593Smuzhiyun
6484*4882a593Smuzhiyun rval = qla2x00_loop_resync(ha);
6485*4882a593Smuzhiyun } else
6486*4882a593Smuzhiyun atomic_set(&ha->loop_state, LOOP_DEAD);
6487*4882a593Smuzhiyun
6488*4882a593Smuzhiyun clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
6489*4882a593Smuzhiyun }
6490*4882a593Smuzhiyun
6491*4882a593Smuzhiyun return rval;
6492*4882a593Smuzhiyun }
6493*4882a593Smuzhiyun
6494*4882a593Smuzhiyun void
qla2x00_update_fcports(scsi_qla_host_t * base_vha)6495*4882a593Smuzhiyun qla2x00_update_fcports(scsi_qla_host_t *base_vha)
6496*4882a593Smuzhiyun {
6497*4882a593Smuzhiyun fc_port_t *fcport;
6498*4882a593Smuzhiyun struct scsi_qla_host *vha;
6499*4882a593Smuzhiyun struct qla_hw_data *ha = base_vha->hw;
6500*4882a593Smuzhiyun unsigned long flags;
6501*4882a593Smuzhiyun
6502*4882a593Smuzhiyun spin_lock_irqsave(&ha->vport_slock, flags);
6503*4882a593Smuzhiyun /* Go with deferred removal of rport references. */
6504*4882a593Smuzhiyun list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
6505*4882a593Smuzhiyun atomic_inc(&vha->vref_count);
6506*4882a593Smuzhiyun list_for_each_entry(fcport, &vha->vp_fcports, list) {
6507*4882a593Smuzhiyun if (fcport->drport &&
6508*4882a593Smuzhiyun atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
6509*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->vport_slock, flags);
6510*4882a593Smuzhiyun qla2x00_rport_del(fcport);
6511*4882a593Smuzhiyun
6512*4882a593Smuzhiyun spin_lock_irqsave(&ha->vport_slock, flags);
6513*4882a593Smuzhiyun }
6514*4882a593Smuzhiyun }
6515*4882a593Smuzhiyun atomic_dec(&vha->vref_count);
6516*4882a593Smuzhiyun wake_up(&vha->vref_waitq);
6517*4882a593Smuzhiyun }
6518*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->vport_slock, flags);
6519*4882a593Smuzhiyun }
6520*4882a593Smuzhiyun
6521*4882a593Smuzhiyun /* Assumes idc_lock always held on entry */
6522*4882a593Smuzhiyun void
qla83xx_reset_ownership(scsi_qla_host_t * vha)6523*4882a593Smuzhiyun qla83xx_reset_ownership(scsi_qla_host_t *vha)
6524*4882a593Smuzhiyun {
6525*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
6526*4882a593Smuzhiyun uint32_t drv_presence, drv_presence_mask;
6527*4882a593Smuzhiyun uint32_t dev_part_info1, dev_part_info2, class_type;
6528*4882a593Smuzhiyun uint32_t class_type_mask = 0x3;
6529*4882a593Smuzhiyun uint16_t fcoe_other_function = 0xffff, i;
6530*4882a593Smuzhiyun
6531*4882a593Smuzhiyun if (IS_QLA8044(ha)) {
6532*4882a593Smuzhiyun drv_presence = qla8044_rd_direct(vha,
6533*4882a593Smuzhiyun QLA8044_CRB_DRV_ACTIVE_INDEX);
6534*4882a593Smuzhiyun dev_part_info1 = qla8044_rd_direct(vha,
6535*4882a593Smuzhiyun QLA8044_CRB_DEV_PART_INFO_INDEX);
6536*4882a593Smuzhiyun dev_part_info2 = qla8044_rd_direct(vha,
6537*4882a593Smuzhiyun QLA8044_CRB_DEV_PART_INFO2);
6538*4882a593Smuzhiyun } else {
6539*4882a593Smuzhiyun qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6540*4882a593Smuzhiyun qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
6541*4882a593Smuzhiyun qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
6542*4882a593Smuzhiyun }
6543*4882a593Smuzhiyun for (i = 0; i < 8; i++) {
6544*4882a593Smuzhiyun class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
6545*4882a593Smuzhiyun if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
6546*4882a593Smuzhiyun (i != ha->portnum)) {
6547*4882a593Smuzhiyun fcoe_other_function = i;
6548*4882a593Smuzhiyun break;
6549*4882a593Smuzhiyun }
6550*4882a593Smuzhiyun }
6551*4882a593Smuzhiyun if (fcoe_other_function == 0xffff) {
6552*4882a593Smuzhiyun for (i = 0; i < 8; i++) {
6553*4882a593Smuzhiyun class_type = ((dev_part_info2 >> (i * 4)) &
6554*4882a593Smuzhiyun class_type_mask);
6555*4882a593Smuzhiyun if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
6556*4882a593Smuzhiyun ((i + 8) != ha->portnum)) {
6557*4882a593Smuzhiyun fcoe_other_function = i + 8;
6558*4882a593Smuzhiyun break;
6559*4882a593Smuzhiyun }
6560*4882a593Smuzhiyun }
6561*4882a593Smuzhiyun }
6562*4882a593Smuzhiyun /*
6563*4882a593Smuzhiyun * Prepare drv-presence mask based on fcoe functions present.
6564*4882a593Smuzhiyun * However consider only valid physical fcoe function numbers (0-15).
6565*4882a593Smuzhiyun */
6566*4882a593Smuzhiyun drv_presence_mask = ~((1 << (ha->portnum)) |
6567*4882a593Smuzhiyun ((fcoe_other_function == 0xffff) ?
6568*4882a593Smuzhiyun 0 : (1 << (fcoe_other_function))));
6569*4882a593Smuzhiyun
6570*4882a593Smuzhiyun /* We are the reset owner iff:
6571*4882a593Smuzhiyun * - No other protocol drivers present.
6572*4882a593Smuzhiyun * - This is the lowest among fcoe functions. */
6573*4882a593Smuzhiyun if (!(drv_presence & drv_presence_mask) &&
6574*4882a593Smuzhiyun (ha->portnum < fcoe_other_function)) {
6575*4882a593Smuzhiyun ql_dbg(ql_dbg_p3p, vha, 0xb07f,
6576*4882a593Smuzhiyun "This host is Reset owner.\n");
6577*4882a593Smuzhiyun ha->flags.nic_core_reset_owner = 1;
6578*4882a593Smuzhiyun }
6579*4882a593Smuzhiyun }
6580*4882a593Smuzhiyun
6581*4882a593Smuzhiyun static int
__qla83xx_set_drv_ack(scsi_qla_host_t * vha)6582*4882a593Smuzhiyun __qla83xx_set_drv_ack(scsi_qla_host_t *vha)
6583*4882a593Smuzhiyun {
6584*4882a593Smuzhiyun int rval = QLA_SUCCESS;
6585*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
6586*4882a593Smuzhiyun uint32_t drv_ack;
6587*4882a593Smuzhiyun
6588*4882a593Smuzhiyun rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6589*4882a593Smuzhiyun if (rval == QLA_SUCCESS) {
6590*4882a593Smuzhiyun drv_ack |= (1 << ha->portnum);
6591*4882a593Smuzhiyun rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
6592*4882a593Smuzhiyun }
6593*4882a593Smuzhiyun
6594*4882a593Smuzhiyun return rval;
6595*4882a593Smuzhiyun }
6596*4882a593Smuzhiyun
6597*4882a593Smuzhiyun static int
__qla83xx_clear_drv_ack(scsi_qla_host_t * vha)6598*4882a593Smuzhiyun __qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
6599*4882a593Smuzhiyun {
6600*4882a593Smuzhiyun int rval = QLA_SUCCESS;
6601*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
6602*4882a593Smuzhiyun uint32_t drv_ack;
6603*4882a593Smuzhiyun
6604*4882a593Smuzhiyun rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6605*4882a593Smuzhiyun if (rval == QLA_SUCCESS) {
6606*4882a593Smuzhiyun drv_ack &= ~(1 << ha->portnum);
6607*4882a593Smuzhiyun rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
6608*4882a593Smuzhiyun }
6609*4882a593Smuzhiyun
6610*4882a593Smuzhiyun return rval;
6611*4882a593Smuzhiyun }
6612*4882a593Smuzhiyun
6613*4882a593Smuzhiyun static const char *
qla83xx_dev_state_to_string(uint32_t dev_state)6614*4882a593Smuzhiyun qla83xx_dev_state_to_string(uint32_t dev_state)
6615*4882a593Smuzhiyun {
6616*4882a593Smuzhiyun switch (dev_state) {
6617*4882a593Smuzhiyun case QLA8XXX_DEV_COLD:
6618*4882a593Smuzhiyun return "COLD/RE-INIT";
6619*4882a593Smuzhiyun case QLA8XXX_DEV_INITIALIZING:
6620*4882a593Smuzhiyun return "INITIALIZING";
6621*4882a593Smuzhiyun case QLA8XXX_DEV_READY:
6622*4882a593Smuzhiyun return "READY";
6623*4882a593Smuzhiyun case QLA8XXX_DEV_NEED_RESET:
6624*4882a593Smuzhiyun return "NEED RESET";
6625*4882a593Smuzhiyun case QLA8XXX_DEV_NEED_QUIESCENT:
6626*4882a593Smuzhiyun return "NEED QUIESCENT";
6627*4882a593Smuzhiyun case QLA8XXX_DEV_FAILED:
6628*4882a593Smuzhiyun return "FAILED";
6629*4882a593Smuzhiyun case QLA8XXX_DEV_QUIESCENT:
6630*4882a593Smuzhiyun return "QUIESCENT";
6631*4882a593Smuzhiyun default:
6632*4882a593Smuzhiyun return "Unknown";
6633*4882a593Smuzhiyun }
6634*4882a593Smuzhiyun }
6635*4882a593Smuzhiyun
6636*4882a593Smuzhiyun /* Assumes idc-lock always held on entry */
6637*4882a593Smuzhiyun void
qla83xx_idc_audit(scsi_qla_host_t * vha,int audit_type)6638*4882a593Smuzhiyun qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
6639*4882a593Smuzhiyun {
6640*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
6641*4882a593Smuzhiyun uint32_t idc_audit_reg = 0, duration_secs = 0;
6642*4882a593Smuzhiyun
6643*4882a593Smuzhiyun switch (audit_type) {
6644*4882a593Smuzhiyun case IDC_AUDIT_TIMESTAMP:
6645*4882a593Smuzhiyun ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
6646*4882a593Smuzhiyun idc_audit_reg = (ha->portnum) |
6647*4882a593Smuzhiyun (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
6648*4882a593Smuzhiyun qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
6649*4882a593Smuzhiyun break;
6650*4882a593Smuzhiyun
6651*4882a593Smuzhiyun case IDC_AUDIT_COMPLETION:
6652*4882a593Smuzhiyun duration_secs = ((jiffies_to_msecs(jiffies) -
6653*4882a593Smuzhiyun jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
6654*4882a593Smuzhiyun idc_audit_reg = (ha->portnum) |
6655*4882a593Smuzhiyun (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
6656*4882a593Smuzhiyun qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
6657*4882a593Smuzhiyun break;
6658*4882a593Smuzhiyun
6659*4882a593Smuzhiyun default:
6660*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0xb078,
6661*4882a593Smuzhiyun "Invalid audit type specified.\n");
6662*4882a593Smuzhiyun break;
6663*4882a593Smuzhiyun }
6664*4882a593Smuzhiyun }
6665*4882a593Smuzhiyun
6666*4882a593Smuzhiyun /* Assumes idc_lock always held on entry */
6667*4882a593Smuzhiyun static int
qla83xx_initiating_reset(scsi_qla_host_t * vha)6668*4882a593Smuzhiyun qla83xx_initiating_reset(scsi_qla_host_t *vha)
6669*4882a593Smuzhiyun {
6670*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
6671*4882a593Smuzhiyun uint32_t idc_control, dev_state;
6672*4882a593Smuzhiyun
6673*4882a593Smuzhiyun __qla83xx_get_idc_control(vha, &idc_control);
6674*4882a593Smuzhiyun if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
6675*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0xb080,
6676*4882a593Smuzhiyun "NIC Core reset has been disabled. idc-control=0x%x\n",
6677*4882a593Smuzhiyun idc_control);
6678*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
6679*4882a593Smuzhiyun }
6680*4882a593Smuzhiyun
6681*4882a593Smuzhiyun /* Set NEED-RESET iff in READY state and we are the reset-owner */
6682*4882a593Smuzhiyun qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6683*4882a593Smuzhiyun if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
6684*4882a593Smuzhiyun qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
6685*4882a593Smuzhiyun QLA8XXX_DEV_NEED_RESET);
6686*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
6687*4882a593Smuzhiyun qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
6688*4882a593Smuzhiyun } else {
6689*4882a593Smuzhiyun const char *state = qla83xx_dev_state_to_string(dev_state);
6690*4882a593Smuzhiyun
6691*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
6692*4882a593Smuzhiyun
6693*4882a593Smuzhiyun /* SV: XXX: Is timeout required here? */
6694*4882a593Smuzhiyun /* Wait for IDC state change READY -> NEED_RESET */
6695*4882a593Smuzhiyun while (dev_state == QLA8XXX_DEV_READY) {
6696*4882a593Smuzhiyun qla83xx_idc_unlock(vha, 0);
6697*4882a593Smuzhiyun msleep(200);
6698*4882a593Smuzhiyun qla83xx_idc_lock(vha, 0);
6699*4882a593Smuzhiyun qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6700*4882a593Smuzhiyun }
6701*4882a593Smuzhiyun }
6702*4882a593Smuzhiyun
6703*4882a593Smuzhiyun /* Send IDC ack by writing to drv-ack register */
6704*4882a593Smuzhiyun __qla83xx_set_drv_ack(vha);
6705*4882a593Smuzhiyun
6706*4882a593Smuzhiyun return QLA_SUCCESS;
6707*4882a593Smuzhiyun }
6708*4882a593Smuzhiyun
6709*4882a593Smuzhiyun int
__qla83xx_set_idc_control(scsi_qla_host_t * vha,uint32_t idc_control)6710*4882a593Smuzhiyun __qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
6711*4882a593Smuzhiyun {
6712*4882a593Smuzhiyun return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
6713*4882a593Smuzhiyun }
6714*4882a593Smuzhiyun
6715*4882a593Smuzhiyun int
__qla83xx_get_idc_control(scsi_qla_host_t * vha,uint32_t * idc_control)6716*4882a593Smuzhiyun __qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
6717*4882a593Smuzhiyun {
6718*4882a593Smuzhiyun return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
6719*4882a593Smuzhiyun }
6720*4882a593Smuzhiyun
6721*4882a593Smuzhiyun static int
qla83xx_check_driver_presence(scsi_qla_host_t * vha)6722*4882a593Smuzhiyun qla83xx_check_driver_presence(scsi_qla_host_t *vha)
6723*4882a593Smuzhiyun {
6724*4882a593Smuzhiyun uint32_t drv_presence = 0;
6725*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
6726*4882a593Smuzhiyun
6727*4882a593Smuzhiyun qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6728*4882a593Smuzhiyun if (drv_presence & (1 << ha->portnum))
6729*4882a593Smuzhiyun return QLA_SUCCESS;
6730*4882a593Smuzhiyun else
6731*4882a593Smuzhiyun return QLA_TEST_FAILED;
6732*4882a593Smuzhiyun }
6733*4882a593Smuzhiyun
6734*4882a593Smuzhiyun int
qla83xx_nic_core_reset(scsi_qla_host_t * vha)6735*4882a593Smuzhiyun qla83xx_nic_core_reset(scsi_qla_host_t *vha)
6736*4882a593Smuzhiyun {
6737*4882a593Smuzhiyun int rval = QLA_SUCCESS;
6738*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
6739*4882a593Smuzhiyun
6740*4882a593Smuzhiyun ql_dbg(ql_dbg_p3p, vha, 0xb058,
6741*4882a593Smuzhiyun "Entered %s().\n", __func__);
6742*4882a593Smuzhiyun
6743*4882a593Smuzhiyun if (vha->device_flags & DFLG_DEV_FAILED) {
6744*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0xb059,
6745*4882a593Smuzhiyun "Device in unrecoverable FAILED state.\n");
6746*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
6747*4882a593Smuzhiyun }
6748*4882a593Smuzhiyun
6749*4882a593Smuzhiyun qla83xx_idc_lock(vha, 0);
6750*4882a593Smuzhiyun
6751*4882a593Smuzhiyun if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
6752*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0xb05a,
6753*4882a593Smuzhiyun "Function=0x%x has been removed from IDC participation.\n",
6754*4882a593Smuzhiyun ha->portnum);
6755*4882a593Smuzhiyun rval = QLA_FUNCTION_FAILED;
6756*4882a593Smuzhiyun goto exit;
6757*4882a593Smuzhiyun }
6758*4882a593Smuzhiyun
6759*4882a593Smuzhiyun qla83xx_reset_ownership(vha);
6760*4882a593Smuzhiyun
6761*4882a593Smuzhiyun rval = qla83xx_initiating_reset(vha);
6762*4882a593Smuzhiyun
6763*4882a593Smuzhiyun /*
6764*4882a593Smuzhiyun * Perform reset if we are the reset-owner,
6765*4882a593Smuzhiyun * else wait till IDC state changes to READY/FAILED.
6766*4882a593Smuzhiyun */
6767*4882a593Smuzhiyun if (rval == QLA_SUCCESS) {
6768*4882a593Smuzhiyun rval = qla83xx_idc_state_handler(vha);
6769*4882a593Smuzhiyun
6770*4882a593Smuzhiyun if (rval == QLA_SUCCESS)
6771*4882a593Smuzhiyun ha->flags.nic_core_hung = 0;
6772*4882a593Smuzhiyun __qla83xx_clear_drv_ack(vha);
6773*4882a593Smuzhiyun }
6774*4882a593Smuzhiyun
6775*4882a593Smuzhiyun exit:
6776*4882a593Smuzhiyun qla83xx_idc_unlock(vha, 0);
6777*4882a593Smuzhiyun
6778*4882a593Smuzhiyun ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
6779*4882a593Smuzhiyun
6780*4882a593Smuzhiyun return rval;
6781*4882a593Smuzhiyun }
6782*4882a593Smuzhiyun
6783*4882a593Smuzhiyun int
qla2xxx_mctp_dump(scsi_qla_host_t * vha)6784*4882a593Smuzhiyun qla2xxx_mctp_dump(scsi_qla_host_t *vha)
6785*4882a593Smuzhiyun {
6786*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
6787*4882a593Smuzhiyun int rval = QLA_FUNCTION_FAILED;
6788*4882a593Smuzhiyun
6789*4882a593Smuzhiyun if (!IS_MCTP_CAPABLE(ha)) {
6790*4882a593Smuzhiyun /* This message can be removed from the final version */
6791*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x506d,
6792*4882a593Smuzhiyun "This board is not MCTP capable\n");
6793*4882a593Smuzhiyun return rval;
6794*4882a593Smuzhiyun }
6795*4882a593Smuzhiyun
6796*4882a593Smuzhiyun if (!ha->mctp_dump) {
6797*4882a593Smuzhiyun ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
6798*4882a593Smuzhiyun MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
6799*4882a593Smuzhiyun
6800*4882a593Smuzhiyun if (!ha->mctp_dump) {
6801*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x506e,
6802*4882a593Smuzhiyun "Failed to allocate memory for mctp dump\n");
6803*4882a593Smuzhiyun return rval;
6804*4882a593Smuzhiyun }
6805*4882a593Smuzhiyun }
6806*4882a593Smuzhiyun
6807*4882a593Smuzhiyun #define MCTP_DUMP_STR_ADDR 0x00000000
6808*4882a593Smuzhiyun rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
6809*4882a593Smuzhiyun MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
6810*4882a593Smuzhiyun if (rval != QLA_SUCCESS) {
6811*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x506f,
6812*4882a593Smuzhiyun "Failed to capture mctp dump\n");
6813*4882a593Smuzhiyun } else {
6814*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x5070,
6815*4882a593Smuzhiyun "Mctp dump capture for host (%ld/%p).\n",
6816*4882a593Smuzhiyun vha->host_no, ha->mctp_dump);
6817*4882a593Smuzhiyun ha->mctp_dumped = 1;
6818*4882a593Smuzhiyun }
6819*4882a593Smuzhiyun
6820*4882a593Smuzhiyun if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
6821*4882a593Smuzhiyun ha->flags.nic_core_reset_hdlr_active = 1;
6822*4882a593Smuzhiyun rval = qla83xx_restart_nic_firmware(vha);
6823*4882a593Smuzhiyun if (rval)
6824*4882a593Smuzhiyun /* NIC Core reset failed. */
6825*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x5071,
6826*4882a593Smuzhiyun "Failed to restart nic firmware\n");
6827*4882a593Smuzhiyun else
6828*4882a593Smuzhiyun ql_dbg(ql_dbg_p3p, vha, 0xb084,
6829*4882a593Smuzhiyun "Restarted NIC firmware successfully.\n");
6830*4882a593Smuzhiyun ha->flags.nic_core_reset_hdlr_active = 0;
6831*4882a593Smuzhiyun }
6832*4882a593Smuzhiyun
6833*4882a593Smuzhiyun return rval;
6834*4882a593Smuzhiyun
6835*4882a593Smuzhiyun }
6836*4882a593Smuzhiyun
6837*4882a593Smuzhiyun /*
6838*4882a593Smuzhiyun * qla2x00_quiesce_io
6839*4882a593Smuzhiyun * Description: This function will block the new I/Os
6840*4882a593Smuzhiyun * Its not aborting any I/Os as context
6841*4882a593Smuzhiyun * is not destroyed during quiescence
6842*4882a593Smuzhiyun * Arguments: scsi_qla_host_t
6843*4882a593Smuzhiyun * return : void
6844*4882a593Smuzhiyun */
6845*4882a593Smuzhiyun void
qla2x00_quiesce_io(scsi_qla_host_t * vha)6846*4882a593Smuzhiyun qla2x00_quiesce_io(scsi_qla_host_t *vha)
6847*4882a593Smuzhiyun {
6848*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
6849*4882a593Smuzhiyun struct scsi_qla_host *vp;
6850*4882a593Smuzhiyun
6851*4882a593Smuzhiyun ql_dbg(ql_dbg_dpc, vha, 0x401d,
6852*4882a593Smuzhiyun "Quiescing I/O - ha=%p.\n", ha);
6853*4882a593Smuzhiyun
6854*4882a593Smuzhiyun atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
6855*4882a593Smuzhiyun if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
6856*4882a593Smuzhiyun atomic_set(&vha->loop_state, LOOP_DOWN);
6857*4882a593Smuzhiyun qla2x00_mark_all_devices_lost(vha);
6858*4882a593Smuzhiyun list_for_each_entry(vp, &ha->vp_list, list)
6859*4882a593Smuzhiyun qla2x00_mark_all_devices_lost(vp);
6860*4882a593Smuzhiyun } else {
6861*4882a593Smuzhiyun if (!atomic_read(&vha->loop_down_timer))
6862*4882a593Smuzhiyun atomic_set(&vha->loop_down_timer,
6863*4882a593Smuzhiyun LOOP_DOWN_TIME);
6864*4882a593Smuzhiyun }
6865*4882a593Smuzhiyun /* Wait for pending cmds to complete */
6866*4882a593Smuzhiyun WARN_ON_ONCE(qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST)
6867*4882a593Smuzhiyun != QLA_SUCCESS);
6868*4882a593Smuzhiyun }
6869*4882a593Smuzhiyun
6870*4882a593Smuzhiyun void
qla2x00_abort_isp_cleanup(scsi_qla_host_t * vha)6871*4882a593Smuzhiyun qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
6872*4882a593Smuzhiyun {
6873*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
6874*4882a593Smuzhiyun struct scsi_qla_host *vp;
6875*4882a593Smuzhiyun unsigned long flags;
6876*4882a593Smuzhiyun fc_port_t *fcport;
6877*4882a593Smuzhiyun u16 i;
6878*4882a593Smuzhiyun
6879*4882a593Smuzhiyun /* For ISP82XX, driver waits for completion of the commands.
6880*4882a593Smuzhiyun * online flag should be set.
6881*4882a593Smuzhiyun */
6882*4882a593Smuzhiyun if (!(IS_P3P_TYPE(ha)))
6883*4882a593Smuzhiyun vha->flags.online = 0;
6884*4882a593Smuzhiyun ha->flags.chip_reset_done = 0;
6885*4882a593Smuzhiyun clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
6886*4882a593Smuzhiyun vha->qla_stats.total_isp_aborts++;
6887*4882a593Smuzhiyun
6888*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x00af,
6889*4882a593Smuzhiyun "Performing ISP error recovery - ha=%p.\n", ha);
6890*4882a593Smuzhiyun
6891*4882a593Smuzhiyun ha->flags.purge_mbox = 1;
6892*4882a593Smuzhiyun /* For ISP82XX, reset_chip is just disabling interrupts.
6893*4882a593Smuzhiyun * Driver waits for the completion of the commands.
6894*4882a593Smuzhiyun * the interrupts need to be enabled.
6895*4882a593Smuzhiyun */
6896*4882a593Smuzhiyun if (!(IS_P3P_TYPE(ha)))
6897*4882a593Smuzhiyun ha->isp_ops->reset_chip(vha);
6898*4882a593Smuzhiyun
6899*4882a593Smuzhiyun ha->link_data_rate = PORT_SPEED_UNKNOWN;
6900*4882a593Smuzhiyun SAVE_TOPO(ha);
6901*4882a593Smuzhiyun ha->flags.rida_fmt2 = 0;
6902*4882a593Smuzhiyun ha->flags.n2n_ae = 0;
6903*4882a593Smuzhiyun ha->flags.lip_ae = 0;
6904*4882a593Smuzhiyun ha->current_topology = 0;
6905*4882a593Smuzhiyun QLA_FW_STOPPED(ha);
6906*4882a593Smuzhiyun ha->flags.fw_init_done = 0;
6907*4882a593Smuzhiyun ha->chip_reset++;
6908*4882a593Smuzhiyun ha->base_qpair->chip_reset = ha->chip_reset;
6909*4882a593Smuzhiyun for (i = 0; i < ha->max_qpairs; i++) {
6910*4882a593Smuzhiyun if (ha->queue_pair_map[i])
6911*4882a593Smuzhiyun ha->queue_pair_map[i]->chip_reset =
6912*4882a593Smuzhiyun ha->base_qpair->chip_reset;
6913*4882a593Smuzhiyun }
6914*4882a593Smuzhiyun
6915*4882a593Smuzhiyun /* purge MBox commands */
6916*4882a593Smuzhiyun if (atomic_read(&ha->num_pend_mbx_stage3)) {
6917*4882a593Smuzhiyun clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
6918*4882a593Smuzhiyun complete(&ha->mbx_intr_comp);
6919*4882a593Smuzhiyun }
6920*4882a593Smuzhiyun
6921*4882a593Smuzhiyun i = 0;
6922*4882a593Smuzhiyun while (atomic_read(&ha->num_pend_mbx_stage3) ||
6923*4882a593Smuzhiyun atomic_read(&ha->num_pend_mbx_stage2) ||
6924*4882a593Smuzhiyun atomic_read(&ha->num_pend_mbx_stage1)) {
6925*4882a593Smuzhiyun msleep(20);
6926*4882a593Smuzhiyun i++;
6927*4882a593Smuzhiyun if (i > 50)
6928*4882a593Smuzhiyun break;
6929*4882a593Smuzhiyun }
6930*4882a593Smuzhiyun ha->flags.purge_mbox = 0;
6931*4882a593Smuzhiyun
6932*4882a593Smuzhiyun atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
6933*4882a593Smuzhiyun if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
6934*4882a593Smuzhiyun atomic_set(&vha->loop_state, LOOP_DOWN);
6935*4882a593Smuzhiyun qla2x00_mark_all_devices_lost(vha);
6936*4882a593Smuzhiyun
6937*4882a593Smuzhiyun spin_lock_irqsave(&ha->vport_slock, flags);
6938*4882a593Smuzhiyun list_for_each_entry(vp, &ha->vp_list, list) {
6939*4882a593Smuzhiyun atomic_inc(&vp->vref_count);
6940*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->vport_slock, flags);
6941*4882a593Smuzhiyun
6942*4882a593Smuzhiyun qla2x00_mark_all_devices_lost(vp);
6943*4882a593Smuzhiyun
6944*4882a593Smuzhiyun spin_lock_irqsave(&ha->vport_slock, flags);
6945*4882a593Smuzhiyun atomic_dec(&vp->vref_count);
6946*4882a593Smuzhiyun }
6947*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->vport_slock, flags);
6948*4882a593Smuzhiyun } else {
6949*4882a593Smuzhiyun if (!atomic_read(&vha->loop_down_timer))
6950*4882a593Smuzhiyun atomic_set(&vha->loop_down_timer,
6951*4882a593Smuzhiyun LOOP_DOWN_TIME);
6952*4882a593Smuzhiyun }
6953*4882a593Smuzhiyun
6954*4882a593Smuzhiyun /* Clear all async request states across all VPs. */
6955*4882a593Smuzhiyun list_for_each_entry(fcport, &vha->vp_fcports, list) {
6956*4882a593Smuzhiyun fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6957*4882a593Smuzhiyun fcport->scan_state = 0;
6958*4882a593Smuzhiyun }
6959*4882a593Smuzhiyun spin_lock_irqsave(&ha->vport_slock, flags);
6960*4882a593Smuzhiyun list_for_each_entry(vp, &ha->vp_list, list) {
6961*4882a593Smuzhiyun atomic_inc(&vp->vref_count);
6962*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->vport_slock, flags);
6963*4882a593Smuzhiyun
6964*4882a593Smuzhiyun list_for_each_entry(fcport, &vp->vp_fcports, list)
6965*4882a593Smuzhiyun fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6966*4882a593Smuzhiyun
6967*4882a593Smuzhiyun spin_lock_irqsave(&ha->vport_slock, flags);
6968*4882a593Smuzhiyun atomic_dec(&vp->vref_count);
6969*4882a593Smuzhiyun }
6970*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->vport_slock, flags);
6971*4882a593Smuzhiyun
6972*4882a593Smuzhiyun if (!ha->flags.eeh_busy) {
6973*4882a593Smuzhiyun /* Make sure for ISP 82XX IO DMA is complete */
6974*4882a593Smuzhiyun if (IS_P3P_TYPE(ha)) {
6975*4882a593Smuzhiyun qla82xx_chip_reset_cleanup(vha);
6976*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x00b4,
6977*4882a593Smuzhiyun "Done chip reset cleanup.\n");
6978*4882a593Smuzhiyun
6979*4882a593Smuzhiyun /* Done waiting for pending commands.
6980*4882a593Smuzhiyun * Reset the online flag.
6981*4882a593Smuzhiyun */
6982*4882a593Smuzhiyun vha->flags.online = 0;
6983*4882a593Smuzhiyun }
6984*4882a593Smuzhiyun
6985*4882a593Smuzhiyun /* Requeue all commands in outstanding command list. */
6986*4882a593Smuzhiyun qla2x00_abort_all_cmds(vha, DID_RESET << 16);
6987*4882a593Smuzhiyun }
6988*4882a593Smuzhiyun /* memory barrier */
6989*4882a593Smuzhiyun wmb();
6990*4882a593Smuzhiyun }
6991*4882a593Smuzhiyun
6992*4882a593Smuzhiyun /*
6993*4882a593Smuzhiyun * qla2x00_abort_isp
6994*4882a593Smuzhiyun * Resets ISP and aborts all outstanding commands.
6995*4882a593Smuzhiyun *
6996*4882a593Smuzhiyun * Input:
6997*4882a593Smuzhiyun * ha = adapter block pointer.
6998*4882a593Smuzhiyun *
6999*4882a593Smuzhiyun * Returns:
7000*4882a593Smuzhiyun * 0 = success
7001*4882a593Smuzhiyun */
7002*4882a593Smuzhiyun int
qla2x00_abort_isp(scsi_qla_host_t * vha)7003*4882a593Smuzhiyun qla2x00_abort_isp(scsi_qla_host_t *vha)
7004*4882a593Smuzhiyun {
7005*4882a593Smuzhiyun int rval;
7006*4882a593Smuzhiyun uint8_t status = 0;
7007*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
7008*4882a593Smuzhiyun struct scsi_qla_host *vp;
7009*4882a593Smuzhiyun struct req_que *req = ha->req_q_map[0];
7010*4882a593Smuzhiyun unsigned long flags;
7011*4882a593Smuzhiyun
7012*4882a593Smuzhiyun if (vha->flags.online) {
7013*4882a593Smuzhiyun qla2x00_abort_isp_cleanup(vha);
7014*4882a593Smuzhiyun
7015*4882a593Smuzhiyun if (test_and_clear_bit(ISP_ABORT_TO_ROM, &vha->dpc_flags)) {
7016*4882a593Smuzhiyun ha->flags.chip_reset_done = 1;
7017*4882a593Smuzhiyun vha->flags.online = 1;
7018*4882a593Smuzhiyun status = 0;
7019*4882a593Smuzhiyun clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
7020*4882a593Smuzhiyun return status;
7021*4882a593Smuzhiyun }
7022*4882a593Smuzhiyun
7023*4882a593Smuzhiyun if (IS_QLA8031(ha)) {
7024*4882a593Smuzhiyun ql_dbg(ql_dbg_p3p, vha, 0xb05c,
7025*4882a593Smuzhiyun "Clearing fcoe driver presence.\n");
7026*4882a593Smuzhiyun if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
7027*4882a593Smuzhiyun ql_dbg(ql_dbg_p3p, vha, 0xb073,
7028*4882a593Smuzhiyun "Error while clearing DRV-Presence.\n");
7029*4882a593Smuzhiyun }
7030*4882a593Smuzhiyun
7031*4882a593Smuzhiyun if (unlikely(pci_channel_offline(ha->pdev) &&
7032*4882a593Smuzhiyun ha->flags.pci_channel_io_perm_failure)) {
7033*4882a593Smuzhiyun clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
7034*4882a593Smuzhiyun status = 0;
7035*4882a593Smuzhiyun return status;
7036*4882a593Smuzhiyun }
7037*4882a593Smuzhiyun
7038*4882a593Smuzhiyun switch (vha->qlini_mode) {
7039*4882a593Smuzhiyun case QLA2XXX_INI_MODE_DISABLED:
7040*4882a593Smuzhiyun if (!qla_tgt_mode_enabled(vha))
7041*4882a593Smuzhiyun return 0;
7042*4882a593Smuzhiyun break;
7043*4882a593Smuzhiyun case QLA2XXX_INI_MODE_DUAL:
7044*4882a593Smuzhiyun if (!qla_dual_mode_enabled(vha) &&
7045*4882a593Smuzhiyun !qla_ini_mode_enabled(vha))
7046*4882a593Smuzhiyun return 0;
7047*4882a593Smuzhiyun break;
7048*4882a593Smuzhiyun case QLA2XXX_INI_MODE_ENABLED:
7049*4882a593Smuzhiyun default:
7050*4882a593Smuzhiyun break;
7051*4882a593Smuzhiyun }
7052*4882a593Smuzhiyun
7053*4882a593Smuzhiyun ha->isp_ops->get_flash_version(vha, req->ring);
7054*4882a593Smuzhiyun
7055*4882a593Smuzhiyun ha->isp_ops->nvram_config(vha);
7056*4882a593Smuzhiyun
7057*4882a593Smuzhiyun if (!qla2x00_restart_isp(vha)) {
7058*4882a593Smuzhiyun clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7059*4882a593Smuzhiyun
7060*4882a593Smuzhiyun if (!atomic_read(&vha->loop_down_timer)) {
7061*4882a593Smuzhiyun /*
7062*4882a593Smuzhiyun * Issue marker command only when we are going
7063*4882a593Smuzhiyun * to start the I/O .
7064*4882a593Smuzhiyun */
7065*4882a593Smuzhiyun vha->marker_needed = 1;
7066*4882a593Smuzhiyun }
7067*4882a593Smuzhiyun
7068*4882a593Smuzhiyun vha->flags.online = 1;
7069*4882a593Smuzhiyun
7070*4882a593Smuzhiyun ha->isp_ops->enable_intrs(ha);
7071*4882a593Smuzhiyun
7072*4882a593Smuzhiyun ha->isp_abort_cnt = 0;
7073*4882a593Smuzhiyun clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
7074*4882a593Smuzhiyun
7075*4882a593Smuzhiyun if (IS_QLA81XX(ha) || IS_QLA8031(ha))
7076*4882a593Smuzhiyun qla2x00_get_fw_version(vha);
7077*4882a593Smuzhiyun if (ha->fce) {
7078*4882a593Smuzhiyun ha->flags.fce_enabled = 1;
7079*4882a593Smuzhiyun memset(ha->fce, 0,
7080*4882a593Smuzhiyun fce_calc_size(ha->fce_bufs));
7081*4882a593Smuzhiyun rval = qla2x00_enable_fce_trace(vha,
7082*4882a593Smuzhiyun ha->fce_dma, ha->fce_bufs, ha->fce_mb,
7083*4882a593Smuzhiyun &ha->fce_bufs);
7084*4882a593Smuzhiyun if (rval) {
7085*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x8033,
7086*4882a593Smuzhiyun "Unable to reinitialize FCE "
7087*4882a593Smuzhiyun "(%d).\n", rval);
7088*4882a593Smuzhiyun ha->flags.fce_enabled = 0;
7089*4882a593Smuzhiyun }
7090*4882a593Smuzhiyun }
7091*4882a593Smuzhiyun
7092*4882a593Smuzhiyun if (ha->eft) {
7093*4882a593Smuzhiyun memset(ha->eft, 0, EFT_SIZE);
7094*4882a593Smuzhiyun rval = qla2x00_enable_eft_trace(vha,
7095*4882a593Smuzhiyun ha->eft_dma, EFT_NUM_BUFFERS);
7096*4882a593Smuzhiyun if (rval) {
7097*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x8034,
7098*4882a593Smuzhiyun "Unable to reinitialize EFT "
7099*4882a593Smuzhiyun "(%d).\n", rval);
7100*4882a593Smuzhiyun }
7101*4882a593Smuzhiyun }
7102*4882a593Smuzhiyun } else { /* failed the ISP abort */
7103*4882a593Smuzhiyun vha->flags.online = 1;
7104*4882a593Smuzhiyun if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
7105*4882a593Smuzhiyun if (ha->isp_abort_cnt == 0) {
7106*4882a593Smuzhiyun ql_log(ql_log_fatal, vha, 0x8035,
7107*4882a593Smuzhiyun "ISP error recover failed - "
7108*4882a593Smuzhiyun "board disabled.\n");
7109*4882a593Smuzhiyun /*
7110*4882a593Smuzhiyun * The next call disables the board
7111*4882a593Smuzhiyun * completely.
7112*4882a593Smuzhiyun */
7113*4882a593Smuzhiyun qla2x00_abort_isp_cleanup(vha);
7114*4882a593Smuzhiyun vha->flags.online = 0;
7115*4882a593Smuzhiyun clear_bit(ISP_ABORT_RETRY,
7116*4882a593Smuzhiyun &vha->dpc_flags);
7117*4882a593Smuzhiyun status = 0;
7118*4882a593Smuzhiyun } else { /* schedule another ISP abort */
7119*4882a593Smuzhiyun ha->isp_abort_cnt--;
7120*4882a593Smuzhiyun ql_dbg(ql_dbg_taskm, vha, 0x8020,
7121*4882a593Smuzhiyun "ISP abort - retry remaining %d.\n",
7122*4882a593Smuzhiyun ha->isp_abort_cnt);
7123*4882a593Smuzhiyun status = 1;
7124*4882a593Smuzhiyun }
7125*4882a593Smuzhiyun } else {
7126*4882a593Smuzhiyun ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7127*4882a593Smuzhiyun ql_dbg(ql_dbg_taskm, vha, 0x8021,
7128*4882a593Smuzhiyun "ISP error recovery - retrying (%d) "
7129*4882a593Smuzhiyun "more times.\n", ha->isp_abort_cnt);
7130*4882a593Smuzhiyun set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
7131*4882a593Smuzhiyun status = 1;
7132*4882a593Smuzhiyun }
7133*4882a593Smuzhiyun }
7134*4882a593Smuzhiyun
7135*4882a593Smuzhiyun }
7136*4882a593Smuzhiyun
7137*4882a593Smuzhiyun if (!status) {
7138*4882a593Smuzhiyun ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
7139*4882a593Smuzhiyun qla2x00_configure_hba(vha);
7140*4882a593Smuzhiyun spin_lock_irqsave(&ha->vport_slock, flags);
7141*4882a593Smuzhiyun list_for_each_entry(vp, &ha->vp_list, list) {
7142*4882a593Smuzhiyun if (vp->vp_idx) {
7143*4882a593Smuzhiyun atomic_inc(&vp->vref_count);
7144*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->vport_slock, flags);
7145*4882a593Smuzhiyun
7146*4882a593Smuzhiyun qla2x00_vp_abort_isp(vp);
7147*4882a593Smuzhiyun
7148*4882a593Smuzhiyun spin_lock_irqsave(&ha->vport_slock, flags);
7149*4882a593Smuzhiyun atomic_dec(&vp->vref_count);
7150*4882a593Smuzhiyun }
7151*4882a593Smuzhiyun }
7152*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->vport_slock, flags);
7153*4882a593Smuzhiyun
7154*4882a593Smuzhiyun if (IS_QLA8031(ha)) {
7155*4882a593Smuzhiyun ql_dbg(ql_dbg_p3p, vha, 0xb05d,
7156*4882a593Smuzhiyun "Setting back fcoe driver presence.\n");
7157*4882a593Smuzhiyun if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
7158*4882a593Smuzhiyun ql_dbg(ql_dbg_p3p, vha, 0xb074,
7159*4882a593Smuzhiyun "Error while setting DRV-Presence.\n");
7160*4882a593Smuzhiyun }
7161*4882a593Smuzhiyun } else {
7162*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
7163*4882a593Smuzhiyun __func__);
7164*4882a593Smuzhiyun }
7165*4882a593Smuzhiyun
7166*4882a593Smuzhiyun return(status);
7167*4882a593Smuzhiyun }
7168*4882a593Smuzhiyun
7169*4882a593Smuzhiyun /*
7170*4882a593Smuzhiyun * qla2x00_restart_isp
7171*4882a593Smuzhiyun * restarts the ISP after a reset
7172*4882a593Smuzhiyun *
7173*4882a593Smuzhiyun * Input:
7174*4882a593Smuzhiyun * ha = adapter block pointer.
7175*4882a593Smuzhiyun *
7176*4882a593Smuzhiyun * Returns:
7177*4882a593Smuzhiyun * 0 = success
7178*4882a593Smuzhiyun */
7179*4882a593Smuzhiyun static int
qla2x00_restart_isp(scsi_qla_host_t * vha)7180*4882a593Smuzhiyun qla2x00_restart_isp(scsi_qla_host_t *vha)
7181*4882a593Smuzhiyun {
7182*4882a593Smuzhiyun int status;
7183*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
7184*4882a593Smuzhiyun
7185*4882a593Smuzhiyun /* If firmware needs to be loaded */
7186*4882a593Smuzhiyun if (qla2x00_isp_firmware(vha)) {
7187*4882a593Smuzhiyun vha->flags.online = 0;
7188*4882a593Smuzhiyun status = ha->isp_ops->chip_diag(vha);
7189*4882a593Smuzhiyun if (status)
7190*4882a593Smuzhiyun return status;
7191*4882a593Smuzhiyun status = qla2x00_setup_chip(vha);
7192*4882a593Smuzhiyun if (status)
7193*4882a593Smuzhiyun return status;
7194*4882a593Smuzhiyun }
7195*4882a593Smuzhiyun
7196*4882a593Smuzhiyun status = qla2x00_init_rings(vha);
7197*4882a593Smuzhiyun if (status)
7198*4882a593Smuzhiyun return status;
7199*4882a593Smuzhiyun
7200*4882a593Smuzhiyun clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7201*4882a593Smuzhiyun ha->flags.chip_reset_done = 1;
7202*4882a593Smuzhiyun
7203*4882a593Smuzhiyun /* Initialize the queues in use */
7204*4882a593Smuzhiyun qla25xx_init_queues(ha);
7205*4882a593Smuzhiyun
7206*4882a593Smuzhiyun status = qla2x00_fw_ready(vha);
7207*4882a593Smuzhiyun if (status) {
7208*4882a593Smuzhiyun /* if no cable then assume it's good */
7209*4882a593Smuzhiyun return vha->device_flags & DFLG_NO_CABLE ? 0 : status;
7210*4882a593Smuzhiyun }
7211*4882a593Smuzhiyun
7212*4882a593Smuzhiyun /* Issue a marker after FW becomes ready. */
7213*4882a593Smuzhiyun qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL);
7214*4882a593Smuzhiyun set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
7215*4882a593Smuzhiyun
7216*4882a593Smuzhiyun return 0;
7217*4882a593Smuzhiyun }
7218*4882a593Smuzhiyun
7219*4882a593Smuzhiyun static int
qla25xx_init_queues(struct qla_hw_data * ha)7220*4882a593Smuzhiyun qla25xx_init_queues(struct qla_hw_data *ha)
7221*4882a593Smuzhiyun {
7222*4882a593Smuzhiyun struct rsp_que *rsp = NULL;
7223*4882a593Smuzhiyun struct req_que *req = NULL;
7224*4882a593Smuzhiyun struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
7225*4882a593Smuzhiyun int ret = -1;
7226*4882a593Smuzhiyun int i;
7227*4882a593Smuzhiyun
7228*4882a593Smuzhiyun for (i = 1; i < ha->max_rsp_queues; i++) {
7229*4882a593Smuzhiyun rsp = ha->rsp_q_map[i];
7230*4882a593Smuzhiyun if (rsp && test_bit(i, ha->rsp_qid_map)) {
7231*4882a593Smuzhiyun rsp->options &= ~BIT_0;
7232*4882a593Smuzhiyun ret = qla25xx_init_rsp_que(base_vha, rsp);
7233*4882a593Smuzhiyun if (ret != QLA_SUCCESS)
7234*4882a593Smuzhiyun ql_dbg(ql_dbg_init, base_vha, 0x00ff,
7235*4882a593Smuzhiyun "%s Rsp que: %d init failed.\n",
7236*4882a593Smuzhiyun __func__, rsp->id);
7237*4882a593Smuzhiyun else
7238*4882a593Smuzhiyun ql_dbg(ql_dbg_init, base_vha, 0x0100,
7239*4882a593Smuzhiyun "%s Rsp que: %d inited.\n",
7240*4882a593Smuzhiyun __func__, rsp->id);
7241*4882a593Smuzhiyun }
7242*4882a593Smuzhiyun }
7243*4882a593Smuzhiyun for (i = 1; i < ha->max_req_queues; i++) {
7244*4882a593Smuzhiyun req = ha->req_q_map[i];
7245*4882a593Smuzhiyun if (req && test_bit(i, ha->req_qid_map)) {
7246*4882a593Smuzhiyun /* Clear outstanding commands array. */
7247*4882a593Smuzhiyun req->options &= ~BIT_0;
7248*4882a593Smuzhiyun ret = qla25xx_init_req_que(base_vha, req);
7249*4882a593Smuzhiyun if (ret != QLA_SUCCESS)
7250*4882a593Smuzhiyun ql_dbg(ql_dbg_init, base_vha, 0x0101,
7251*4882a593Smuzhiyun "%s Req que: %d init failed.\n",
7252*4882a593Smuzhiyun __func__, req->id);
7253*4882a593Smuzhiyun else
7254*4882a593Smuzhiyun ql_dbg(ql_dbg_init, base_vha, 0x0102,
7255*4882a593Smuzhiyun "%s Req que: %d inited.\n",
7256*4882a593Smuzhiyun __func__, req->id);
7257*4882a593Smuzhiyun }
7258*4882a593Smuzhiyun }
7259*4882a593Smuzhiyun return ret;
7260*4882a593Smuzhiyun }
7261*4882a593Smuzhiyun
7262*4882a593Smuzhiyun /*
7263*4882a593Smuzhiyun * qla2x00_reset_adapter
7264*4882a593Smuzhiyun * Reset adapter.
7265*4882a593Smuzhiyun *
7266*4882a593Smuzhiyun * Input:
7267*4882a593Smuzhiyun * ha = adapter block pointer.
7268*4882a593Smuzhiyun */
7269*4882a593Smuzhiyun int
qla2x00_reset_adapter(scsi_qla_host_t * vha)7270*4882a593Smuzhiyun qla2x00_reset_adapter(scsi_qla_host_t *vha)
7271*4882a593Smuzhiyun {
7272*4882a593Smuzhiyun unsigned long flags = 0;
7273*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
7274*4882a593Smuzhiyun struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
7275*4882a593Smuzhiyun
7276*4882a593Smuzhiyun vha->flags.online = 0;
7277*4882a593Smuzhiyun ha->isp_ops->disable_intrs(ha);
7278*4882a593Smuzhiyun
7279*4882a593Smuzhiyun spin_lock_irqsave(&ha->hardware_lock, flags);
7280*4882a593Smuzhiyun wrt_reg_word(®->hccr, HCCR_RESET_RISC);
7281*4882a593Smuzhiyun rd_reg_word(®->hccr); /* PCI Posting. */
7282*4882a593Smuzhiyun wrt_reg_word(®->hccr, HCCR_RELEASE_RISC);
7283*4882a593Smuzhiyun rd_reg_word(®->hccr); /* PCI Posting. */
7284*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->hardware_lock, flags);
7285*4882a593Smuzhiyun
7286*4882a593Smuzhiyun return QLA_SUCCESS;
7287*4882a593Smuzhiyun }
7288*4882a593Smuzhiyun
7289*4882a593Smuzhiyun int
qla24xx_reset_adapter(scsi_qla_host_t * vha)7290*4882a593Smuzhiyun qla24xx_reset_adapter(scsi_qla_host_t *vha)
7291*4882a593Smuzhiyun {
7292*4882a593Smuzhiyun unsigned long flags = 0;
7293*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
7294*4882a593Smuzhiyun struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
7295*4882a593Smuzhiyun
7296*4882a593Smuzhiyun if (IS_P3P_TYPE(ha))
7297*4882a593Smuzhiyun return QLA_SUCCESS;
7298*4882a593Smuzhiyun
7299*4882a593Smuzhiyun vha->flags.online = 0;
7300*4882a593Smuzhiyun ha->isp_ops->disable_intrs(ha);
7301*4882a593Smuzhiyun
7302*4882a593Smuzhiyun spin_lock_irqsave(&ha->hardware_lock, flags);
7303*4882a593Smuzhiyun wrt_reg_dword(®->hccr, HCCRX_SET_RISC_RESET);
7304*4882a593Smuzhiyun rd_reg_dword(®->hccr);
7305*4882a593Smuzhiyun wrt_reg_dword(®->hccr, HCCRX_REL_RISC_PAUSE);
7306*4882a593Smuzhiyun rd_reg_dword(®->hccr);
7307*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->hardware_lock, flags);
7308*4882a593Smuzhiyun
7309*4882a593Smuzhiyun if (IS_NOPOLLING_TYPE(ha))
7310*4882a593Smuzhiyun ha->isp_ops->enable_intrs(ha);
7311*4882a593Smuzhiyun
7312*4882a593Smuzhiyun return QLA_SUCCESS;
7313*4882a593Smuzhiyun }
7314*4882a593Smuzhiyun
7315*4882a593Smuzhiyun /* On sparc systems, obtain port and node WWN from firmware
7316*4882a593Smuzhiyun * properties.
7317*4882a593Smuzhiyun */
qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t * vha,struct nvram_24xx * nv)7318*4882a593Smuzhiyun static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
7319*4882a593Smuzhiyun struct nvram_24xx *nv)
7320*4882a593Smuzhiyun {
7321*4882a593Smuzhiyun #ifdef CONFIG_SPARC
7322*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
7323*4882a593Smuzhiyun struct pci_dev *pdev = ha->pdev;
7324*4882a593Smuzhiyun struct device_node *dp = pci_device_to_OF_node(pdev);
7325*4882a593Smuzhiyun const u8 *val;
7326*4882a593Smuzhiyun int len;
7327*4882a593Smuzhiyun
7328*4882a593Smuzhiyun val = of_get_property(dp, "port-wwn", &len);
7329*4882a593Smuzhiyun if (val && len >= WWN_SIZE)
7330*4882a593Smuzhiyun memcpy(nv->port_name, val, WWN_SIZE);
7331*4882a593Smuzhiyun
7332*4882a593Smuzhiyun val = of_get_property(dp, "node-wwn", &len);
7333*4882a593Smuzhiyun if (val && len >= WWN_SIZE)
7334*4882a593Smuzhiyun memcpy(nv->node_name, val, WWN_SIZE);
7335*4882a593Smuzhiyun #endif
7336*4882a593Smuzhiyun }
7337*4882a593Smuzhiyun
7338*4882a593Smuzhiyun int
qla24xx_nvram_config(scsi_qla_host_t * vha)7339*4882a593Smuzhiyun qla24xx_nvram_config(scsi_qla_host_t *vha)
7340*4882a593Smuzhiyun {
7341*4882a593Smuzhiyun int rval;
7342*4882a593Smuzhiyun struct init_cb_24xx *icb;
7343*4882a593Smuzhiyun struct nvram_24xx *nv;
7344*4882a593Smuzhiyun __le32 *dptr;
7345*4882a593Smuzhiyun uint8_t *dptr1, *dptr2;
7346*4882a593Smuzhiyun uint32_t chksum;
7347*4882a593Smuzhiyun uint16_t cnt;
7348*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
7349*4882a593Smuzhiyun
7350*4882a593Smuzhiyun rval = QLA_SUCCESS;
7351*4882a593Smuzhiyun icb = (struct init_cb_24xx *)ha->init_cb;
7352*4882a593Smuzhiyun nv = ha->nvram;
7353*4882a593Smuzhiyun
7354*4882a593Smuzhiyun /* Determine NVRAM starting address. */
7355*4882a593Smuzhiyun if (ha->port_no == 0) {
7356*4882a593Smuzhiyun ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
7357*4882a593Smuzhiyun ha->vpd_base = FA_NVRAM_VPD0_ADDR;
7358*4882a593Smuzhiyun } else {
7359*4882a593Smuzhiyun ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
7360*4882a593Smuzhiyun ha->vpd_base = FA_NVRAM_VPD1_ADDR;
7361*4882a593Smuzhiyun }
7362*4882a593Smuzhiyun
7363*4882a593Smuzhiyun ha->nvram_size = sizeof(*nv);
7364*4882a593Smuzhiyun ha->vpd_size = FA_NVRAM_VPD_SIZE;
7365*4882a593Smuzhiyun
7366*4882a593Smuzhiyun /* Get VPD data into cache */
7367*4882a593Smuzhiyun ha->vpd = ha->nvram + VPD_OFFSET;
7368*4882a593Smuzhiyun ha->isp_ops->read_nvram(vha, ha->vpd,
7369*4882a593Smuzhiyun ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
7370*4882a593Smuzhiyun
7371*4882a593Smuzhiyun /* Get NVRAM data into cache and calculate checksum. */
7372*4882a593Smuzhiyun dptr = (__force __le32 *)nv;
7373*4882a593Smuzhiyun ha->isp_ops->read_nvram(vha, dptr, ha->nvram_base, ha->nvram_size);
7374*4882a593Smuzhiyun for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
7375*4882a593Smuzhiyun chksum += le32_to_cpu(*dptr);
7376*4882a593Smuzhiyun
7377*4882a593Smuzhiyun ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
7378*4882a593Smuzhiyun "Contents of NVRAM\n");
7379*4882a593Smuzhiyun ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
7380*4882a593Smuzhiyun nv, ha->nvram_size);
7381*4882a593Smuzhiyun
7382*4882a593Smuzhiyun /* Bad NVRAM data, set defaults parameters. */
7383*4882a593Smuzhiyun if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) ||
7384*4882a593Smuzhiyun le16_to_cpu(nv->nvram_version) < ICB_VERSION) {
7385*4882a593Smuzhiyun /* Reset NVRAM data. */
7386*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x006b,
7387*4882a593Smuzhiyun "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n",
7388*4882a593Smuzhiyun chksum, nv->id, nv->nvram_version);
7389*4882a593Smuzhiyun ql_dump_buffer(ql_dbg_init, vha, 0x006b, nv, sizeof(*nv));
7390*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x006c,
7391*4882a593Smuzhiyun "Falling back to functioning (yet invalid -- WWPN) "
7392*4882a593Smuzhiyun "defaults.\n");
7393*4882a593Smuzhiyun
7394*4882a593Smuzhiyun /*
7395*4882a593Smuzhiyun * Set default initialization control block.
7396*4882a593Smuzhiyun */
7397*4882a593Smuzhiyun memset(nv, 0, ha->nvram_size);
7398*4882a593Smuzhiyun nv->nvram_version = cpu_to_le16(ICB_VERSION);
7399*4882a593Smuzhiyun nv->version = cpu_to_le16(ICB_VERSION);
7400*4882a593Smuzhiyun nv->frame_payload_size = cpu_to_le16(2048);
7401*4882a593Smuzhiyun nv->execution_throttle = cpu_to_le16(0xFFFF);
7402*4882a593Smuzhiyun nv->exchange_count = cpu_to_le16(0);
7403*4882a593Smuzhiyun nv->hard_address = cpu_to_le16(124);
7404*4882a593Smuzhiyun nv->port_name[0] = 0x21;
7405*4882a593Smuzhiyun nv->port_name[1] = 0x00 + ha->port_no + 1;
7406*4882a593Smuzhiyun nv->port_name[2] = 0x00;
7407*4882a593Smuzhiyun nv->port_name[3] = 0xe0;
7408*4882a593Smuzhiyun nv->port_name[4] = 0x8b;
7409*4882a593Smuzhiyun nv->port_name[5] = 0x1c;
7410*4882a593Smuzhiyun nv->port_name[6] = 0x55;
7411*4882a593Smuzhiyun nv->port_name[7] = 0x86;
7412*4882a593Smuzhiyun nv->node_name[0] = 0x20;
7413*4882a593Smuzhiyun nv->node_name[1] = 0x00;
7414*4882a593Smuzhiyun nv->node_name[2] = 0x00;
7415*4882a593Smuzhiyun nv->node_name[3] = 0xe0;
7416*4882a593Smuzhiyun nv->node_name[4] = 0x8b;
7417*4882a593Smuzhiyun nv->node_name[5] = 0x1c;
7418*4882a593Smuzhiyun nv->node_name[6] = 0x55;
7419*4882a593Smuzhiyun nv->node_name[7] = 0x86;
7420*4882a593Smuzhiyun qla24xx_nvram_wwn_from_ofw(vha, nv);
7421*4882a593Smuzhiyun nv->login_retry_count = cpu_to_le16(8);
7422*4882a593Smuzhiyun nv->interrupt_delay_timer = cpu_to_le16(0);
7423*4882a593Smuzhiyun nv->login_timeout = cpu_to_le16(0);
7424*4882a593Smuzhiyun nv->firmware_options_1 =
7425*4882a593Smuzhiyun cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
7426*4882a593Smuzhiyun nv->firmware_options_2 = cpu_to_le32(2 << 4);
7427*4882a593Smuzhiyun nv->firmware_options_2 |= cpu_to_le32(BIT_12);
7428*4882a593Smuzhiyun nv->firmware_options_3 = cpu_to_le32(2 << 13);
7429*4882a593Smuzhiyun nv->host_p = cpu_to_le32(BIT_11|BIT_10);
7430*4882a593Smuzhiyun nv->efi_parameters = cpu_to_le32(0);
7431*4882a593Smuzhiyun nv->reset_delay = 5;
7432*4882a593Smuzhiyun nv->max_luns_per_target = cpu_to_le16(128);
7433*4882a593Smuzhiyun nv->port_down_retry_count = cpu_to_le16(30);
7434*4882a593Smuzhiyun nv->link_down_timeout = cpu_to_le16(30);
7435*4882a593Smuzhiyun
7436*4882a593Smuzhiyun rval = 1;
7437*4882a593Smuzhiyun }
7438*4882a593Smuzhiyun
7439*4882a593Smuzhiyun if (qla_tgt_mode_enabled(vha)) {
7440*4882a593Smuzhiyun /* Don't enable full login after initial LIP */
7441*4882a593Smuzhiyun nv->firmware_options_1 &= cpu_to_le32(~BIT_13);
7442*4882a593Smuzhiyun /* Don't enable LIP full login for initiator */
7443*4882a593Smuzhiyun nv->host_p &= cpu_to_le32(~BIT_10);
7444*4882a593Smuzhiyun }
7445*4882a593Smuzhiyun
7446*4882a593Smuzhiyun qlt_24xx_config_nvram_stage1(vha, nv);
7447*4882a593Smuzhiyun
7448*4882a593Smuzhiyun /* Reset Initialization control block */
7449*4882a593Smuzhiyun memset(icb, 0, ha->init_cb_size);
7450*4882a593Smuzhiyun
7451*4882a593Smuzhiyun /* Copy 1st segment. */
7452*4882a593Smuzhiyun dptr1 = (uint8_t *)icb;
7453*4882a593Smuzhiyun dptr2 = (uint8_t *)&nv->version;
7454*4882a593Smuzhiyun cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
7455*4882a593Smuzhiyun while (cnt--)
7456*4882a593Smuzhiyun *dptr1++ = *dptr2++;
7457*4882a593Smuzhiyun
7458*4882a593Smuzhiyun icb->login_retry_count = nv->login_retry_count;
7459*4882a593Smuzhiyun icb->link_down_on_nos = nv->link_down_on_nos;
7460*4882a593Smuzhiyun
7461*4882a593Smuzhiyun /* Copy 2nd segment. */
7462*4882a593Smuzhiyun dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
7463*4882a593Smuzhiyun dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
7464*4882a593Smuzhiyun cnt = (uint8_t *)&icb->reserved_3 -
7465*4882a593Smuzhiyun (uint8_t *)&icb->interrupt_delay_timer;
7466*4882a593Smuzhiyun while (cnt--)
7467*4882a593Smuzhiyun *dptr1++ = *dptr2++;
7468*4882a593Smuzhiyun ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
7469*4882a593Smuzhiyun /*
7470*4882a593Smuzhiyun * Setup driver NVRAM options.
7471*4882a593Smuzhiyun */
7472*4882a593Smuzhiyun qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
7473*4882a593Smuzhiyun "QLA2462");
7474*4882a593Smuzhiyun
7475*4882a593Smuzhiyun qlt_24xx_config_nvram_stage2(vha, icb);
7476*4882a593Smuzhiyun
7477*4882a593Smuzhiyun if (nv->host_p & cpu_to_le32(BIT_15)) {
7478*4882a593Smuzhiyun /* Use alternate WWN? */
7479*4882a593Smuzhiyun memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
7480*4882a593Smuzhiyun memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
7481*4882a593Smuzhiyun }
7482*4882a593Smuzhiyun
7483*4882a593Smuzhiyun /* Prepare nodename */
7484*4882a593Smuzhiyun if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
7485*4882a593Smuzhiyun /*
7486*4882a593Smuzhiyun * Firmware will apply the following mask if the nodename was
7487*4882a593Smuzhiyun * not provided.
7488*4882a593Smuzhiyun */
7489*4882a593Smuzhiyun memcpy(icb->node_name, icb->port_name, WWN_SIZE);
7490*4882a593Smuzhiyun icb->node_name[0] &= 0xF0;
7491*4882a593Smuzhiyun }
7492*4882a593Smuzhiyun
7493*4882a593Smuzhiyun /* Set host adapter parameters. */
7494*4882a593Smuzhiyun ha->flags.disable_risc_code_load = 0;
7495*4882a593Smuzhiyun ha->flags.enable_lip_reset = 0;
7496*4882a593Smuzhiyun ha->flags.enable_lip_full_login =
7497*4882a593Smuzhiyun le32_to_cpu(nv->host_p) & BIT_10 ? 1 : 0;
7498*4882a593Smuzhiyun ha->flags.enable_target_reset =
7499*4882a593Smuzhiyun le32_to_cpu(nv->host_p) & BIT_11 ? 1 : 0;
7500*4882a593Smuzhiyun ha->flags.enable_led_scheme = 0;
7501*4882a593Smuzhiyun ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1 : 0;
7502*4882a593Smuzhiyun
7503*4882a593Smuzhiyun ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
7504*4882a593Smuzhiyun (BIT_6 | BIT_5 | BIT_4)) >> 4;
7505*4882a593Smuzhiyun
7506*4882a593Smuzhiyun memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
7507*4882a593Smuzhiyun sizeof(ha->fw_seriallink_options24));
7508*4882a593Smuzhiyun
7509*4882a593Smuzhiyun /* save HBA serial number */
7510*4882a593Smuzhiyun ha->serial0 = icb->port_name[5];
7511*4882a593Smuzhiyun ha->serial1 = icb->port_name[6];
7512*4882a593Smuzhiyun ha->serial2 = icb->port_name[7];
7513*4882a593Smuzhiyun memcpy(vha->node_name, icb->node_name, WWN_SIZE);
7514*4882a593Smuzhiyun memcpy(vha->port_name, icb->port_name, WWN_SIZE);
7515*4882a593Smuzhiyun
7516*4882a593Smuzhiyun icb->execution_throttle = cpu_to_le16(0xFFFF);
7517*4882a593Smuzhiyun
7518*4882a593Smuzhiyun ha->retry_count = le16_to_cpu(nv->login_retry_count);
7519*4882a593Smuzhiyun
7520*4882a593Smuzhiyun /* Set minimum login_timeout to 4 seconds. */
7521*4882a593Smuzhiyun if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
7522*4882a593Smuzhiyun nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
7523*4882a593Smuzhiyun if (le16_to_cpu(nv->login_timeout) < 4)
7524*4882a593Smuzhiyun nv->login_timeout = cpu_to_le16(4);
7525*4882a593Smuzhiyun ha->login_timeout = le16_to_cpu(nv->login_timeout);
7526*4882a593Smuzhiyun
7527*4882a593Smuzhiyun /* Set minimum RATOV to 100 tenths of a second. */
7528*4882a593Smuzhiyun ha->r_a_tov = 100;
7529*4882a593Smuzhiyun
7530*4882a593Smuzhiyun ha->loop_reset_delay = nv->reset_delay;
7531*4882a593Smuzhiyun
7532*4882a593Smuzhiyun /* Link Down Timeout = 0:
7533*4882a593Smuzhiyun *
7534*4882a593Smuzhiyun * When Port Down timer expires we will start returning
7535*4882a593Smuzhiyun * I/O's to OS with "DID_NO_CONNECT".
7536*4882a593Smuzhiyun *
7537*4882a593Smuzhiyun * Link Down Timeout != 0:
7538*4882a593Smuzhiyun *
7539*4882a593Smuzhiyun * The driver waits for the link to come up after link down
7540*4882a593Smuzhiyun * before returning I/Os to OS with "DID_NO_CONNECT".
7541*4882a593Smuzhiyun */
7542*4882a593Smuzhiyun if (le16_to_cpu(nv->link_down_timeout) == 0) {
7543*4882a593Smuzhiyun ha->loop_down_abort_time =
7544*4882a593Smuzhiyun (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
7545*4882a593Smuzhiyun } else {
7546*4882a593Smuzhiyun ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
7547*4882a593Smuzhiyun ha->loop_down_abort_time =
7548*4882a593Smuzhiyun (LOOP_DOWN_TIME - ha->link_down_timeout);
7549*4882a593Smuzhiyun }
7550*4882a593Smuzhiyun
7551*4882a593Smuzhiyun /* Need enough time to try and get the port back. */
7552*4882a593Smuzhiyun ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
7553*4882a593Smuzhiyun if (qlport_down_retry)
7554*4882a593Smuzhiyun ha->port_down_retry_count = qlport_down_retry;
7555*4882a593Smuzhiyun
7556*4882a593Smuzhiyun /* Set login_retry_count */
7557*4882a593Smuzhiyun ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
7558*4882a593Smuzhiyun if (ha->port_down_retry_count ==
7559*4882a593Smuzhiyun le16_to_cpu(nv->port_down_retry_count) &&
7560*4882a593Smuzhiyun ha->port_down_retry_count > 3)
7561*4882a593Smuzhiyun ha->login_retry_count = ha->port_down_retry_count;
7562*4882a593Smuzhiyun else if (ha->port_down_retry_count > (int)ha->login_retry_count)
7563*4882a593Smuzhiyun ha->login_retry_count = ha->port_down_retry_count;
7564*4882a593Smuzhiyun if (ql2xloginretrycount)
7565*4882a593Smuzhiyun ha->login_retry_count = ql2xloginretrycount;
7566*4882a593Smuzhiyun
7567*4882a593Smuzhiyun /* N2N: driver will initiate Login instead of FW */
7568*4882a593Smuzhiyun icb->firmware_options_3 |= cpu_to_le32(BIT_8);
7569*4882a593Smuzhiyun
7570*4882a593Smuzhiyun /* Enable ZIO. */
7571*4882a593Smuzhiyun if (!vha->flags.init_done) {
7572*4882a593Smuzhiyun ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
7573*4882a593Smuzhiyun (BIT_3 | BIT_2 | BIT_1 | BIT_0);
7574*4882a593Smuzhiyun ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
7575*4882a593Smuzhiyun le16_to_cpu(icb->interrupt_delay_timer) : 2;
7576*4882a593Smuzhiyun }
7577*4882a593Smuzhiyun icb->firmware_options_2 &= cpu_to_le32(
7578*4882a593Smuzhiyun ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
7579*4882a593Smuzhiyun if (ha->zio_mode != QLA_ZIO_DISABLED) {
7580*4882a593Smuzhiyun ha->zio_mode = QLA_ZIO_MODE_6;
7581*4882a593Smuzhiyun
7582*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x006f,
7583*4882a593Smuzhiyun "ZIO mode %d enabled; timer delay (%d us).\n",
7584*4882a593Smuzhiyun ha->zio_mode, ha->zio_timer * 100);
7585*4882a593Smuzhiyun
7586*4882a593Smuzhiyun icb->firmware_options_2 |= cpu_to_le32(
7587*4882a593Smuzhiyun (uint32_t)ha->zio_mode);
7588*4882a593Smuzhiyun icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
7589*4882a593Smuzhiyun }
7590*4882a593Smuzhiyun
7591*4882a593Smuzhiyun if (rval) {
7592*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0070,
7593*4882a593Smuzhiyun "NVRAM configuration failed.\n");
7594*4882a593Smuzhiyun }
7595*4882a593Smuzhiyun return (rval);
7596*4882a593Smuzhiyun }
7597*4882a593Smuzhiyun
7598*4882a593Smuzhiyun static void
qla27xx_print_image(struct scsi_qla_host * vha,char * name,struct qla27xx_image_status * image_status)7599*4882a593Smuzhiyun qla27xx_print_image(struct scsi_qla_host *vha, char *name,
7600*4882a593Smuzhiyun struct qla27xx_image_status *image_status)
7601*4882a593Smuzhiyun {
7602*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x018b,
7603*4882a593Smuzhiyun "%s %s: mask=%#02x gen=%#04x ver=%u.%u map=%#01x sum=%#08x sig=%#08x\n",
7604*4882a593Smuzhiyun name, "status",
7605*4882a593Smuzhiyun image_status->image_status_mask,
7606*4882a593Smuzhiyun le16_to_cpu(image_status->generation),
7607*4882a593Smuzhiyun image_status->ver_major,
7608*4882a593Smuzhiyun image_status->ver_minor,
7609*4882a593Smuzhiyun image_status->bitmap,
7610*4882a593Smuzhiyun le32_to_cpu(image_status->checksum),
7611*4882a593Smuzhiyun le32_to_cpu(image_status->signature));
7612*4882a593Smuzhiyun }
7613*4882a593Smuzhiyun
7614*4882a593Smuzhiyun static bool
qla28xx_check_aux_image_status_signature(struct qla27xx_image_status * image_status)7615*4882a593Smuzhiyun qla28xx_check_aux_image_status_signature(
7616*4882a593Smuzhiyun struct qla27xx_image_status *image_status)
7617*4882a593Smuzhiyun {
7618*4882a593Smuzhiyun ulong signature = le32_to_cpu(image_status->signature);
7619*4882a593Smuzhiyun
7620*4882a593Smuzhiyun return signature != QLA28XX_AUX_IMG_STATUS_SIGN;
7621*4882a593Smuzhiyun }
7622*4882a593Smuzhiyun
7623*4882a593Smuzhiyun static bool
qla27xx_check_image_status_signature(struct qla27xx_image_status * image_status)7624*4882a593Smuzhiyun qla27xx_check_image_status_signature(struct qla27xx_image_status *image_status)
7625*4882a593Smuzhiyun {
7626*4882a593Smuzhiyun ulong signature = le32_to_cpu(image_status->signature);
7627*4882a593Smuzhiyun
7628*4882a593Smuzhiyun return
7629*4882a593Smuzhiyun signature != QLA27XX_IMG_STATUS_SIGN &&
7630*4882a593Smuzhiyun signature != QLA28XX_IMG_STATUS_SIGN;
7631*4882a593Smuzhiyun }
7632*4882a593Smuzhiyun
7633*4882a593Smuzhiyun static ulong
qla27xx_image_status_checksum(struct qla27xx_image_status * image_status)7634*4882a593Smuzhiyun qla27xx_image_status_checksum(struct qla27xx_image_status *image_status)
7635*4882a593Smuzhiyun {
7636*4882a593Smuzhiyun __le32 *p = (__force __le32 *)image_status;
7637*4882a593Smuzhiyun uint n = sizeof(*image_status) / sizeof(*p);
7638*4882a593Smuzhiyun uint32_t sum = 0;
7639*4882a593Smuzhiyun
7640*4882a593Smuzhiyun for ( ; n--; p++)
7641*4882a593Smuzhiyun sum += le32_to_cpup(p);
7642*4882a593Smuzhiyun
7643*4882a593Smuzhiyun return sum;
7644*4882a593Smuzhiyun }
7645*4882a593Smuzhiyun
7646*4882a593Smuzhiyun static inline uint
qla28xx_component_bitmask(struct qla27xx_image_status * aux,uint bitmask)7647*4882a593Smuzhiyun qla28xx_component_bitmask(struct qla27xx_image_status *aux, uint bitmask)
7648*4882a593Smuzhiyun {
7649*4882a593Smuzhiyun return aux->bitmap & bitmask ?
7650*4882a593Smuzhiyun QLA27XX_SECONDARY_IMAGE : QLA27XX_PRIMARY_IMAGE;
7651*4882a593Smuzhiyun }
7652*4882a593Smuzhiyun
7653*4882a593Smuzhiyun static void
qla28xx_component_status(struct active_regions * active_regions,struct qla27xx_image_status * aux)7654*4882a593Smuzhiyun qla28xx_component_status(
7655*4882a593Smuzhiyun struct active_regions *active_regions, struct qla27xx_image_status *aux)
7656*4882a593Smuzhiyun {
7657*4882a593Smuzhiyun active_regions->aux.board_config =
7658*4882a593Smuzhiyun qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_BOARD_CONFIG);
7659*4882a593Smuzhiyun
7660*4882a593Smuzhiyun active_regions->aux.vpd_nvram =
7661*4882a593Smuzhiyun qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_VPD_NVRAM);
7662*4882a593Smuzhiyun
7663*4882a593Smuzhiyun active_regions->aux.npiv_config_0_1 =
7664*4882a593Smuzhiyun qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NPIV_CONFIG_0_1);
7665*4882a593Smuzhiyun
7666*4882a593Smuzhiyun active_regions->aux.npiv_config_2_3 =
7667*4882a593Smuzhiyun qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NPIV_CONFIG_2_3);
7668*4882a593Smuzhiyun }
7669*4882a593Smuzhiyun
7670*4882a593Smuzhiyun static int
qla27xx_compare_image_generation(struct qla27xx_image_status * pri_image_status,struct qla27xx_image_status * sec_image_status)7671*4882a593Smuzhiyun qla27xx_compare_image_generation(
7672*4882a593Smuzhiyun struct qla27xx_image_status *pri_image_status,
7673*4882a593Smuzhiyun struct qla27xx_image_status *sec_image_status)
7674*4882a593Smuzhiyun {
7675*4882a593Smuzhiyun /* calculate generation delta as uint16 (this accounts for wrap) */
7676*4882a593Smuzhiyun int16_t delta =
7677*4882a593Smuzhiyun le16_to_cpu(pri_image_status->generation) -
7678*4882a593Smuzhiyun le16_to_cpu(sec_image_status->generation);
7679*4882a593Smuzhiyun
7680*4882a593Smuzhiyun ql_dbg(ql_dbg_init, NULL, 0x0180, "generation delta = %d\n", delta);
7681*4882a593Smuzhiyun
7682*4882a593Smuzhiyun return delta;
7683*4882a593Smuzhiyun }
7684*4882a593Smuzhiyun
7685*4882a593Smuzhiyun void
qla28xx_get_aux_images(struct scsi_qla_host * vha,struct active_regions * active_regions)7686*4882a593Smuzhiyun qla28xx_get_aux_images(
7687*4882a593Smuzhiyun struct scsi_qla_host *vha, struct active_regions *active_regions)
7688*4882a593Smuzhiyun {
7689*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
7690*4882a593Smuzhiyun struct qla27xx_image_status pri_aux_image_status, sec_aux_image_status;
7691*4882a593Smuzhiyun bool valid_pri_image = false, valid_sec_image = false;
7692*4882a593Smuzhiyun bool active_pri_image = false, active_sec_image = false;
7693*4882a593Smuzhiyun
7694*4882a593Smuzhiyun if (!ha->flt_region_aux_img_status_pri) {
7695*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x018a, "Primary aux image not addressed\n");
7696*4882a593Smuzhiyun goto check_sec_image;
7697*4882a593Smuzhiyun }
7698*4882a593Smuzhiyun
7699*4882a593Smuzhiyun qla24xx_read_flash_data(vha, (uint32_t *)&pri_aux_image_status,
7700*4882a593Smuzhiyun ha->flt_region_aux_img_status_pri,
7701*4882a593Smuzhiyun sizeof(pri_aux_image_status) >> 2);
7702*4882a593Smuzhiyun qla27xx_print_image(vha, "Primary aux image", &pri_aux_image_status);
7703*4882a593Smuzhiyun
7704*4882a593Smuzhiyun if (qla28xx_check_aux_image_status_signature(&pri_aux_image_status)) {
7705*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x018b,
7706*4882a593Smuzhiyun "Primary aux image signature (%#x) not valid\n",
7707*4882a593Smuzhiyun le32_to_cpu(pri_aux_image_status.signature));
7708*4882a593Smuzhiyun goto check_sec_image;
7709*4882a593Smuzhiyun }
7710*4882a593Smuzhiyun
7711*4882a593Smuzhiyun if (qla27xx_image_status_checksum(&pri_aux_image_status)) {
7712*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x018c,
7713*4882a593Smuzhiyun "Primary aux image checksum failed\n");
7714*4882a593Smuzhiyun goto check_sec_image;
7715*4882a593Smuzhiyun }
7716*4882a593Smuzhiyun
7717*4882a593Smuzhiyun valid_pri_image = true;
7718*4882a593Smuzhiyun
7719*4882a593Smuzhiyun if (pri_aux_image_status.image_status_mask & 1) {
7720*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x018d,
7721*4882a593Smuzhiyun "Primary aux image is active\n");
7722*4882a593Smuzhiyun active_pri_image = true;
7723*4882a593Smuzhiyun }
7724*4882a593Smuzhiyun
7725*4882a593Smuzhiyun check_sec_image:
7726*4882a593Smuzhiyun if (!ha->flt_region_aux_img_status_sec) {
7727*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x018a,
7728*4882a593Smuzhiyun "Secondary aux image not addressed\n");
7729*4882a593Smuzhiyun goto check_valid_image;
7730*4882a593Smuzhiyun }
7731*4882a593Smuzhiyun
7732*4882a593Smuzhiyun qla24xx_read_flash_data(vha, (uint32_t *)&sec_aux_image_status,
7733*4882a593Smuzhiyun ha->flt_region_aux_img_status_sec,
7734*4882a593Smuzhiyun sizeof(sec_aux_image_status) >> 2);
7735*4882a593Smuzhiyun qla27xx_print_image(vha, "Secondary aux image", &sec_aux_image_status);
7736*4882a593Smuzhiyun
7737*4882a593Smuzhiyun if (qla28xx_check_aux_image_status_signature(&sec_aux_image_status)) {
7738*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x018b,
7739*4882a593Smuzhiyun "Secondary aux image signature (%#x) not valid\n",
7740*4882a593Smuzhiyun le32_to_cpu(sec_aux_image_status.signature));
7741*4882a593Smuzhiyun goto check_valid_image;
7742*4882a593Smuzhiyun }
7743*4882a593Smuzhiyun
7744*4882a593Smuzhiyun if (qla27xx_image_status_checksum(&sec_aux_image_status)) {
7745*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x018c,
7746*4882a593Smuzhiyun "Secondary aux image checksum failed\n");
7747*4882a593Smuzhiyun goto check_valid_image;
7748*4882a593Smuzhiyun }
7749*4882a593Smuzhiyun
7750*4882a593Smuzhiyun valid_sec_image = true;
7751*4882a593Smuzhiyun
7752*4882a593Smuzhiyun if (sec_aux_image_status.image_status_mask & 1) {
7753*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x018d,
7754*4882a593Smuzhiyun "Secondary aux image is active\n");
7755*4882a593Smuzhiyun active_sec_image = true;
7756*4882a593Smuzhiyun }
7757*4882a593Smuzhiyun
7758*4882a593Smuzhiyun check_valid_image:
7759*4882a593Smuzhiyun if (valid_pri_image && active_pri_image &&
7760*4882a593Smuzhiyun valid_sec_image && active_sec_image) {
7761*4882a593Smuzhiyun if (qla27xx_compare_image_generation(&pri_aux_image_status,
7762*4882a593Smuzhiyun &sec_aux_image_status) >= 0) {
7763*4882a593Smuzhiyun qla28xx_component_status(active_regions,
7764*4882a593Smuzhiyun &pri_aux_image_status);
7765*4882a593Smuzhiyun } else {
7766*4882a593Smuzhiyun qla28xx_component_status(active_regions,
7767*4882a593Smuzhiyun &sec_aux_image_status);
7768*4882a593Smuzhiyun }
7769*4882a593Smuzhiyun } else if (valid_pri_image && active_pri_image) {
7770*4882a593Smuzhiyun qla28xx_component_status(active_regions, &pri_aux_image_status);
7771*4882a593Smuzhiyun } else if (valid_sec_image && active_sec_image) {
7772*4882a593Smuzhiyun qla28xx_component_status(active_regions, &sec_aux_image_status);
7773*4882a593Smuzhiyun }
7774*4882a593Smuzhiyun
7775*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x018f,
7776*4882a593Smuzhiyun "aux images active: BCFG=%u VPD/NVR=%u NPIV0/1=%u NPIV2/3=%u\n",
7777*4882a593Smuzhiyun active_regions->aux.board_config,
7778*4882a593Smuzhiyun active_regions->aux.vpd_nvram,
7779*4882a593Smuzhiyun active_regions->aux.npiv_config_0_1,
7780*4882a593Smuzhiyun active_regions->aux.npiv_config_2_3);
7781*4882a593Smuzhiyun }
7782*4882a593Smuzhiyun
7783*4882a593Smuzhiyun void
qla27xx_get_active_image(struct scsi_qla_host * vha,struct active_regions * active_regions)7784*4882a593Smuzhiyun qla27xx_get_active_image(struct scsi_qla_host *vha,
7785*4882a593Smuzhiyun struct active_regions *active_regions)
7786*4882a593Smuzhiyun {
7787*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
7788*4882a593Smuzhiyun struct qla27xx_image_status pri_image_status, sec_image_status;
7789*4882a593Smuzhiyun bool valid_pri_image = false, valid_sec_image = false;
7790*4882a593Smuzhiyun bool active_pri_image = false, active_sec_image = false;
7791*4882a593Smuzhiyun
7792*4882a593Smuzhiyun if (!ha->flt_region_img_status_pri) {
7793*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x018a, "Primary image not addressed\n");
7794*4882a593Smuzhiyun goto check_sec_image;
7795*4882a593Smuzhiyun }
7796*4882a593Smuzhiyun
7797*4882a593Smuzhiyun if (qla24xx_read_flash_data(vha, (uint32_t *)&pri_image_status,
7798*4882a593Smuzhiyun ha->flt_region_img_status_pri, sizeof(pri_image_status) >> 2) !=
7799*4882a593Smuzhiyun QLA_SUCCESS) {
7800*4882a593Smuzhiyun WARN_ON_ONCE(true);
7801*4882a593Smuzhiyun goto check_sec_image;
7802*4882a593Smuzhiyun }
7803*4882a593Smuzhiyun qla27xx_print_image(vha, "Primary image", &pri_image_status);
7804*4882a593Smuzhiyun
7805*4882a593Smuzhiyun if (qla27xx_check_image_status_signature(&pri_image_status)) {
7806*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x018b,
7807*4882a593Smuzhiyun "Primary image signature (%#x) not valid\n",
7808*4882a593Smuzhiyun le32_to_cpu(pri_image_status.signature));
7809*4882a593Smuzhiyun goto check_sec_image;
7810*4882a593Smuzhiyun }
7811*4882a593Smuzhiyun
7812*4882a593Smuzhiyun if (qla27xx_image_status_checksum(&pri_image_status)) {
7813*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x018c,
7814*4882a593Smuzhiyun "Primary image checksum failed\n");
7815*4882a593Smuzhiyun goto check_sec_image;
7816*4882a593Smuzhiyun }
7817*4882a593Smuzhiyun
7818*4882a593Smuzhiyun valid_pri_image = true;
7819*4882a593Smuzhiyun
7820*4882a593Smuzhiyun if (pri_image_status.image_status_mask & 1) {
7821*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x018d,
7822*4882a593Smuzhiyun "Primary image is active\n");
7823*4882a593Smuzhiyun active_pri_image = true;
7824*4882a593Smuzhiyun }
7825*4882a593Smuzhiyun
7826*4882a593Smuzhiyun check_sec_image:
7827*4882a593Smuzhiyun if (!ha->flt_region_img_status_sec) {
7828*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x018a, "Secondary image not addressed\n");
7829*4882a593Smuzhiyun goto check_valid_image;
7830*4882a593Smuzhiyun }
7831*4882a593Smuzhiyun
7832*4882a593Smuzhiyun qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status),
7833*4882a593Smuzhiyun ha->flt_region_img_status_sec, sizeof(sec_image_status) >> 2);
7834*4882a593Smuzhiyun qla27xx_print_image(vha, "Secondary image", &sec_image_status);
7835*4882a593Smuzhiyun
7836*4882a593Smuzhiyun if (qla27xx_check_image_status_signature(&sec_image_status)) {
7837*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x018b,
7838*4882a593Smuzhiyun "Secondary image signature (%#x) not valid\n",
7839*4882a593Smuzhiyun le32_to_cpu(sec_image_status.signature));
7840*4882a593Smuzhiyun goto check_valid_image;
7841*4882a593Smuzhiyun }
7842*4882a593Smuzhiyun
7843*4882a593Smuzhiyun if (qla27xx_image_status_checksum(&sec_image_status)) {
7844*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x018c,
7845*4882a593Smuzhiyun "Secondary image checksum failed\n");
7846*4882a593Smuzhiyun goto check_valid_image;
7847*4882a593Smuzhiyun }
7848*4882a593Smuzhiyun
7849*4882a593Smuzhiyun valid_sec_image = true;
7850*4882a593Smuzhiyun
7851*4882a593Smuzhiyun if (sec_image_status.image_status_mask & 1) {
7852*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x018d,
7853*4882a593Smuzhiyun "Secondary image is active\n");
7854*4882a593Smuzhiyun active_sec_image = true;
7855*4882a593Smuzhiyun }
7856*4882a593Smuzhiyun
7857*4882a593Smuzhiyun check_valid_image:
7858*4882a593Smuzhiyun if (valid_pri_image && active_pri_image)
7859*4882a593Smuzhiyun active_regions->global = QLA27XX_PRIMARY_IMAGE;
7860*4882a593Smuzhiyun
7861*4882a593Smuzhiyun if (valid_sec_image && active_sec_image) {
7862*4882a593Smuzhiyun if (!active_regions->global ||
7863*4882a593Smuzhiyun qla27xx_compare_image_generation(
7864*4882a593Smuzhiyun &pri_image_status, &sec_image_status) < 0) {
7865*4882a593Smuzhiyun active_regions->global = QLA27XX_SECONDARY_IMAGE;
7866*4882a593Smuzhiyun }
7867*4882a593Smuzhiyun }
7868*4882a593Smuzhiyun
7869*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x018f, "active image %s (%u)\n",
7870*4882a593Smuzhiyun active_regions->global == QLA27XX_DEFAULT_IMAGE ?
7871*4882a593Smuzhiyun "default (boot/fw)" :
7872*4882a593Smuzhiyun active_regions->global == QLA27XX_PRIMARY_IMAGE ?
7873*4882a593Smuzhiyun "primary" :
7874*4882a593Smuzhiyun active_regions->global == QLA27XX_SECONDARY_IMAGE ?
7875*4882a593Smuzhiyun "secondary" : "invalid",
7876*4882a593Smuzhiyun active_regions->global);
7877*4882a593Smuzhiyun }
7878*4882a593Smuzhiyun
qla24xx_risc_firmware_invalid(uint32_t * dword)7879*4882a593Smuzhiyun bool qla24xx_risc_firmware_invalid(uint32_t *dword)
7880*4882a593Smuzhiyun {
7881*4882a593Smuzhiyun return
7882*4882a593Smuzhiyun !(dword[4] | dword[5] | dword[6] | dword[7]) ||
7883*4882a593Smuzhiyun !(~dword[4] | ~dword[5] | ~dword[6] | ~dword[7]);
7884*4882a593Smuzhiyun }
7885*4882a593Smuzhiyun
7886*4882a593Smuzhiyun static int
qla24xx_load_risc_flash(scsi_qla_host_t * vha,uint32_t * srisc_addr,uint32_t faddr)7887*4882a593Smuzhiyun qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
7888*4882a593Smuzhiyun uint32_t faddr)
7889*4882a593Smuzhiyun {
7890*4882a593Smuzhiyun int rval;
7891*4882a593Smuzhiyun uint templates, segments, fragment;
7892*4882a593Smuzhiyun ulong i;
7893*4882a593Smuzhiyun uint j;
7894*4882a593Smuzhiyun ulong dlen;
7895*4882a593Smuzhiyun uint32_t *dcode;
7896*4882a593Smuzhiyun uint32_t risc_addr, risc_size, risc_attr = 0;
7897*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
7898*4882a593Smuzhiyun struct req_que *req = ha->req_q_map[0];
7899*4882a593Smuzhiyun struct fwdt *fwdt = ha->fwdt;
7900*4882a593Smuzhiyun
7901*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x008b,
7902*4882a593Smuzhiyun "FW: Loading firmware from flash (%x).\n", faddr);
7903*4882a593Smuzhiyun
7904*4882a593Smuzhiyun dcode = (uint32_t *)req->ring;
7905*4882a593Smuzhiyun qla24xx_read_flash_data(vha, dcode, faddr, 8);
7906*4882a593Smuzhiyun if (qla24xx_risc_firmware_invalid(dcode)) {
7907*4882a593Smuzhiyun ql_log(ql_log_fatal, vha, 0x008c,
7908*4882a593Smuzhiyun "Unable to verify the integrity of flash firmware "
7909*4882a593Smuzhiyun "image.\n");
7910*4882a593Smuzhiyun ql_log(ql_log_fatal, vha, 0x008d,
7911*4882a593Smuzhiyun "Firmware data: %08x %08x %08x %08x.\n",
7912*4882a593Smuzhiyun dcode[0], dcode[1], dcode[2], dcode[3]);
7913*4882a593Smuzhiyun
7914*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
7915*4882a593Smuzhiyun }
7916*4882a593Smuzhiyun
7917*4882a593Smuzhiyun dcode = (uint32_t *)req->ring;
7918*4882a593Smuzhiyun *srisc_addr = 0;
7919*4882a593Smuzhiyun segments = FA_RISC_CODE_SEGMENTS;
7920*4882a593Smuzhiyun for (j = 0; j < segments; j++) {
7921*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x008d,
7922*4882a593Smuzhiyun "-> Loading segment %u...\n", j);
7923*4882a593Smuzhiyun qla24xx_read_flash_data(vha, dcode, faddr, 10);
7924*4882a593Smuzhiyun risc_addr = be32_to_cpu((__force __be32)dcode[2]);
7925*4882a593Smuzhiyun risc_size = be32_to_cpu((__force __be32)dcode[3]);
7926*4882a593Smuzhiyun if (!*srisc_addr) {
7927*4882a593Smuzhiyun *srisc_addr = risc_addr;
7928*4882a593Smuzhiyun risc_attr = be32_to_cpu((__force __be32)dcode[9]);
7929*4882a593Smuzhiyun }
7930*4882a593Smuzhiyun
7931*4882a593Smuzhiyun dlen = ha->fw_transfer_size >> 2;
7932*4882a593Smuzhiyun for (fragment = 0; risc_size; fragment++) {
7933*4882a593Smuzhiyun if (dlen > risc_size)
7934*4882a593Smuzhiyun dlen = risc_size;
7935*4882a593Smuzhiyun
7936*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x008e,
7937*4882a593Smuzhiyun "-> Loading fragment %u: %#x <- %#x (%#lx dwords)...\n",
7938*4882a593Smuzhiyun fragment, risc_addr, faddr, dlen);
7939*4882a593Smuzhiyun qla24xx_read_flash_data(vha, dcode, faddr, dlen);
7940*4882a593Smuzhiyun for (i = 0; i < dlen; i++)
7941*4882a593Smuzhiyun dcode[i] = swab32(dcode[i]);
7942*4882a593Smuzhiyun
7943*4882a593Smuzhiyun rval = qla2x00_load_ram(vha, req->dma, risc_addr, dlen);
7944*4882a593Smuzhiyun if (rval) {
7945*4882a593Smuzhiyun ql_log(ql_log_fatal, vha, 0x008f,
7946*4882a593Smuzhiyun "-> Failed load firmware fragment %u.\n",
7947*4882a593Smuzhiyun fragment);
7948*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
7949*4882a593Smuzhiyun }
7950*4882a593Smuzhiyun
7951*4882a593Smuzhiyun faddr += dlen;
7952*4882a593Smuzhiyun risc_addr += dlen;
7953*4882a593Smuzhiyun risc_size -= dlen;
7954*4882a593Smuzhiyun }
7955*4882a593Smuzhiyun }
7956*4882a593Smuzhiyun
7957*4882a593Smuzhiyun if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
7958*4882a593Smuzhiyun return QLA_SUCCESS;
7959*4882a593Smuzhiyun
7960*4882a593Smuzhiyun templates = (risc_attr & BIT_9) ? 2 : 1;
7961*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0160, "-> templates = %u\n", templates);
7962*4882a593Smuzhiyun for (j = 0; j < templates; j++, fwdt++) {
7963*4882a593Smuzhiyun if (fwdt->template)
7964*4882a593Smuzhiyun vfree(fwdt->template);
7965*4882a593Smuzhiyun fwdt->template = NULL;
7966*4882a593Smuzhiyun fwdt->length = 0;
7967*4882a593Smuzhiyun
7968*4882a593Smuzhiyun dcode = (uint32_t *)req->ring;
7969*4882a593Smuzhiyun qla24xx_read_flash_data(vha, dcode, faddr, 7);
7970*4882a593Smuzhiyun risc_size = be32_to_cpu((__force __be32)dcode[2]);
7971*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0161,
7972*4882a593Smuzhiyun "-> fwdt%u template array at %#x (%#x dwords)\n",
7973*4882a593Smuzhiyun j, faddr, risc_size);
7974*4882a593Smuzhiyun if (!risc_size || !~risc_size) {
7975*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0162,
7976*4882a593Smuzhiyun "-> fwdt%u failed to read array\n", j);
7977*4882a593Smuzhiyun goto failed;
7978*4882a593Smuzhiyun }
7979*4882a593Smuzhiyun
7980*4882a593Smuzhiyun /* skip header and ignore checksum */
7981*4882a593Smuzhiyun faddr += 7;
7982*4882a593Smuzhiyun risc_size -= 8;
7983*4882a593Smuzhiyun
7984*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0163,
7985*4882a593Smuzhiyun "-> fwdt%u template allocate template %#x words...\n",
7986*4882a593Smuzhiyun j, risc_size);
7987*4882a593Smuzhiyun fwdt->template = vmalloc(risc_size * sizeof(*dcode));
7988*4882a593Smuzhiyun if (!fwdt->template) {
7989*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0164,
7990*4882a593Smuzhiyun "-> fwdt%u failed allocate template.\n", j);
7991*4882a593Smuzhiyun goto failed;
7992*4882a593Smuzhiyun }
7993*4882a593Smuzhiyun
7994*4882a593Smuzhiyun dcode = fwdt->template;
7995*4882a593Smuzhiyun qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
7996*4882a593Smuzhiyun
7997*4882a593Smuzhiyun if (!qla27xx_fwdt_template_valid(dcode)) {
7998*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0165,
7999*4882a593Smuzhiyun "-> fwdt%u failed template validate\n", j);
8000*4882a593Smuzhiyun goto failed;
8001*4882a593Smuzhiyun }
8002*4882a593Smuzhiyun
8003*4882a593Smuzhiyun dlen = qla27xx_fwdt_template_size(dcode);
8004*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0166,
8005*4882a593Smuzhiyun "-> fwdt%u template size %#lx bytes (%#lx words)\n",
8006*4882a593Smuzhiyun j, dlen, dlen / sizeof(*dcode));
8007*4882a593Smuzhiyun if (dlen > risc_size * sizeof(*dcode)) {
8008*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0167,
8009*4882a593Smuzhiyun "-> fwdt%u template exceeds array (%-lu bytes)\n",
8010*4882a593Smuzhiyun j, dlen - risc_size * sizeof(*dcode));
8011*4882a593Smuzhiyun goto failed;
8012*4882a593Smuzhiyun }
8013*4882a593Smuzhiyun
8014*4882a593Smuzhiyun fwdt->length = dlen;
8015*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0168,
8016*4882a593Smuzhiyun "-> fwdt%u loaded template ok\n", j);
8017*4882a593Smuzhiyun
8018*4882a593Smuzhiyun faddr += risc_size + 1;
8019*4882a593Smuzhiyun }
8020*4882a593Smuzhiyun
8021*4882a593Smuzhiyun return QLA_SUCCESS;
8022*4882a593Smuzhiyun
8023*4882a593Smuzhiyun failed:
8024*4882a593Smuzhiyun if (fwdt->template)
8025*4882a593Smuzhiyun vfree(fwdt->template);
8026*4882a593Smuzhiyun fwdt->template = NULL;
8027*4882a593Smuzhiyun fwdt->length = 0;
8028*4882a593Smuzhiyun
8029*4882a593Smuzhiyun return QLA_SUCCESS;
8030*4882a593Smuzhiyun }
8031*4882a593Smuzhiyun
8032*4882a593Smuzhiyun #define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
8033*4882a593Smuzhiyun
8034*4882a593Smuzhiyun int
qla2x00_load_risc(scsi_qla_host_t * vha,uint32_t * srisc_addr)8035*4882a593Smuzhiyun qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
8036*4882a593Smuzhiyun {
8037*4882a593Smuzhiyun int rval;
8038*4882a593Smuzhiyun int i, fragment;
8039*4882a593Smuzhiyun uint16_t *wcode;
8040*4882a593Smuzhiyun __be16 *fwcode;
8041*4882a593Smuzhiyun uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
8042*4882a593Smuzhiyun struct fw_blob *blob;
8043*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
8044*4882a593Smuzhiyun struct req_que *req = ha->req_q_map[0];
8045*4882a593Smuzhiyun
8046*4882a593Smuzhiyun /* Load firmware blob. */
8047*4882a593Smuzhiyun blob = qla2x00_request_firmware(vha);
8048*4882a593Smuzhiyun if (!blob) {
8049*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x0083,
8050*4882a593Smuzhiyun "Firmware image unavailable.\n");
8051*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x0084,
8052*4882a593Smuzhiyun "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
8053*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
8054*4882a593Smuzhiyun }
8055*4882a593Smuzhiyun
8056*4882a593Smuzhiyun rval = QLA_SUCCESS;
8057*4882a593Smuzhiyun
8058*4882a593Smuzhiyun wcode = (uint16_t *)req->ring;
8059*4882a593Smuzhiyun *srisc_addr = 0;
8060*4882a593Smuzhiyun fwcode = (__force __be16 *)blob->fw->data;
8061*4882a593Smuzhiyun fwclen = 0;
8062*4882a593Smuzhiyun
8063*4882a593Smuzhiyun /* Validate firmware image by checking version. */
8064*4882a593Smuzhiyun if (blob->fw->size < 8 * sizeof(uint16_t)) {
8065*4882a593Smuzhiyun ql_log(ql_log_fatal, vha, 0x0085,
8066*4882a593Smuzhiyun "Unable to verify integrity of firmware image (%zd).\n",
8067*4882a593Smuzhiyun blob->fw->size);
8068*4882a593Smuzhiyun goto fail_fw_integrity;
8069*4882a593Smuzhiyun }
8070*4882a593Smuzhiyun for (i = 0; i < 4; i++)
8071*4882a593Smuzhiyun wcode[i] = be16_to_cpu(fwcode[i + 4]);
8072*4882a593Smuzhiyun if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
8073*4882a593Smuzhiyun wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
8074*4882a593Smuzhiyun wcode[2] == 0 && wcode[3] == 0)) {
8075*4882a593Smuzhiyun ql_log(ql_log_fatal, vha, 0x0086,
8076*4882a593Smuzhiyun "Unable to verify integrity of firmware image.\n");
8077*4882a593Smuzhiyun ql_log(ql_log_fatal, vha, 0x0087,
8078*4882a593Smuzhiyun "Firmware data: %04x %04x %04x %04x.\n",
8079*4882a593Smuzhiyun wcode[0], wcode[1], wcode[2], wcode[3]);
8080*4882a593Smuzhiyun goto fail_fw_integrity;
8081*4882a593Smuzhiyun }
8082*4882a593Smuzhiyun
8083*4882a593Smuzhiyun seg = blob->segs;
8084*4882a593Smuzhiyun while (*seg && rval == QLA_SUCCESS) {
8085*4882a593Smuzhiyun risc_addr = *seg;
8086*4882a593Smuzhiyun *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
8087*4882a593Smuzhiyun risc_size = be16_to_cpu(fwcode[3]);
8088*4882a593Smuzhiyun
8089*4882a593Smuzhiyun /* Validate firmware image size. */
8090*4882a593Smuzhiyun fwclen += risc_size * sizeof(uint16_t);
8091*4882a593Smuzhiyun if (blob->fw->size < fwclen) {
8092*4882a593Smuzhiyun ql_log(ql_log_fatal, vha, 0x0088,
8093*4882a593Smuzhiyun "Unable to verify integrity of firmware image "
8094*4882a593Smuzhiyun "(%zd).\n", blob->fw->size);
8095*4882a593Smuzhiyun goto fail_fw_integrity;
8096*4882a593Smuzhiyun }
8097*4882a593Smuzhiyun
8098*4882a593Smuzhiyun fragment = 0;
8099*4882a593Smuzhiyun while (risc_size > 0 && rval == QLA_SUCCESS) {
8100*4882a593Smuzhiyun wlen = (uint16_t)(ha->fw_transfer_size >> 1);
8101*4882a593Smuzhiyun if (wlen > risc_size)
8102*4882a593Smuzhiyun wlen = risc_size;
8103*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0089,
8104*4882a593Smuzhiyun "Loading risc segment@ risc addr %x number of "
8105*4882a593Smuzhiyun "words 0x%x.\n", risc_addr, wlen);
8106*4882a593Smuzhiyun
8107*4882a593Smuzhiyun for (i = 0; i < wlen; i++)
8108*4882a593Smuzhiyun wcode[i] = swab16((__force u32)fwcode[i]);
8109*4882a593Smuzhiyun
8110*4882a593Smuzhiyun rval = qla2x00_load_ram(vha, req->dma, risc_addr,
8111*4882a593Smuzhiyun wlen);
8112*4882a593Smuzhiyun if (rval) {
8113*4882a593Smuzhiyun ql_log(ql_log_fatal, vha, 0x008a,
8114*4882a593Smuzhiyun "Failed to load segment %d of firmware.\n",
8115*4882a593Smuzhiyun fragment);
8116*4882a593Smuzhiyun break;
8117*4882a593Smuzhiyun }
8118*4882a593Smuzhiyun
8119*4882a593Smuzhiyun fwcode += wlen;
8120*4882a593Smuzhiyun risc_addr += wlen;
8121*4882a593Smuzhiyun risc_size -= wlen;
8122*4882a593Smuzhiyun fragment++;
8123*4882a593Smuzhiyun }
8124*4882a593Smuzhiyun
8125*4882a593Smuzhiyun /* Next segment. */
8126*4882a593Smuzhiyun seg++;
8127*4882a593Smuzhiyun }
8128*4882a593Smuzhiyun return rval;
8129*4882a593Smuzhiyun
8130*4882a593Smuzhiyun fail_fw_integrity:
8131*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
8132*4882a593Smuzhiyun }
8133*4882a593Smuzhiyun
8134*4882a593Smuzhiyun static int
qla24xx_load_risc_blob(scsi_qla_host_t * vha,uint32_t * srisc_addr)8135*4882a593Smuzhiyun qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
8136*4882a593Smuzhiyun {
8137*4882a593Smuzhiyun int rval;
8138*4882a593Smuzhiyun uint templates, segments, fragment;
8139*4882a593Smuzhiyun uint32_t *dcode;
8140*4882a593Smuzhiyun ulong dlen;
8141*4882a593Smuzhiyun uint32_t risc_addr, risc_size, risc_attr = 0;
8142*4882a593Smuzhiyun ulong i;
8143*4882a593Smuzhiyun uint j;
8144*4882a593Smuzhiyun struct fw_blob *blob;
8145*4882a593Smuzhiyun __be32 *fwcode;
8146*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
8147*4882a593Smuzhiyun struct req_que *req = ha->req_q_map[0];
8148*4882a593Smuzhiyun struct fwdt *fwdt = ha->fwdt;
8149*4882a593Smuzhiyun
8150*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0090,
8151*4882a593Smuzhiyun "-> FW: Loading via request-firmware.\n");
8152*4882a593Smuzhiyun
8153*4882a593Smuzhiyun blob = qla2x00_request_firmware(vha);
8154*4882a593Smuzhiyun if (!blob) {
8155*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0092,
8156*4882a593Smuzhiyun "-> Firmware file not found.\n");
8157*4882a593Smuzhiyun
8158*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
8159*4882a593Smuzhiyun }
8160*4882a593Smuzhiyun
8161*4882a593Smuzhiyun fwcode = (__force __be32 *)blob->fw->data;
8162*4882a593Smuzhiyun dcode = (__force uint32_t *)fwcode;
8163*4882a593Smuzhiyun if (qla24xx_risc_firmware_invalid(dcode)) {
8164*4882a593Smuzhiyun ql_log(ql_log_fatal, vha, 0x0093,
8165*4882a593Smuzhiyun "Unable to verify integrity of firmware image (%zd).\n",
8166*4882a593Smuzhiyun blob->fw->size);
8167*4882a593Smuzhiyun ql_log(ql_log_fatal, vha, 0x0095,
8168*4882a593Smuzhiyun "Firmware data: %08x %08x %08x %08x.\n",
8169*4882a593Smuzhiyun dcode[0], dcode[1], dcode[2], dcode[3]);
8170*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
8171*4882a593Smuzhiyun }
8172*4882a593Smuzhiyun
8173*4882a593Smuzhiyun dcode = (uint32_t *)req->ring;
8174*4882a593Smuzhiyun *srisc_addr = 0;
8175*4882a593Smuzhiyun segments = FA_RISC_CODE_SEGMENTS;
8176*4882a593Smuzhiyun for (j = 0; j < segments; j++) {
8177*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0096,
8178*4882a593Smuzhiyun "-> Loading segment %u...\n", j);
8179*4882a593Smuzhiyun risc_addr = be32_to_cpu(fwcode[2]);
8180*4882a593Smuzhiyun risc_size = be32_to_cpu(fwcode[3]);
8181*4882a593Smuzhiyun
8182*4882a593Smuzhiyun if (!*srisc_addr) {
8183*4882a593Smuzhiyun *srisc_addr = risc_addr;
8184*4882a593Smuzhiyun risc_attr = be32_to_cpu(fwcode[9]);
8185*4882a593Smuzhiyun }
8186*4882a593Smuzhiyun
8187*4882a593Smuzhiyun dlen = ha->fw_transfer_size >> 2;
8188*4882a593Smuzhiyun for (fragment = 0; risc_size; fragment++) {
8189*4882a593Smuzhiyun if (dlen > risc_size)
8190*4882a593Smuzhiyun dlen = risc_size;
8191*4882a593Smuzhiyun
8192*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0097,
8193*4882a593Smuzhiyun "-> Loading fragment %u: %#x <- %#x (%#lx words)...\n",
8194*4882a593Smuzhiyun fragment, risc_addr,
8195*4882a593Smuzhiyun (uint32_t)(fwcode - (typeof(fwcode))blob->fw->data),
8196*4882a593Smuzhiyun dlen);
8197*4882a593Smuzhiyun
8198*4882a593Smuzhiyun for (i = 0; i < dlen; i++)
8199*4882a593Smuzhiyun dcode[i] = swab32((__force u32)fwcode[i]);
8200*4882a593Smuzhiyun
8201*4882a593Smuzhiyun rval = qla2x00_load_ram(vha, req->dma, risc_addr, dlen);
8202*4882a593Smuzhiyun if (rval) {
8203*4882a593Smuzhiyun ql_log(ql_log_fatal, vha, 0x0098,
8204*4882a593Smuzhiyun "-> Failed load firmware fragment %u.\n",
8205*4882a593Smuzhiyun fragment);
8206*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
8207*4882a593Smuzhiyun }
8208*4882a593Smuzhiyun
8209*4882a593Smuzhiyun fwcode += dlen;
8210*4882a593Smuzhiyun risc_addr += dlen;
8211*4882a593Smuzhiyun risc_size -= dlen;
8212*4882a593Smuzhiyun }
8213*4882a593Smuzhiyun }
8214*4882a593Smuzhiyun
8215*4882a593Smuzhiyun if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
8216*4882a593Smuzhiyun return QLA_SUCCESS;
8217*4882a593Smuzhiyun
8218*4882a593Smuzhiyun templates = (risc_attr & BIT_9) ? 2 : 1;
8219*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0170, "-> templates = %u\n", templates);
8220*4882a593Smuzhiyun for (j = 0; j < templates; j++, fwdt++) {
8221*4882a593Smuzhiyun if (fwdt->template)
8222*4882a593Smuzhiyun vfree(fwdt->template);
8223*4882a593Smuzhiyun fwdt->template = NULL;
8224*4882a593Smuzhiyun fwdt->length = 0;
8225*4882a593Smuzhiyun
8226*4882a593Smuzhiyun risc_size = be32_to_cpu(fwcode[2]);
8227*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0171,
8228*4882a593Smuzhiyun "-> fwdt%u template array at %#x (%#x dwords)\n",
8229*4882a593Smuzhiyun j, (uint32_t)((void *)fwcode - (void *)blob->fw->data),
8230*4882a593Smuzhiyun risc_size);
8231*4882a593Smuzhiyun if (!risc_size || !~risc_size) {
8232*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0172,
8233*4882a593Smuzhiyun "-> fwdt%u failed to read array\n", j);
8234*4882a593Smuzhiyun goto failed;
8235*4882a593Smuzhiyun }
8236*4882a593Smuzhiyun
8237*4882a593Smuzhiyun /* skip header and ignore checksum */
8238*4882a593Smuzhiyun fwcode += 7;
8239*4882a593Smuzhiyun risc_size -= 8;
8240*4882a593Smuzhiyun
8241*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0173,
8242*4882a593Smuzhiyun "-> fwdt%u template allocate template %#x words...\n",
8243*4882a593Smuzhiyun j, risc_size);
8244*4882a593Smuzhiyun fwdt->template = vmalloc(risc_size * sizeof(*dcode));
8245*4882a593Smuzhiyun if (!fwdt->template) {
8246*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0174,
8247*4882a593Smuzhiyun "-> fwdt%u failed allocate template.\n", j);
8248*4882a593Smuzhiyun goto failed;
8249*4882a593Smuzhiyun }
8250*4882a593Smuzhiyun
8251*4882a593Smuzhiyun dcode = fwdt->template;
8252*4882a593Smuzhiyun for (i = 0; i < risc_size; i++)
8253*4882a593Smuzhiyun dcode[i] = (__force u32)fwcode[i];
8254*4882a593Smuzhiyun
8255*4882a593Smuzhiyun if (!qla27xx_fwdt_template_valid(dcode)) {
8256*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0175,
8257*4882a593Smuzhiyun "-> fwdt%u failed template validate\n", j);
8258*4882a593Smuzhiyun goto failed;
8259*4882a593Smuzhiyun }
8260*4882a593Smuzhiyun
8261*4882a593Smuzhiyun dlen = qla27xx_fwdt_template_size(dcode);
8262*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0176,
8263*4882a593Smuzhiyun "-> fwdt%u template size %#lx bytes (%#lx words)\n",
8264*4882a593Smuzhiyun j, dlen, dlen / sizeof(*dcode));
8265*4882a593Smuzhiyun if (dlen > risc_size * sizeof(*dcode)) {
8266*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0177,
8267*4882a593Smuzhiyun "-> fwdt%u template exceeds array (%-lu bytes)\n",
8268*4882a593Smuzhiyun j, dlen - risc_size * sizeof(*dcode));
8269*4882a593Smuzhiyun goto failed;
8270*4882a593Smuzhiyun }
8271*4882a593Smuzhiyun
8272*4882a593Smuzhiyun fwdt->length = dlen;
8273*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0178,
8274*4882a593Smuzhiyun "-> fwdt%u loaded template ok\n", j);
8275*4882a593Smuzhiyun
8276*4882a593Smuzhiyun fwcode += risc_size + 1;
8277*4882a593Smuzhiyun }
8278*4882a593Smuzhiyun
8279*4882a593Smuzhiyun return QLA_SUCCESS;
8280*4882a593Smuzhiyun
8281*4882a593Smuzhiyun failed:
8282*4882a593Smuzhiyun if (fwdt->template)
8283*4882a593Smuzhiyun vfree(fwdt->template);
8284*4882a593Smuzhiyun fwdt->template = NULL;
8285*4882a593Smuzhiyun fwdt->length = 0;
8286*4882a593Smuzhiyun
8287*4882a593Smuzhiyun return QLA_SUCCESS;
8288*4882a593Smuzhiyun }
8289*4882a593Smuzhiyun
8290*4882a593Smuzhiyun int
qla24xx_load_risc(scsi_qla_host_t * vha,uint32_t * srisc_addr)8291*4882a593Smuzhiyun qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
8292*4882a593Smuzhiyun {
8293*4882a593Smuzhiyun int rval;
8294*4882a593Smuzhiyun
8295*4882a593Smuzhiyun if (ql2xfwloadbin == 1)
8296*4882a593Smuzhiyun return qla81xx_load_risc(vha, srisc_addr);
8297*4882a593Smuzhiyun
8298*4882a593Smuzhiyun /*
8299*4882a593Smuzhiyun * FW Load priority:
8300*4882a593Smuzhiyun * 1) Firmware via request-firmware interface (.bin file).
8301*4882a593Smuzhiyun * 2) Firmware residing in flash.
8302*4882a593Smuzhiyun */
8303*4882a593Smuzhiyun rval = qla24xx_load_risc_blob(vha, srisc_addr);
8304*4882a593Smuzhiyun if (rval == QLA_SUCCESS)
8305*4882a593Smuzhiyun return rval;
8306*4882a593Smuzhiyun
8307*4882a593Smuzhiyun return qla24xx_load_risc_flash(vha, srisc_addr,
8308*4882a593Smuzhiyun vha->hw->flt_region_fw);
8309*4882a593Smuzhiyun }
8310*4882a593Smuzhiyun
8311*4882a593Smuzhiyun int
qla81xx_load_risc(scsi_qla_host_t * vha,uint32_t * srisc_addr)8312*4882a593Smuzhiyun qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
8313*4882a593Smuzhiyun {
8314*4882a593Smuzhiyun int rval;
8315*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
8316*4882a593Smuzhiyun struct active_regions active_regions = { };
8317*4882a593Smuzhiyun
8318*4882a593Smuzhiyun if (ql2xfwloadbin == 2)
8319*4882a593Smuzhiyun goto try_blob_fw;
8320*4882a593Smuzhiyun
8321*4882a593Smuzhiyun /* FW Load priority:
8322*4882a593Smuzhiyun * 1) Firmware residing in flash.
8323*4882a593Smuzhiyun * 2) Firmware via request-firmware interface (.bin file).
8324*4882a593Smuzhiyun * 3) Golden-Firmware residing in flash -- (limited operation).
8325*4882a593Smuzhiyun */
8326*4882a593Smuzhiyun
8327*4882a593Smuzhiyun if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
8328*4882a593Smuzhiyun goto try_primary_fw;
8329*4882a593Smuzhiyun
8330*4882a593Smuzhiyun qla27xx_get_active_image(vha, &active_regions);
8331*4882a593Smuzhiyun
8332*4882a593Smuzhiyun if (active_regions.global != QLA27XX_SECONDARY_IMAGE)
8333*4882a593Smuzhiyun goto try_primary_fw;
8334*4882a593Smuzhiyun
8335*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x008b,
8336*4882a593Smuzhiyun "Loading secondary firmware image.\n");
8337*4882a593Smuzhiyun rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw_sec);
8338*4882a593Smuzhiyun if (!rval)
8339*4882a593Smuzhiyun return rval;
8340*4882a593Smuzhiyun
8341*4882a593Smuzhiyun try_primary_fw:
8342*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x008b,
8343*4882a593Smuzhiyun "Loading primary firmware image.\n");
8344*4882a593Smuzhiyun rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
8345*4882a593Smuzhiyun if (!rval)
8346*4882a593Smuzhiyun return rval;
8347*4882a593Smuzhiyun
8348*4882a593Smuzhiyun try_blob_fw:
8349*4882a593Smuzhiyun rval = qla24xx_load_risc_blob(vha, srisc_addr);
8350*4882a593Smuzhiyun if (!rval || !ha->flt_region_gold_fw)
8351*4882a593Smuzhiyun return rval;
8352*4882a593Smuzhiyun
8353*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x0099,
8354*4882a593Smuzhiyun "Attempting to fallback to golden firmware.\n");
8355*4882a593Smuzhiyun rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
8356*4882a593Smuzhiyun if (rval)
8357*4882a593Smuzhiyun return rval;
8358*4882a593Smuzhiyun
8359*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x009a, "Need firmware flash update.\n");
8360*4882a593Smuzhiyun ha->flags.running_gold_fw = 1;
8361*4882a593Smuzhiyun return rval;
8362*4882a593Smuzhiyun }
8363*4882a593Smuzhiyun
8364*4882a593Smuzhiyun void
qla2x00_try_to_stop_firmware(scsi_qla_host_t * vha)8365*4882a593Smuzhiyun qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
8366*4882a593Smuzhiyun {
8367*4882a593Smuzhiyun int ret, retries;
8368*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
8369*4882a593Smuzhiyun
8370*4882a593Smuzhiyun if (ha->flags.pci_channel_io_perm_failure)
8371*4882a593Smuzhiyun return;
8372*4882a593Smuzhiyun if (!IS_FWI2_CAPABLE(ha))
8373*4882a593Smuzhiyun return;
8374*4882a593Smuzhiyun if (!ha->fw_major_version)
8375*4882a593Smuzhiyun return;
8376*4882a593Smuzhiyun if (!ha->flags.fw_started)
8377*4882a593Smuzhiyun return;
8378*4882a593Smuzhiyun
8379*4882a593Smuzhiyun ret = qla2x00_stop_firmware(vha);
8380*4882a593Smuzhiyun for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
8381*4882a593Smuzhiyun ret != QLA_INVALID_COMMAND && retries ; retries--) {
8382*4882a593Smuzhiyun ha->isp_ops->reset_chip(vha);
8383*4882a593Smuzhiyun if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
8384*4882a593Smuzhiyun continue;
8385*4882a593Smuzhiyun if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
8386*4882a593Smuzhiyun continue;
8387*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x8015,
8388*4882a593Smuzhiyun "Attempting retry of stop-firmware command.\n");
8389*4882a593Smuzhiyun ret = qla2x00_stop_firmware(vha);
8390*4882a593Smuzhiyun }
8391*4882a593Smuzhiyun
8392*4882a593Smuzhiyun QLA_FW_STOPPED(ha);
8393*4882a593Smuzhiyun ha->flags.fw_init_done = 0;
8394*4882a593Smuzhiyun }
8395*4882a593Smuzhiyun
8396*4882a593Smuzhiyun int
qla24xx_configure_vhba(scsi_qla_host_t * vha)8397*4882a593Smuzhiyun qla24xx_configure_vhba(scsi_qla_host_t *vha)
8398*4882a593Smuzhiyun {
8399*4882a593Smuzhiyun int rval = QLA_SUCCESS;
8400*4882a593Smuzhiyun int rval2;
8401*4882a593Smuzhiyun uint16_t mb[MAILBOX_REGISTER_COUNT];
8402*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
8403*4882a593Smuzhiyun struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
8404*4882a593Smuzhiyun
8405*4882a593Smuzhiyun if (!vha->vp_idx)
8406*4882a593Smuzhiyun return -EINVAL;
8407*4882a593Smuzhiyun
8408*4882a593Smuzhiyun rval = qla2x00_fw_ready(base_vha);
8409*4882a593Smuzhiyun
8410*4882a593Smuzhiyun if (rval == QLA_SUCCESS) {
8411*4882a593Smuzhiyun clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
8412*4882a593Smuzhiyun qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL);
8413*4882a593Smuzhiyun }
8414*4882a593Smuzhiyun
8415*4882a593Smuzhiyun vha->flags.management_server_logged_in = 0;
8416*4882a593Smuzhiyun
8417*4882a593Smuzhiyun /* Login to SNS first */
8418*4882a593Smuzhiyun rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
8419*4882a593Smuzhiyun BIT_1);
8420*4882a593Smuzhiyun if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
8421*4882a593Smuzhiyun if (rval2 == QLA_MEMORY_ALLOC_FAILED)
8422*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0120,
8423*4882a593Smuzhiyun "Failed SNS login: loop_id=%x, rval2=%d\n",
8424*4882a593Smuzhiyun NPH_SNS, rval2);
8425*4882a593Smuzhiyun else
8426*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0103,
8427*4882a593Smuzhiyun "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
8428*4882a593Smuzhiyun "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
8429*4882a593Smuzhiyun NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
8430*4882a593Smuzhiyun return (QLA_FUNCTION_FAILED);
8431*4882a593Smuzhiyun }
8432*4882a593Smuzhiyun
8433*4882a593Smuzhiyun atomic_set(&vha->loop_down_timer, 0);
8434*4882a593Smuzhiyun atomic_set(&vha->loop_state, LOOP_UP);
8435*4882a593Smuzhiyun set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
8436*4882a593Smuzhiyun set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
8437*4882a593Smuzhiyun rval = qla2x00_loop_resync(base_vha);
8438*4882a593Smuzhiyun
8439*4882a593Smuzhiyun return rval;
8440*4882a593Smuzhiyun }
8441*4882a593Smuzhiyun
8442*4882a593Smuzhiyun /* 84XX Support **************************************************************/
8443*4882a593Smuzhiyun
8444*4882a593Smuzhiyun static LIST_HEAD(qla_cs84xx_list);
8445*4882a593Smuzhiyun static DEFINE_MUTEX(qla_cs84xx_mutex);
8446*4882a593Smuzhiyun
8447*4882a593Smuzhiyun static struct qla_chip_state_84xx *
qla84xx_get_chip(struct scsi_qla_host * vha)8448*4882a593Smuzhiyun qla84xx_get_chip(struct scsi_qla_host *vha)
8449*4882a593Smuzhiyun {
8450*4882a593Smuzhiyun struct qla_chip_state_84xx *cs84xx;
8451*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
8452*4882a593Smuzhiyun
8453*4882a593Smuzhiyun mutex_lock(&qla_cs84xx_mutex);
8454*4882a593Smuzhiyun
8455*4882a593Smuzhiyun /* Find any shared 84xx chip. */
8456*4882a593Smuzhiyun list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
8457*4882a593Smuzhiyun if (cs84xx->bus == ha->pdev->bus) {
8458*4882a593Smuzhiyun kref_get(&cs84xx->kref);
8459*4882a593Smuzhiyun goto done;
8460*4882a593Smuzhiyun }
8461*4882a593Smuzhiyun }
8462*4882a593Smuzhiyun
8463*4882a593Smuzhiyun cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
8464*4882a593Smuzhiyun if (!cs84xx)
8465*4882a593Smuzhiyun goto done;
8466*4882a593Smuzhiyun
8467*4882a593Smuzhiyun kref_init(&cs84xx->kref);
8468*4882a593Smuzhiyun spin_lock_init(&cs84xx->access_lock);
8469*4882a593Smuzhiyun mutex_init(&cs84xx->fw_update_mutex);
8470*4882a593Smuzhiyun cs84xx->bus = ha->pdev->bus;
8471*4882a593Smuzhiyun
8472*4882a593Smuzhiyun list_add_tail(&cs84xx->list, &qla_cs84xx_list);
8473*4882a593Smuzhiyun done:
8474*4882a593Smuzhiyun mutex_unlock(&qla_cs84xx_mutex);
8475*4882a593Smuzhiyun return cs84xx;
8476*4882a593Smuzhiyun }
8477*4882a593Smuzhiyun
8478*4882a593Smuzhiyun static void
__qla84xx_chip_release(struct kref * kref)8479*4882a593Smuzhiyun __qla84xx_chip_release(struct kref *kref)
8480*4882a593Smuzhiyun {
8481*4882a593Smuzhiyun struct qla_chip_state_84xx *cs84xx =
8482*4882a593Smuzhiyun container_of(kref, struct qla_chip_state_84xx, kref);
8483*4882a593Smuzhiyun
8484*4882a593Smuzhiyun mutex_lock(&qla_cs84xx_mutex);
8485*4882a593Smuzhiyun list_del(&cs84xx->list);
8486*4882a593Smuzhiyun mutex_unlock(&qla_cs84xx_mutex);
8487*4882a593Smuzhiyun kfree(cs84xx);
8488*4882a593Smuzhiyun }
8489*4882a593Smuzhiyun
8490*4882a593Smuzhiyun void
qla84xx_put_chip(struct scsi_qla_host * vha)8491*4882a593Smuzhiyun qla84xx_put_chip(struct scsi_qla_host *vha)
8492*4882a593Smuzhiyun {
8493*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
8494*4882a593Smuzhiyun
8495*4882a593Smuzhiyun if (ha->cs84xx)
8496*4882a593Smuzhiyun kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
8497*4882a593Smuzhiyun }
8498*4882a593Smuzhiyun
8499*4882a593Smuzhiyun static int
qla84xx_init_chip(scsi_qla_host_t * vha)8500*4882a593Smuzhiyun qla84xx_init_chip(scsi_qla_host_t *vha)
8501*4882a593Smuzhiyun {
8502*4882a593Smuzhiyun int rval;
8503*4882a593Smuzhiyun uint16_t status[2];
8504*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
8505*4882a593Smuzhiyun
8506*4882a593Smuzhiyun mutex_lock(&ha->cs84xx->fw_update_mutex);
8507*4882a593Smuzhiyun
8508*4882a593Smuzhiyun rval = qla84xx_verify_chip(vha, status);
8509*4882a593Smuzhiyun
8510*4882a593Smuzhiyun mutex_unlock(&ha->cs84xx->fw_update_mutex);
8511*4882a593Smuzhiyun
8512*4882a593Smuzhiyun return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED :
8513*4882a593Smuzhiyun QLA_SUCCESS;
8514*4882a593Smuzhiyun }
8515*4882a593Smuzhiyun
8516*4882a593Smuzhiyun /* 81XX Support **************************************************************/
8517*4882a593Smuzhiyun
8518*4882a593Smuzhiyun int
qla81xx_nvram_config(scsi_qla_host_t * vha)8519*4882a593Smuzhiyun qla81xx_nvram_config(scsi_qla_host_t *vha)
8520*4882a593Smuzhiyun {
8521*4882a593Smuzhiyun int rval;
8522*4882a593Smuzhiyun struct init_cb_81xx *icb;
8523*4882a593Smuzhiyun struct nvram_81xx *nv;
8524*4882a593Smuzhiyun __le32 *dptr;
8525*4882a593Smuzhiyun uint8_t *dptr1, *dptr2;
8526*4882a593Smuzhiyun uint32_t chksum;
8527*4882a593Smuzhiyun uint16_t cnt;
8528*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
8529*4882a593Smuzhiyun uint32_t faddr;
8530*4882a593Smuzhiyun struct active_regions active_regions = { };
8531*4882a593Smuzhiyun
8532*4882a593Smuzhiyun rval = QLA_SUCCESS;
8533*4882a593Smuzhiyun icb = (struct init_cb_81xx *)ha->init_cb;
8534*4882a593Smuzhiyun nv = ha->nvram;
8535*4882a593Smuzhiyun
8536*4882a593Smuzhiyun /* Determine NVRAM starting address. */
8537*4882a593Smuzhiyun ha->nvram_size = sizeof(*nv);
8538*4882a593Smuzhiyun ha->vpd_size = FA_NVRAM_VPD_SIZE;
8539*4882a593Smuzhiyun if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
8540*4882a593Smuzhiyun ha->vpd_size = FA_VPD_SIZE_82XX;
8541*4882a593Smuzhiyun
8542*4882a593Smuzhiyun if (IS_QLA28XX(ha) || IS_QLA27XX(ha))
8543*4882a593Smuzhiyun qla28xx_get_aux_images(vha, &active_regions);
8544*4882a593Smuzhiyun
8545*4882a593Smuzhiyun /* Get VPD data into cache */
8546*4882a593Smuzhiyun ha->vpd = ha->nvram + VPD_OFFSET;
8547*4882a593Smuzhiyun
8548*4882a593Smuzhiyun faddr = ha->flt_region_vpd;
8549*4882a593Smuzhiyun if (IS_QLA28XX(ha)) {
8550*4882a593Smuzhiyun if (active_regions.aux.vpd_nvram == QLA27XX_SECONDARY_IMAGE)
8551*4882a593Smuzhiyun faddr = ha->flt_region_vpd_sec;
8552*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0110,
8553*4882a593Smuzhiyun "Loading %s nvram image.\n",
8554*4882a593Smuzhiyun active_regions.aux.vpd_nvram == QLA27XX_PRIMARY_IMAGE ?
8555*4882a593Smuzhiyun "primary" : "secondary");
8556*4882a593Smuzhiyun }
8557*4882a593Smuzhiyun ha->isp_ops->read_optrom(vha, ha->vpd, faddr << 2, ha->vpd_size);
8558*4882a593Smuzhiyun
8559*4882a593Smuzhiyun /* Get NVRAM data into cache and calculate checksum. */
8560*4882a593Smuzhiyun faddr = ha->flt_region_nvram;
8561*4882a593Smuzhiyun if (IS_QLA28XX(ha)) {
8562*4882a593Smuzhiyun if (active_regions.aux.vpd_nvram == QLA27XX_SECONDARY_IMAGE)
8563*4882a593Smuzhiyun faddr = ha->flt_region_nvram_sec;
8564*4882a593Smuzhiyun }
8565*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0110,
8566*4882a593Smuzhiyun "Loading %s nvram image.\n",
8567*4882a593Smuzhiyun active_regions.aux.vpd_nvram == QLA27XX_PRIMARY_IMAGE ?
8568*4882a593Smuzhiyun "primary" : "secondary");
8569*4882a593Smuzhiyun ha->isp_ops->read_optrom(vha, ha->nvram, faddr << 2, ha->nvram_size);
8570*4882a593Smuzhiyun
8571*4882a593Smuzhiyun dptr = (__force __le32 *)nv;
8572*4882a593Smuzhiyun for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
8573*4882a593Smuzhiyun chksum += le32_to_cpu(*dptr);
8574*4882a593Smuzhiyun
8575*4882a593Smuzhiyun ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
8576*4882a593Smuzhiyun "Contents of NVRAM:\n");
8577*4882a593Smuzhiyun ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
8578*4882a593Smuzhiyun nv, ha->nvram_size);
8579*4882a593Smuzhiyun
8580*4882a593Smuzhiyun /* Bad NVRAM data, set defaults parameters. */
8581*4882a593Smuzhiyun if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) ||
8582*4882a593Smuzhiyun le16_to_cpu(nv->nvram_version) < ICB_VERSION) {
8583*4882a593Smuzhiyun /* Reset NVRAM data. */
8584*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x0073,
8585*4882a593Smuzhiyun "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n",
8586*4882a593Smuzhiyun chksum, nv->id, le16_to_cpu(nv->nvram_version));
8587*4882a593Smuzhiyun ql_dump_buffer(ql_dbg_init, vha, 0x0073, nv, sizeof(*nv));
8588*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x0074,
8589*4882a593Smuzhiyun "Falling back to functioning (yet invalid -- WWPN) "
8590*4882a593Smuzhiyun "defaults.\n");
8591*4882a593Smuzhiyun
8592*4882a593Smuzhiyun /*
8593*4882a593Smuzhiyun * Set default initialization control block.
8594*4882a593Smuzhiyun */
8595*4882a593Smuzhiyun memset(nv, 0, ha->nvram_size);
8596*4882a593Smuzhiyun nv->nvram_version = cpu_to_le16(ICB_VERSION);
8597*4882a593Smuzhiyun nv->version = cpu_to_le16(ICB_VERSION);
8598*4882a593Smuzhiyun nv->frame_payload_size = cpu_to_le16(2048);
8599*4882a593Smuzhiyun nv->execution_throttle = cpu_to_le16(0xFFFF);
8600*4882a593Smuzhiyun nv->exchange_count = cpu_to_le16(0);
8601*4882a593Smuzhiyun nv->port_name[0] = 0x21;
8602*4882a593Smuzhiyun nv->port_name[1] = 0x00 + ha->port_no + 1;
8603*4882a593Smuzhiyun nv->port_name[2] = 0x00;
8604*4882a593Smuzhiyun nv->port_name[3] = 0xe0;
8605*4882a593Smuzhiyun nv->port_name[4] = 0x8b;
8606*4882a593Smuzhiyun nv->port_name[5] = 0x1c;
8607*4882a593Smuzhiyun nv->port_name[6] = 0x55;
8608*4882a593Smuzhiyun nv->port_name[7] = 0x86;
8609*4882a593Smuzhiyun nv->node_name[0] = 0x20;
8610*4882a593Smuzhiyun nv->node_name[1] = 0x00;
8611*4882a593Smuzhiyun nv->node_name[2] = 0x00;
8612*4882a593Smuzhiyun nv->node_name[3] = 0xe0;
8613*4882a593Smuzhiyun nv->node_name[4] = 0x8b;
8614*4882a593Smuzhiyun nv->node_name[5] = 0x1c;
8615*4882a593Smuzhiyun nv->node_name[6] = 0x55;
8616*4882a593Smuzhiyun nv->node_name[7] = 0x86;
8617*4882a593Smuzhiyun nv->login_retry_count = cpu_to_le16(8);
8618*4882a593Smuzhiyun nv->interrupt_delay_timer = cpu_to_le16(0);
8619*4882a593Smuzhiyun nv->login_timeout = cpu_to_le16(0);
8620*4882a593Smuzhiyun nv->firmware_options_1 =
8621*4882a593Smuzhiyun cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
8622*4882a593Smuzhiyun nv->firmware_options_2 = cpu_to_le32(2 << 4);
8623*4882a593Smuzhiyun nv->firmware_options_2 |= cpu_to_le32(BIT_12);
8624*4882a593Smuzhiyun nv->firmware_options_3 = cpu_to_le32(2 << 13);
8625*4882a593Smuzhiyun nv->host_p = cpu_to_le32(BIT_11|BIT_10);
8626*4882a593Smuzhiyun nv->efi_parameters = cpu_to_le32(0);
8627*4882a593Smuzhiyun nv->reset_delay = 5;
8628*4882a593Smuzhiyun nv->max_luns_per_target = cpu_to_le16(128);
8629*4882a593Smuzhiyun nv->port_down_retry_count = cpu_to_le16(30);
8630*4882a593Smuzhiyun nv->link_down_timeout = cpu_to_le16(180);
8631*4882a593Smuzhiyun nv->enode_mac[0] = 0x00;
8632*4882a593Smuzhiyun nv->enode_mac[1] = 0xC0;
8633*4882a593Smuzhiyun nv->enode_mac[2] = 0xDD;
8634*4882a593Smuzhiyun nv->enode_mac[3] = 0x04;
8635*4882a593Smuzhiyun nv->enode_mac[4] = 0x05;
8636*4882a593Smuzhiyun nv->enode_mac[5] = 0x06 + ha->port_no + 1;
8637*4882a593Smuzhiyun
8638*4882a593Smuzhiyun rval = 1;
8639*4882a593Smuzhiyun }
8640*4882a593Smuzhiyun
8641*4882a593Smuzhiyun if (IS_T10_PI_CAPABLE(ha))
8642*4882a593Smuzhiyun nv->frame_payload_size &= cpu_to_le16(~7);
8643*4882a593Smuzhiyun
8644*4882a593Smuzhiyun qlt_81xx_config_nvram_stage1(vha, nv);
8645*4882a593Smuzhiyun
8646*4882a593Smuzhiyun /* Reset Initialization control block */
8647*4882a593Smuzhiyun memset(icb, 0, ha->init_cb_size);
8648*4882a593Smuzhiyun
8649*4882a593Smuzhiyun /* Copy 1st segment. */
8650*4882a593Smuzhiyun dptr1 = (uint8_t *)icb;
8651*4882a593Smuzhiyun dptr2 = (uint8_t *)&nv->version;
8652*4882a593Smuzhiyun cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
8653*4882a593Smuzhiyun while (cnt--)
8654*4882a593Smuzhiyun *dptr1++ = *dptr2++;
8655*4882a593Smuzhiyun
8656*4882a593Smuzhiyun icb->login_retry_count = nv->login_retry_count;
8657*4882a593Smuzhiyun
8658*4882a593Smuzhiyun /* Copy 2nd segment. */
8659*4882a593Smuzhiyun dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
8660*4882a593Smuzhiyun dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
8661*4882a593Smuzhiyun cnt = (uint8_t *)&icb->reserved_5 -
8662*4882a593Smuzhiyun (uint8_t *)&icb->interrupt_delay_timer;
8663*4882a593Smuzhiyun while (cnt--)
8664*4882a593Smuzhiyun *dptr1++ = *dptr2++;
8665*4882a593Smuzhiyun
8666*4882a593Smuzhiyun memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
8667*4882a593Smuzhiyun /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
8668*4882a593Smuzhiyun if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
8669*4882a593Smuzhiyun icb->enode_mac[0] = 0x00;
8670*4882a593Smuzhiyun icb->enode_mac[1] = 0xC0;
8671*4882a593Smuzhiyun icb->enode_mac[2] = 0xDD;
8672*4882a593Smuzhiyun icb->enode_mac[3] = 0x04;
8673*4882a593Smuzhiyun icb->enode_mac[4] = 0x05;
8674*4882a593Smuzhiyun icb->enode_mac[5] = 0x06 + ha->port_no + 1;
8675*4882a593Smuzhiyun }
8676*4882a593Smuzhiyun
8677*4882a593Smuzhiyun /* Use extended-initialization control block. */
8678*4882a593Smuzhiyun memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
8679*4882a593Smuzhiyun ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
8680*4882a593Smuzhiyun /*
8681*4882a593Smuzhiyun * Setup driver NVRAM options.
8682*4882a593Smuzhiyun */
8683*4882a593Smuzhiyun qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
8684*4882a593Smuzhiyun "QLE8XXX");
8685*4882a593Smuzhiyun
8686*4882a593Smuzhiyun qlt_81xx_config_nvram_stage2(vha, icb);
8687*4882a593Smuzhiyun
8688*4882a593Smuzhiyun /* Use alternate WWN? */
8689*4882a593Smuzhiyun if (nv->host_p & cpu_to_le32(BIT_15)) {
8690*4882a593Smuzhiyun memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
8691*4882a593Smuzhiyun memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
8692*4882a593Smuzhiyun }
8693*4882a593Smuzhiyun
8694*4882a593Smuzhiyun /* Prepare nodename */
8695*4882a593Smuzhiyun if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
8696*4882a593Smuzhiyun /*
8697*4882a593Smuzhiyun * Firmware will apply the following mask if the nodename was
8698*4882a593Smuzhiyun * not provided.
8699*4882a593Smuzhiyun */
8700*4882a593Smuzhiyun memcpy(icb->node_name, icb->port_name, WWN_SIZE);
8701*4882a593Smuzhiyun icb->node_name[0] &= 0xF0;
8702*4882a593Smuzhiyun }
8703*4882a593Smuzhiyun
8704*4882a593Smuzhiyun if (IS_QLA28XX(ha) || IS_QLA27XX(ha)) {
8705*4882a593Smuzhiyun if ((nv->enhanced_features & BIT_7) == 0)
8706*4882a593Smuzhiyun ha->flags.scm_supported_a = 1;
8707*4882a593Smuzhiyun }
8708*4882a593Smuzhiyun
8709*4882a593Smuzhiyun /* Set host adapter parameters. */
8710*4882a593Smuzhiyun ha->flags.disable_risc_code_load = 0;
8711*4882a593Smuzhiyun ha->flags.enable_lip_reset = 0;
8712*4882a593Smuzhiyun ha->flags.enable_lip_full_login =
8713*4882a593Smuzhiyun le32_to_cpu(nv->host_p) & BIT_10 ? 1 : 0;
8714*4882a593Smuzhiyun ha->flags.enable_target_reset =
8715*4882a593Smuzhiyun le32_to_cpu(nv->host_p) & BIT_11 ? 1 : 0;
8716*4882a593Smuzhiyun ha->flags.enable_led_scheme = 0;
8717*4882a593Smuzhiyun ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1 : 0;
8718*4882a593Smuzhiyun
8719*4882a593Smuzhiyun ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
8720*4882a593Smuzhiyun (BIT_6 | BIT_5 | BIT_4)) >> 4;
8721*4882a593Smuzhiyun
8722*4882a593Smuzhiyun /* save HBA serial number */
8723*4882a593Smuzhiyun ha->serial0 = icb->port_name[5];
8724*4882a593Smuzhiyun ha->serial1 = icb->port_name[6];
8725*4882a593Smuzhiyun ha->serial2 = icb->port_name[7];
8726*4882a593Smuzhiyun memcpy(vha->node_name, icb->node_name, WWN_SIZE);
8727*4882a593Smuzhiyun memcpy(vha->port_name, icb->port_name, WWN_SIZE);
8728*4882a593Smuzhiyun
8729*4882a593Smuzhiyun icb->execution_throttle = cpu_to_le16(0xFFFF);
8730*4882a593Smuzhiyun
8731*4882a593Smuzhiyun ha->retry_count = le16_to_cpu(nv->login_retry_count);
8732*4882a593Smuzhiyun
8733*4882a593Smuzhiyun /* Set minimum login_timeout to 4 seconds. */
8734*4882a593Smuzhiyun if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
8735*4882a593Smuzhiyun nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
8736*4882a593Smuzhiyun if (le16_to_cpu(nv->login_timeout) < 4)
8737*4882a593Smuzhiyun nv->login_timeout = cpu_to_le16(4);
8738*4882a593Smuzhiyun ha->login_timeout = le16_to_cpu(nv->login_timeout);
8739*4882a593Smuzhiyun
8740*4882a593Smuzhiyun /* Set minimum RATOV to 100 tenths of a second. */
8741*4882a593Smuzhiyun ha->r_a_tov = 100;
8742*4882a593Smuzhiyun
8743*4882a593Smuzhiyun ha->loop_reset_delay = nv->reset_delay;
8744*4882a593Smuzhiyun
8745*4882a593Smuzhiyun /* Link Down Timeout = 0:
8746*4882a593Smuzhiyun *
8747*4882a593Smuzhiyun * When Port Down timer expires we will start returning
8748*4882a593Smuzhiyun * I/O's to OS with "DID_NO_CONNECT".
8749*4882a593Smuzhiyun *
8750*4882a593Smuzhiyun * Link Down Timeout != 0:
8751*4882a593Smuzhiyun *
8752*4882a593Smuzhiyun * The driver waits for the link to come up after link down
8753*4882a593Smuzhiyun * before returning I/Os to OS with "DID_NO_CONNECT".
8754*4882a593Smuzhiyun */
8755*4882a593Smuzhiyun if (le16_to_cpu(nv->link_down_timeout) == 0) {
8756*4882a593Smuzhiyun ha->loop_down_abort_time =
8757*4882a593Smuzhiyun (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
8758*4882a593Smuzhiyun } else {
8759*4882a593Smuzhiyun ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
8760*4882a593Smuzhiyun ha->loop_down_abort_time =
8761*4882a593Smuzhiyun (LOOP_DOWN_TIME - ha->link_down_timeout);
8762*4882a593Smuzhiyun }
8763*4882a593Smuzhiyun
8764*4882a593Smuzhiyun /* Need enough time to try and get the port back. */
8765*4882a593Smuzhiyun ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
8766*4882a593Smuzhiyun if (qlport_down_retry)
8767*4882a593Smuzhiyun ha->port_down_retry_count = qlport_down_retry;
8768*4882a593Smuzhiyun
8769*4882a593Smuzhiyun /* Set login_retry_count */
8770*4882a593Smuzhiyun ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
8771*4882a593Smuzhiyun if (ha->port_down_retry_count ==
8772*4882a593Smuzhiyun le16_to_cpu(nv->port_down_retry_count) &&
8773*4882a593Smuzhiyun ha->port_down_retry_count > 3)
8774*4882a593Smuzhiyun ha->login_retry_count = ha->port_down_retry_count;
8775*4882a593Smuzhiyun else if (ha->port_down_retry_count > (int)ha->login_retry_count)
8776*4882a593Smuzhiyun ha->login_retry_count = ha->port_down_retry_count;
8777*4882a593Smuzhiyun if (ql2xloginretrycount)
8778*4882a593Smuzhiyun ha->login_retry_count = ql2xloginretrycount;
8779*4882a593Smuzhiyun
8780*4882a593Smuzhiyun /* if not running MSI-X we need handshaking on interrupts */
8781*4882a593Smuzhiyun if (!vha->hw->flags.msix_enabled &&
8782*4882a593Smuzhiyun (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)))
8783*4882a593Smuzhiyun icb->firmware_options_2 |= cpu_to_le32(BIT_22);
8784*4882a593Smuzhiyun
8785*4882a593Smuzhiyun /* Enable ZIO. */
8786*4882a593Smuzhiyun if (!vha->flags.init_done) {
8787*4882a593Smuzhiyun ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
8788*4882a593Smuzhiyun (BIT_3 | BIT_2 | BIT_1 | BIT_0);
8789*4882a593Smuzhiyun ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
8790*4882a593Smuzhiyun le16_to_cpu(icb->interrupt_delay_timer) : 2;
8791*4882a593Smuzhiyun }
8792*4882a593Smuzhiyun icb->firmware_options_2 &= cpu_to_le32(
8793*4882a593Smuzhiyun ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
8794*4882a593Smuzhiyun vha->flags.process_response_queue = 0;
8795*4882a593Smuzhiyun if (ha->zio_mode != QLA_ZIO_DISABLED) {
8796*4882a593Smuzhiyun ha->zio_mode = QLA_ZIO_MODE_6;
8797*4882a593Smuzhiyun
8798*4882a593Smuzhiyun ql_log(ql_log_info, vha, 0x0075,
8799*4882a593Smuzhiyun "ZIO mode %d enabled; timer delay (%d us).\n",
8800*4882a593Smuzhiyun ha->zio_mode,
8801*4882a593Smuzhiyun ha->zio_timer * 100);
8802*4882a593Smuzhiyun
8803*4882a593Smuzhiyun icb->firmware_options_2 |= cpu_to_le32(
8804*4882a593Smuzhiyun (uint32_t)ha->zio_mode);
8805*4882a593Smuzhiyun icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
8806*4882a593Smuzhiyun vha->flags.process_response_queue = 1;
8807*4882a593Smuzhiyun }
8808*4882a593Smuzhiyun
8809*4882a593Smuzhiyun /* enable RIDA Format2 */
8810*4882a593Smuzhiyun icb->firmware_options_3 |= cpu_to_le32(BIT_0);
8811*4882a593Smuzhiyun
8812*4882a593Smuzhiyun /* N2N: driver will initiate Login instead of FW */
8813*4882a593Smuzhiyun icb->firmware_options_3 |= cpu_to_le32(BIT_8);
8814*4882a593Smuzhiyun
8815*4882a593Smuzhiyun /* Determine NVMe/FCP priority for target ports */
8816*4882a593Smuzhiyun ha->fc4_type_priority = qla2xxx_get_fc4_priority(vha);
8817*4882a593Smuzhiyun
8818*4882a593Smuzhiyun if (rval) {
8819*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0076,
8820*4882a593Smuzhiyun "NVRAM configuration failed.\n");
8821*4882a593Smuzhiyun }
8822*4882a593Smuzhiyun return (rval);
8823*4882a593Smuzhiyun }
8824*4882a593Smuzhiyun
8825*4882a593Smuzhiyun int
qla82xx_restart_isp(scsi_qla_host_t * vha)8826*4882a593Smuzhiyun qla82xx_restart_isp(scsi_qla_host_t *vha)
8827*4882a593Smuzhiyun {
8828*4882a593Smuzhiyun int status, rval;
8829*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
8830*4882a593Smuzhiyun struct scsi_qla_host *vp;
8831*4882a593Smuzhiyun unsigned long flags;
8832*4882a593Smuzhiyun
8833*4882a593Smuzhiyun status = qla2x00_init_rings(vha);
8834*4882a593Smuzhiyun if (!status) {
8835*4882a593Smuzhiyun clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
8836*4882a593Smuzhiyun ha->flags.chip_reset_done = 1;
8837*4882a593Smuzhiyun
8838*4882a593Smuzhiyun status = qla2x00_fw_ready(vha);
8839*4882a593Smuzhiyun if (!status) {
8840*4882a593Smuzhiyun /* Issue a marker after FW becomes ready. */
8841*4882a593Smuzhiyun qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL);
8842*4882a593Smuzhiyun vha->flags.online = 1;
8843*4882a593Smuzhiyun set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
8844*4882a593Smuzhiyun }
8845*4882a593Smuzhiyun
8846*4882a593Smuzhiyun /* if no cable then assume it's good */
8847*4882a593Smuzhiyun if ((vha->device_flags & DFLG_NO_CABLE))
8848*4882a593Smuzhiyun status = 0;
8849*4882a593Smuzhiyun }
8850*4882a593Smuzhiyun
8851*4882a593Smuzhiyun if (!status) {
8852*4882a593Smuzhiyun clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
8853*4882a593Smuzhiyun
8854*4882a593Smuzhiyun if (!atomic_read(&vha->loop_down_timer)) {
8855*4882a593Smuzhiyun /*
8856*4882a593Smuzhiyun * Issue marker command only when we are going
8857*4882a593Smuzhiyun * to start the I/O .
8858*4882a593Smuzhiyun */
8859*4882a593Smuzhiyun vha->marker_needed = 1;
8860*4882a593Smuzhiyun }
8861*4882a593Smuzhiyun
8862*4882a593Smuzhiyun ha->isp_ops->enable_intrs(ha);
8863*4882a593Smuzhiyun
8864*4882a593Smuzhiyun ha->isp_abort_cnt = 0;
8865*4882a593Smuzhiyun clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
8866*4882a593Smuzhiyun
8867*4882a593Smuzhiyun /* Update the firmware version */
8868*4882a593Smuzhiyun status = qla82xx_check_md_needed(vha);
8869*4882a593Smuzhiyun
8870*4882a593Smuzhiyun if (ha->fce) {
8871*4882a593Smuzhiyun ha->flags.fce_enabled = 1;
8872*4882a593Smuzhiyun memset(ha->fce, 0,
8873*4882a593Smuzhiyun fce_calc_size(ha->fce_bufs));
8874*4882a593Smuzhiyun rval = qla2x00_enable_fce_trace(vha,
8875*4882a593Smuzhiyun ha->fce_dma, ha->fce_bufs, ha->fce_mb,
8876*4882a593Smuzhiyun &ha->fce_bufs);
8877*4882a593Smuzhiyun if (rval) {
8878*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x8001,
8879*4882a593Smuzhiyun "Unable to reinitialize FCE (%d).\n",
8880*4882a593Smuzhiyun rval);
8881*4882a593Smuzhiyun ha->flags.fce_enabled = 0;
8882*4882a593Smuzhiyun }
8883*4882a593Smuzhiyun }
8884*4882a593Smuzhiyun
8885*4882a593Smuzhiyun if (ha->eft) {
8886*4882a593Smuzhiyun memset(ha->eft, 0, EFT_SIZE);
8887*4882a593Smuzhiyun rval = qla2x00_enable_eft_trace(vha,
8888*4882a593Smuzhiyun ha->eft_dma, EFT_NUM_BUFFERS);
8889*4882a593Smuzhiyun if (rval) {
8890*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x8010,
8891*4882a593Smuzhiyun "Unable to reinitialize EFT (%d).\n",
8892*4882a593Smuzhiyun rval);
8893*4882a593Smuzhiyun }
8894*4882a593Smuzhiyun }
8895*4882a593Smuzhiyun }
8896*4882a593Smuzhiyun
8897*4882a593Smuzhiyun if (!status) {
8898*4882a593Smuzhiyun ql_dbg(ql_dbg_taskm, vha, 0x8011,
8899*4882a593Smuzhiyun "qla82xx_restart_isp succeeded.\n");
8900*4882a593Smuzhiyun
8901*4882a593Smuzhiyun spin_lock_irqsave(&ha->vport_slock, flags);
8902*4882a593Smuzhiyun list_for_each_entry(vp, &ha->vp_list, list) {
8903*4882a593Smuzhiyun if (vp->vp_idx) {
8904*4882a593Smuzhiyun atomic_inc(&vp->vref_count);
8905*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->vport_slock, flags);
8906*4882a593Smuzhiyun
8907*4882a593Smuzhiyun qla2x00_vp_abort_isp(vp);
8908*4882a593Smuzhiyun
8909*4882a593Smuzhiyun spin_lock_irqsave(&ha->vport_slock, flags);
8910*4882a593Smuzhiyun atomic_dec(&vp->vref_count);
8911*4882a593Smuzhiyun }
8912*4882a593Smuzhiyun }
8913*4882a593Smuzhiyun spin_unlock_irqrestore(&ha->vport_slock, flags);
8914*4882a593Smuzhiyun
8915*4882a593Smuzhiyun } else {
8916*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x8016,
8917*4882a593Smuzhiyun "qla82xx_restart_isp **** FAILED ****.\n");
8918*4882a593Smuzhiyun }
8919*4882a593Smuzhiyun
8920*4882a593Smuzhiyun return status;
8921*4882a593Smuzhiyun }
8922*4882a593Smuzhiyun
8923*4882a593Smuzhiyun /*
8924*4882a593Smuzhiyun * qla24xx_get_fcp_prio
8925*4882a593Smuzhiyun * Gets the fcp cmd priority value for the logged in port.
8926*4882a593Smuzhiyun * Looks for a match of the port descriptors within
8927*4882a593Smuzhiyun * each of the fcp prio config entries. If a match is found,
8928*4882a593Smuzhiyun * the tag (priority) value is returned.
8929*4882a593Smuzhiyun *
8930*4882a593Smuzhiyun * Input:
8931*4882a593Smuzhiyun * vha = scsi host structure pointer.
8932*4882a593Smuzhiyun * fcport = port structure pointer.
8933*4882a593Smuzhiyun *
8934*4882a593Smuzhiyun * Return:
8935*4882a593Smuzhiyun * non-zero (if found)
8936*4882a593Smuzhiyun * -1 (if not found)
8937*4882a593Smuzhiyun *
8938*4882a593Smuzhiyun * Context:
8939*4882a593Smuzhiyun * Kernel context
8940*4882a593Smuzhiyun */
8941*4882a593Smuzhiyun static int
qla24xx_get_fcp_prio(scsi_qla_host_t * vha,fc_port_t * fcport)8942*4882a593Smuzhiyun qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
8943*4882a593Smuzhiyun {
8944*4882a593Smuzhiyun int i, entries;
8945*4882a593Smuzhiyun uint8_t pid_match, wwn_match;
8946*4882a593Smuzhiyun int priority;
8947*4882a593Smuzhiyun uint32_t pid1, pid2;
8948*4882a593Smuzhiyun uint64_t wwn1, wwn2;
8949*4882a593Smuzhiyun struct qla_fcp_prio_entry *pri_entry;
8950*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
8951*4882a593Smuzhiyun
8952*4882a593Smuzhiyun if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
8953*4882a593Smuzhiyun return -1;
8954*4882a593Smuzhiyun
8955*4882a593Smuzhiyun priority = -1;
8956*4882a593Smuzhiyun entries = ha->fcp_prio_cfg->num_entries;
8957*4882a593Smuzhiyun pri_entry = &ha->fcp_prio_cfg->entry[0];
8958*4882a593Smuzhiyun
8959*4882a593Smuzhiyun for (i = 0; i < entries; i++) {
8960*4882a593Smuzhiyun pid_match = wwn_match = 0;
8961*4882a593Smuzhiyun
8962*4882a593Smuzhiyun if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
8963*4882a593Smuzhiyun pri_entry++;
8964*4882a593Smuzhiyun continue;
8965*4882a593Smuzhiyun }
8966*4882a593Smuzhiyun
8967*4882a593Smuzhiyun /* check source pid for a match */
8968*4882a593Smuzhiyun if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
8969*4882a593Smuzhiyun pid1 = pri_entry->src_pid & INVALID_PORT_ID;
8970*4882a593Smuzhiyun pid2 = vha->d_id.b24 & INVALID_PORT_ID;
8971*4882a593Smuzhiyun if (pid1 == INVALID_PORT_ID)
8972*4882a593Smuzhiyun pid_match++;
8973*4882a593Smuzhiyun else if (pid1 == pid2)
8974*4882a593Smuzhiyun pid_match++;
8975*4882a593Smuzhiyun }
8976*4882a593Smuzhiyun
8977*4882a593Smuzhiyun /* check destination pid for a match */
8978*4882a593Smuzhiyun if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
8979*4882a593Smuzhiyun pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
8980*4882a593Smuzhiyun pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
8981*4882a593Smuzhiyun if (pid1 == INVALID_PORT_ID)
8982*4882a593Smuzhiyun pid_match++;
8983*4882a593Smuzhiyun else if (pid1 == pid2)
8984*4882a593Smuzhiyun pid_match++;
8985*4882a593Smuzhiyun }
8986*4882a593Smuzhiyun
8987*4882a593Smuzhiyun /* check source WWN for a match */
8988*4882a593Smuzhiyun if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
8989*4882a593Smuzhiyun wwn1 = wwn_to_u64(vha->port_name);
8990*4882a593Smuzhiyun wwn2 = wwn_to_u64(pri_entry->src_wwpn);
8991*4882a593Smuzhiyun if (wwn2 == (uint64_t)-1)
8992*4882a593Smuzhiyun wwn_match++;
8993*4882a593Smuzhiyun else if (wwn1 == wwn2)
8994*4882a593Smuzhiyun wwn_match++;
8995*4882a593Smuzhiyun }
8996*4882a593Smuzhiyun
8997*4882a593Smuzhiyun /* check destination WWN for a match */
8998*4882a593Smuzhiyun if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
8999*4882a593Smuzhiyun wwn1 = wwn_to_u64(fcport->port_name);
9000*4882a593Smuzhiyun wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
9001*4882a593Smuzhiyun if (wwn2 == (uint64_t)-1)
9002*4882a593Smuzhiyun wwn_match++;
9003*4882a593Smuzhiyun else if (wwn1 == wwn2)
9004*4882a593Smuzhiyun wwn_match++;
9005*4882a593Smuzhiyun }
9006*4882a593Smuzhiyun
9007*4882a593Smuzhiyun if (pid_match == 2 || wwn_match == 2) {
9008*4882a593Smuzhiyun /* Found a matching entry */
9009*4882a593Smuzhiyun if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
9010*4882a593Smuzhiyun priority = pri_entry->tag;
9011*4882a593Smuzhiyun break;
9012*4882a593Smuzhiyun }
9013*4882a593Smuzhiyun
9014*4882a593Smuzhiyun pri_entry++;
9015*4882a593Smuzhiyun }
9016*4882a593Smuzhiyun
9017*4882a593Smuzhiyun return priority;
9018*4882a593Smuzhiyun }
9019*4882a593Smuzhiyun
9020*4882a593Smuzhiyun /*
9021*4882a593Smuzhiyun * qla24xx_update_fcport_fcp_prio
9022*4882a593Smuzhiyun * Activates fcp priority for the logged in fc port
9023*4882a593Smuzhiyun *
9024*4882a593Smuzhiyun * Input:
9025*4882a593Smuzhiyun * vha = scsi host structure pointer.
9026*4882a593Smuzhiyun * fcp = port structure pointer.
9027*4882a593Smuzhiyun *
9028*4882a593Smuzhiyun * Return:
9029*4882a593Smuzhiyun * QLA_SUCCESS or QLA_FUNCTION_FAILED
9030*4882a593Smuzhiyun *
9031*4882a593Smuzhiyun * Context:
9032*4882a593Smuzhiyun * Kernel context.
9033*4882a593Smuzhiyun */
9034*4882a593Smuzhiyun int
qla24xx_update_fcport_fcp_prio(scsi_qla_host_t * vha,fc_port_t * fcport)9035*4882a593Smuzhiyun qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
9036*4882a593Smuzhiyun {
9037*4882a593Smuzhiyun int ret;
9038*4882a593Smuzhiyun int priority;
9039*4882a593Smuzhiyun uint16_t mb[5];
9040*4882a593Smuzhiyun
9041*4882a593Smuzhiyun if (fcport->port_type != FCT_TARGET ||
9042*4882a593Smuzhiyun fcport->loop_id == FC_NO_LOOP_ID)
9043*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
9044*4882a593Smuzhiyun
9045*4882a593Smuzhiyun priority = qla24xx_get_fcp_prio(vha, fcport);
9046*4882a593Smuzhiyun if (priority < 0)
9047*4882a593Smuzhiyun return QLA_FUNCTION_FAILED;
9048*4882a593Smuzhiyun
9049*4882a593Smuzhiyun if (IS_P3P_TYPE(vha->hw)) {
9050*4882a593Smuzhiyun fcport->fcp_prio = priority & 0xf;
9051*4882a593Smuzhiyun return QLA_SUCCESS;
9052*4882a593Smuzhiyun }
9053*4882a593Smuzhiyun
9054*4882a593Smuzhiyun ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
9055*4882a593Smuzhiyun if (ret == QLA_SUCCESS) {
9056*4882a593Smuzhiyun if (fcport->fcp_prio != priority)
9057*4882a593Smuzhiyun ql_dbg(ql_dbg_user, vha, 0x709e,
9058*4882a593Smuzhiyun "Updated FCP_CMND priority - value=%d loop_id=%d "
9059*4882a593Smuzhiyun "port_id=%02x%02x%02x.\n", priority,
9060*4882a593Smuzhiyun fcport->loop_id, fcport->d_id.b.domain,
9061*4882a593Smuzhiyun fcport->d_id.b.area, fcport->d_id.b.al_pa);
9062*4882a593Smuzhiyun fcport->fcp_prio = priority & 0xf;
9063*4882a593Smuzhiyun } else
9064*4882a593Smuzhiyun ql_dbg(ql_dbg_user, vha, 0x704f,
9065*4882a593Smuzhiyun "Unable to update FCP_CMND priority - ret=0x%x for "
9066*4882a593Smuzhiyun "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
9067*4882a593Smuzhiyun fcport->d_id.b.domain, fcport->d_id.b.area,
9068*4882a593Smuzhiyun fcport->d_id.b.al_pa);
9069*4882a593Smuzhiyun return ret;
9070*4882a593Smuzhiyun }
9071*4882a593Smuzhiyun
9072*4882a593Smuzhiyun /*
9073*4882a593Smuzhiyun * qla24xx_update_all_fcp_prio
9074*4882a593Smuzhiyun * Activates fcp priority for all the logged in ports
9075*4882a593Smuzhiyun *
9076*4882a593Smuzhiyun * Input:
9077*4882a593Smuzhiyun * ha = adapter block pointer.
9078*4882a593Smuzhiyun *
9079*4882a593Smuzhiyun * Return:
9080*4882a593Smuzhiyun * QLA_SUCCESS or QLA_FUNCTION_FAILED
9081*4882a593Smuzhiyun *
9082*4882a593Smuzhiyun * Context:
9083*4882a593Smuzhiyun * Kernel context.
9084*4882a593Smuzhiyun */
9085*4882a593Smuzhiyun int
qla24xx_update_all_fcp_prio(scsi_qla_host_t * vha)9086*4882a593Smuzhiyun qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
9087*4882a593Smuzhiyun {
9088*4882a593Smuzhiyun int ret;
9089*4882a593Smuzhiyun fc_port_t *fcport;
9090*4882a593Smuzhiyun
9091*4882a593Smuzhiyun ret = QLA_FUNCTION_FAILED;
9092*4882a593Smuzhiyun /* We need to set priority for all logged in ports */
9093*4882a593Smuzhiyun list_for_each_entry(fcport, &vha->vp_fcports, list)
9094*4882a593Smuzhiyun ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
9095*4882a593Smuzhiyun
9096*4882a593Smuzhiyun return ret;
9097*4882a593Smuzhiyun }
9098*4882a593Smuzhiyun
qla2xxx_create_qpair(struct scsi_qla_host * vha,int qos,int vp_idx,bool startqp)9099*4882a593Smuzhiyun struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos,
9100*4882a593Smuzhiyun int vp_idx, bool startqp)
9101*4882a593Smuzhiyun {
9102*4882a593Smuzhiyun int rsp_id = 0;
9103*4882a593Smuzhiyun int req_id = 0;
9104*4882a593Smuzhiyun int i;
9105*4882a593Smuzhiyun struct qla_hw_data *ha = vha->hw;
9106*4882a593Smuzhiyun uint16_t qpair_id = 0;
9107*4882a593Smuzhiyun struct qla_qpair *qpair = NULL;
9108*4882a593Smuzhiyun struct qla_msix_entry *msix;
9109*4882a593Smuzhiyun
9110*4882a593Smuzhiyun if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) {
9111*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x00181,
9112*4882a593Smuzhiyun "FW/Driver is not multi-queue capable.\n");
9113*4882a593Smuzhiyun return NULL;
9114*4882a593Smuzhiyun }
9115*4882a593Smuzhiyun
9116*4882a593Smuzhiyun if (ql2xmqsupport || ql2xnvmeenable) {
9117*4882a593Smuzhiyun qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
9118*4882a593Smuzhiyun if (qpair == NULL) {
9119*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0182,
9120*4882a593Smuzhiyun "Failed to allocate memory for queue pair.\n");
9121*4882a593Smuzhiyun return NULL;
9122*4882a593Smuzhiyun }
9123*4882a593Smuzhiyun
9124*4882a593Smuzhiyun qpair->hw = vha->hw;
9125*4882a593Smuzhiyun qpair->vha = vha;
9126*4882a593Smuzhiyun qpair->qp_lock_ptr = &qpair->qp_lock;
9127*4882a593Smuzhiyun spin_lock_init(&qpair->qp_lock);
9128*4882a593Smuzhiyun qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
9129*4882a593Smuzhiyun
9130*4882a593Smuzhiyun /* Assign available que pair id */
9131*4882a593Smuzhiyun mutex_lock(&ha->mq_lock);
9132*4882a593Smuzhiyun qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs);
9133*4882a593Smuzhiyun if (ha->num_qpairs >= ha->max_qpairs) {
9134*4882a593Smuzhiyun mutex_unlock(&ha->mq_lock);
9135*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0183,
9136*4882a593Smuzhiyun "No resources to create additional q pair.\n");
9137*4882a593Smuzhiyun goto fail_qid_map;
9138*4882a593Smuzhiyun }
9139*4882a593Smuzhiyun ha->num_qpairs++;
9140*4882a593Smuzhiyun set_bit(qpair_id, ha->qpair_qid_map);
9141*4882a593Smuzhiyun ha->queue_pair_map[qpair_id] = qpair;
9142*4882a593Smuzhiyun qpair->id = qpair_id;
9143*4882a593Smuzhiyun qpair->vp_idx = vp_idx;
9144*4882a593Smuzhiyun qpair->fw_started = ha->flags.fw_started;
9145*4882a593Smuzhiyun INIT_LIST_HEAD(&qpair->hints_list);
9146*4882a593Smuzhiyun qpair->chip_reset = ha->base_qpair->chip_reset;
9147*4882a593Smuzhiyun qpair->enable_class_2 = ha->base_qpair->enable_class_2;
9148*4882a593Smuzhiyun qpair->enable_explicit_conf =
9149*4882a593Smuzhiyun ha->base_qpair->enable_explicit_conf;
9150*4882a593Smuzhiyun
9151*4882a593Smuzhiyun for (i = 0; i < ha->msix_count; i++) {
9152*4882a593Smuzhiyun msix = &ha->msix_entries[i];
9153*4882a593Smuzhiyun if (msix->in_use)
9154*4882a593Smuzhiyun continue;
9155*4882a593Smuzhiyun qpair->msix = msix;
9156*4882a593Smuzhiyun ql_dbg(ql_dbg_multiq, vha, 0xc00f,
9157*4882a593Smuzhiyun "Vector %x selected for qpair\n", msix->vector);
9158*4882a593Smuzhiyun break;
9159*4882a593Smuzhiyun }
9160*4882a593Smuzhiyun if (!qpair->msix) {
9161*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0184,
9162*4882a593Smuzhiyun "Out of MSI-X vectors!.\n");
9163*4882a593Smuzhiyun goto fail_msix;
9164*4882a593Smuzhiyun }
9165*4882a593Smuzhiyun
9166*4882a593Smuzhiyun qpair->msix->in_use = 1;
9167*4882a593Smuzhiyun list_add_tail(&qpair->qp_list_elem, &vha->qp_list);
9168*4882a593Smuzhiyun qpair->pdev = ha->pdev;
9169*4882a593Smuzhiyun if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
9170*4882a593Smuzhiyun qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
9171*4882a593Smuzhiyun
9172*4882a593Smuzhiyun mutex_unlock(&ha->mq_lock);
9173*4882a593Smuzhiyun
9174*4882a593Smuzhiyun /* Create response queue first */
9175*4882a593Smuzhiyun rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair, startqp);
9176*4882a593Smuzhiyun if (!rsp_id) {
9177*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0185,
9178*4882a593Smuzhiyun "Failed to create response queue.\n");
9179*4882a593Smuzhiyun goto fail_rsp;
9180*4882a593Smuzhiyun }
9181*4882a593Smuzhiyun
9182*4882a593Smuzhiyun qpair->rsp = ha->rsp_q_map[rsp_id];
9183*4882a593Smuzhiyun
9184*4882a593Smuzhiyun /* Create request queue */
9185*4882a593Smuzhiyun req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos,
9186*4882a593Smuzhiyun startqp);
9187*4882a593Smuzhiyun if (!req_id) {
9188*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0x0186,
9189*4882a593Smuzhiyun "Failed to create request queue.\n");
9190*4882a593Smuzhiyun goto fail_req;
9191*4882a593Smuzhiyun }
9192*4882a593Smuzhiyun
9193*4882a593Smuzhiyun qpair->req = ha->req_q_map[req_id];
9194*4882a593Smuzhiyun qpair->rsp->req = qpair->req;
9195*4882a593Smuzhiyun qpair->rsp->qpair = qpair;
9196*4882a593Smuzhiyun /* init qpair to this cpu. Will adjust at run time. */
9197*4882a593Smuzhiyun qla_cpu_update(qpair, raw_smp_processor_id());
9198*4882a593Smuzhiyun
9199*4882a593Smuzhiyun if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
9200*4882a593Smuzhiyun if (ha->fw_attributes & BIT_4)
9201*4882a593Smuzhiyun qpair->difdix_supported = 1;
9202*4882a593Smuzhiyun }
9203*4882a593Smuzhiyun
9204*4882a593Smuzhiyun qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
9205*4882a593Smuzhiyun if (!qpair->srb_mempool) {
9206*4882a593Smuzhiyun ql_log(ql_log_warn, vha, 0xd036,
9207*4882a593Smuzhiyun "Failed to create srb mempool for qpair %d\n",
9208*4882a593Smuzhiyun qpair->id);
9209*4882a593Smuzhiyun goto fail_mempool;
9210*4882a593Smuzhiyun }
9211*4882a593Smuzhiyun
9212*4882a593Smuzhiyun /* Mark as online */
9213*4882a593Smuzhiyun qpair->online = 1;
9214*4882a593Smuzhiyun
9215*4882a593Smuzhiyun if (!vha->flags.qpairs_available)
9216*4882a593Smuzhiyun vha->flags.qpairs_available = 1;
9217*4882a593Smuzhiyun
9218*4882a593Smuzhiyun ql_dbg(ql_dbg_multiq, vha, 0xc00d,
9219*4882a593Smuzhiyun "Request/Response queue pair created, id %d\n",
9220*4882a593Smuzhiyun qpair->id);
9221*4882a593Smuzhiyun ql_dbg(ql_dbg_init, vha, 0x0187,
9222*4882a593Smuzhiyun "Request/Response queue pair created, id %d\n",
9223*4882a593Smuzhiyun qpair->id);
9224*4882a593Smuzhiyun }
9225*4882a593Smuzhiyun return qpair;
9226*4882a593Smuzhiyun
9227*4882a593Smuzhiyun fail_mempool:
9228*4882a593Smuzhiyun fail_req:
9229*4882a593Smuzhiyun qla25xx_delete_rsp_que(vha, qpair->rsp);
9230*4882a593Smuzhiyun fail_rsp:
9231*4882a593Smuzhiyun mutex_lock(&ha->mq_lock);
9232*4882a593Smuzhiyun qpair->msix->in_use = 0;
9233*4882a593Smuzhiyun list_del(&qpair->qp_list_elem);
9234*4882a593Smuzhiyun if (list_empty(&vha->qp_list))
9235*4882a593Smuzhiyun vha->flags.qpairs_available = 0;
9236*4882a593Smuzhiyun fail_msix:
9237*4882a593Smuzhiyun ha->queue_pair_map[qpair_id] = NULL;
9238*4882a593Smuzhiyun clear_bit(qpair_id, ha->qpair_qid_map);
9239*4882a593Smuzhiyun ha->num_qpairs--;
9240*4882a593Smuzhiyun mutex_unlock(&ha->mq_lock);
9241*4882a593Smuzhiyun fail_qid_map:
9242*4882a593Smuzhiyun kfree(qpair);
9243*4882a593Smuzhiyun return NULL;
9244*4882a593Smuzhiyun }
9245*4882a593Smuzhiyun
qla2xxx_delete_qpair(struct scsi_qla_host * vha,struct qla_qpair * qpair)9246*4882a593Smuzhiyun int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair)
9247*4882a593Smuzhiyun {
9248*4882a593Smuzhiyun int ret = QLA_FUNCTION_FAILED;
9249*4882a593Smuzhiyun struct qla_hw_data *ha = qpair->hw;
9250*4882a593Smuzhiyun
9251*4882a593Smuzhiyun qpair->delete_in_progress = 1;
9252*4882a593Smuzhiyun
9253*4882a593Smuzhiyun ret = qla25xx_delete_req_que(vha, qpair->req);
9254*4882a593Smuzhiyun if (ret != QLA_SUCCESS)
9255*4882a593Smuzhiyun goto fail;
9256*4882a593Smuzhiyun
9257*4882a593Smuzhiyun ret = qla25xx_delete_rsp_que(vha, qpair->rsp);
9258*4882a593Smuzhiyun if (ret != QLA_SUCCESS)
9259*4882a593Smuzhiyun goto fail;
9260*4882a593Smuzhiyun
9261*4882a593Smuzhiyun mutex_lock(&ha->mq_lock);
9262*4882a593Smuzhiyun ha->queue_pair_map[qpair->id] = NULL;
9263*4882a593Smuzhiyun clear_bit(qpair->id, ha->qpair_qid_map);
9264*4882a593Smuzhiyun ha->num_qpairs--;
9265*4882a593Smuzhiyun list_del(&qpair->qp_list_elem);
9266*4882a593Smuzhiyun if (list_empty(&vha->qp_list)) {
9267*4882a593Smuzhiyun vha->flags.qpairs_available = 0;
9268*4882a593Smuzhiyun vha->flags.qpairs_req_created = 0;
9269*4882a593Smuzhiyun vha->flags.qpairs_rsp_created = 0;
9270*4882a593Smuzhiyun }
9271*4882a593Smuzhiyun mempool_destroy(qpair->srb_mempool);
9272*4882a593Smuzhiyun kfree(qpair);
9273*4882a593Smuzhiyun mutex_unlock(&ha->mq_lock);
9274*4882a593Smuzhiyun
9275*4882a593Smuzhiyun return QLA_SUCCESS;
9276*4882a593Smuzhiyun fail:
9277*4882a593Smuzhiyun return ret;
9278*4882a593Smuzhiyun }
9279