1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * PMC-Sierra 8001/8081/8088/8089 SAS/SATA based host adapters driver 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (c) 2008-2009 USI Co., Ltd. 5*4882a593Smuzhiyun * All rights reserved. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without 8*4882a593Smuzhiyun * modification, are permitted provided that the following conditions 9*4882a593Smuzhiyun * are met: 10*4882a593Smuzhiyun * 1. Redistributions of source code must retain the above copyright 11*4882a593Smuzhiyun * notice, this list of conditions, and the following disclaimer, 12*4882a593Smuzhiyun * without modification. 13*4882a593Smuzhiyun * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14*4882a593Smuzhiyun * substantially similar to the "NO WARRANTY" disclaimer below 15*4882a593Smuzhiyun * ("Disclaimer") and any redistribution must be conditioned upon 16*4882a593Smuzhiyun * including a substantially similar Disclaimer requirement for further 17*4882a593Smuzhiyun * binary redistribution. 18*4882a593Smuzhiyun * 3. Neither the names of the above-listed copyright holders nor the names 19*4882a593Smuzhiyun * of any contributors may be used to endorse or promote products derived 20*4882a593Smuzhiyun * from this software without specific prior written permission. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Alternatively, this software may be distributed under the terms of the 23*4882a593Smuzhiyun * GNU General Public License ("GPL") version 2 as published by the Free 24*4882a593Smuzhiyun * Software Foundation. 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * NO WARRANTY 27*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28*4882a593Smuzhiyun * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29*4882a593Smuzhiyun * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30*4882a593Smuzhiyun * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31*4882a593Smuzhiyun * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32*4882a593Smuzhiyun * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33*4882a593Smuzhiyun * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34*4882a593Smuzhiyun * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35*4882a593Smuzhiyun * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36*4882a593Smuzhiyun * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37*4882a593Smuzhiyun * POSSIBILITY OF SUCH DAMAGES. 38*4882a593Smuzhiyun * 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #ifndef _PM8001_DEFS_H_ 42*4882a593Smuzhiyun #define _PM8001_DEFS_H_ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun enum chip_flavors { 45*4882a593Smuzhiyun chip_8001, 46*4882a593Smuzhiyun chip_8008, 47*4882a593Smuzhiyun chip_8009, 48*4882a593Smuzhiyun chip_8018, 49*4882a593Smuzhiyun chip_8019, 50*4882a593Smuzhiyun chip_8074, 51*4882a593Smuzhiyun chip_8076, 52*4882a593Smuzhiyun chip_8077, 53*4882a593Smuzhiyun chip_8006, 54*4882a593Smuzhiyun chip_8070, 55*4882a593Smuzhiyun chip_8072 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun enum phy_speed { 59*4882a593Smuzhiyun PHY_SPEED_15 = 0x01, 60*4882a593Smuzhiyun PHY_SPEED_30 = 0x02, 61*4882a593Smuzhiyun PHY_SPEED_60 = 0x04, 62*4882a593Smuzhiyun PHY_SPEED_120 = 0x08, 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun enum data_direction { 66*4882a593Smuzhiyun DATA_DIR_NONE = 0x0, /* NO TRANSFER */ 67*4882a593Smuzhiyun DATA_DIR_IN = 0x01, /* INBOUND */ 68*4882a593Smuzhiyun DATA_DIR_OUT = 0x02, /* OUTBOUND */ 69*4882a593Smuzhiyun DATA_DIR_BYRECIPIENT = 0x04, /* UNSPECIFIED */ 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun enum port_type { 73*4882a593Smuzhiyun PORT_TYPE_SAS = (1L << 1), 74*4882a593Smuzhiyun PORT_TYPE_SATA = (1L << 0), 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* driver compile-time configuration */ 78*4882a593Smuzhiyun #define PM8001_MAX_CCB 1024 /* max ccbs supported */ 79*4882a593Smuzhiyun #define PM8001_MPI_QUEUE 1024 /* maximum mpi queue entries */ 80*4882a593Smuzhiyun #define PM8001_MAX_INB_NUM 64 81*4882a593Smuzhiyun #define PM8001_MAX_OUTB_NUM 64 82*4882a593Smuzhiyun #define PM8001_CAN_QUEUE 508 /* SCSI Queue depth */ 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* Inbound/Outbound queue size */ 85*4882a593Smuzhiyun #define IOMB_SIZE_SPC 64 86*4882a593Smuzhiyun #define IOMB_SIZE_SPCV 128 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* unchangeable hardware details */ 89*4882a593Smuzhiyun #define PM8001_MAX_PHYS 16 /* max. possible phys */ 90*4882a593Smuzhiyun #define PM8001_MAX_PORTS 16 /* max. possible ports */ 91*4882a593Smuzhiyun #define PM8001_MAX_DEVICES 2048 /* max supported device */ 92*4882a593Smuzhiyun #define PM8001_MAX_MSIX_VEC 64 /* max msi-x int for spcv/ve */ 93*4882a593Smuzhiyun #define PM8001_RESERVE_SLOT 8 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define CONFIG_SCSI_PM8001_MAX_DMA_SG 528 96*4882a593Smuzhiyun #define PM8001_MAX_DMA_SG CONFIG_SCSI_PM8001_MAX_DMA_SG 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun enum memory_region_num { 99*4882a593Smuzhiyun AAP1 = 0x0, /* application acceleration processor */ 100*4882a593Smuzhiyun IOP, /* IO processor */ 101*4882a593Smuzhiyun NVMD, /* NVM device */ 102*4882a593Smuzhiyun FW_FLASH, /* memory for fw flash update */ 103*4882a593Smuzhiyun FORENSIC_MEM, /* memory for fw forensic data */ 104*4882a593Smuzhiyun USI_MAX_MEMCNT_BASE 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun #define PM8001_EVENT_LOG_SIZE (128 * 1024) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /** 109*4882a593Smuzhiyun * maximum DMA memory regions(number of IBQ + number of IBQ CI 110*4882a593Smuzhiyun * + number of OBQ + number of OBQ PI) 111*4882a593Smuzhiyun */ 112*4882a593Smuzhiyun #define USI_MAX_MEMCNT (USI_MAX_MEMCNT_BASE + ((2 * PM8001_MAX_INB_NUM) \ 113*4882a593Smuzhiyun + (2 * PM8001_MAX_OUTB_NUM))) 114*4882a593Smuzhiyun /*error code*/ 115*4882a593Smuzhiyun enum mpi_err { 116*4882a593Smuzhiyun MPI_IO_STATUS_SUCCESS = 0x0, 117*4882a593Smuzhiyun MPI_IO_STATUS_BUSY = 0x01, 118*4882a593Smuzhiyun MPI_IO_STATUS_FAIL = 0x02, 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /** 122*4882a593Smuzhiyun * Phy Control constants 123*4882a593Smuzhiyun */ 124*4882a593Smuzhiyun enum phy_control_type { 125*4882a593Smuzhiyun PHY_LINK_RESET = 0x01, 126*4882a593Smuzhiyun PHY_HARD_RESET = 0x02, 127*4882a593Smuzhiyun PHY_NOTIFY_ENABLE_SPINUP = 0x10, 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun enum pm8001_hba_info_flags { 131*4882a593Smuzhiyun PM8001F_INIT_TIME = (1U << 0), 132*4882a593Smuzhiyun PM8001F_RUN_TIME = (1U << 1), 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /** 136*4882a593Smuzhiyun * Phy Status 137*4882a593Smuzhiyun */ 138*4882a593Smuzhiyun #define PHY_LINK_DISABLE 0x00 139*4882a593Smuzhiyun #define PHY_LINK_DOWN 0x01 140*4882a593Smuzhiyun #define PHY_STATE_LINK_UP_SPCV 0x2 141*4882a593Smuzhiyun #define PHY_STATE_LINK_UP_SPC 0x1 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #endif 144