1*4882a593Smuzhiyun /*=======================================================/ 2*4882a593Smuzhiyun Header file for nsp_cs.c 3*4882a593Smuzhiyun By: YOKOTA Hiroshi <yokota@netlab.is.tsukuba.ac.jp> 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun Ver.1.0 : Cut unused lines. 6*4882a593Smuzhiyun Ver 0.1 : Initial version. 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun This software may be used and distributed according to the terms of 9*4882a593Smuzhiyun the GNU General Public License. 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun =========================================================*/ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef __nsp_cs__ 14*4882a593Smuzhiyun #define __nsp_cs__ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* for debugging */ 17*4882a593Smuzhiyun //#define NSP_DEBUG 9 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun #define static 21*4882a593Smuzhiyun #define inline 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /************************************ 25*4882a593Smuzhiyun * Some useful macros... 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* SCSI initiator must be ID 7 */ 29*4882a593Smuzhiyun #define NSP_INITIATOR_ID 7 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define NSP_SELTIMEOUT 200 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /*************************************************************************** 34*4882a593Smuzhiyun * register definitions 35*4882a593Smuzhiyun ***************************************************************************/ 36*4882a593Smuzhiyun /*======================================================================== 37*4882a593Smuzhiyun * base register 38*4882a593Smuzhiyun ========================================================================*/ 39*4882a593Smuzhiyun #define IRQCONTROL 0x00 /* R */ 40*4882a593Smuzhiyun # define IRQCONTROL_RESELECT_CLEAR BIT(0) 41*4882a593Smuzhiyun # define IRQCONTROL_PHASE_CHANGE_CLEAR BIT(1) 42*4882a593Smuzhiyun # define IRQCONTROL_TIMER_CLEAR BIT(2) 43*4882a593Smuzhiyun # define IRQCONTROL_FIFO_CLEAR BIT(3) 44*4882a593Smuzhiyun # define IRQCONTROL_ALLMASK 0xff 45*4882a593Smuzhiyun # define IRQCONTROL_ALLCLEAR (IRQCONTROL_RESELECT_CLEAR | \ 46*4882a593Smuzhiyun IRQCONTROL_PHASE_CHANGE_CLEAR | \ 47*4882a593Smuzhiyun IRQCONTROL_TIMER_CLEAR | \ 48*4882a593Smuzhiyun IRQCONTROL_FIFO_CLEAR ) 49*4882a593Smuzhiyun # define IRQCONTROL_IRQDISABLE 0xf0 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define IRQSTATUS 0x00 /* W */ 52*4882a593Smuzhiyun # define IRQSTATUS_SCSI BIT(0) 53*4882a593Smuzhiyun # define IRQSTATUS_TIMER BIT(2) 54*4882a593Smuzhiyun # define IRQSTATUS_FIFO BIT(3) 55*4882a593Smuzhiyun # define IRQSTATUS_MASK 0x0f 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define IFSELECT 0x01 /* W */ 58*4882a593Smuzhiyun # define IF_IFSEL BIT(0) 59*4882a593Smuzhiyun # define IF_REGSEL BIT(2) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define FIFOSTATUS 0x01 /* R */ 62*4882a593Smuzhiyun # define FIFOSTATUS_CHIP_REVISION_MASK 0x0f 63*4882a593Smuzhiyun # define FIFOSTATUS_CHIP_ID_MASK 0x70 64*4882a593Smuzhiyun # define FIFOSTATUS_FULL_EMPTY BIT(7) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define INDEXREG 0x02 /* R/W */ 67*4882a593Smuzhiyun #define DATAREG 0x03 /* R/W */ 68*4882a593Smuzhiyun #define FIFODATA 0x04 /* R/W */ 69*4882a593Smuzhiyun #define FIFODATA1 0x05 /* R/W */ 70*4882a593Smuzhiyun #define FIFODATA2 0x06 /* R/W */ 71*4882a593Smuzhiyun #define FIFODATA3 0x07 /* R/W */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /*==================================================================== 74*4882a593Smuzhiyun * indexed register 75*4882a593Smuzhiyun ====================================================================*/ 76*4882a593Smuzhiyun #define EXTBUSCTRL 0x10 /* R/W,deleted */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define CLOCKDIV 0x11 /* R/W */ 79*4882a593Smuzhiyun # define CLOCK_40M 0x02 80*4882a593Smuzhiyun # define CLOCK_20M 0x01 81*4882a593Smuzhiyun # define FAST_20 BIT(2) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define TERMPWRCTRL 0x13 /* R/W */ 84*4882a593Smuzhiyun # define POWER_ON BIT(0) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define SCSIIRQMODE 0x15 /* R/W */ 87*4882a593Smuzhiyun # define SCSI_PHASE_CHANGE_EI BIT(0) 88*4882a593Smuzhiyun # define RESELECT_EI BIT(4) 89*4882a593Smuzhiyun # define FIFO_IRQ_EI BIT(5) 90*4882a593Smuzhiyun # define SCSI_RESET_IRQ_EI BIT(6) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define IRQPHASESENCE 0x16 /* R */ 93*4882a593Smuzhiyun # define LATCHED_MSG BIT(0) 94*4882a593Smuzhiyun # define LATCHED_IO BIT(1) 95*4882a593Smuzhiyun # define LATCHED_CD BIT(2) 96*4882a593Smuzhiyun # define LATCHED_BUS_FREE BIT(3) 97*4882a593Smuzhiyun # define PHASE_CHANGE_IRQ BIT(4) 98*4882a593Smuzhiyun # define RESELECT_IRQ BIT(5) 99*4882a593Smuzhiyun # define FIFO_IRQ BIT(6) 100*4882a593Smuzhiyun # define SCSI_RESET_IRQ BIT(7) 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define TIMERCOUNT 0x17 /* R/W */ 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define SCSIBUSCTRL 0x18 /* R/W */ 105*4882a593Smuzhiyun # define SCSI_SEL BIT(0) 106*4882a593Smuzhiyun # define SCSI_RST BIT(1) 107*4882a593Smuzhiyun # define SCSI_DATAOUT_ENB BIT(2) 108*4882a593Smuzhiyun # define SCSI_ATN BIT(3) 109*4882a593Smuzhiyun # define SCSI_ACK BIT(4) 110*4882a593Smuzhiyun # define SCSI_BSY BIT(5) 111*4882a593Smuzhiyun # define AUTODIRECTION BIT(6) 112*4882a593Smuzhiyun # define ACKENB BIT(7) 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define SCSIBUSMON 0x19 /* R */ 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #define SETARBIT 0x1A /* W */ 117*4882a593Smuzhiyun # define ARBIT_GO BIT(0) 118*4882a593Smuzhiyun # define ARBIT_FLAG_CLEAR BIT(1) 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define ARBITSTATUS 0x1A /* R */ 121*4882a593Smuzhiyun /*# define ARBIT_GO BIT(0)*/ 122*4882a593Smuzhiyun # define ARBIT_WIN BIT(1) 123*4882a593Smuzhiyun # define ARBIT_FAIL BIT(2) 124*4882a593Smuzhiyun # define RESELECT_FLAG BIT(3) 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define PARITYCTRL 0x1B /* W */ 127*4882a593Smuzhiyun #define PARITYSTATUS 0x1B /* R */ 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define COMMANDCTRL 0x1C /* W */ 130*4882a593Smuzhiyun # define CLEAR_COMMAND_POINTER BIT(0) 131*4882a593Smuzhiyun # define AUTO_COMMAND_GO BIT(1) 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define RESELECTID 0x1C /* R */ 134*4882a593Smuzhiyun #define COMMANDDATA 0x1D /* R/W */ 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define POINTERCLR 0x1E /* W */ 137*4882a593Smuzhiyun # define POINTER_CLEAR BIT(0) 138*4882a593Smuzhiyun # define ACK_COUNTER_CLEAR BIT(1) 139*4882a593Smuzhiyun # define REQ_COUNTER_CLEAR BIT(2) 140*4882a593Smuzhiyun # define HOST_COUNTER_CLEAR BIT(3) 141*4882a593Smuzhiyun # define READ_SOURCE (BIT(4) | BIT(5)) 142*4882a593Smuzhiyun # define ACK_COUNTER (0) 143*4882a593Smuzhiyun # define REQ_COUNTER (BIT(4)) 144*4882a593Smuzhiyun # define HOST_COUNTER (BIT(5)) 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define TRANSFERCOUNT 0x1E /* R */ 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #define TRANSFERMODE 0x20 /* R/W */ 149*4882a593Smuzhiyun # define MODE_MEM8 BIT(0) 150*4882a593Smuzhiyun # define MODE_MEM32 BIT(1) 151*4882a593Smuzhiyun # define MODE_ADR24 BIT(2) 152*4882a593Smuzhiyun # define MODE_ADR32 BIT(3) 153*4882a593Smuzhiyun # define MODE_IO8 BIT(4) 154*4882a593Smuzhiyun # define MODE_IO32 BIT(5) 155*4882a593Smuzhiyun # define TRANSFER_GO BIT(6) 156*4882a593Smuzhiyun # define BRAIND BIT(7) 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun #define SYNCREG 0x21 /* R/W */ 159*4882a593Smuzhiyun # define SYNCREG_OFFSET_MASK 0x0f 160*4882a593Smuzhiyun # define SYNCREG_PERIOD_MASK 0xf0 161*4882a593Smuzhiyun # define SYNCREG_PERIOD_SHIFT 4 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun #define SCSIDATALATCH 0x22 /* W */ 164*4882a593Smuzhiyun #define SCSIDATAIN 0x22 /* R */ 165*4882a593Smuzhiyun #define SCSIDATAWITHACK 0x23 /* R/W */ 166*4882a593Smuzhiyun #define SCAMCONTROL 0x24 /* W */ 167*4882a593Smuzhiyun #define SCAMSTATUS 0x24 /* R */ 168*4882a593Smuzhiyun #define SCAMDATA 0x25 /* R/W */ 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun #define OTHERCONTROL 0x26 /* R/W */ 171*4882a593Smuzhiyun # define TPL_ROM_WRITE_EN BIT(0) 172*4882a593Smuzhiyun # define TPWR_OUT BIT(1) 173*4882a593Smuzhiyun # define TPWR_SENSE BIT(2) 174*4882a593Smuzhiyun # define RA8_CONTROL BIT(3) 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun #define ACKWIDTH 0x27 /* R/W */ 177*4882a593Smuzhiyun #define CLRTESTPNT 0x28 /* W */ 178*4882a593Smuzhiyun #define ACKCNTLD 0x29 /* W */ 179*4882a593Smuzhiyun #define REQCNTLD 0x2A /* W */ 180*4882a593Smuzhiyun #define HSTCNTLD 0x2B /* W */ 181*4882a593Smuzhiyun #define CHECKSUM 0x2C /* R/W */ 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun /************************************************************************ 184*4882a593Smuzhiyun * Input status bit definitions. 185*4882a593Smuzhiyun ************************************************************************/ 186*4882a593Smuzhiyun #define S_MESSAGE BIT(0) /* Message line from SCSI bus */ 187*4882a593Smuzhiyun #define S_IO BIT(1) /* Input/Output line from SCSI bus */ 188*4882a593Smuzhiyun #define S_CD BIT(2) /* Command/Data line from SCSI bus */ 189*4882a593Smuzhiyun #define S_BUSY BIT(3) /* Busy line from SCSI bus */ 190*4882a593Smuzhiyun #define S_ACK BIT(4) /* Acknowledge line from SCSI bus */ 191*4882a593Smuzhiyun #define S_REQUEST BIT(5) /* Request line from SCSI bus */ 192*4882a593Smuzhiyun #define S_SELECT BIT(6) /* */ 193*4882a593Smuzhiyun #define S_ATN BIT(7) /* */ 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun /*********************************************************************** 196*4882a593Smuzhiyun * Useful Bus Monitor status combinations. 197*4882a593Smuzhiyun ***********************************************************************/ 198*4882a593Smuzhiyun #define BUSMON_SEL S_SELECT 199*4882a593Smuzhiyun #define BUSMON_BSY S_BUSY 200*4882a593Smuzhiyun #define BUSMON_REQ S_REQUEST 201*4882a593Smuzhiyun #define BUSMON_IO S_IO 202*4882a593Smuzhiyun #define BUSMON_ACK S_ACK 203*4882a593Smuzhiyun #define BUSMON_BUS_FREE 0 204*4882a593Smuzhiyun #define BUSMON_COMMAND ( S_BUSY | S_CD | S_REQUEST ) 205*4882a593Smuzhiyun #define BUSMON_MESSAGE_IN ( S_BUSY | S_CD | S_IO | S_MESSAGE | S_REQUEST ) 206*4882a593Smuzhiyun #define BUSMON_MESSAGE_OUT ( S_BUSY | S_CD | S_MESSAGE | S_REQUEST ) 207*4882a593Smuzhiyun #define BUSMON_DATA_IN ( S_BUSY | S_IO | S_REQUEST ) 208*4882a593Smuzhiyun #define BUSMON_DATA_OUT ( S_BUSY | S_REQUEST ) 209*4882a593Smuzhiyun #define BUSMON_STATUS ( S_BUSY | S_CD | S_IO | S_REQUEST ) 210*4882a593Smuzhiyun #define BUSMON_SELECT ( S_IO | S_SELECT ) 211*4882a593Smuzhiyun #define BUSMON_RESELECT ( S_IO | S_SELECT ) 212*4882a593Smuzhiyun #define BUSMON_PHASE_MASK ( S_CD | S_IO | S_MESSAGE | S_SELECT ) 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun #define BUSPHASE_SELECT ( BUSMON_SELECT & BUSMON_PHASE_MASK ) 215*4882a593Smuzhiyun #define BUSPHASE_COMMAND ( BUSMON_COMMAND & BUSMON_PHASE_MASK ) 216*4882a593Smuzhiyun #define BUSPHASE_MESSAGE_IN ( BUSMON_MESSAGE_IN & BUSMON_PHASE_MASK ) 217*4882a593Smuzhiyun #define BUSPHASE_MESSAGE_OUT ( BUSMON_MESSAGE_OUT & BUSMON_PHASE_MASK ) 218*4882a593Smuzhiyun #define BUSPHASE_DATA_IN ( BUSMON_DATA_IN & BUSMON_PHASE_MASK ) 219*4882a593Smuzhiyun #define BUSPHASE_DATA_OUT ( BUSMON_DATA_OUT & BUSMON_PHASE_MASK ) 220*4882a593Smuzhiyun #define BUSPHASE_STATUS ( BUSMON_STATUS & BUSMON_PHASE_MASK ) 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun /*====================================================================*/ 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun typedef struct scsi_info_t { 225*4882a593Smuzhiyun struct pcmcia_device *p_dev; 226*4882a593Smuzhiyun struct Scsi_Host *host; 227*4882a593Smuzhiyun int stop; 228*4882a593Smuzhiyun } scsi_info_t; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun /* synchronous transfer negotiation data */ 232*4882a593Smuzhiyun typedef struct _sync_data { 233*4882a593Smuzhiyun unsigned int SyncNegotiation; 234*4882a593Smuzhiyun #define SYNC_NOT_YET 0 235*4882a593Smuzhiyun #define SYNC_OK 1 236*4882a593Smuzhiyun #define SYNC_NG 2 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun unsigned int SyncPeriod; 239*4882a593Smuzhiyun unsigned int SyncOffset; 240*4882a593Smuzhiyun unsigned char SyncRegister; 241*4882a593Smuzhiyun unsigned char AckWidth; 242*4882a593Smuzhiyun } sync_data; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun typedef struct _nsp_hw_data { 245*4882a593Smuzhiyun unsigned int BaseAddress; 246*4882a593Smuzhiyun unsigned int NumAddress; 247*4882a593Smuzhiyun unsigned int IrqNumber; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun unsigned long MmioAddress; 250*4882a593Smuzhiyun #define NSP_MMIO_OFFSET 0x0800 251*4882a593Smuzhiyun unsigned long MmioLength; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun unsigned char ScsiClockDiv; 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun unsigned char TransferMode; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun int TimerCount; 258*4882a593Smuzhiyun int SelectionTimeOut; 259*4882a593Smuzhiyun struct scsi_cmnd *CurrentSC; 260*4882a593Smuzhiyun //int CurrnetTarget; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun int FifoCount; 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun #define MSGBUF_SIZE 20 265*4882a593Smuzhiyun unsigned char MsgBuffer[MSGBUF_SIZE]; 266*4882a593Smuzhiyun int MsgLen; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun #define N_TARGET 8 269*4882a593Smuzhiyun sync_data Sync[N_TARGET]; 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun char nspinfo[110]; /* description */ 272*4882a593Smuzhiyun spinlock_t Lock; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun scsi_info_t *ScsiInfo; /* attach <-> detect glue */ 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun #ifdef NSP_DEBUG 278*4882a593Smuzhiyun int CmdId; /* Accepted command serial number. 279*4882a593Smuzhiyun Used for debugging. */ 280*4882a593Smuzhiyun #endif 281*4882a593Smuzhiyun } nsp_hw_data; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun /**************************************************************************** 284*4882a593Smuzhiyun * 285*4882a593Smuzhiyun */ 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun /* Card service functions */ 288*4882a593Smuzhiyun static void nsp_cs_detach (struct pcmcia_device *p_dev); 289*4882a593Smuzhiyun static void nsp_cs_release(struct pcmcia_device *link); 290*4882a593Smuzhiyun static int nsp_cs_config (struct pcmcia_device *link); 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun /* Linux SCSI subsystem specific functions */ 293*4882a593Smuzhiyun static struct Scsi_Host *nsp_detect (struct scsi_host_template *sht); 294*4882a593Smuzhiyun static const char *nsp_info (struct Scsi_Host *shpnt); 295*4882a593Smuzhiyun static int nsp_show_info (struct seq_file *m, 296*4882a593Smuzhiyun struct Scsi_Host *host); 297*4882a593Smuzhiyun static int nsp_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *SCpnt); 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun /* Error handler */ 300*4882a593Smuzhiyun /*static int nsp_eh_abort (struct scsi_cmnd *SCpnt);*/ 301*4882a593Smuzhiyun /*static int nsp_eh_device_reset(struct scsi_cmnd *SCpnt);*/ 302*4882a593Smuzhiyun static int nsp_eh_bus_reset (struct scsi_cmnd *SCpnt); 303*4882a593Smuzhiyun static int nsp_eh_host_reset (struct scsi_cmnd *SCpnt); 304*4882a593Smuzhiyun static int nsp_bus_reset (nsp_hw_data *data); 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun /* */ 307*4882a593Smuzhiyun static int nsphw_init (nsp_hw_data *data); 308*4882a593Smuzhiyun static int nsphw_start_selection(struct scsi_cmnd *SCpnt); 309*4882a593Smuzhiyun static void nsp_start_timer (struct scsi_cmnd *SCpnt, int time); 310*4882a593Smuzhiyun static int nsp_fifo_count (struct scsi_cmnd *SCpnt); 311*4882a593Smuzhiyun static void nsp_pio_read (struct scsi_cmnd *SCpnt); 312*4882a593Smuzhiyun static void nsp_pio_write (struct scsi_cmnd *SCpnt); 313*4882a593Smuzhiyun static int nsp_nexus (struct scsi_cmnd *SCpnt); 314*4882a593Smuzhiyun static void nsp_scsi_done (struct scsi_cmnd *SCpnt); 315*4882a593Smuzhiyun static int nsp_analyze_sdtr (struct scsi_cmnd *SCpnt); 316*4882a593Smuzhiyun static int nsp_negate_signal (struct scsi_cmnd *SCpnt, 317*4882a593Smuzhiyun unsigned char mask, char *str); 318*4882a593Smuzhiyun static int nsp_expect_signal (struct scsi_cmnd *SCpnt, 319*4882a593Smuzhiyun unsigned char current_phase, 320*4882a593Smuzhiyun unsigned char mask); 321*4882a593Smuzhiyun static int nsp_xfer (struct scsi_cmnd *SCpnt, int phase); 322*4882a593Smuzhiyun static int nsp_dataphase_bypass (struct scsi_cmnd *SCpnt); 323*4882a593Smuzhiyun static int nsp_reselected (struct scsi_cmnd *SCpnt); 324*4882a593Smuzhiyun static struct Scsi_Host *nsp_detect(struct scsi_host_template *sht); 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun /* Interrupt handler */ 327*4882a593Smuzhiyun //static irqreturn_t nspintr(int irq, void *dev_id); 328*4882a593Smuzhiyun 329*4882a593Smuzhiyun /* Debug */ 330*4882a593Smuzhiyun #ifdef NSP_DEBUG 331*4882a593Smuzhiyun static void show_command (struct scsi_cmnd *SCpnt); 332*4882a593Smuzhiyun static void show_phase (struct scsi_cmnd *SCpnt); 333*4882a593Smuzhiyun static void show_busphase(unsigned char stat); 334*4882a593Smuzhiyun static void show_message (nsp_hw_data *data); 335*4882a593Smuzhiyun #else 336*4882a593Smuzhiyun # define show_command(ptr) /* */ 337*4882a593Smuzhiyun # define show_phase(SCpnt) /* */ 338*4882a593Smuzhiyun # define show_busphase(stat) /* */ 339*4882a593Smuzhiyun # define show_message(data) /* */ 340*4882a593Smuzhiyun #endif 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun /* 343*4882a593Smuzhiyun * SCSI phase 344*4882a593Smuzhiyun */ 345*4882a593Smuzhiyun enum _scsi_phase { 346*4882a593Smuzhiyun PH_UNDETERMINED , 347*4882a593Smuzhiyun PH_ARBSTART , 348*4882a593Smuzhiyun PH_SELSTART , 349*4882a593Smuzhiyun PH_SELECTED , 350*4882a593Smuzhiyun PH_COMMAND , 351*4882a593Smuzhiyun PH_DATA , 352*4882a593Smuzhiyun PH_STATUS , 353*4882a593Smuzhiyun PH_MSG_IN , 354*4882a593Smuzhiyun PH_MSG_OUT , 355*4882a593Smuzhiyun PH_DISCONNECT , 356*4882a593Smuzhiyun PH_RESELECT , 357*4882a593Smuzhiyun PH_ABORT , 358*4882a593Smuzhiyun PH_RESET 359*4882a593Smuzhiyun }; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun enum _data_in_out { 362*4882a593Smuzhiyun IO_UNKNOWN, 363*4882a593Smuzhiyun IO_IN, 364*4882a593Smuzhiyun IO_OUT 365*4882a593Smuzhiyun }; 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun enum _burst_mode { 368*4882a593Smuzhiyun BURST_IO8 = 0, 369*4882a593Smuzhiyun BURST_IO32 = 1, 370*4882a593Smuzhiyun BURST_MEM32 = 2, 371*4882a593Smuzhiyun }; 372*4882a593Smuzhiyun 373*4882a593Smuzhiyun /************************************************************************** 374*4882a593Smuzhiyun * SCSI messaage 375*4882a593Smuzhiyun */ 376*4882a593Smuzhiyun #define MSG_COMMAND_COMPLETE 0x00 377*4882a593Smuzhiyun #define MSG_EXTENDED 0x01 378*4882a593Smuzhiyun #define MSG_ABORT 0x06 379*4882a593Smuzhiyun #define MSG_NO_OPERATION 0x08 380*4882a593Smuzhiyun #define MSG_BUS_DEVICE_RESET 0x0c 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun #define MSG_EXT_SDTR 0x01 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun /* scatter-gather table */ 385*4882a593Smuzhiyun # define BUFFER_ADDR ((char *)((sg_virt(SCpnt->SCp.buffer)))) 386*4882a593Smuzhiyun 387*4882a593Smuzhiyun #endif /*__nsp_cs__*/ 388*4882a593Smuzhiyun /* end */ 389