xref: /OK3568_Linux_fs/kernel/drivers/scsi/myrb.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Linux Driver for Mylex DAC960/AcceleRAID/eXtremeRAID PCI RAID Controllers
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2017 Hannes Reinecke, SUSE Linux GmbH <hare@suse.com>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Based on the original DAC960 driver,
8*4882a593Smuzhiyun  * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
9*4882a593Smuzhiyun  * Portions Copyright 2002 by Mylex (An IBM Business Unit)
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/types.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/interrupt.h>
17*4882a593Smuzhiyun #include <linux/pci.h>
18*4882a593Smuzhiyun #include <linux/raid_class.h>
19*4882a593Smuzhiyun #include <asm/unaligned.h>
20*4882a593Smuzhiyun #include <scsi/scsi.h>
21*4882a593Smuzhiyun #include <scsi/scsi_host.h>
22*4882a593Smuzhiyun #include <scsi/scsi_device.h>
23*4882a593Smuzhiyun #include <scsi/scsi_cmnd.h>
24*4882a593Smuzhiyun #include <scsi/scsi_tcq.h>
25*4882a593Smuzhiyun #include "myrb.h"
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun static struct raid_template *myrb_raid_template;
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun static void myrb_monitor(struct work_struct *work);
30*4882a593Smuzhiyun static inline void myrb_translate_devstate(void *DeviceState);
31*4882a593Smuzhiyun 
myrb_logical_channel(struct Scsi_Host * shost)32*4882a593Smuzhiyun static inline int myrb_logical_channel(struct Scsi_Host *shost)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun 	return shost->max_channel - 1;
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun static struct myrb_devstate_name_entry {
38*4882a593Smuzhiyun 	enum myrb_devstate state;
39*4882a593Smuzhiyun 	const char *name;
40*4882a593Smuzhiyun } myrb_devstate_name_list[] = {
41*4882a593Smuzhiyun 	{ MYRB_DEVICE_DEAD, "Dead" },
42*4882a593Smuzhiyun 	{ MYRB_DEVICE_WO, "WriteOnly" },
43*4882a593Smuzhiyun 	{ MYRB_DEVICE_ONLINE, "Online" },
44*4882a593Smuzhiyun 	{ MYRB_DEVICE_CRITICAL, "Critical" },
45*4882a593Smuzhiyun 	{ MYRB_DEVICE_STANDBY, "Standby" },
46*4882a593Smuzhiyun 	{ MYRB_DEVICE_OFFLINE, "Offline" },
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun 
myrb_devstate_name(enum myrb_devstate state)49*4882a593Smuzhiyun static const char *myrb_devstate_name(enum myrb_devstate state)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun 	struct myrb_devstate_name_entry *entry = myrb_devstate_name_list;
52*4882a593Smuzhiyun 	int i;
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(myrb_devstate_name_list); i++) {
55*4882a593Smuzhiyun 		if (entry[i].state == state)
56*4882a593Smuzhiyun 			return entry[i].name;
57*4882a593Smuzhiyun 	}
58*4882a593Smuzhiyun 	return "Unknown";
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun static struct myrb_raidlevel_name_entry {
62*4882a593Smuzhiyun 	enum myrb_raidlevel level;
63*4882a593Smuzhiyun 	const char *name;
64*4882a593Smuzhiyun } myrb_raidlevel_name_list[] = {
65*4882a593Smuzhiyun 	{ MYRB_RAID_LEVEL0, "RAID0" },
66*4882a593Smuzhiyun 	{ MYRB_RAID_LEVEL1, "RAID1" },
67*4882a593Smuzhiyun 	{ MYRB_RAID_LEVEL3, "RAID3" },
68*4882a593Smuzhiyun 	{ MYRB_RAID_LEVEL5, "RAID5" },
69*4882a593Smuzhiyun 	{ MYRB_RAID_LEVEL6, "RAID6" },
70*4882a593Smuzhiyun 	{ MYRB_RAID_JBOD, "JBOD" },
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun 
myrb_raidlevel_name(enum myrb_raidlevel level)73*4882a593Smuzhiyun static const char *myrb_raidlevel_name(enum myrb_raidlevel level)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun 	struct myrb_raidlevel_name_entry *entry = myrb_raidlevel_name_list;
76*4882a593Smuzhiyun 	int i;
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(myrb_raidlevel_name_list); i++) {
79*4882a593Smuzhiyun 		if (entry[i].level == level)
80*4882a593Smuzhiyun 			return entry[i].name;
81*4882a593Smuzhiyun 	}
82*4882a593Smuzhiyun 	return NULL;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun /**
86*4882a593Smuzhiyun  * myrb_create_mempools - allocates auxiliary data structures
87*4882a593Smuzhiyun  *
88*4882a593Smuzhiyun  * Return: true on success, false otherwise.
89*4882a593Smuzhiyun  */
myrb_create_mempools(struct pci_dev * pdev,struct myrb_hba * cb)90*4882a593Smuzhiyun static bool myrb_create_mempools(struct pci_dev *pdev, struct myrb_hba *cb)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun 	size_t elem_size, elem_align;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	elem_align = sizeof(struct myrb_sge);
95*4882a593Smuzhiyun 	elem_size = cb->host->sg_tablesize * elem_align;
96*4882a593Smuzhiyun 	cb->sg_pool = dma_pool_create("myrb_sg", &pdev->dev,
97*4882a593Smuzhiyun 				      elem_size, elem_align, 0);
98*4882a593Smuzhiyun 	if (cb->sg_pool == NULL) {
99*4882a593Smuzhiyun 		shost_printk(KERN_ERR, cb->host,
100*4882a593Smuzhiyun 			     "Failed to allocate SG pool\n");
101*4882a593Smuzhiyun 		return false;
102*4882a593Smuzhiyun 	}
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	cb->dcdb_pool = dma_pool_create("myrb_dcdb", &pdev->dev,
105*4882a593Smuzhiyun 				       sizeof(struct myrb_dcdb),
106*4882a593Smuzhiyun 				       sizeof(unsigned int), 0);
107*4882a593Smuzhiyun 	if (!cb->dcdb_pool) {
108*4882a593Smuzhiyun 		dma_pool_destroy(cb->sg_pool);
109*4882a593Smuzhiyun 		cb->sg_pool = NULL;
110*4882a593Smuzhiyun 		shost_printk(KERN_ERR, cb->host,
111*4882a593Smuzhiyun 			     "Failed to allocate DCDB pool\n");
112*4882a593Smuzhiyun 		return false;
113*4882a593Smuzhiyun 	}
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	snprintf(cb->work_q_name, sizeof(cb->work_q_name),
116*4882a593Smuzhiyun 		 "myrb_wq_%d", cb->host->host_no);
117*4882a593Smuzhiyun 	cb->work_q = create_singlethread_workqueue(cb->work_q_name);
118*4882a593Smuzhiyun 	if (!cb->work_q) {
119*4882a593Smuzhiyun 		dma_pool_destroy(cb->dcdb_pool);
120*4882a593Smuzhiyun 		cb->dcdb_pool = NULL;
121*4882a593Smuzhiyun 		dma_pool_destroy(cb->sg_pool);
122*4882a593Smuzhiyun 		cb->sg_pool = NULL;
123*4882a593Smuzhiyun 		shost_printk(KERN_ERR, cb->host,
124*4882a593Smuzhiyun 			     "Failed to create workqueue\n");
125*4882a593Smuzhiyun 		return false;
126*4882a593Smuzhiyun 	}
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	/*
129*4882a593Smuzhiyun 	 * Initialize the Monitoring Timer.
130*4882a593Smuzhiyun 	 */
131*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&cb->monitor_work, myrb_monitor);
132*4882a593Smuzhiyun 	queue_delayed_work(cb->work_q, &cb->monitor_work, 1);
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	return true;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun /**
138*4882a593Smuzhiyun  * myrb_destroy_mempools - tears down the memory pools for the controller
139*4882a593Smuzhiyun  */
myrb_destroy_mempools(struct myrb_hba * cb)140*4882a593Smuzhiyun static void myrb_destroy_mempools(struct myrb_hba *cb)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun 	cancel_delayed_work_sync(&cb->monitor_work);
143*4882a593Smuzhiyun 	destroy_workqueue(cb->work_q);
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	dma_pool_destroy(cb->sg_pool);
146*4882a593Smuzhiyun 	dma_pool_destroy(cb->dcdb_pool);
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun /**
150*4882a593Smuzhiyun  * myrb_reset_cmd - reset command block
151*4882a593Smuzhiyun  */
myrb_reset_cmd(struct myrb_cmdblk * cmd_blk)152*4882a593Smuzhiyun static inline void myrb_reset_cmd(struct myrb_cmdblk *cmd_blk)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun 	union myrb_cmd_mbox *mbox = &cmd_blk->mbox;
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	memset(mbox, 0, sizeof(union myrb_cmd_mbox));
157*4882a593Smuzhiyun 	cmd_blk->status = 0;
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun /**
161*4882a593Smuzhiyun  * myrb_qcmd - queues command block for execution
162*4882a593Smuzhiyun  */
myrb_qcmd(struct myrb_hba * cb,struct myrb_cmdblk * cmd_blk)163*4882a593Smuzhiyun static void myrb_qcmd(struct myrb_hba *cb, struct myrb_cmdblk *cmd_blk)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun 	void __iomem *base = cb->io_base;
166*4882a593Smuzhiyun 	union myrb_cmd_mbox *mbox = &cmd_blk->mbox;
167*4882a593Smuzhiyun 	union myrb_cmd_mbox *next_mbox = cb->next_cmd_mbox;
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	cb->write_cmd_mbox(next_mbox, mbox);
170*4882a593Smuzhiyun 	if (cb->prev_cmd_mbox1->words[0] == 0 ||
171*4882a593Smuzhiyun 	    cb->prev_cmd_mbox2->words[0] == 0)
172*4882a593Smuzhiyun 		cb->get_cmd_mbox(base);
173*4882a593Smuzhiyun 	cb->prev_cmd_mbox2 = cb->prev_cmd_mbox1;
174*4882a593Smuzhiyun 	cb->prev_cmd_mbox1 = next_mbox;
175*4882a593Smuzhiyun 	if (++next_mbox > cb->last_cmd_mbox)
176*4882a593Smuzhiyun 		next_mbox = cb->first_cmd_mbox;
177*4882a593Smuzhiyun 	cb->next_cmd_mbox = next_mbox;
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun /**
181*4882a593Smuzhiyun  * myrb_exec_cmd - executes command block and waits for completion.
182*4882a593Smuzhiyun  *
183*4882a593Smuzhiyun  * Return: command status
184*4882a593Smuzhiyun  */
myrb_exec_cmd(struct myrb_hba * cb,struct myrb_cmdblk * cmd_blk)185*4882a593Smuzhiyun static unsigned short myrb_exec_cmd(struct myrb_hba *cb,
186*4882a593Smuzhiyun 		struct myrb_cmdblk *cmd_blk)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun 	DECLARE_COMPLETION_ONSTACK(cmpl);
189*4882a593Smuzhiyun 	unsigned long flags;
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	cmd_blk->completion = &cmpl;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	spin_lock_irqsave(&cb->queue_lock, flags);
194*4882a593Smuzhiyun 	cb->qcmd(cb, cmd_blk);
195*4882a593Smuzhiyun 	spin_unlock_irqrestore(&cb->queue_lock, flags);
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	WARN_ON(in_interrupt());
198*4882a593Smuzhiyun 	wait_for_completion(&cmpl);
199*4882a593Smuzhiyun 	return cmd_blk->status;
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun /**
203*4882a593Smuzhiyun  * myrb_exec_type3 - executes a type 3 command and waits for completion.
204*4882a593Smuzhiyun  *
205*4882a593Smuzhiyun  * Return: command status
206*4882a593Smuzhiyun  */
myrb_exec_type3(struct myrb_hba * cb,enum myrb_cmd_opcode op,dma_addr_t addr)207*4882a593Smuzhiyun static unsigned short myrb_exec_type3(struct myrb_hba *cb,
208*4882a593Smuzhiyun 		enum myrb_cmd_opcode op, dma_addr_t addr)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun 	struct myrb_cmdblk *cmd_blk = &cb->dcmd_blk;
211*4882a593Smuzhiyun 	union myrb_cmd_mbox *mbox = &cmd_blk->mbox;
212*4882a593Smuzhiyun 	unsigned short status;
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	mutex_lock(&cb->dcmd_mutex);
215*4882a593Smuzhiyun 	myrb_reset_cmd(cmd_blk);
216*4882a593Smuzhiyun 	mbox->type3.id = MYRB_DCMD_TAG;
217*4882a593Smuzhiyun 	mbox->type3.opcode = op;
218*4882a593Smuzhiyun 	mbox->type3.addr = addr;
219*4882a593Smuzhiyun 	status = myrb_exec_cmd(cb, cmd_blk);
220*4882a593Smuzhiyun 	mutex_unlock(&cb->dcmd_mutex);
221*4882a593Smuzhiyun 	return status;
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun /**
225*4882a593Smuzhiyun  * myrb_exec_type3D - executes a type 3D command and waits for completion.
226*4882a593Smuzhiyun  *
227*4882a593Smuzhiyun  * Return: command status
228*4882a593Smuzhiyun  */
myrb_exec_type3D(struct myrb_hba * cb,enum myrb_cmd_opcode op,struct scsi_device * sdev,struct myrb_pdev_state * pdev_info)229*4882a593Smuzhiyun static unsigned short myrb_exec_type3D(struct myrb_hba *cb,
230*4882a593Smuzhiyun 		enum myrb_cmd_opcode op, struct scsi_device *sdev,
231*4882a593Smuzhiyun 		struct myrb_pdev_state *pdev_info)
232*4882a593Smuzhiyun {
233*4882a593Smuzhiyun 	struct myrb_cmdblk *cmd_blk = &cb->dcmd_blk;
234*4882a593Smuzhiyun 	union myrb_cmd_mbox *mbox = &cmd_blk->mbox;
235*4882a593Smuzhiyun 	unsigned short status;
236*4882a593Smuzhiyun 	dma_addr_t pdev_info_addr;
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	pdev_info_addr = dma_map_single(&cb->pdev->dev, pdev_info,
239*4882a593Smuzhiyun 					sizeof(struct myrb_pdev_state),
240*4882a593Smuzhiyun 					DMA_FROM_DEVICE);
241*4882a593Smuzhiyun 	if (dma_mapping_error(&cb->pdev->dev, pdev_info_addr))
242*4882a593Smuzhiyun 		return MYRB_STATUS_SUBSYS_FAILED;
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	mutex_lock(&cb->dcmd_mutex);
245*4882a593Smuzhiyun 	myrb_reset_cmd(cmd_blk);
246*4882a593Smuzhiyun 	mbox->type3D.id = MYRB_DCMD_TAG;
247*4882a593Smuzhiyun 	mbox->type3D.opcode = op;
248*4882a593Smuzhiyun 	mbox->type3D.channel = sdev->channel;
249*4882a593Smuzhiyun 	mbox->type3D.target = sdev->id;
250*4882a593Smuzhiyun 	mbox->type3D.addr = pdev_info_addr;
251*4882a593Smuzhiyun 	status = myrb_exec_cmd(cb, cmd_blk);
252*4882a593Smuzhiyun 	mutex_unlock(&cb->dcmd_mutex);
253*4882a593Smuzhiyun 	dma_unmap_single(&cb->pdev->dev, pdev_info_addr,
254*4882a593Smuzhiyun 			 sizeof(struct myrb_pdev_state), DMA_FROM_DEVICE);
255*4882a593Smuzhiyun 	if (status == MYRB_STATUS_SUCCESS &&
256*4882a593Smuzhiyun 	    mbox->type3D.opcode == MYRB_CMD_GET_DEVICE_STATE_OLD)
257*4882a593Smuzhiyun 		myrb_translate_devstate(pdev_info);
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	return status;
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun static char *myrb_event_msg[] = {
263*4882a593Smuzhiyun 	"killed because write recovery failed",
264*4882a593Smuzhiyun 	"killed because of SCSI bus reset failure",
265*4882a593Smuzhiyun 	"killed because of double check condition",
266*4882a593Smuzhiyun 	"killed because it was removed",
267*4882a593Smuzhiyun 	"killed because of gross error on SCSI chip",
268*4882a593Smuzhiyun 	"killed because of bad tag returned from drive",
269*4882a593Smuzhiyun 	"killed because of timeout on SCSI command",
270*4882a593Smuzhiyun 	"killed because of reset SCSI command issued from system",
271*4882a593Smuzhiyun 	"killed because busy or parity error count exceeded limit",
272*4882a593Smuzhiyun 	"killed because of 'kill drive' command from system",
273*4882a593Smuzhiyun 	"killed because of selection timeout",
274*4882a593Smuzhiyun 	"killed due to SCSI phase sequence error",
275*4882a593Smuzhiyun 	"killed due to unknown status",
276*4882a593Smuzhiyun };
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun /**
279*4882a593Smuzhiyun  * myrb_get_event - get event log from HBA
280*4882a593Smuzhiyun  * @cb: pointer to the hba structure
281*4882a593Smuzhiyun  * @event: number of the event
282*4882a593Smuzhiyun  *
283*4882a593Smuzhiyun  * Execute a type 3E command and logs the event message
284*4882a593Smuzhiyun  */
myrb_get_event(struct myrb_hba * cb,unsigned int event)285*4882a593Smuzhiyun static void myrb_get_event(struct myrb_hba *cb, unsigned int event)
286*4882a593Smuzhiyun {
287*4882a593Smuzhiyun 	struct myrb_cmdblk *cmd_blk = &cb->mcmd_blk;
288*4882a593Smuzhiyun 	union myrb_cmd_mbox *mbox = &cmd_blk->mbox;
289*4882a593Smuzhiyun 	struct myrb_log_entry *ev_buf;
290*4882a593Smuzhiyun 	dma_addr_t ev_addr;
291*4882a593Smuzhiyun 	unsigned short status;
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	ev_buf = dma_alloc_coherent(&cb->pdev->dev,
294*4882a593Smuzhiyun 				    sizeof(struct myrb_log_entry),
295*4882a593Smuzhiyun 				    &ev_addr, GFP_KERNEL);
296*4882a593Smuzhiyun 	if (!ev_buf)
297*4882a593Smuzhiyun 		return;
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun 	myrb_reset_cmd(cmd_blk);
300*4882a593Smuzhiyun 	mbox->type3E.id = MYRB_MCMD_TAG;
301*4882a593Smuzhiyun 	mbox->type3E.opcode = MYRB_CMD_EVENT_LOG_OPERATION;
302*4882a593Smuzhiyun 	mbox->type3E.optype = DAC960_V1_GetEventLogEntry;
303*4882a593Smuzhiyun 	mbox->type3E.opqual = 1;
304*4882a593Smuzhiyun 	mbox->type3E.ev_seq = event;
305*4882a593Smuzhiyun 	mbox->type3E.addr = ev_addr;
306*4882a593Smuzhiyun 	status = myrb_exec_cmd(cb, cmd_blk);
307*4882a593Smuzhiyun 	if (status != MYRB_STATUS_SUCCESS)
308*4882a593Smuzhiyun 		shost_printk(KERN_INFO, cb->host,
309*4882a593Smuzhiyun 			     "Failed to get event log %d, status %04x\n",
310*4882a593Smuzhiyun 			     event, status);
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	else if (ev_buf->seq_num == event) {
313*4882a593Smuzhiyun 		struct scsi_sense_hdr sshdr;
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 		memset(&sshdr, 0, sizeof(sshdr));
316*4882a593Smuzhiyun 		scsi_normalize_sense(ev_buf->sense, 32, &sshdr);
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 		if (sshdr.sense_key == VENDOR_SPECIFIC &&
319*4882a593Smuzhiyun 		    sshdr.asc == 0x80 &&
320*4882a593Smuzhiyun 		    sshdr.ascq < ARRAY_SIZE(myrb_event_msg))
321*4882a593Smuzhiyun 			shost_printk(KERN_CRIT, cb->host,
322*4882a593Smuzhiyun 				     "Physical drive %d:%d: %s\n",
323*4882a593Smuzhiyun 				     ev_buf->channel, ev_buf->target,
324*4882a593Smuzhiyun 				     myrb_event_msg[sshdr.ascq]);
325*4882a593Smuzhiyun 		else
326*4882a593Smuzhiyun 			shost_printk(KERN_CRIT, cb->host,
327*4882a593Smuzhiyun 				     "Physical drive %d:%d: Sense: %X/%02X/%02X\n",
328*4882a593Smuzhiyun 				     ev_buf->channel, ev_buf->target,
329*4882a593Smuzhiyun 				     sshdr.sense_key, sshdr.asc, sshdr.ascq);
330*4882a593Smuzhiyun 	}
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	dma_free_coherent(&cb->pdev->dev, sizeof(struct myrb_log_entry),
333*4882a593Smuzhiyun 			  ev_buf, ev_addr);
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun /**
337*4882a593Smuzhiyun  * myrb_get_errtable - retrieves the error table from the controller
338*4882a593Smuzhiyun  *
339*4882a593Smuzhiyun  * Executes a type 3 command and logs the error table from the controller.
340*4882a593Smuzhiyun  */
myrb_get_errtable(struct myrb_hba * cb)341*4882a593Smuzhiyun static void myrb_get_errtable(struct myrb_hba *cb)
342*4882a593Smuzhiyun {
343*4882a593Smuzhiyun 	struct myrb_cmdblk *cmd_blk = &cb->mcmd_blk;
344*4882a593Smuzhiyun 	union myrb_cmd_mbox *mbox = &cmd_blk->mbox;
345*4882a593Smuzhiyun 	unsigned short status;
346*4882a593Smuzhiyun 	struct myrb_error_entry old_table[MYRB_MAX_CHANNELS * MYRB_MAX_TARGETS];
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	memcpy(&old_table, cb->err_table, sizeof(old_table));
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 	myrb_reset_cmd(cmd_blk);
351*4882a593Smuzhiyun 	mbox->type3.id = MYRB_MCMD_TAG;
352*4882a593Smuzhiyun 	mbox->type3.opcode = MYRB_CMD_GET_ERROR_TABLE;
353*4882a593Smuzhiyun 	mbox->type3.addr = cb->err_table_addr;
354*4882a593Smuzhiyun 	status = myrb_exec_cmd(cb, cmd_blk);
355*4882a593Smuzhiyun 	if (status == MYRB_STATUS_SUCCESS) {
356*4882a593Smuzhiyun 		struct myrb_error_entry *table = cb->err_table;
357*4882a593Smuzhiyun 		struct myrb_error_entry *new, *old;
358*4882a593Smuzhiyun 		size_t err_table_offset;
359*4882a593Smuzhiyun 		struct scsi_device *sdev;
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun 		shost_for_each_device(sdev, cb->host) {
362*4882a593Smuzhiyun 			if (sdev->channel >= myrb_logical_channel(cb->host))
363*4882a593Smuzhiyun 				continue;
364*4882a593Smuzhiyun 			err_table_offset = sdev->channel * MYRB_MAX_TARGETS
365*4882a593Smuzhiyun 				+ sdev->id;
366*4882a593Smuzhiyun 			new = table + err_table_offset;
367*4882a593Smuzhiyun 			old = &old_table[err_table_offset];
368*4882a593Smuzhiyun 			if (new->parity_err == old->parity_err &&
369*4882a593Smuzhiyun 			    new->soft_err == old->soft_err &&
370*4882a593Smuzhiyun 			    new->hard_err == old->hard_err &&
371*4882a593Smuzhiyun 			    new->misc_err == old->misc_err)
372*4882a593Smuzhiyun 				continue;
373*4882a593Smuzhiyun 			sdev_printk(KERN_CRIT, sdev,
374*4882a593Smuzhiyun 				    "Errors: Parity = %d, Soft = %d, Hard = %d, Misc = %d\n",
375*4882a593Smuzhiyun 				    new->parity_err, new->soft_err,
376*4882a593Smuzhiyun 				    new->hard_err, new->misc_err);
377*4882a593Smuzhiyun 		}
378*4882a593Smuzhiyun 	}
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun /**
382*4882a593Smuzhiyun  * myrb_get_ldev_info - retrieves the logical device table from the controller
383*4882a593Smuzhiyun  *
384*4882a593Smuzhiyun  * Executes a type 3 command and updates the logical device table.
385*4882a593Smuzhiyun  *
386*4882a593Smuzhiyun  * Return: command status
387*4882a593Smuzhiyun  */
myrb_get_ldev_info(struct myrb_hba * cb)388*4882a593Smuzhiyun static unsigned short myrb_get_ldev_info(struct myrb_hba *cb)
389*4882a593Smuzhiyun {
390*4882a593Smuzhiyun 	unsigned short status;
391*4882a593Smuzhiyun 	int ldev_num, ldev_cnt = cb->enquiry->ldev_count;
392*4882a593Smuzhiyun 	struct Scsi_Host *shost = cb->host;
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun 	status = myrb_exec_type3(cb, MYRB_CMD_GET_LDEV_INFO,
395*4882a593Smuzhiyun 				 cb->ldev_info_addr);
396*4882a593Smuzhiyun 	if (status != MYRB_STATUS_SUCCESS)
397*4882a593Smuzhiyun 		return status;
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun 	for (ldev_num = 0; ldev_num < ldev_cnt; ldev_num++) {
400*4882a593Smuzhiyun 		struct myrb_ldev_info *old = NULL;
401*4882a593Smuzhiyun 		struct myrb_ldev_info *new = cb->ldev_info_buf + ldev_num;
402*4882a593Smuzhiyun 		struct scsi_device *sdev;
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 		sdev = scsi_device_lookup(shost, myrb_logical_channel(shost),
405*4882a593Smuzhiyun 					  ldev_num, 0);
406*4882a593Smuzhiyun 		if (!sdev) {
407*4882a593Smuzhiyun 			if (new->state == MYRB_DEVICE_OFFLINE)
408*4882a593Smuzhiyun 				continue;
409*4882a593Smuzhiyun 			shost_printk(KERN_INFO, shost,
410*4882a593Smuzhiyun 				     "Adding Logical Drive %d in state %s\n",
411*4882a593Smuzhiyun 				     ldev_num, myrb_devstate_name(new->state));
412*4882a593Smuzhiyun 			scsi_add_device(shost, myrb_logical_channel(shost),
413*4882a593Smuzhiyun 					ldev_num, 0);
414*4882a593Smuzhiyun 			continue;
415*4882a593Smuzhiyun 		}
416*4882a593Smuzhiyun 		old = sdev->hostdata;
417*4882a593Smuzhiyun 		if (new->state != old->state)
418*4882a593Smuzhiyun 			shost_printk(KERN_INFO, shost,
419*4882a593Smuzhiyun 				     "Logical Drive %d is now %s\n",
420*4882a593Smuzhiyun 				     ldev_num, myrb_devstate_name(new->state));
421*4882a593Smuzhiyun 		if (new->wb_enabled != old->wb_enabled)
422*4882a593Smuzhiyun 			sdev_printk(KERN_INFO, sdev,
423*4882a593Smuzhiyun 				    "Logical Drive is now WRITE %s\n",
424*4882a593Smuzhiyun 				    (new->wb_enabled ? "BACK" : "THRU"));
425*4882a593Smuzhiyun 		memcpy(old, new, sizeof(*new));
426*4882a593Smuzhiyun 		scsi_device_put(sdev);
427*4882a593Smuzhiyun 	}
428*4882a593Smuzhiyun 	return status;
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun /**
432*4882a593Smuzhiyun  * myrb_get_rbld_progress - get rebuild progress information
433*4882a593Smuzhiyun  *
434*4882a593Smuzhiyun  * Executes a type 3 command and returns the rebuild progress
435*4882a593Smuzhiyun  * information.
436*4882a593Smuzhiyun  *
437*4882a593Smuzhiyun  * Return: command status
438*4882a593Smuzhiyun  */
myrb_get_rbld_progress(struct myrb_hba * cb,struct myrb_rbld_progress * rbld)439*4882a593Smuzhiyun static unsigned short myrb_get_rbld_progress(struct myrb_hba *cb,
440*4882a593Smuzhiyun 		struct myrb_rbld_progress *rbld)
441*4882a593Smuzhiyun {
442*4882a593Smuzhiyun 	struct myrb_cmdblk *cmd_blk = &cb->mcmd_blk;
443*4882a593Smuzhiyun 	union myrb_cmd_mbox *mbox = &cmd_blk->mbox;
444*4882a593Smuzhiyun 	struct myrb_rbld_progress *rbld_buf;
445*4882a593Smuzhiyun 	dma_addr_t rbld_addr;
446*4882a593Smuzhiyun 	unsigned short status;
447*4882a593Smuzhiyun 
448*4882a593Smuzhiyun 	rbld_buf = dma_alloc_coherent(&cb->pdev->dev,
449*4882a593Smuzhiyun 				      sizeof(struct myrb_rbld_progress),
450*4882a593Smuzhiyun 				      &rbld_addr, GFP_KERNEL);
451*4882a593Smuzhiyun 	if (!rbld_buf)
452*4882a593Smuzhiyun 		return MYRB_STATUS_RBLD_NOT_CHECKED;
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun 	myrb_reset_cmd(cmd_blk);
455*4882a593Smuzhiyun 	mbox->type3.id = MYRB_MCMD_TAG;
456*4882a593Smuzhiyun 	mbox->type3.opcode = MYRB_CMD_GET_REBUILD_PROGRESS;
457*4882a593Smuzhiyun 	mbox->type3.addr = rbld_addr;
458*4882a593Smuzhiyun 	status = myrb_exec_cmd(cb, cmd_blk);
459*4882a593Smuzhiyun 	if (rbld)
460*4882a593Smuzhiyun 		memcpy(rbld, rbld_buf, sizeof(struct myrb_rbld_progress));
461*4882a593Smuzhiyun 	dma_free_coherent(&cb->pdev->dev, sizeof(struct myrb_rbld_progress),
462*4882a593Smuzhiyun 			  rbld_buf, rbld_addr);
463*4882a593Smuzhiyun 	return status;
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun /**
467*4882a593Smuzhiyun  * myrb_update_rbld_progress - updates the rebuild status
468*4882a593Smuzhiyun  *
469*4882a593Smuzhiyun  * Updates the rebuild status for the attached logical devices.
470*4882a593Smuzhiyun  *
471*4882a593Smuzhiyun  */
myrb_update_rbld_progress(struct myrb_hba * cb)472*4882a593Smuzhiyun static void myrb_update_rbld_progress(struct myrb_hba *cb)
473*4882a593Smuzhiyun {
474*4882a593Smuzhiyun 	struct myrb_rbld_progress rbld_buf;
475*4882a593Smuzhiyun 	unsigned short status;
476*4882a593Smuzhiyun 
477*4882a593Smuzhiyun 	status = myrb_get_rbld_progress(cb, &rbld_buf);
478*4882a593Smuzhiyun 	if (status == MYRB_NO_STDBY_RBLD_OR_CHECK_IN_PROGRESS &&
479*4882a593Smuzhiyun 	    cb->last_rbld_status == MYRB_STATUS_SUCCESS)
480*4882a593Smuzhiyun 		status = MYRB_STATUS_RBLD_SUCCESS;
481*4882a593Smuzhiyun 	if (status != MYRB_NO_STDBY_RBLD_OR_CHECK_IN_PROGRESS) {
482*4882a593Smuzhiyun 		unsigned int blocks_done =
483*4882a593Smuzhiyun 			rbld_buf.ldev_size - rbld_buf.blocks_left;
484*4882a593Smuzhiyun 		struct scsi_device *sdev;
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 		sdev = scsi_device_lookup(cb->host,
487*4882a593Smuzhiyun 					  myrb_logical_channel(cb->host),
488*4882a593Smuzhiyun 					  rbld_buf.ldev_num, 0);
489*4882a593Smuzhiyun 		if (!sdev)
490*4882a593Smuzhiyun 			return;
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 		switch (status) {
493*4882a593Smuzhiyun 		case MYRB_STATUS_SUCCESS:
494*4882a593Smuzhiyun 			sdev_printk(KERN_INFO, sdev,
495*4882a593Smuzhiyun 				    "Rebuild in Progress, %d%% completed\n",
496*4882a593Smuzhiyun 				    (100 * (blocks_done >> 7))
497*4882a593Smuzhiyun 				    / (rbld_buf.ldev_size >> 7));
498*4882a593Smuzhiyun 			break;
499*4882a593Smuzhiyun 		case MYRB_STATUS_RBLD_FAILED_LDEV_FAILURE:
500*4882a593Smuzhiyun 			sdev_printk(KERN_INFO, sdev,
501*4882a593Smuzhiyun 				    "Rebuild Failed due to Logical Drive Failure\n");
502*4882a593Smuzhiyun 			break;
503*4882a593Smuzhiyun 		case MYRB_STATUS_RBLD_FAILED_BADBLOCKS:
504*4882a593Smuzhiyun 			sdev_printk(KERN_INFO, sdev,
505*4882a593Smuzhiyun 				    "Rebuild Failed due to Bad Blocks on Other Drives\n");
506*4882a593Smuzhiyun 			break;
507*4882a593Smuzhiyun 		case MYRB_STATUS_RBLD_FAILED_NEW_DRIVE_FAILED:
508*4882a593Smuzhiyun 			sdev_printk(KERN_INFO, sdev,
509*4882a593Smuzhiyun 				    "Rebuild Failed due to Failure of Drive Being Rebuilt\n");
510*4882a593Smuzhiyun 			break;
511*4882a593Smuzhiyun 		case MYRB_STATUS_RBLD_SUCCESS:
512*4882a593Smuzhiyun 			sdev_printk(KERN_INFO, sdev,
513*4882a593Smuzhiyun 				    "Rebuild Completed Successfully\n");
514*4882a593Smuzhiyun 			break;
515*4882a593Smuzhiyun 		case MYRB_STATUS_RBLD_SUCCESS_TERMINATED:
516*4882a593Smuzhiyun 			sdev_printk(KERN_INFO, sdev,
517*4882a593Smuzhiyun 				     "Rebuild Successfully Terminated\n");
518*4882a593Smuzhiyun 			break;
519*4882a593Smuzhiyun 		default:
520*4882a593Smuzhiyun 			break;
521*4882a593Smuzhiyun 		}
522*4882a593Smuzhiyun 		scsi_device_put(sdev);
523*4882a593Smuzhiyun 	}
524*4882a593Smuzhiyun 	cb->last_rbld_status = status;
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun /**
528*4882a593Smuzhiyun  * myrb_get_cc_progress - retrieve the rebuild status
529*4882a593Smuzhiyun  *
530*4882a593Smuzhiyun  * Execute a type 3 Command and fetch the rebuild / consistency check
531*4882a593Smuzhiyun  * status.
532*4882a593Smuzhiyun  */
myrb_get_cc_progress(struct myrb_hba * cb)533*4882a593Smuzhiyun static void myrb_get_cc_progress(struct myrb_hba *cb)
534*4882a593Smuzhiyun {
535*4882a593Smuzhiyun 	struct myrb_cmdblk *cmd_blk = &cb->mcmd_blk;
536*4882a593Smuzhiyun 	union myrb_cmd_mbox *mbox = &cmd_blk->mbox;
537*4882a593Smuzhiyun 	struct myrb_rbld_progress *rbld_buf;
538*4882a593Smuzhiyun 	dma_addr_t rbld_addr;
539*4882a593Smuzhiyun 	unsigned short status;
540*4882a593Smuzhiyun 
541*4882a593Smuzhiyun 	rbld_buf = dma_alloc_coherent(&cb->pdev->dev,
542*4882a593Smuzhiyun 				      sizeof(struct myrb_rbld_progress),
543*4882a593Smuzhiyun 				      &rbld_addr, GFP_KERNEL);
544*4882a593Smuzhiyun 	if (!rbld_buf) {
545*4882a593Smuzhiyun 		cb->need_cc_status = true;
546*4882a593Smuzhiyun 		return;
547*4882a593Smuzhiyun 	}
548*4882a593Smuzhiyun 	myrb_reset_cmd(cmd_blk);
549*4882a593Smuzhiyun 	mbox->type3.id = MYRB_MCMD_TAG;
550*4882a593Smuzhiyun 	mbox->type3.opcode = MYRB_CMD_REBUILD_STAT;
551*4882a593Smuzhiyun 	mbox->type3.addr = rbld_addr;
552*4882a593Smuzhiyun 	status = myrb_exec_cmd(cb, cmd_blk);
553*4882a593Smuzhiyun 	if (status == MYRB_STATUS_SUCCESS) {
554*4882a593Smuzhiyun 		unsigned int ldev_num = rbld_buf->ldev_num;
555*4882a593Smuzhiyun 		unsigned int ldev_size = rbld_buf->ldev_size;
556*4882a593Smuzhiyun 		unsigned int blocks_done =
557*4882a593Smuzhiyun 			ldev_size - rbld_buf->blocks_left;
558*4882a593Smuzhiyun 		struct scsi_device *sdev;
559*4882a593Smuzhiyun 
560*4882a593Smuzhiyun 		sdev = scsi_device_lookup(cb->host,
561*4882a593Smuzhiyun 					  myrb_logical_channel(cb->host),
562*4882a593Smuzhiyun 					  ldev_num, 0);
563*4882a593Smuzhiyun 		if (sdev) {
564*4882a593Smuzhiyun 			sdev_printk(KERN_INFO, sdev,
565*4882a593Smuzhiyun 				    "Consistency Check in Progress: %d%% completed\n",
566*4882a593Smuzhiyun 				    (100 * (blocks_done >> 7))
567*4882a593Smuzhiyun 				    / (ldev_size >> 7));
568*4882a593Smuzhiyun 			scsi_device_put(sdev);
569*4882a593Smuzhiyun 		}
570*4882a593Smuzhiyun 	}
571*4882a593Smuzhiyun 	dma_free_coherent(&cb->pdev->dev, sizeof(struct myrb_rbld_progress),
572*4882a593Smuzhiyun 			  rbld_buf, rbld_addr);
573*4882a593Smuzhiyun }
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun /**
576*4882a593Smuzhiyun  * myrb_bgi_control - updates background initialisation status
577*4882a593Smuzhiyun  *
578*4882a593Smuzhiyun  * Executes a type 3B command and updates the background initialisation status
579*4882a593Smuzhiyun  */
myrb_bgi_control(struct myrb_hba * cb)580*4882a593Smuzhiyun static void myrb_bgi_control(struct myrb_hba *cb)
581*4882a593Smuzhiyun {
582*4882a593Smuzhiyun 	struct myrb_cmdblk *cmd_blk = &cb->mcmd_blk;
583*4882a593Smuzhiyun 	union myrb_cmd_mbox *mbox = &cmd_blk->mbox;
584*4882a593Smuzhiyun 	struct myrb_bgi_status *bgi, *last_bgi;
585*4882a593Smuzhiyun 	dma_addr_t bgi_addr;
586*4882a593Smuzhiyun 	struct scsi_device *sdev = NULL;
587*4882a593Smuzhiyun 	unsigned short status;
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun 	bgi = dma_alloc_coherent(&cb->pdev->dev, sizeof(struct myrb_bgi_status),
590*4882a593Smuzhiyun 				 &bgi_addr, GFP_KERNEL);
591*4882a593Smuzhiyun 	if (!bgi) {
592*4882a593Smuzhiyun 		shost_printk(KERN_ERR, cb->host,
593*4882a593Smuzhiyun 			     "Failed to allocate bgi memory\n");
594*4882a593Smuzhiyun 		return;
595*4882a593Smuzhiyun 	}
596*4882a593Smuzhiyun 	myrb_reset_cmd(cmd_blk);
597*4882a593Smuzhiyun 	mbox->type3B.id = MYRB_DCMD_TAG;
598*4882a593Smuzhiyun 	mbox->type3B.opcode = MYRB_CMD_BGI_CONTROL;
599*4882a593Smuzhiyun 	mbox->type3B.optype = 0x20;
600*4882a593Smuzhiyun 	mbox->type3B.addr = bgi_addr;
601*4882a593Smuzhiyun 	status = myrb_exec_cmd(cb, cmd_blk);
602*4882a593Smuzhiyun 	last_bgi = &cb->bgi_status;
603*4882a593Smuzhiyun 	sdev = scsi_device_lookup(cb->host,
604*4882a593Smuzhiyun 				  myrb_logical_channel(cb->host),
605*4882a593Smuzhiyun 				  bgi->ldev_num, 0);
606*4882a593Smuzhiyun 	switch (status) {
607*4882a593Smuzhiyun 	case MYRB_STATUS_SUCCESS:
608*4882a593Smuzhiyun 		switch (bgi->status) {
609*4882a593Smuzhiyun 		case MYRB_BGI_INVALID:
610*4882a593Smuzhiyun 			break;
611*4882a593Smuzhiyun 		case MYRB_BGI_STARTED:
612*4882a593Smuzhiyun 			if (!sdev)
613*4882a593Smuzhiyun 				break;
614*4882a593Smuzhiyun 			sdev_printk(KERN_INFO, sdev,
615*4882a593Smuzhiyun 				    "Background Initialization Started\n");
616*4882a593Smuzhiyun 			break;
617*4882a593Smuzhiyun 		case MYRB_BGI_INPROGRESS:
618*4882a593Smuzhiyun 			if (!sdev)
619*4882a593Smuzhiyun 				break;
620*4882a593Smuzhiyun 			if (bgi->blocks_done == last_bgi->blocks_done &&
621*4882a593Smuzhiyun 			    bgi->ldev_num == last_bgi->ldev_num)
622*4882a593Smuzhiyun 				break;
623*4882a593Smuzhiyun 			sdev_printk(KERN_INFO, sdev,
624*4882a593Smuzhiyun 				 "Background Initialization in Progress: %d%% completed\n",
625*4882a593Smuzhiyun 				 (100 * (bgi->blocks_done >> 7))
626*4882a593Smuzhiyun 				 / (bgi->ldev_size >> 7));
627*4882a593Smuzhiyun 			break;
628*4882a593Smuzhiyun 		case MYRB_BGI_SUSPENDED:
629*4882a593Smuzhiyun 			if (!sdev)
630*4882a593Smuzhiyun 				break;
631*4882a593Smuzhiyun 			sdev_printk(KERN_INFO, sdev,
632*4882a593Smuzhiyun 				    "Background Initialization Suspended\n");
633*4882a593Smuzhiyun 			break;
634*4882a593Smuzhiyun 		case MYRB_BGI_CANCELLED:
635*4882a593Smuzhiyun 			if (!sdev)
636*4882a593Smuzhiyun 				break;
637*4882a593Smuzhiyun 			sdev_printk(KERN_INFO, sdev,
638*4882a593Smuzhiyun 				    "Background Initialization Cancelled\n");
639*4882a593Smuzhiyun 			break;
640*4882a593Smuzhiyun 		}
641*4882a593Smuzhiyun 		memcpy(&cb->bgi_status, bgi, sizeof(struct myrb_bgi_status));
642*4882a593Smuzhiyun 		break;
643*4882a593Smuzhiyun 	case MYRB_STATUS_BGI_SUCCESS:
644*4882a593Smuzhiyun 		if (sdev && cb->bgi_status.status == MYRB_BGI_INPROGRESS)
645*4882a593Smuzhiyun 			sdev_printk(KERN_INFO, sdev,
646*4882a593Smuzhiyun 				    "Background Initialization Completed Successfully\n");
647*4882a593Smuzhiyun 		cb->bgi_status.status = MYRB_BGI_INVALID;
648*4882a593Smuzhiyun 		break;
649*4882a593Smuzhiyun 	case MYRB_STATUS_BGI_ABORTED:
650*4882a593Smuzhiyun 		if (sdev && cb->bgi_status.status == MYRB_BGI_INPROGRESS)
651*4882a593Smuzhiyun 			sdev_printk(KERN_INFO, sdev,
652*4882a593Smuzhiyun 				    "Background Initialization Aborted\n");
653*4882a593Smuzhiyun 		fallthrough;
654*4882a593Smuzhiyun 	case MYRB_STATUS_NO_BGI_INPROGRESS:
655*4882a593Smuzhiyun 		cb->bgi_status.status = MYRB_BGI_INVALID;
656*4882a593Smuzhiyun 		break;
657*4882a593Smuzhiyun 	}
658*4882a593Smuzhiyun 	if (sdev)
659*4882a593Smuzhiyun 		scsi_device_put(sdev);
660*4882a593Smuzhiyun 	dma_free_coherent(&cb->pdev->dev, sizeof(struct myrb_bgi_status),
661*4882a593Smuzhiyun 			  bgi, bgi_addr);
662*4882a593Smuzhiyun }
663*4882a593Smuzhiyun 
664*4882a593Smuzhiyun /**
665*4882a593Smuzhiyun  * myrb_hba_enquiry - updates the controller status
666*4882a593Smuzhiyun  *
667*4882a593Smuzhiyun  * Executes a DAC_V1_Enquiry command and updates the controller status.
668*4882a593Smuzhiyun  *
669*4882a593Smuzhiyun  * Return: command status
670*4882a593Smuzhiyun  */
myrb_hba_enquiry(struct myrb_hba * cb)671*4882a593Smuzhiyun static unsigned short myrb_hba_enquiry(struct myrb_hba *cb)
672*4882a593Smuzhiyun {
673*4882a593Smuzhiyun 	struct myrb_enquiry old, *new;
674*4882a593Smuzhiyun 	unsigned short status;
675*4882a593Smuzhiyun 
676*4882a593Smuzhiyun 	memcpy(&old, cb->enquiry, sizeof(struct myrb_enquiry));
677*4882a593Smuzhiyun 
678*4882a593Smuzhiyun 	status = myrb_exec_type3(cb, MYRB_CMD_ENQUIRY, cb->enquiry_addr);
679*4882a593Smuzhiyun 	if (status != MYRB_STATUS_SUCCESS)
680*4882a593Smuzhiyun 		return status;
681*4882a593Smuzhiyun 
682*4882a593Smuzhiyun 	new = cb->enquiry;
683*4882a593Smuzhiyun 	if (new->ldev_count > old.ldev_count) {
684*4882a593Smuzhiyun 		int ldev_num = old.ldev_count - 1;
685*4882a593Smuzhiyun 
686*4882a593Smuzhiyun 		while (++ldev_num < new->ldev_count)
687*4882a593Smuzhiyun 			shost_printk(KERN_CRIT, cb->host,
688*4882a593Smuzhiyun 				     "Logical Drive %d Now Exists\n",
689*4882a593Smuzhiyun 				     ldev_num);
690*4882a593Smuzhiyun 	}
691*4882a593Smuzhiyun 	if (new->ldev_count < old.ldev_count) {
692*4882a593Smuzhiyun 		int ldev_num = new->ldev_count - 1;
693*4882a593Smuzhiyun 
694*4882a593Smuzhiyun 		while (++ldev_num < old.ldev_count)
695*4882a593Smuzhiyun 			shost_printk(KERN_CRIT, cb->host,
696*4882a593Smuzhiyun 				     "Logical Drive %d No Longer Exists\n",
697*4882a593Smuzhiyun 				     ldev_num);
698*4882a593Smuzhiyun 	}
699*4882a593Smuzhiyun 	if (new->status.deferred != old.status.deferred)
700*4882a593Smuzhiyun 		shost_printk(KERN_CRIT, cb->host,
701*4882a593Smuzhiyun 			     "Deferred Write Error Flag is now %s\n",
702*4882a593Smuzhiyun 			     (new->status.deferred ? "TRUE" : "FALSE"));
703*4882a593Smuzhiyun 	if (new->ev_seq != old.ev_seq) {
704*4882a593Smuzhiyun 		cb->new_ev_seq = new->ev_seq;
705*4882a593Smuzhiyun 		cb->need_err_info = true;
706*4882a593Smuzhiyun 		shost_printk(KERN_INFO, cb->host,
707*4882a593Smuzhiyun 			     "Event log %d/%d (%d/%d) available\n",
708*4882a593Smuzhiyun 			     cb->old_ev_seq, cb->new_ev_seq,
709*4882a593Smuzhiyun 			     old.ev_seq, new->ev_seq);
710*4882a593Smuzhiyun 	}
711*4882a593Smuzhiyun 	if ((new->ldev_critical > 0 &&
712*4882a593Smuzhiyun 	     new->ldev_critical != old.ldev_critical) ||
713*4882a593Smuzhiyun 	    (new->ldev_offline > 0 &&
714*4882a593Smuzhiyun 	     new->ldev_offline != old.ldev_offline) ||
715*4882a593Smuzhiyun 	    (new->ldev_count != old.ldev_count)) {
716*4882a593Smuzhiyun 		shost_printk(KERN_INFO, cb->host,
717*4882a593Smuzhiyun 			     "Logical drive count changed (%d/%d/%d)\n",
718*4882a593Smuzhiyun 			     new->ldev_critical,
719*4882a593Smuzhiyun 			     new->ldev_offline,
720*4882a593Smuzhiyun 			     new->ldev_count);
721*4882a593Smuzhiyun 		cb->need_ldev_info = true;
722*4882a593Smuzhiyun 	}
723*4882a593Smuzhiyun 	if (new->pdev_dead > 0 ||
724*4882a593Smuzhiyun 	    new->pdev_dead != old.pdev_dead ||
725*4882a593Smuzhiyun 	    time_after_eq(jiffies, cb->secondary_monitor_time
726*4882a593Smuzhiyun 			  + MYRB_SECONDARY_MONITOR_INTERVAL)) {
727*4882a593Smuzhiyun 		cb->need_bgi_status = cb->bgi_status_supported;
728*4882a593Smuzhiyun 		cb->secondary_monitor_time = jiffies;
729*4882a593Smuzhiyun 	}
730*4882a593Smuzhiyun 	if (new->rbld == MYRB_STDBY_RBLD_IN_PROGRESS ||
731*4882a593Smuzhiyun 	    new->rbld == MYRB_BG_RBLD_IN_PROGRESS ||
732*4882a593Smuzhiyun 	    old.rbld == MYRB_STDBY_RBLD_IN_PROGRESS ||
733*4882a593Smuzhiyun 	    old.rbld == MYRB_BG_RBLD_IN_PROGRESS) {
734*4882a593Smuzhiyun 		cb->need_rbld = true;
735*4882a593Smuzhiyun 		cb->rbld_first = (new->ldev_critical < old.ldev_critical);
736*4882a593Smuzhiyun 	}
737*4882a593Smuzhiyun 	if (old.rbld == MYRB_BG_CHECK_IN_PROGRESS)
738*4882a593Smuzhiyun 		switch (new->rbld) {
739*4882a593Smuzhiyun 		case MYRB_NO_STDBY_RBLD_OR_CHECK_IN_PROGRESS:
740*4882a593Smuzhiyun 			shost_printk(KERN_INFO, cb->host,
741*4882a593Smuzhiyun 				     "Consistency Check Completed Successfully\n");
742*4882a593Smuzhiyun 			break;
743*4882a593Smuzhiyun 		case MYRB_STDBY_RBLD_IN_PROGRESS:
744*4882a593Smuzhiyun 		case MYRB_BG_RBLD_IN_PROGRESS:
745*4882a593Smuzhiyun 			break;
746*4882a593Smuzhiyun 		case MYRB_BG_CHECK_IN_PROGRESS:
747*4882a593Smuzhiyun 			cb->need_cc_status = true;
748*4882a593Smuzhiyun 			break;
749*4882a593Smuzhiyun 		case MYRB_STDBY_RBLD_COMPLETED_WITH_ERROR:
750*4882a593Smuzhiyun 			shost_printk(KERN_INFO, cb->host,
751*4882a593Smuzhiyun 				     "Consistency Check Completed with Error\n");
752*4882a593Smuzhiyun 			break;
753*4882a593Smuzhiyun 		case MYRB_BG_RBLD_OR_CHECK_FAILED_DRIVE_FAILED:
754*4882a593Smuzhiyun 			shost_printk(KERN_INFO, cb->host,
755*4882a593Smuzhiyun 				     "Consistency Check Failed - Physical Device Failed\n");
756*4882a593Smuzhiyun 			break;
757*4882a593Smuzhiyun 		case MYRB_BG_RBLD_OR_CHECK_FAILED_LDEV_FAILED:
758*4882a593Smuzhiyun 			shost_printk(KERN_INFO, cb->host,
759*4882a593Smuzhiyun 				     "Consistency Check Failed - Logical Drive Failed\n");
760*4882a593Smuzhiyun 			break;
761*4882a593Smuzhiyun 		case MYRB_BG_RBLD_OR_CHECK_FAILED_OTHER:
762*4882a593Smuzhiyun 			shost_printk(KERN_INFO, cb->host,
763*4882a593Smuzhiyun 				     "Consistency Check Failed - Other Causes\n");
764*4882a593Smuzhiyun 			break;
765*4882a593Smuzhiyun 		case MYRB_BG_RBLD_OR_CHECK_SUCCESS_TERMINATED:
766*4882a593Smuzhiyun 			shost_printk(KERN_INFO, cb->host,
767*4882a593Smuzhiyun 				     "Consistency Check Successfully Terminated\n");
768*4882a593Smuzhiyun 			break;
769*4882a593Smuzhiyun 		}
770*4882a593Smuzhiyun 	else if (new->rbld == MYRB_BG_CHECK_IN_PROGRESS)
771*4882a593Smuzhiyun 		cb->need_cc_status = true;
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun 	return MYRB_STATUS_SUCCESS;
774*4882a593Smuzhiyun }
775*4882a593Smuzhiyun 
776*4882a593Smuzhiyun /**
777*4882a593Smuzhiyun  * myrb_set_pdev_state - sets the device state for a physical device
778*4882a593Smuzhiyun  *
779*4882a593Smuzhiyun  * Return: command status
780*4882a593Smuzhiyun  */
myrb_set_pdev_state(struct myrb_hba * cb,struct scsi_device * sdev,enum myrb_devstate state)781*4882a593Smuzhiyun static unsigned short myrb_set_pdev_state(struct myrb_hba *cb,
782*4882a593Smuzhiyun 		struct scsi_device *sdev, enum myrb_devstate state)
783*4882a593Smuzhiyun {
784*4882a593Smuzhiyun 	struct myrb_cmdblk *cmd_blk = &cb->dcmd_blk;
785*4882a593Smuzhiyun 	union myrb_cmd_mbox *mbox = &cmd_blk->mbox;
786*4882a593Smuzhiyun 	unsigned short status;
787*4882a593Smuzhiyun 
788*4882a593Smuzhiyun 	mutex_lock(&cb->dcmd_mutex);
789*4882a593Smuzhiyun 	mbox->type3D.opcode = MYRB_CMD_START_DEVICE;
790*4882a593Smuzhiyun 	mbox->type3D.id = MYRB_DCMD_TAG;
791*4882a593Smuzhiyun 	mbox->type3D.channel = sdev->channel;
792*4882a593Smuzhiyun 	mbox->type3D.target = sdev->id;
793*4882a593Smuzhiyun 	mbox->type3D.state = state & 0x1F;
794*4882a593Smuzhiyun 	status = myrb_exec_cmd(cb, cmd_blk);
795*4882a593Smuzhiyun 	mutex_unlock(&cb->dcmd_mutex);
796*4882a593Smuzhiyun 
797*4882a593Smuzhiyun 	return status;
798*4882a593Smuzhiyun }
799*4882a593Smuzhiyun 
800*4882a593Smuzhiyun /**
801*4882a593Smuzhiyun  * myrb_enable_mmio - enables the Memory Mailbox Interface
802*4882a593Smuzhiyun  *
803*4882a593Smuzhiyun  * PD and P controller types have no memory mailbox, but still need the
804*4882a593Smuzhiyun  * other dma mapped memory.
805*4882a593Smuzhiyun  *
806*4882a593Smuzhiyun  * Return: true on success, false otherwise.
807*4882a593Smuzhiyun  */
myrb_enable_mmio(struct myrb_hba * cb,mbox_mmio_init_t mmio_init_fn)808*4882a593Smuzhiyun static bool myrb_enable_mmio(struct myrb_hba *cb, mbox_mmio_init_t mmio_init_fn)
809*4882a593Smuzhiyun {
810*4882a593Smuzhiyun 	void __iomem *base = cb->io_base;
811*4882a593Smuzhiyun 	struct pci_dev *pdev = cb->pdev;
812*4882a593Smuzhiyun 	size_t err_table_size;
813*4882a593Smuzhiyun 	size_t ldev_info_size;
814*4882a593Smuzhiyun 	union myrb_cmd_mbox *cmd_mbox_mem;
815*4882a593Smuzhiyun 	struct myrb_stat_mbox *stat_mbox_mem;
816*4882a593Smuzhiyun 	union myrb_cmd_mbox mbox;
817*4882a593Smuzhiyun 	unsigned short status;
818*4882a593Smuzhiyun 
819*4882a593Smuzhiyun 	memset(&mbox, 0, sizeof(union myrb_cmd_mbox));
820*4882a593Smuzhiyun 
821*4882a593Smuzhiyun 	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
822*4882a593Smuzhiyun 		dev_err(&pdev->dev, "DMA mask out of range\n");
823*4882a593Smuzhiyun 		return false;
824*4882a593Smuzhiyun 	}
825*4882a593Smuzhiyun 
826*4882a593Smuzhiyun 	cb->enquiry = dma_alloc_coherent(&pdev->dev,
827*4882a593Smuzhiyun 					 sizeof(struct myrb_enquiry),
828*4882a593Smuzhiyun 					 &cb->enquiry_addr, GFP_KERNEL);
829*4882a593Smuzhiyun 	if (!cb->enquiry)
830*4882a593Smuzhiyun 		return false;
831*4882a593Smuzhiyun 
832*4882a593Smuzhiyun 	err_table_size = sizeof(struct myrb_error_entry) *
833*4882a593Smuzhiyun 		MYRB_MAX_CHANNELS * MYRB_MAX_TARGETS;
834*4882a593Smuzhiyun 	cb->err_table = dma_alloc_coherent(&pdev->dev, err_table_size,
835*4882a593Smuzhiyun 					   &cb->err_table_addr, GFP_KERNEL);
836*4882a593Smuzhiyun 	if (!cb->err_table)
837*4882a593Smuzhiyun 		return false;
838*4882a593Smuzhiyun 
839*4882a593Smuzhiyun 	ldev_info_size = sizeof(struct myrb_ldev_info) * MYRB_MAX_LDEVS;
840*4882a593Smuzhiyun 	cb->ldev_info_buf = dma_alloc_coherent(&pdev->dev, ldev_info_size,
841*4882a593Smuzhiyun 					       &cb->ldev_info_addr, GFP_KERNEL);
842*4882a593Smuzhiyun 	if (!cb->ldev_info_buf)
843*4882a593Smuzhiyun 		return false;
844*4882a593Smuzhiyun 
845*4882a593Smuzhiyun 	/*
846*4882a593Smuzhiyun 	 * Skip mailbox initialisation for PD and P Controllers
847*4882a593Smuzhiyun 	 */
848*4882a593Smuzhiyun 	if (!mmio_init_fn)
849*4882a593Smuzhiyun 		return true;
850*4882a593Smuzhiyun 
851*4882a593Smuzhiyun 	/* These are the base addresses for the command memory mailbox array */
852*4882a593Smuzhiyun 	cb->cmd_mbox_size =  MYRB_CMD_MBOX_COUNT * sizeof(union myrb_cmd_mbox);
853*4882a593Smuzhiyun 	cb->first_cmd_mbox = dma_alloc_coherent(&pdev->dev,
854*4882a593Smuzhiyun 						cb->cmd_mbox_size,
855*4882a593Smuzhiyun 						&cb->cmd_mbox_addr,
856*4882a593Smuzhiyun 						GFP_KERNEL);
857*4882a593Smuzhiyun 	if (!cb->first_cmd_mbox)
858*4882a593Smuzhiyun 		return false;
859*4882a593Smuzhiyun 
860*4882a593Smuzhiyun 	cmd_mbox_mem = cb->first_cmd_mbox;
861*4882a593Smuzhiyun 	cmd_mbox_mem += MYRB_CMD_MBOX_COUNT - 1;
862*4882a593Smuzhiyun 	cb->last_cmd_mbox = cmd_mbox_mem;
863*4882a593Smuzhiyun 	cb->next_cmd_mbox = cb->first_cmd_mbox;
864*4882a593Smuzhiyun 	cb->prev_cmd_mbox1 = cb->last_cmd_mbox;
865*4882a593Smuzhiyun 	cb->prev_cmd_mbox2 = cb->last_cmd_mbox - 1;
866*4882a593Smuzhiyun 
867*4882a593Smuzhiyun 	/* These are the base addresses for the status memory mailbox array */
868*4882a593Smuzhiyun 	cb->stat_mbox_size = MYRB_STAT_MBOX_COUNT *
869*4882a593Smuzhiyun 	    sizeof(struct myrb_stat_mbox);
870*4882a593Smuzhiyun 	cb->first_stat_mbox = dma_alloc_coherent(&pdev->dev,
871*4882a593Smuzhiyun 						 cb->stat_mbox_size,
872*4882a593Smuzhiyun 						 &cb->stat_mbox_addr,
873*4882a593Smuzhiyun 						 GFP_KERNEL);
874*4882a593Smuzhiyun 	if (!cb->first_stat_mbox)
875*4882a593Smuzhiyun 		return false;
876*4882a593Smuzhiyun 
877*4882a593Smuzhiyun 	stat_mbox_mem = cb->first_stat_mbox;
878*4882a593Smuzhiyun 	stat_mbox_mem += MYRB_STAT_MBOX_COUNT - 1;
879*4882a593Smuzhiyun 	cb->last_stat_mbox = stat_mbox_mem;
880*4882a593Smuzhiyun 	cb->next_stat_mbox = cb->first_stat_mbox;
881*4882a593Smuzhiyun 
882*4882a593Smuzhiyun 	/* Enable the Memory Mailbox Interface. */
883*4882a593Smuzhiyun 	cb->dual_mode_interface = true;
884*4882a593Smuzhiyun 	mbox.typeX.opcode = 0x2B;
885*4882a593Smuzhiyun 	mbox.typeX.id = 0;
886*4882a593Smuzhiyun 	mbox.typeX.opcode2 = 0x14;
887*4882a593Smuzhiyun 	mbox.typeX.cmd_mbox_addr = cb->cmd_mbox_addr;
888*4882a593Smuzhiyun 	mbox.typeX.stat_mbox_addr = cb->stat_mbox_addr;
889*4882a593Smuzhiyun 
890*4882a593Smuzhiyun 	status = mmio_init_fn(pdev, base, &mbox);
891*4882a593Smuzhiyun 	if (status != MYRB_STATUS_SUCCESS) {
892*4882a593Smuzhiyun 		cb->dual_mode_interface = false;
893*4882a593Smuzhiyun 		mbox.typeX.opcode2 = 0x10;
894*4882a593Smuzhiyun 		status = mmio_init_fn(pdev, base, &mbox);
895*4882a593Smuzhiyun 		if (status != MYRB_STATUS_SUCCESS) {
896*4882a593Smuzhiyun 			dev_err(&pdev->dev,
897*4882a593Smuzhiyun 				"Failed to enable mailbox, statux %02X\n",
898*4882a593Smuzhiyun 				status);
899*4882a593Smuzhiyun 			return false;
900*4882a593Smuzhiyun 		}
901*4882a593Smuzhiyun 	}
902*4882a593Smuzhiyun 	return true;
903*4882a593Smuzhiyun }
904*4882a593Smuzhiyun 
905*4882a593Smuzhiyun /**
906*4882a593Smuzhiyun  * myrb_get_hba_config - reads the configuration information
907*4882a593Smuzhiyun  *
908*4882a593Smuzhiyun  * Reads the configuration information from the controller and
909*4882a593Smuzhiyun  * initializes the controller structure.
910*4882a593Smuzhiyun  *
911*4882a593Smuzhiyun  * Return: 0 on success, errno otherwise
912*4882a593Smuzhiyun  */
myrb_get_hba_config(struct myrb_hba * cb)913*4882a593Smuzhiyun static int myrb_get_hba_config(struct myrb_hba *cb)
914*4882a593Smuzhiyun {
915*4882a593Smuzhiyun 	struct myrb_enquiry2 *enquiry2;
916*4882a593Smuzhiyun 	dma_addr_t enquiry2_addr;
917*4882a593Smuzhiyun 	struct myrb_config2 *config2;
918*4882a593Smuzhiyun 	dma_addr_t config2_addr;
919*4882a593Smuzhiyun 	struct Scsi_Host *shost = cb->host;
920*4882a593Smuzhiyun 	struct pci_dev *pdev = cb->pdev;
921*4882a593Smuzhiyun 	int pchan_max = 0, pchan_cur = 0;
922*4882a593Smuzhiyun 	unsigned short status;
923*4882a593Smuzhiyun 	int ret = -ENODEV, memsize = 0;
924*4882a593Smuzhiyun 
925*4882a593Smuzhiyun 	enquiry2 = dma_alloc_coherent(&pdev->dev, sizeof(struct myrb_enquiry2),
926*4882a593Smuzhiyun 				      &enquiry2_addr, GFP_KERNEL);
927*4882a593Smuzhiyun 	if (!enquiry2) {
928*4882a593Smuzhiyun 		shost_printk(KERN_ERR, cb->host,
929*4882a593Smuzhiyun 			     "Failed to allocate V1 enquiry2 memory\n");
930*4882a593Smuzhiyun 		return -ENOMEM;
931*4882a593Smuzhiyun 	}
932*4882a593Smuzhiyun 	config2 = dma_alloc_coherent(&pdev->dev, sizeof(struct myrb_config2),
933*4882a593Smuzhiyun 				     &config2_addr, GFP_KERNEL);
934*4882a593Smuzhiyun 	if (!config2) {
935*4882a593Smuzhiyun 		shost_printk(KERN_ERR, cb->host,
936*4882a593Smuzhiyun 			     "Failed to allocate V1 config2 memory\n");
937*4882a593Smuzhiyun 		dma_free_coherent(&pdev->dev, sizeof(struct myrb_enquiry2),
938*4882a593Smuzhiyun 				  enquiry2, enquiry2_addr);
939*4882a593Smuzhiyun 		return -ENOMEM;
940*4882a593Smuzhiyun 	}
941*4882a593Smuzhiyun 	mutex_lock(&cb->dma_mutex);
942*4882a593Smuzhiyun 	status = myrb_hba_enquiry(cb);
943*4882a593Smuzhiyun 	mutex_unlock(&cb->dma_mutex);
944*4882a593Smuzhiyun 	if (status != MYRB_STATUS_SUCCESS) {
945*4882a593Smuzhiyun 		shost_printk(KERN_WARNING, cb->host,
946*4882a593Smuzhiyun 			     "Failed it issue V1 Enquiry\n");
947*4882a593Smuzhiyun 		goto out_free;
948*4882a593Smuzhiyun 	}
949*4882a593Smuzhiyun 
950*4882a593Smuzhiyun 	status = myrb_exec_type3(cb, MYRB_CMD_ENQUIRY2, enquiry2_addr);
951*4882a593Smuzhiyun 	if (status != MYRB_STATUS_SUCCESS) {
952*4882a593Smuzhiyun 		shost_printk(KERN_WARNING, cb->host,
953*4882a593Smuzhiyun 			     "Failed to issue V1 Enquiry2\n");
954*4882a593Smuzhiyun 		goto out_free;
955*4882a593Smuzhiyun 	}
956*4882a593Smuzhiyun 
957*4882a593Smuzhiyun 	status = myrb_exec_type3(cb, MYRB_CMD_READ_CONFIG2, config2_addr);
958*4882a593Smuzhiyun 	if (status != MYRB_STATUS_SUCCESS) {
959*4882a593Smuzhiyun 		shost_printk(KERN_WARNING, cb->host,
960*4882a593Smuzhiyun 			     "Failed to issue ReadConfig2\n");
961*4882a593Smuzhiyun 		goto out_free;
962*4882a593Smuzhiyun 	}
963*4882a593Smuzhiyun 
964*4882a593Smuzhiyun 	status = myrb_get_ldev_info(cb);
965*4882a593Smuzhiyun 	if (status != MYRB_STATUS_SUCCESS) {
966*4882a593Smuzhiyun 		shost_printk(KERN_WARNING, cb->host,
967*4882a593Smuzhiyun 			     "Failed to get logical drive information\n");
968*4882a593Smuzhiyun 		goto out_free;
969*4882a593Smuzhiyun 	}
970*4882a593Smuzhiyun 
971*4882a593Smuzhiyun 	/*
972*4882a593Smuzhiyun 	 * Initialize the Controller Model Name and Full Model Name fields.
973*4882a593Smuzhiyun 	 */
974*4882a593Smuzhiyun 	switch (enquiry2->hw.sub_model) {
975*4882a593Smuzhiyun 	case DAC960_V1_P_PD_PU:
976*4882a593Smuzhiyun 		if (enquiry2->scsi_cap.bus_speed == MYRB_SCSI_SPEED_ULTRA)
977*4882a593Smuzhiyun 			strcpy(cb->model_name, "DAC960PU");
978*4882a593Smuzhiyun 		else
979*4882a593Smuzhiyun 			strcpy(cb->model_name, "DAC960PD");
980*4882a593Smuzhiyun 		break;
981*4882a593Smuzhiyun 	case DAC960_V1_PL:
982*4882a593Smuzhiyun 		strcpy(cb->model_name, "DAC960PL");
983*4882a593Smuzhiyun 		break;
984*4882a593Smuzhiyun 	case DAC960_V1_PG:
985*4882a593Smuzhiyun 		strcpy(cb->model_name, "DAC960PG");
986*4882a593Smuzhiyun 		break;
987*4882a593Smuzhiyun 	case DAC960_V1_PJ:
988*4882a593Smuzhiyun 		strcpy(cb->model_name, "DAC960PJ");
989*4882a593Smuzhiyun 		break;
990*4882a593Smuzhiyun 	case DAC960_V1_PR:
991*4882a593Smuzhiyun 		strcpy(cb->model_name, "DAC960PR");
992*4882a593Smuzhiyun 		break;
993*4882a593Smuzhiyun 	case DAC960_V1_PT:
994*4882a593Smuzhiyun 		strcpy(cb->model_name, "DAC960PT");
995*4882a593Smuzhiyun 		break;
996*4882a593Smuzhiyun 	case DAC960_V1_PTL0:
997*4882a593Smuzhiyun 		strcpy(cb->model_name, "DAC960PTL0");
998*4882a593Smuzhiyun 		break;
999*4882a593Smuzhiyun 	case DAC960_V1_PRL:
1000*4882a593Smuzhiyun 		strcpy(cb->model_name, "DAC960PRL");
1001*4882a593Smuzhiyun 		break;
1002*4882a593Smuzhiyun 	case DAC960_V1_PTL1:
1003*4882a593Smuzhiyun 		strcpy(cb->model_name, "DAC960PTL1");
1004*4882a593Smuzhiyun 		break;
1005*4882a593Smuzhiyun 	case DAC960_V1_1164P:
1006*4882a593Smuzhiyun 		strcpy(cb->model_name, "eXtremeRAID 1100");
1007*4882a593Smuzhiyun 		break;
1008*4882a593Smuzhiyun 	default:
1009*4882a593Smuzhiyun 		shost_printk(KERN_WARNING, cb->host,
1010*4882a593Smuzhiyun 			     "Unknown Model %X\n",
1011*4882a593Smuzhiyun 			     enquiry2->hw.sub_model);
1012*4882a593Smuzhiyun 		goto out;
1013*4882a593Smuzhiyun 	}
1014*4882a593Smuzhiyun 	/*
1015*4882a593Smuzhiyun 	 * Initialize the Controller Firmware Version field and verify that it
1016*4882a593Smuzhiyun 	 * is a supported firmware version.
1017*4882a593Smuzhiyun 	 * The supported firmware versions are:
1018*4882a593Smuzhiyun 	 *
1019*4882a593Smuzhiyun 	 * DAC1164P		    5.06 and above
1020*4882a593Smuzhiyun 	 * DAC960PTL/PRL/PJ/PG	    4.06 and above
1021*4882a593Smuzhiyun 	 * DAC960PU/PD/PL	    3.51 and above
1022*4882a593Smuzhiyun 	 * DAC960PU/PD/PL/P	    2.73 and above
1023*4882a593Smuzhiyun 	 */
1024*4882a593Smuzhiyun #if defined(CONFIG_ALPHA)
1025*4882a593Smuzhiyun 	/*
1026*4882a593Smuzhiyun 	 * DEC Alpha machines were often equipped with DAC960 cards that were
1027*4882a593Smuzhiyun 	 * OEMed from Mylex, and had their own custom firmware. Version 2.70,
1028*4882a593Smuzhiyun 	 * the last custom FW revision to be released by DEC for these older
1029*4882a593Smuzhiyun 	 * controllers, appears to work quite well with this driver.
1030*4882a593Smuzhiyun 	 *
1031*4882a593Smuzhiyun 	 * Cards tested successfully were several versions each of the PD and
1032*4882a593Smuzhiyun 	 * PU, called by DEC the KZPSC and KZPAC, respectively, and having
1033*4882a593Smuzhiyun 	 * the Manufacturer Numbers (from Mylex), usually on a sticker on the
1034*4882a593Smuzhiyun 	 * back of the board, of:
1035*4882a593Smuzhiyun 	 *
1036*4882a593Smuzhiyun 	 * KZPSC:  D040347 (1-channel) or D040348 (2-channel)
1037*4882a593Smuzhiyun 	 *         or D040349 (3-channel)
1038*4882a593Smuzhiyun 	 * KZPAC:  D040395 (1-channel) or D040396 (2-channel)
1039*4882a593Smuzhiyun 	 *         or D040397 (3-channel)
1040*4882a593Smuzhiyun 	 */
1041*4882a593Smuzhiyun # define FIRMWARE_27X	"2.70"
1042*4882a593Smuzhiyun #else
1043*4882a593Smuzhiyun # define FIRMWARE_27X	"2.73"
1044*4882a593Smuzhiyun #endif
1045*4882a593Smuzhiyun 
1046*4882a593Smuzhiyun 	if (enquiry2->fw.major_version == 0) {
1047*4882a593Smuzhiyun 		enquiry2->fw.major_version = cb->enquiry->fw_major_version;
1048*4882a593Smuzhiyun 		enquiry2->fw.minor_version = cb->enquiry->fw_minor_version;
1049*4882a593Smuzhiyun 		enquiry2->fw.firmware_type = '0';
1050*4882a593Smuzhiyun 		enquiry2->fw.turn_id = 0;
1051*4882a593Smuzhiyun 	}
1052*4882a593Smuzhiyun 	snprintf(cb->fw_version, sizeof(cb->fw_version),
1053*4882a593Smuzhiyun 		"%u.%02u-%c-%02u",
1054*4882a593Smuzhiyun 		enquiry2->fw.major_version,
1055*4882a593Smuzhiyun 		enquiry2->fw.minor_version,
1056*4882a593Smuzhiyun 		enquiry2->fw.firmware_type,
1057*4882a593Smuzhiyun 		enquiry2->fw.turn_id);
1058*4882a593Smuzhiyun 	if (!((enquiry2->fw.major_version == 5 &&
1059*4882a593Smuzhiyun 	       enquiry2->fw.minor_version >= 6) ||
1060*4882a593Smuzhiyun 	      (enquiry2->fw.major_version == 4 &&
1061*4882a593Smuzhiyun 	       enquiry2->fw.minor_version >= 6) ||
1062*4882a593Smuzhiyun 	      (enquiry2->fw.major_version == 3 &&
1063*4882a593Smuzhiyun 	       enquiry2->fw.minor_version >= 51) ||
1064*4882a593Smuzhiyun 	      (enquiry2->fw.major_version == 2 &&
1065*4882a593Smuzhiyun 	       strcmp(cb->fw_version, FIRMWARE_27X) >= 0))) {
1066*4882a593Smuzhiyun 		shost_printk(KERN_WARNING, cb->host,
1067*4882a593Smuzhiyun 			"Firmware Version '%s' unsupported\n",
1068*4882a593Smuzhiyun 			cb->fw_version);
1069*4882a593Smuzhiyun 		goto out;
1070*4882a593Smuzhiyun 	}
1071*4882a593Smuzhiyun 	/*
1072*4882a593Smuzhiyun 	 * Initialize the Channels, Targets, Memory Size, and SAF-TE
1073*4882a593Smuzhiyun 	 * Enclosure Management Enabled fields.
1074*4882a593Smuzhiyun 	 */
1075*4882a593Smuzhiyun 	switch (enquiry2->hw.model) {
1076*4882a593Smuzhiyun 	case MYRB_5_CHANNEL_BOARD:
1077*4882a593Smuzhiyun 		pchan_max = 5;
1078*4882a593Smuzhiyun 		break;
1079*4882a593Smuzhiyun 	case MYRB_3_CHANNEL_BOARD:
1080*4882a593Smuzhiyun 	case MYRB_3_CHANNEL_ASIC_DAC:
1081*4882a593Smuzhiyun 		pchan_max = 3;
1082*4882a593Smuzhiyun 		break;
1083*4882a593Smuzhiyun 	case MYRB_2_CHANNEL_BOARD:
1084*4882a593Smuzhiyun 		pchan_max = 2;
1085*4882a593Smuzhiyun 		break;
1086*4882a593Smuzhiyun 	default:
1087*4882a593Smuzhiyun 		pchan_max = enquiry2->cfg_chan;
1088*4882a593Smuzhiyun 		break;
1089*4882a593Smuzhiyun 	}
1090*4882a593Smuzhiyun 	pchan_cur = enquiry2->cur_chan;
1091*4882a593Smuzhiyun 	if (enquiry2->scsi_cap.bus_width == MYRB_WIDTH_WIDE_32BIT)
1092*4882a593Smuzhiyun 		cb->bus_width = 32;
1093*4882a593Smuzhiyun 	else if (enquiry2->scsi_cap.bus_width == MYRB_WIDTH_WIDE_16BIT)
1094*4882a593Smuzhiyun 		cb->bus_width = 16;
1095*4882a593Smuzhiyun 	else
1096*4882a593Smuzhiyun 		cb->bus_width = 8;
1097*4882a593Smuzhiyun 	cb->ldev_block_size = enquiry2->ldev_block_size;
1098*4882a593Smuzhiyun 	shost->max_channel = pchan_cur;
1099*4882a593Smuzhiyun 	shost->max_id = enquiry2->max_targets;
1100*4882a593Smuzhiyun 	memsize = enquiry2->mem_size >> 20;
1101*4882a593Smuzhiyun 	cb->safte_enabled = (enquiry2->fault_mgmt == MYRB_FAULT_SAFTE);
1102*4882a593Smuzhiyun 	/*
1103*4882a593Smuzhiyun 	 * Initialize the Controller Queue Depth, Driver Queue Depth,
1104*4882a593Smuzhiyun 	 * Logical Drive Count, Maximum Blocks per Command, Controller
1105*4882a593Smuzhiyun 	 * Scatter/Gather Limit, and Driver Scatter/Gather Limit.
1106*4882a593Smuzhiyun 	 * The Driver Queue Depth must be at most one less than the
1107*4882a593Smuzhiyun 	 * Controller Queue Depth to allow for an automatic drive
1108*4882a593Smuzhiyun 	 * rebuild operation.
1109*4882a593Smuzhiyun 	 */
1110*4882a593Smuzhiyun 	shost->can_queue = cb->enquiry->max_tcq;
1111*4882a593Smuzhiyun 	if (shost->can_queue < 3)
1112*4882a593Smuzhiyun 		shost->can_queue = enquiry2->max_cmds;
1113*4882a593Smuzhiyun 	if (shost->can_queue < 3)
1114*4882a593Smuzhiyun 		/* Play safe and disable TCQ */
1115*4882a593Smuzhiyun 		shost->can_queue = 1;
1116*4882a593Smuzhiyun 
1117*4882a593Smuzhiyun 	if (shost->can_queue > MYRB_CMD_MBOX_COUNT - 2)
1118*4882a593Smuzhiyun 		shost->can_queue = MYRB_CMD_MBOX_COUNT - 2;
1119*4882a593Smuzhiyun 	shost->max_sectors = enquiry2->max_sectors;
1120*4882a593Smuzhiyun 	shost->sg_tablesize = enquiry2->max_sge;
1121*4882a593Smuzhiyun 	if (shost->sg_tablesize > MYRB_SCATTER_GATHER_LIMIT)
1122*4882a593Smuzhiyun 		shost->sg_tablesize = MYRB_SCATTER_GATHER_LIMIT;
1123*4882a593Smuzhiyun 	/*
1124*4882a593Smuzhiyun 	 * Initialize the Stripe Size, Segment Size, and Geometry Translation.
1125*4882a593Smuzhiyun 	 */
1126*4882a593Smuzhiyun 	cb->stripe_size = config2->blocks_per_stripe * config2->block_factor
1127*4882a593Smuzhiyun 		>> (10 - MYRB_BLKSIZE_BITS);
1128*4882a593Smuzhiyun 	cb->segment_size = config2->blocks_per_cacheline * config2->block_factor
1129*4882a593Smuzhiyun 		>> (10 - MYRB_BLKSIZE_BITS);
1130*4882a593Smuzhiyun 	/* Assume 255/63 translation */
1131*4882a593Smuzhiyun 	cb->ldev_geom_heads = 255;
1132*4882a593Smuzhiyun 	cb->ldev_geom_sectors = 63;
1133*4882a593Smuzhiyun 	if (config2->drive_geometry) {
1134*4882a593Smuzhiyun 		cb->ldev_geom_heads = 128;
1135*4882a593Smuzhiyun 		cb->ldev_geom_sectors = 32;
1136*4882a593Smuzhiyun 	}
1137*4882a593Smuzhiyun 
1138*4882a593Smuzhiyun 	/*
1139*4882a593Smuzhiyun 	 * Initialize the Background Initialization Status.
1140*4882a593Smuzhiyun 	 */
1141*4882a593Smuzhiyun 	if ((cb->fw_version[0] == '4' &&
1142*4882a593Smuzhiyun 	     strcmp(cb->fw_version, "4.08") >= 0) ||
1143*4882a593Smuzhiyun 	    (cb->fw_version[0] == '5' &&
1144*4882a593Smuzhiyun 	     strcmp(cb->fw_version, "5.08") >= 0)) {
1145*4882a593Smuzhiyun 		cb->bgi_status_supported = true;
1146*4882a593Smuzhiyun 		myrb_bgi_control(cb);
1147*4882a593Smuzhiyun 	}
1148*4882a593Smuzhiyun 	cb->last_rbld_status = MYRB_NO_STDBY_RBLD_OR_CHECK_IN_PROGRESS;
1149*4882a593Smuzhiyun 	ret = 0;
1150*4882a593Smuzhiyun 
1151*4882a593Smuzhiyun out:
1152*4882a593Smuzhiyun 	shost_printk(KERN_INFO, cb->host,
1153*4882a593Smuzhiyun 		"Configuring %s PCI RAID Controller\n", cb->model_name);
1154*4882a593Smuzhiyun 	shost_printk(KERN_INFO, cb->host,
1155*4882a593Smuzhiyun 		"  Firmware Version: %s, Memory Size: %dMB\n",
1156*4882a593Smuzhiyun 		cb->fw_version, memsize);
1157*4882a593Smuzhiyun 	if (cb->io_addr == 0)
1158*4882a593Smuzhiyun 		shost_printk(KERN_INFO, cb->host,
1159*4882a593Smuzhiyun 			"  I/O Address: n/a, PCI Address: 0x%lX, IRQ Channel: %d\n",
1160*4882a593Smuzhiyun 			(unsigned long)cb->pci_addr, cb->irq);
1161*4882a593Smuzhiyun 	else
1162*4882a593Smuzhiyun 		shost_printk(KERN_INFO, cb->host,
1163*4882a593Smuzhiyun 			"  I/O Address: 0x%lX, PCI Address: 0x%lX, IRQ Channel: %d\n",
1164*4882a593Smuzhiyun 			(unsigned long)cb->io_addr, (unsigned long)cb->pci_addr,
1165*4882a593Smuzhiyun 			cb->irq);
1166*4882a593Smuzhiyun 	shost_printk(KERN_INFO, cb->host,
1167*4882a593Smuzhiyun 		"  Controller Queue Depth: %d, Maximum Blocks per Command: %d\n",
1168*4882a593Smuzhiyun 		cb->host->can_queue, cb->host->max_sectors);
1169*4882a593Smuzhiyun 	shost_printk(KERN_INFO, cb->host,
1170*4882a593Smuzhiyun 		     "  Driver Queue Depth: %d, Scatter/Gather Limit: %d of %d Segments\n",
1171*4882a593Smuzhiyun 		     cb->host->can_queue, cb->host->sg_tablesize,
1172*4882a593Smuzhiyun 		     MYRB_SCATTER_GATHER_LIMIT);
1173*4882a593Smuzhiyun 	shost_printk(KERN_INFO, cb->host,
1174*4882a593Smuzhiyun 		     "  Stripe Size: %dKB, Segment Size: %dKB, BIOS Geometry: %d/%d%s\n",
1175*4882a593Smuzhiyun 		     cb->stripe_size, cb->segment_size,
1176*4882a593Smuzhiyun 		     cb->ldev_geom_heads, cb->ldev_geom_sectors,
1177*4882a593Smuzhiyun 		     cb->safte_enabled ?
1178*4882a593Smuzhiyun 		     "  SAF-TE Enclosure Management Enabled" : "");
1179*4882a593Smuzhiyun 	shost_printk(KERN_INFO, cb->host,
1180*4882a593Smuzhiyun 		     "  Physical: %d/%d channels %d/%d/%d devices\n",
1181*4882a593Smuzhiyun 		     pchan_cur, pchan_max, 0, cb->enquiry->pdev_dead,
1182*4882a593Smuzhiyun 		     cb->host->max_id);
1183*4882a593Smuzhiyun 
1184*4882a593Smuzhiyun 	shost_printk(KERN_INFO, cb->host,
1185*4882a593Smuzhiyun 		     "  Logical: 1/1 channels, %d/%d disks\n",
1186*4882a593Smuzhiyun 		     cb->enquiry->ldev_count, MYRB_MAX_LDEVS);
1187*4882a593Smuzhiyun 
1188*4882a593Smuzhiyun out_free:
1189*4882a593Smuzhiyun 	dma_free_coherent(&pdev->dev, sizeof(struct myrb_enquiry2),
1190*4882a593Smuzhiyun 			  enquiry2, enquiry2_addr);
1191*4882a593Smuzhiyun 	dma_free_coherent(&pdev->dev, sizeof(struct myrb_config2),
1192*4882a593Smuzhiyun 			  config2, config2_addr);
1193*4882a593Smuzhiyun 
1194*4882a593Smuzhiyun 	return ret;
1195*4882a593Smuzhiyun }
1196*4882a593Smuzhiyun 
1197*4882a593Smuzhiyun /**
1198*4882a593Smuzhiyun  * myrb_unmap - unmaps controller structures
1199*4882a593Smuzhiyun  */
myrb_unmap(struct myrb_hba * cb)1200*4882a593Smuzhiyun static void myrb_unmap(struct myrb_hba *cb)
1201*4882a593Smuzhiyun {
1202*4882a593Smuzhiyun 	if (cb->ldev_info_buf) {
1203*4882a593Smuzhiyun 		size_t ldev_info_size = sizeof(struct myrb_ldev_info) *
1204*4882a593Smuzhiyun 			MYRB_MAX_LDEVS;
1205*4882a593Smuzhiyun 		dma_free_coherent(&cb->pdev->dev, ldev_info_size,
1206*4882a593Smuzhiyun 				  cb->ldev_info_buf, cb->ldev_info_addr);
1207*4882a593Smuzhiyun 		cb->ldev_info_buf = NULL;
1208*4882a593Smuzhiyun 	}
1209*4882a593Smuzhiyun 	if (cb->err_table) {
1210*4882a593Smuzhiyun 		size_t err_table_size = sizeof(struct myrb_error_entry) *
1211*4882a593Smuzhiyun 			MYRB_MAX_CHANNELS * MYRB_MAX_TARGETS;
1212*4882a593Smuzhiyun 		dma_free_coherent(&cb->pdev->dev, err_table_size,
1213*4882a593Smuzhiyun 				  cb->err_table, cb->err_table_addr);
1214*4882a593Smuzhiyun 		cb->err_table = NULL;
1215*4882a593Smuzhiyun 	}
1216*4882a593Smuzhiyun 	if (cb->enquiry) {
1217*4882a593Smuzhiyun 		dma_free_coherent(&cb->pdev->dev, sizeof(struct myrb_enquiry),
1218*4882a593Smuzhiyun 				  cb->enquiry, cb->enquiry_addr);
1219*4882a593Smuzhiyun 		cb->enquiry = NULL;
1220*4882a593Smuzhiyun 	}
1221*4882a593Smuzhiyun 	if (cb->first_stat_mbox) {
1222*4882a593Smuzhiyun 		dma_free_coherent(&cb->pdev->dev, cb->stat_mbox_size,
1223*4882a593Smuzhiyun 				  cb->first_stat_mbox, cb->stat_mbox_addr);
1224*4882a593Smuzhiyun 		cb->first_stat_mbox = NULL;
1225*4882a593Smuzhiyun 	}
1226*4882a593Smuzhiyun 	if (cb->first_cmd_mbox) {
1227*4882a593Smuzhiyun 		dma_free_coherent(&cb->pdev->dev, cb->cmd_mbox_size,
1228*4882a593Smuzhiyun 				  cb->first_cmd_mbox, cb->cmd_mbox_addr);
1229*4882a593Smuzhiyun 		cb->first_cmd_mbox = NULL;
1230*4882a593Smuzhiyun 	}
1231*4882a593Smuzhiyun }
1232*4882a593Smuzhiyun 
1233*4882a593Smuzhiyun /**
1234*4882a593Smuzhiyun  * myrb_cleanup - cleanup controller structures
1235*4882a593Smuzhiyun  */
myrb_cleanup(struct myrb_hba * cb)1236*4882a593Smuzhiyun static void myrb_cleanup(struct myrb_hba *cb)
1237*4882a593Smuzhiyun {
1238*4882a593Smuzhiyun 	struct pci_dev *pdev = cb->pdev;
1239*4882a593Smuzhiyun 
1240*4882a593Smuzhiyun 	/* Free the memory mailbox, status, and related structures */
1241*4882a593Smuzhiyun 	myrb_unmap(cb);
1242*4882a593Smuzhiyun 
1243*4882a593Smuzhiyun 	if (cb->mmio_base) {
1244*4882a593Smuzhiyun 		if (cb->disable_intr)
1245*4882a593Smuzhiyun 			cb->disable_intr(cb->io_base);
1246*4882a593Smuzhiyun 		iounmap(cb->mmio_base);
1247*4882a593Smuzhiyun 	}
1248*4882a593Smuzhiyun 	if (cb->irq)
1249*4882a593Smuzhiyun 		free_irq(cb->irq, cb);
1250*4882a593Smuzhiyun 	if (cb->io_addr)
1251*4882a593Smuzhiyun 		release_region(cb->io_addr, 0x80);
1252*4882a593Smuzhiyun 	pci_set_drvdata(pdev, NULL);
1253*4882a593Smuzhiyun 	pci_disable_device(pdev);
1254*4882a593Smuzhiyun 	scsi_host_put(cb->host);
1255*4882a593Smuzhiyun }
1256*4882a593Smuzhiyun 
myrb_host_reset(struct scsi_cmnd * scmd)1257*4882a593Smuzhiyun static int myrb_host_reset(struct scsi_cmnd *scmd)
1258*4882a593Smuzhiyun {
1259*4882a593Smuzhiyun 	struct Scsi_Host *shost = scmd->device->host;
1260*4882a593Smuzhiyun 	struct myrb_hba *cb = shost_priv(shost);
1261*4882a593Smuzhiyun 
1262*4882a593Smuzhiyun 	cb->reset(cb->io_base);
1263*4882a593Smuzhiyun 	return SUCCESS;
1264*4882a593Smuzhiyun }
1265*4882a593Smuzhiyun 
myrb_pthru_queuecommand(struct Scsi_Host * shost,struct scsi_cmnd * scmd)1266*4882a593Smuzhiyun static int myrb_pthru_queuecommand(struct Scsi_Host *shost,
1267*4882a593Smuzhiyun 		struct scsi_cmnd *scmd)
1268*4882a593Smuzhiyun {
1269*4882a593Smuzhiyun 	struct myrb_hba *cb = shost_priv(shost);
1270*4882a593Smuzhiyun 	struct myrb_cmdblk *cmd_blk = scsi_cmd_priv(scmd);
1271*4882a593Smuzhiyun 	union myrb_cmd_mbox *mbox = &cmd_blk->mbox;
1272*4882a593Smuzhiyun 	struct myrb_dcdb *dcdb;
1273*4882a593Smuzhiyun 	dma_addr_t dcdb_addr;
1274*4882a593Smuzhiyun 	struct scsi_device *sdev = scmd->device;
1275*4882a593Smuzhiyun 	struct scatterlist *sgl;
1276*4882a593Smuzhiyun 	unsigned long flags;
1277*4882a593Smuzhiyun 	int nsge;
1278*4882a593Smuzhiyun 
1279*4882a593Smuzhiyun 	myrb_reset_cmd(cmd_blk);
1280*4882a593Smuzhiyun 	dcdb = dma_pool_alloc(cb->dcdb_pool, GFP_ATOMIC, &dcdb_addr);
1281*4882a593Smuzhiyun 	if (!dcdb)
1282*4882a593Smuzhiyun 		return SCSI_MLQUEUE_HOST_BUSY;
1283*4882a593Smuzhiyun 	nsge = scsi_dma_map(scmd);
1284*4882a593Smuzhiyun 	if (nsge > 1) {
1285*4882a593Smuzhiyun 		dma_pool_free(cb->dcdb_pool, dcdb, dcdb_addr);
1286*4882a593Smuzhiyun 		scmd->result = (DID_ERROR << 16);
1287*4882a593Smuzhiyun 		scmd->scsi_done(scmd);
1288*4882a593Smuzhiyun 		return 0;
1289*4882a593Smuzhiyun 	}
1290*4882a593Smuzhiyun 
1291*4882a593Smuzhiyun 	mbox->type3.opcode = MYRB_CMD_DCDB;
1292*4882a593Smuzhiyun 	mbox->type3.id = scmd->request->tag + 3;
1293*4882a593Smuzhiyun 	mbox->type3.addr = dcdb_addr;
1294*4882a593Smuzhiyun 	dcdb->channel = sdev->channel;
1295*4882a593Smuzhiyun 	dcdb->target = sdev->id;
1296*4882a593Smuzhiyun 	switch (scmd->sc_data_direction) {
1297*4882a593Smuzhiyun 	case DMA_NONE:
1298*4882a593Smuzhiyun 		dcdb->data_xfer = MYRB_DCDB_XFER_NONE;
1299*4882a593Smuzhiyun 		break;
1300*4882a593Smuzhiyun 	case DMA_TO_DEVICE:
1301*4882a593Smuzhiyun 		dcdb->data_xfer = MYRB_DCDB_XFER_SYSTEM_TO_DEVICE;
1302*4882a593Smuzhiyun 		break;
1303*4882a593Smuzhiyun 	case DMA_FROM_DEVICE:
1304*4882a593Smuzhiyun 		dcdb->data_xfer = MYRB_DCDB_XFER_DEVICE_TO_SYSTEM;
1305*4882a593Smuzhiyun 		break;
1306*4882a593Smuzhiyun 	default:
1307*4882a593Smuzhiyun 		dcdb->data_xfer = MYRB_DCDB_XFER_ILLEGAL;
1308*4882a593Smuzhiyun 		break;
1309*4882a593Smuzhiyun 	}
1310*4882a593Smuzhiyun 	dcdb->early_status = false;
1311*4882a593Smuzhiyun 	if (scmd->request->timeout <= 10)
1312*4882a593Smuzhiyun 		dcdb->timeout = MYRB_DCDB_TMO_10_SECS;
1313*4882a593Smuzhiyun 	else if (scmd->request->timeout <= 60)
1314*4882a593Smuzhiyun 		dcdb->timeout = MYRB_DCDB_TMO_60_SECS;
1315*4882a593Smuzhiyun 	else if (scmd->request->timeout <= 600)
1316*4882a593Smuzhiyun 		dcdb->timeout = MYRB_DCDB_TMO_10_MINS;
1317*4882a593Smuzhiyun 	else
1318*4882a593Smuzhiyun 		dcdb->timeout = MYRB_DCDB_TMO_24_HRS;
1319*4882a593Smuzhiyun 	dcdb->no_autosense = false;
1320*4882a593Smuzhiyun 	dcdb->allow_disconnect = true;
1321*4882a593Smuzhiyun 	sgl = scsi_sglist(scmd);
1322*4882a593Smuzhiyun 	dcdb->dma_addr = sg_dma_address(sgl);
1323*4882a593Smuzhiyun 	if (sg_dma_len(sgl) > USHRT_MAX) {
1324*4882a593Smuzhiyun 		dcdb->xfer_len_lo = sg_dma_len(sgl) & 0xffff;
1325*4882a593Smuzhiyun 		dcdb->xfer_len_hi4 = sg_dma_len(sgl) >> 16;
1326*4882a593Smuzhiyun 	} else {
1327*4882a593Smuzhiyun 		dcdb->xfer_len_lo = sg_dma_len(sgl);
1328*4882a593Smuzhiyun 		dcdb->xfer_len_hi4 = 0;
1329*4882a593Smuzhiyun 	}
1330*4882a593Smuzhiyun 	dcdb->cdb_len = scmd->cmd_len;
1331*4882a593Smuzhiyun 	dcdb->sense_len = sizeof(dcdb->sense);
1332*4882a593Smuzhiyun 	memcpy(&dcdb->cdb, scmd->cmnd, scmd->cmd_len);
1333*4882a593Smuzhiyun 
1334*4882a593Smuzhiyun 	spin_lock_irqsave(&cb->queue_lock, flags);
1335*4882a593Smuzhiyun 	cb->qcmd(cb, cmd_blk);
1336*4882a593Smuzhiyun 	spin_unlock_irqrestore(&cb->queue_lock, flags);
1337*4882a593Smuzhiyun 	return 0;
1338*4882a593Smuzhiyun }
1339*4882a593Smuzhiyun 
myrb_inquiry(struct myrb_hba * cb,struct scsi_cmnd * scmd)1340*4882a593Smuzhiyun static void myrb_inquiry(struct myrb_hba *cb,
1341*4882a593Smuzhiyun 		struct scsi_cmnd *scmd)
1342*4882a593Smuzhiyun {
1343*4882a593Smuzhiyun 	unsigned char inq[36] = {
1344*4882a593Smuzhiyun 		0x00, 0x00, 0x03, 0x02, 0x20, 0x00, 0x01, 0x00,
1345*4882a593Smuzhiyun 		0x4d, 0x59, 0x4c, 0x45, 0x58, 0x20, 0x20, 0x20,
1346*4882a593Smuzhiyun 		0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
1347*4882a593Smuzhiyun 		0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
1348*4882a593Smuzhiyun 		0x20, 0x20, 0x20, 0x20,
1349*4882a593Smuzhiyun 	};
1350*4882a593Smuzhiyun 
1351*4882a593Smuzhiyun 	if (cb->bus_width > 16)
1352*4882a593Smuzhiyun 		inq[7] |= 1 << 6;
1353*4882a593Smuzhiyun 	if (cb->bus_width > 8)
1354*4882a593Smuzhiyun 		inq[7] |= 1 << 5;
1355*4882a593Smuzhiyun 	memcpy(&inq[16], cb->model_name, 16);
1356*4882a593Smuzhiyun 	memcpy(&inq[32], cb->fw_version, 1);
1357*4882a593Smuzhiyun 	memcpy(&inq[33], &cb->fw_version[2], 2);
1358*4882a593Smuzhiyun 	memcpy(&inq[35], &cb->fw_version[7], 1);
1359*4882a593Smuzhiyun 
1360*4882a593Smuzhiyun 	scsi_sg_copy_from_buffer(scmd, (void *)inq, 36);
1361*4882a593Smuzhiyun }
1362*4882a593Smuzhiyun 
1363*4882a593Smuzhiyun static void
myrb_mode_sense(struct myrb_hba * cb,struct scsi_cmnd * scmd,struct myrb_ldev_info * ldev_info)1364*4882a593Smuzhiyun myrb_mode_sense(struct myrb_hba *cb, struct scsi_cmnd *scmd,
1365*4882a593Smuzhiyun 		struct myrb_ldev_info *ldev_info)
1366*4882a593Smuzhiyun {
1367*4882a593Smuzhiyun 	unsigned char modes[32], *mode_pg;
1368*4882a593Smuzhiyun 	bool dbd;
1369*4882a593Smuzhiyun 	size_t mode_len;
1370*4882a593Smuzhiyun 
1371*4882a593Smuzhiyun 	dbd = (scmd->cmnd[1] & 0x08) == 0x08;
1372*4882a593Smuzhiyun 	if (dbd) {
1373*4882a593Smuzhiyun 		mode_len = 24;
1374*4882a593Smuzhiyun 		mode_pg = &modes[4];
1375*4882a593Smuzhiyun 	} else {
1376*4882a593Smuzhiyun 		mode_len = 32;
1377*4882a593Smuzhiyun 		mode_pg = &modes[12];
1378*4882a593Smuzhiyun 	}
1379*4882a593Smuzhiyun 	memset(modes, 0, sizeof(modes));
1380*4882a593Smuzhiyun 	modes[0] = mode_len - 1;
1381*4882a593Smuzhiyun 	if (!dbd) {
1382*4882a593Smuzhiyun 		unsigned char *block_desc = &modes[4];
1383*4882a593Smuzhiyun 
1384*4882a593Smuzhiyun 		modes[3] = 8;
1385*4882a593Smuzhiyun 		put_unaligned_be32(ldev_info->size, &block_desc[0]);
1386*4882a593Smuzhiyun 		put_unaligned_be32(cb->ldev_block_size, &block_desc[5]);
1387*4882a593Smuzhiyun 	}
1388*4882a593Smuzhiyun 	mode_pg[0] = 0x08;
1389*4882a593Smuzhiyun 	mode_pg[1] = 0x12;
1390*4882a593Smuzhiyun 	if (ldev_info->wb_enabled)
1391*4882a593Smuzhiyun 		mode_pg[2] |= 0x04;
1392*4882a593Smuzhiyun 	if (cb->segment_size) {
1393*4882a593Smuzhiyun 		mode_pg[2] |= 0x08;
1394*4882a593Smuzhiyun 		put_unaligned_be16(cb->segment_size, &mode_pg[14]);
1395*4882a593Smuzhiyun 	}
1396*4882a593Smuzhiyun 
1397*4882a593Smuzhiyun 	scsi_sg_copy_from_buffer(scmd, modes, mode_len);
1398*4882a593Smuzhiyun }
1399*4882a593Smuzhiyun 
myrb_request_sense(struct myrb_hba * cb,struct scsi_cmnd * scmd)1400*4882a593Smuzhiyun static void myrb_request_sense(struct myrb_hba *cb,
1401*4882a593Smuzhiyun 		struct scsi_cmnd *scmd)
1402*4882a593Smuzhiyun {
1403*4882a593Smuzhiyun 	scsi_build_sense_buffer(0, scmd->sense_buffer,
1404*4882a593Smuzhiyun 				NO_SENSE, 0, 0);
1405*4882a593Smuzhiyun 	scsi_sg_copy_from_buffer(scmd, scmd->sense_buffer,
1406*4882a593Smuzhiyun 				 SCSI_SENSE_BUFFERSIZE);
1407*4882a593Smuzhiyun }
1408*4882a593Smuzhiyun 
myrb_read_capacity(struct myrb_hba * cb,struct scsi_cmnd * scmd,struct myrb_ldev_info * ldev_info)1409*4882a593Smuzhiyun static void myrb_read_capacity(struct myrb_hba *cb, struct scsi_cmnd *scmd,
1410*4882a593Smuzhiyun 		struct myrb_ldev_info *ldev_info)
1411*4882a593Smuzhiyun {
1412*4882a593Smuzhiyun 	unsigned char data[8];
1413*4882a593Smuzhiyun 
1414*4882a593Smuzhiyun 	dev_dbg(&scmd->device->sdev_gendev,
1415*4882a593Smuzhiyun 		"Capacity %u, blocksize %u\n",
1416*4882a593Smuzhiyun 		ldev_info->size, cb->ldev_block_size);
1417*4882a593Smuzhiyun 	put_unaligned_be32(ldev_info->size - 1, &data[0]);
1418*4882a593Smuzhiyun 	put_unaligned_be32(cb->ldev_block_size, &data[4]);
1419*4882a593Smuzhiyun 	scsi_sg_copy_from_buffer(scmd, data, 8);
1420*4882a593Smuzhiyun }
1421*4882a593Smuzhiyun 
myrb_ldev_queuecommand(struct Scsi_Host * shost,struct scsi_cmnd * scmd)1422*4882a593Smuzhiyun static int myrb_ldev_queuecommand(struct Scsi_Host *shost,
1423*4882a593Smuzhiyun 		struct scsi_cmnd *scmd)
1424*4882a593Smuzhiyun {
1425*4882a593Smuzhiyun 	struct myrb_hba *cb = shost_priv(shost);
1426*4882a593Smuzhiyun 	struct myrb_cmdblk *cmd_blk = scsi_cmd_priv(scmd);
1427*4882a593Smuzhiyun 	union myrb_cmd_mbox *mbox = &cmd_blk->mbox;
1428*4882a593Smuzhiyun 	struct myrb_ldev_info *ldev_info;
1429*4882a593Smuzhiyun 	struct scsi_device *sdev = scmd->device;
1430*4882a593Smuzhiyun 	struct scatterlist *sgl;
1431*4882a593Smuzhiyun 	unsigned long flags;
1432*4882a593Smuzhiyun 	u64 lba;
1433*4882a593Smuzhiyun 	u32 block_cnt;
1434*4882a593Smuzhiyun 	int nsge;
1435*4882a593Smuzhiyun 
1436*4882a593Smuzhiyun 	ldev_info = sdev->hostdata;
1437*4882a593Smuzhiyun 	if (ldev_info->state != MYRB_DEVICE_ONLINE &&
1438*4882a593Smuzhiyun 	    ldev_info->state != MYRB_DEVICE_WO) {
1439*4882a593Smuzhiyun 		dev_dbg(&shost->shost_gendev, "ldev %u in state %x, skip\n",
1440*4882a593Smuzhiyun 			sdev->id, ldev_info ? ldev_info->state : 0xff);
1441*4882a593Smuzhiyun 		scmd->result = (DID_BAD_TARGET << 16);
1442*4882a593Smuzhiyun 		scmd->scsi_done(scmd);
1443*4882a593Smuzhiyun 		return 0;
1444*4882a593Smuzhiyun 	}
1445*4882a593Smuzhiyun 	switch (scmd->cmnd[0]) {
1446*4882a593Smuzhiyun 	case TEST_UNIT_READY:
1447*4882a593Smuzhiyun 		scmd->result = (DID_OK << 16);
1448*4882a593Smuzhiyun 		scmd->scsi_done(scmd);
1449*4882a593Smuzhiyun 		return 0;
1450*4882a593Smuzhiyun 	case INQUIRY:
1451*4882a593Smuzhiyun 		if (scmd->cmnd[1] & 1) {
1452*4882a593Smuzhiyun 			/* Illegal request, invalid field in CDB */
1453*4882a593Smuzhiyun 			scsi_build_sense_buffer(0, scmd->sense_buffer,
1454*4882a593Smuzhiyun 						ILLEGAL_REQUEST, 0x24, 0);
1455*4882a593Smuzhiyun 			scmd->result = (DRIVER_SENSE << 24) |
1456*4882a593Smuzhiyun 				SAM_STAT_CHECK_CONDITION;
1457*4882a593Smuzhiyun 		} else {
1458*4882a593Smuzhiyun 			myrb_inquiry(cb, scmd);
1459*4882a593Smuzhiyun 			scmd->result = (DID_OK << 16);
1460*4882a593Smuzhiyun 		}
1461*4882a593Smuzhiyun 		scmd->scsi_done(scmd);
1462*4882a593Smuzhiyun 		return 0;
1463*4882a593Smuzhiyun 	case SYNCHRONIZE_CACHE:
1464*4882a593Smuzhiyun 		scmd->result = (DID_OK << 16);
1465*4882a593Smuzhiyun 		scmd->scsi_done(scmd);
1466*4882a593Smuzhiyun 		return 0;
1467*4882a593Smuzhiyun 	case MODE_SENSE:
1468*4882a593Smuzhiyun 		if ((scmd->cmnd[2] & 0x3F) != 0x3F &&
1469*4882a593Smuzhiyun 		    (scmd->cmnd[2] & 0x3F) != 0x08) {
1470*4882a593Smuzhiyun 			/* Illegal request, invalid field in CDB */
1471*4882a593Smuzhiyun 			scsi_build_sense_buffer(0, scmd->sense_buffer,
1472*4882a593Smuzhiyun 						ILLEGAL_REQUEST, 0x24, 0);
1473*4882a593Smuzhiyun 			scmd->result = (DRIVER_SENSE << 24) |
1474*4882a593Smuzhiyun 				SAM_STAT_CHECK_CONDITION;
1475*4882a593Smuzhiyun 		} else {
1476*4882a593Smuzhiyun 			myrb_mode_sense(cb, scmd, ldev_info);
1477*4882a593Smuzhiyun 			scmd->result = (DID_OK << 16);
1478*4882a593Smuzhiyun 		}
1479*4882a593Smuzhiyun 		scmd->scsi_done(scmd);
1480*4882a593Smuzhiyun 		return 0;
1481*4882a593Smuzhiyun 	case READ_CAPACITY:
1482*4882a593Smuzhiyun 		if ((scmd->cmnd[1] & 1) ||
1483*4882a593Smuzhiyun 		    (scmd->cmnd[8] & 1)) {
1484*4882a593Smuzhiyun 			/* Illegal request, invalid field in CDB */
1485*4882a593Smuzhiyun 			scsi_build_sense_buffer(0, scmd->sense_buffer,
1486*4882a593Smuzhiyun 						ILLEGAL_REQUEST, 0x24, 0);
1487*4882a593Smuzhiyun 			scmd->result = (DRIVER_SENSE << 24) |
1488*4882a593Smuzhiyun 				SAM_STAT_CHECK_CONDITION;
1489*4882a593Smuzhiyun 			scmd->scsi_done(scmd);
1490*4882a593Smuzhiyun 			return 0;
1491*4882a593Smuzhiyun 		}
1492*4882a593Smuzhiyun 		lba = get_unaligned_be32(&scmd->cmnd[2]);
1493*4882a593Smuzhiyun 		if (lba) {
1494*4882a593Smuzhiyun 			/* Illegal request, invalid field in CDB */
1495*4882a593Smuzhiyun 			scsi_build_sense_buffer(0, scmd->sense_buffer,
1496*4882a593Smuzhiyun 						ILLEGAL_REQUEST, 0x24, 0);
1497*4882a593Smuzhiyun 			scmd->result = (DRIVER_SENSE << 24) |
1498*4882a593Smuzhiyun 				SAM_STAT_CHECK_CONDITION;
1499*4882a593Smuzhiyun 			scmd->scsi_done(scmd);
1500*4882a593Smuzhiyun 			return 0;
1501*4882a593Smuzhiyun 		}
1502*4882a593Smuzhiyun 		myrb_read_capacity(cb, scmd, ldev_info);
1503*4882a593Smuzhiyun 		scmd->scsi_done(scmd);
1504*4882a593Smuzhiyun 		return 0;
1505*4882a593Smuzhiyun 	case REQUEST_SENSE:
1506*4882a593Smuzhiyun 		myrb_request_sense(cb, scmd);
1507*4882a593Smuzhiyun 		scmd->result = (DID_OK << 16);
1508*4882a593Smuzhiyun 		return 0;
1509*4882a593Smuzhiyun 	case SEND_DIAGNOSTIC:
1510*4882a593Smuzhiyun 		if (scmd->cmnd[1] != 0x04) {
1511*4882a593Smuzhiyun 			/* Illegal request, invalid field in CDB */
1512*4882a593Smuzhiyun 			scsi_build_sense_buffer(0, scmd->sense_buffer,
1513*4882a593Smuzhiyun 						ILLEGAL_REQUEST, 0x24, 0);
1514*4882a593Smuzhiyun 			scmd->result = (DRIVER_SENSE << 24) |
1515*4882a593Smuzhiyun 				SAM_STAT_CHECK_CONDITION;
1516*4882a593Smuzhiyun 		} else {
1517*4882a593Smuzhiyun 			/* Assume good status */
1518*4882a593Smuzhiyun 			scmd->result = (DID_OK << 16);
1519*4882a593Smuzhiyun 		}
1520*4882a593Smuzhiyun 		scmd->scsi_done(scmd);
1521*4882a593Smuzhiyun 		return 0;
1522*4882a593Smuzhiyun 	case READ_6:
1523*4882a593Smuzhiyun 		if (ldev_info->state == MYRB_DEVICE_WO) {
1524*4882a593Smuzhiyun 			/* Data protect, attempt to read invalid data */
1525*4882a593Smuzhiyun 			scsi_build_sense_buffer(0, scmd->sense_buffer,
1526*4882a593Smuzhiyun 						DATA_PROTECT, 0x21, 0x06);
1527*4882a593Smuzhiyun 			scmd->result = (DRIVER_SENSE << 24) |
1528*4882a593Smuzhiyun 				SAM_STAT_CHECK_CONDITION;
1529*4882a593Smuzhiyun 			scmd->scsi_done(scmd);
1530*4882a593Smuzhiyun 			return 0;
1531*4882a593Smuzhiyun 		}
1532*4882a593Smuzhiyun 		fallthrough;
1533*4882a593Smuzhiyun 	case WRITE_6:
1534*4882a593Smuzhiyun 		lba = (((scmd->cmnd[1] & 0x1F) << 16) |
1535*4882a593Smuzhiyun 		       (scmd->cmnd[2] << 8) |
1536*4882a593Smuzhiyun 		       scmd->cmnd[3]);
1537*4882a593Smuzhiyun 		block_cnt = scmd->cmnd[4];
1538*4882a593Smuzhiyun 		break;
1539*4882a593Smuzhiyun 	case READ_10:
1540*4882a593Smuzhiyun 		if (ldev_info->state == MYRB_DEVICE_WO) {
1541*4882a593Smuzhiyun 			/* Data protect, attempt to read invalid data */
1542*4882a593Smuzhiyun 			scsi_build_sense_buffer(0, scmd->sense_buffer,
1543*4882a593Smuzhiyun 						DATA_PROTECT, 0x21, 0x06);
1544*4882a593Smuzhiyun 			scmd->result = (DRIVER_SENSE << 24) |
1545*4882a593Smuzhiyun 				SAM_STAT_CHECK_CONDITION;
1546*4882a593Smuzhiyun 			scmd->scsi_done(scmd);
1547*4882a593Smuzhiyun 			return 0;
1548*4882a593Smuzhiyun 		}
1549*4882a593Smuzhiyun 		fallthrough;
1550*4882a593Smuzhiyun 	case WRITE_10:
1551*4882a593Smuzhiyun 	case VERIFY:		/* 0x2F */
1552*4882a593Smuzhiyun 	case WRITE_VERIFY:	/* 0x2E */
1553*4882a593Smuzhiyun 		lba = get_unaligned_be32(&scmd->cmnd[2]);
1554*4882a593Smuzhiyun 		block_cnt = get_unaligned_be16(&scmd->cmnd[7]);
1555*4882a593Smuzhiyun 		break;
1556*4882a593Smuzhiyun 	case READ_12:
1557*4882a593Smuzhiyun 		if (ldev_info->state == MYRB_DEVICE_WO) {
1558*4882a593Smuzhiyun 			/* Data protect, attempt to read invalid data */
1559*4882a593Smuzhiyun 			scsi_build_sense_buffer(0, scmd->sense_buffer,
1560*4882a593Smuzhiyun 						DATA_PROTECT, 0x21, 0x06);
1561*4882a593Smuzhiyun 			scmd->result = (DRIVER_SENSE << 24) |
1562*4882a593Smuzhiyun 				SAM_STAT_CHECK_CONDITION;
1563*4882a593Smuzhiyun 			scmd->scsi_done(scmd);
1564*4882a593Smuzhiyun 			return 0;
1565*4882a593Smuzhiyun 		}
1566*4882a593Smuzhiyun 		fallthrough;
1567*4882a593Smuzhiyun 	case WRITE_12:
1568*4882a593Smuzhiyun 	case VERIFY_12: /* 0xAF */
1569*4882a593Smuzhiyun 	case WRITE_VERIFY_12:	/* 0xAE */
1570*4882a593Smuzhiyun 		lba = get_unaligned_be32(&scmd->cmnd[2]);
1571*4882a593Smuzhiyun 		block_cnt = get_unaligned_be32(&scmd->cmnd[6]);
1572*4882a593Smuzhiyun 		break;
1573*4882a593Smuzhiyun 	default:
1574*4882a593Smuzhiyun 		/* Illegal request, invalid opcode */
1575*4882a593Smuzhiyun 		scsi_build_sense_buffer(0, scmd->sense_buffer,
1576*4882a593Smuzhiyun 					ILLEGAL_REQUEST, 0x20, 0);
1577*4882a593Smuzhiyun 		scmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
1578*4882a593Smuzhiyun 		scmd->scsi_done(scmd);
1579*4882a593Smuzhiyun 		return 0;
1580*4882a593Smuzhiyun 	}
1581*4882a593Smuzhiyun 
1582*4882a593Smuzhiyun 	myrb_reset_cmd(cmd_blk);
1583*4882a593Smuzhiyun 	mbox->type5.id = scmd->request->tag + 3;
1584*4882a593Smuzhiyun 	if (scmd->sc_data_direction == DMA_NONE)
1585*4882a593Smuzhiyun 		goto submit;
1586*4882a593Smuzhiyun 	nsge = scsi_dma_map(scmd);
1587*4882a593Smuzhiyun 	if (nsge == 1) {
1588*4882a593Smuzhiyun 		sgl = scsi_sglist(scmd);
1589*4882a593Smuzhiyun 		if (scmd->sc_data_direction == DMA_FROM_DEVICE)
1590*4882a593Smuzhiyun 			mbox->type5.opcode = MYRB_CMD_READ;
1591*4882a593Smuzhiyun 		else
1592*4882a593Smuzhiyun 			mbox->type5.opcode = MYRB_CMD_WRITE;
1593*4882a593Smuzhiyun 
1594*4882a593Smuzhiyun 		mbox->type5.ld.xfer_len = block_cnt;
1595*4882a593Smuzhiyun 		mbox->type5.ld.ldev_num = sdev->id;
1596*4882a593Smuzhiyun 		mbox->type5.lba = lba;
1597*4882a593Smuzhiyun 		mbox->type5.addr = (u32)sg_dma_address(sgl);
1598*4882a593Smuzhiyun 	} else {
1599*4882a593Smuzhiyun 		struct myrb_sge *hw_sgl;
1600*4882a593Smuzhiyun 		dma_addr_t hw_sgl_addr;
1601*4882a593Smuzhiyun 		int i;
1602*4882a593Smuzhiyun 
1603*4882a593Smuzhiyun 		hw_sgl = dma_pool_alloc(cb->sg_pool, GFP_ATOMIC, &hw_sgl_addr);
1604*4882a593Smuzhiyun 		if (!hw_sgl)
1605*4882a593Smuzhiyun 			return SCSI_MLQUEUE_HOST_BUSY;
1606*4882a593Smuzhiyun 
1607*4882a593Smuzhiyun 		cmd_blk->sgl = hw_sgl;
1608*4882a593Smuzhiyun 		cmd_blk->sgl_addr = hw_sgl_addr;
1609*4882a593Smuzhiyun 
1610*4882a593Smuzhiyun 		if (scmd->sc_data_direction == DMA_FROM_DEVICE)
1611*4882a593Smuzhiyun 			mbox->type5.opcode = MYRB_CMD_READ_SG;
1612*4882a593Smuzhiyun 		else
1613*4882a593Smuzhiyun 			mbox->type5.opcode = MYRB_CMD_WRITE_SG;
1614*4882a593Smuzhiyun 
1615*4882a593Smuzhiyun 		mbox->type5.ld.xfer_len = block_cnt;
1616*4882a593Smuzhiyun 		mbox->type5.ld.ldev_num = sdev->id;
1617*4882a593Smuzhiyun 		mbox->type5.lba = lba;
1618*4882a593Smuzhiyun 		mbox->type5.addr = hw_sgl_addr;
1619*4882a593Smuzhiyun 		mbox->type5.sg_count = nsge;
1620*4882a593Smuzhiyun 
1621*4882a593Smuzhiyun 		scsi_for_each_sg(scmd, sgl, nsge, i) {
1622*4882a593Smuzhiyun 			hw_sgl->sge_addr = (u32)sg_dma_address(sgl);
1623*4882a593Smuzhiyun 			hw_sgl->sge_count = (u32)sg_dma_len(sgl);
1624*4882a593Smuzhiyun 			hw_sgl++;
1625*4882a593Smuzhiyun 		}
1626*4882a593Smuzhiyun 	}
1627*4882a593Smuzhiyun submit:
1628*4882a593Smuzhiyun 	spin_lock_irqsave(&cb->queue_lock, flags);
1629*4882a593Smuzhiyun 	cb->qcmd(cb, cmd_blk);
1630*4882a593Smuzhiyun 	spin_unlock_irqrestore(&cb->queue_lock, flags);
1631*4882a593Smuzhiyun 
1632*4882a593Smuzhiyun 	return 0;
1633*4882a593Smuzhiyun }
1634*4882a593Smuzhiyun 
myrb_queuecommand(struct Scsi_Host * shost,struct scsi_cmnd * scmd)1635*4882a593Smuzhiyun static int myrb_queuecommand(struct Scsi_Host *shost,
1636*4882a593Smuzhiyun 		struct scsi_cmnd *scmd)
1637*4882a593Smuzhiyun {
1638*4882a593Smuzhiyun 	struct scsi_device *sdev = scmd->device;
1639*4882a593Smuzhiyun 
1640*4882a593Smuzhiyun 	if (sdev->channel > myrb_logical_channel(shost)) {
1641*4882a593Smuzhiyun 		scmd->result = (DID_BAD_TARGET << 16);
1642*4882a593Smuzhiyun 		scmd->scsi_done(scmd);
1643*4882a593Smuzhiyun 		return 0;
1644*4882a593Smuzhiyun 	}
1645*4882a593Smuzhiyun 	if (sdev->channel == myrb_logical_channel(shost))
1646*4882a593Smuzhiyun 		return myrb_ldev_queuecommand(shost, scmd);
1647*4882a593Smuzhiyun 
1648*4882a593Smuzhiyun 	return myrb_pthru_queuecommand(shost, scmd);
1649*4882a593Smuzhiyun }
1650*4882a593Smuzhiyun 
myrb_ldev_slave_alloc(struct scsi_device * sdev)1651*4882a593Smuzhiyun static int myrb_ldev_slave_alloc(struct scsi_device *sdev)
1652*4882a593Smuzhiyun {
1653*4882a593Smuzhiyun 	struct myrb_hba *cb = shost_priv(sdev->host);
1654*4882a593Smuzhiyun 	struct myrb_ldev_info *ldev_info;
1655*4882a593Smuzhiyun 	unsigned short ldev_num = sdev->id;
1656*4882a593Smuzhiyun 	enum raid_level level;
1657*4882a593Smuzhiyun 
1658*4882a593Smuzhiyun 	ldev_info = cb->ldev_info_buf + ldev_num;
1659*4882a593Smuzhiyun 	if (!ldev_info)
1660*4882a593Smuzhiyun 		return -ENXIO;
1661*4882a593Smuzhiyun 
1662*4882a593Smuzhiyun 	sdev->hostdata = kzalloc(sizeof(*ldev_info), GFP_KERNEL);
1663*4882a593Smuzhiyun 	if (!sdev->hostdata)
1664*4882a593Smuzhiyun 		return -ENOMEM;
1665*4882a593Smuzhiyun 	dev_dbg(&sdev->sdev_gendev,
1666*4882a593Smuzhiyun 		"slave alloc ldev %d state %x\n",
1667*4882a593Smuzhiyun 		ldev_num, ldev_info->state);
1668*4882a593Smuzhiyun 	memcpy(sdev->hostdata, ldev_info,
1669*4882a593Smuzhiyun 	       sizeof(*ldev_info));
1670*4882a593Smuzhiyun 	switch (ldev_info->raid_level) {
1671*4882a593Smuzhiyun 	case MYRB_RAID_LEVEL0:
1672*4882a593Smuzhiyun 		level = RAID_LEVEL_LINEAR;
1673*4882a593Smuzhiyun 		break;
1674*4882a593Smuzhiyun 	case MYRB_RAID_LEVEL1:
1675*4882a593Smuzhiyun 		level = RAID_LEVEL_1;
1676*4882a593Smuzhiyun 		break;
1677*4882a593Smuzhiyun 	case MYRB_RAID_LEVEL3:
1678*4882a593Smuzhiyun 		level = RAID_LEVEL_3;
1679*4882a593Smuzhiyun 		break;
1680*4882a593Smuzhiyun 	case MYRB_RAID_LEVEL5:
1681*4882a593Smuzhiyun 		level = RAID_LEVEL_5;
1682*4882a593Smuzhiyun 		break;
1683*4882a593Smuzhiyun 	case MYRB_RAID_LEVEL6:
1684*4882a593Smuzhiyun 		level = RAID_LEVEL_6;
1685*4882a593Smuzhiyun 		break;
1686*4882a593Smuzhiyun 	case MYRB_RAID_JBOD:
1687*4882a593Smuzhiyun 		level = RAID_LEVEL_JBOD;
1688*4882a593Smuzhiyun 		break;
1689*4882a593Smuzhiyun 	default:
1690*4882a593Smuzhiyun 		level = RAID_LEVEL_UNKNOWN;
1691*4882a593Smuzhiyun 		break;
1692*4882a593Smuzhiyun 	}
1693*4882a593Smuzhiyun 	raid_set_level(myrb_raid_template, &sdev->sdev_gendev, level);
1694*4882a593Smuzhiyun 	return 0;
1695*4882a593Smuzhiyun }
1696*4882a593Smuzhiyun 
myrb_pdev_slave_alloc(struct scsi_device * sdev)1697*4882a593Smuzhiyun static int myrb_pdev_slave_alloc(struct scsi_device *sdev)
1698*4882a593Smuzhiyun {
1699*4882a593Smuzhiyun 	struct myrb_hba *cb = shost_priv(sdev->host);
1700*4882a593Smuzhiyun 	struct myrb_pdev_state *pdev_info;
1701*4882a593Smuzhiyun 	unsigned short status;
1702*4882a593Smuzhiyun 
1703*4882a593Smuzhiyun 	if (sdev->id > MYRB_MAX_TARGETS)
1704*4882a593Smuzhiyun 		return -ENXIO;
1705*4882a593Smuzhiyun 
1706*4882a593Smuzhiyun 	pdev_info = kzalloc(sizeof(*pdev_info), GFP_KERNEL|GFP_DMA);
1707*4882a593Smuzhiyun 	if (!pdev_info)
1708*4882a593Smuzhiyun 		return -ENOMEM;
1709*4882a593Smuzhiyun 
1710*4882a593Smuzhiyun 	status = myrb_exec_type3D(cb, MYRB_CMD_GET_DEVICE_STATE,
1711*4882a593Smuzhiyun 				  sdev, pdev_info);
1712*4882a593Smuzhiyun 	if (status != MYRB_STATUS_SUCCESS) {
1713*4882a593Smuzhiyun 		dev_dbg(&sdev->sdev_gendev,
1714*4882a593Smuzhiyun 			"Failed to get device state, status %x\n",
1715*4882a593Smuzhiyun 			status);
1716*4882a593Smuzhiyun 		kfree(pdev_info);
1717*4882a593Smuzhiyun 		return -ENXIO;
1718*4882a593Smuzhiyun 	}
1719*4882a593Smuzhiyun 	if (!pdev_info->present) {
1720*4882a593Smuzhiyun 		dev_dbg(&sdev->sdev_gendev,
1721*4882a593Smuzhiyun 			"device not present, skip\n");
1722*4882a593Smuzhiyun 		kfree(pdev_info);
1723*4882a593Smuzhiyun 		return -ENXIO;
1724*4882a593Smuzhiyun 	}
1725*4882a593Smuzhiyun 	dev_dbg(&sdev->sdev_gendev,
1726*4882a593Smuzhiyun 		"slave alloc pdev %d:%d state %x\n",
1727*4882a593Smuzhiyun 		sdev->channel, sdev->id, pdev_info->state);
1728*4882a593Smuzhiyun 	sdev->hostdata = pdev_info;
1729*4882a593Smuzhiyun 
1730*4882a593Smuzhiyun 	return 0;
1731*4882a593Smuzhiyun }
1732*4882a593Smuzhiyun 
myrb_slave_alloc(struct scsi_device * sdev)1733*4882a593Smuzhiyun static int myrb_slave_alloc(struct scsi_device *sdev)
1734*4882a593Smuzhiyun {
1735*4882a593Smuzhiyun 	if (sdev->channel > myrb_logical_channel(sdev->host))
1736*4882a593Smuzhiyun 		return -ENXIO;
1737*4882a593Smuzhiyun 
1738*4882a593Smuzhiyun 	if (sdev->lun > 0)
1739*4882a593Smuzhiyun 		return -ENXIO;
1740*4882a593Smuzhiyun 
1741*4882a593Smuzhiyun 	if (sdev->channel == myrb_logical_channel(sdev->host))
1742*4882a593Smuzhiyun 		return myrb_ldev_slave_alloc(sdev);
1743*4882a593Smuzhiyun 
1744*4882a593Smuzhiyun 	return myrb_pdev_slave_alloc(sdev);
1745*4882a593Smuzhiyun }
1746*4882a593Smuzhiyun 
myrb_slave_configure(struct scsi_device * sdev)1747*4882a593Smuzhiyun static int myrb_slave_configure(struct scsi_device *sdev)
1748*4882a593Smuzhiyun {
1749*4882a593Smuzhiyun 	struct myrb_ldev_info *ldev_info;
1750*4882a593Smuzhiyun 
1751*4882a593Smuzhiyun 	if (sdev->channel > myrb_logical_channel(sdev->host))
1752*4882a593Smuzhiyun 		return -ENXIO;
1753*4882a593Smuzhiyun 
1754*4882a593Smuzhiyun 	if (sdev->channel < myrb_logical_channel(sdev->host)) {
1755*4882a593Smuzhiyun 		sdev->no_uld_attach = 1;
1756*4882a593Smuzhiyun 		return 0;
1757*4882a593Smuzhiyun 	}
1758*4882a593Smuzhiyun 	if (sdev->lun != 0)
1759*4882a593Smuzhiyun 		return -ENXIO;
1760*4882a593Smuzhiyun 
1761*4882a593Smuzhiyun 	ldev_info = sdev->hostdata;
1762*4882a593Smuzhiyun 	if (!ldev_info)
1763*4882a593Smuzhiyun 		return -ENXIO;
1764*4882a593Smuzhiyun 	if (ldev_info->state != MYRB_DEVICE_ONLINE)
1765*4882a593Smuzhiyun 		sdev_printk(KERN_INFO, sdev,
1766*4882a593Smuzhiyun 			    "Logical drive is %s\n",
1767*4882a593Smuzhiyun 			    myrb_devstate_name(ldev_info->state));
1768*4882a593Smuzhiyun 
1769*4882a593Smuzhiyun 	sdev->tagged_supported = 1;
1770*4882a593Smuzhiyun 	return 0;
1771*4882a593Smuzhiyun }
1772*4882a593Smuzhiyun 
myrb_slave_destroy(struct scsi_device * sdev)1773*4882a593Smuzhiyun static void myrb_slave_destroy(struct scsi_device *sdev)
1774*4882a593Smuzhiyun {
1775*4882a593Smuzhiyun 	kfree(sdev->hostdata);
1776*4882a593Smuzhiyun }
1777*4882a593Smuzhiyun 
myrb_biosparam(struct scsi_device * sdev,struct block_device * bdev,sector_t capacity,int geom[])1778*4882a593Smuzhiyun static int myrb_biosparam(struct scsi_device *sdev, struct block_device *bdev,
1779*4882a593Smuzhiyun 		sector_t capacity, int geom[])
1780*4882a593Smuzhiyun {
1781*4882a593Smuzhiyun 	struct myrb_hba *cb = shost_priv(sdev->host);
1782*4882a593Smuzhiyun 
1783*4882a593Smuzhiyun 	geom[0] = cb->ldev_geom_heads;
1784*4882a593Smuzhiyun 	geom[1] = cb->ldev_geom_sectors;
1785*4882a593Smuzhiyun 	geom[2] = sector_div(capacity, geom[0] * geom[1]);
1786*4882a593Smuzhiyun 
1787*4882a593Smuzhiyun 	return 0;
1788*4882a593Smuzhiyun }
1789*4882a593Smuzhiyun 
raid_state_show(struct device * dev,struct device_attribute * attr,char * buf)1790*4882a593Smuzhiyun static ssize_t raid_state_show(struct device *dev,
1791*4882a593Smuzhiyun 		struct device_attribute *attr, char *buf)
1792*4882a593Smuzhiyun {
1793*4882a593Smuzhiyun 	struct scsi_device *sdev = to_scsi_device(dev);
1794*4882a593Smuzhiyun 	struct myrb_hba *cb = shost_priv(sdev->host);
1795*4882a593Smuzhiyun 	int ret;
1796*4882a593Smuzhiyun 
1797*4882a593Smuzhiyun 	if (!sdev->hostdata)
1798*4882a593Smuzhiyun 		return snprintf(buf, 16, "Unknown\n");
1799*4882a593Smuzhiyun 
1800*4882a593Smuzhiyun 	if (sdev->channel == myrb_logical_channel(sdev->host)) {
1801*4882a593Smuzhiyun 		struct myrb_ldev_info *ldev_info = sdev->hostdata;
1802*4882a593Smuzhiyun 		const char *name;
1803*4882a593Smuzhiyun 
1804*4882a593Smuzhiyun 		name = myrb_devstate_name(ldev_info->state);
1805*4882a593Smuzhiyun 		if (name)
1806*4882a593Smuzhiyun 			ret = snprintf(buf, 32, "%s\n", name);
1807*4882a593Smuzhiyun 		else
1808*4882a593Smuzhiyun 			ret = snprintf(buf, 32, "Invalid (%02X)\n",
1809*4882a593Smuzhiyun 				       ldev_info->state);
1810*4882a593Smuzhiyun 	} else {
1811*4882a593Smuzhiyun 		struct myrb_pdev_state *pdev_info = sdev->hostdata;
1812*4882a593Smuzhiyun 		unsigned short status;
1813*4882a593Smuzhiyun 		const char *name;
1814*4882a593Smuzhiyun 
1815*4882a593Smuzhiyun 		status = myrb_exec_type3D(cb, MYRB_CMD_GET_DEVICE_STATE,
1816*4882a593Smuzhiyun 					  sdev, pdev_info);
1817*4882a593Smuzhiyun 		if (status != MYRB_STATUS_SUCCESS)
1818*4882a593Smuzhiyun 			sdev_printk(KERN_INFO, sdev,
1819*4882a593Smuzhiyun 				    "Failed to get device state, status %x\n",
1820*4882a593Smuzhiyun 				    status);
1821*4882a593Smuzhiyun 
1822*4882a593Smuzhiyun 		if (!pdev_info->present)
1823*4882a593Smuzhiyun 			name = "Removed";
1824*4882a593Smuzhiyun 		else
1825*4882a593Smuzhiyun 			name = myrb_devstate_name(pdev_info->state);
1826*4882a593Smuzhiyun 		if (name)
1827*4882a593Smuzhiyun 			ret = snprintf(buf, 32, "%s\n", name);
1828*4882a593Smuzhiyun 		else
1829*4882a593Smuzhiyun 			ret = snprintf(buf, 32, "Invalid (%02X)\n",
1830*4882a593Smuzhiyun 				       pdev_info->state);
1831*4882a593Smuzhiyun 	}
1832*4882a593Smuzhiyun 	return ret;
1833*4882a593Smuzhiyun }
1834*4882a593Smuzhiyun 
raid_state_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1835*4882a593Smuzhiyun static ssize_t raid_state_store(struct device *dev,
1836*4882a593Smuzhiyun 		struct device_attribute *attr, const char *buf, size_t count)
1837*4882a593Smuzhiyun {
1838*4882a593Smuzhiyun 	struct scsi_device *sdev = to_scsi_device(dev);
1839*4882a593Smuzhiyun 	struct myrb_hba *cb = shost_priv(sdev->host);
1840*4882a593Smuzhiyun 	struct myrb_pdev_state *pdev_info;
1841*4882a593Smuzhiyun 	enum myrb_devstate new_state;
1842*4882a593Smuzhiyun 	unsigned short status;
1843*4882a593Smuzhiyun 
1844*4882a593Smuzhiyun 	if (!strncmp(buf, "kill", 4) ||
1845*4882a593Smuzhiyun 	    !strncmp(buf, "offline", 7))
1846*4882a593Smuzhiyun 		new_state = MYRB_DEVICE_DEAD;
1847*4882a593Smuzhiyun 	else if (!strncmp(buf, "online", 6))
1848*4882a593Smuzhiyun 		new_state = MYRB_DEVICE_ONLINE;
1849*4882a593Smuzhiyun 	else if (!strncmp(buf, "standby", 7))
1850*4882a593Smuzhiyun 		new_state = MYRB_DEVICE_STANDBY;
1851*4882a593Smuzhiyun 	else
1852*4882a593Smuzhiyun 		return -EINVAL;
1853*4882a593Smuzhiyun 
1854*4882a593Smuzhiyun 	pdev_info = sdev->hostdata;
1855*4882a593Smuzhiyun 	if (!pdev_info) {
1856*4882a593Smuzhiyun 		sdev_printk(KERN_INFO, sdev,
1857*4882a593Smuzhiyun 			    "Failed - no physical device information\n");
1858*4882a593Smuzhiyun 		return -ENXIO;
1859*4882a593Smuzhiyun 	}
1860*4882a593Smuzhiyun 	if (!pdev_info->present) {
1861*4882a593Smuzhiyun 		sdev_printk(KERN_INFO, sdev,
1862*4882a593Smuzhiyun 			    "Failed - device not present\n");
1863*4882a593Smuzhiyun 		return -ENXIO;
1864*4882a593Smuzhiyun 	}
1865*4882a593Smuzhiyun 
1866*4882a593Smuzhiyun 	if (pdev_info->state == new_state)
1867*4882a593Smuzhiyun 		return count;
1868*4882a593Smuzhiyun 
1869*4882a593Smuzhiyun 	status = myrb_set_pdev_state(cb, sdev, new_state);
1870*4882a593Smuzhiyun 	switch (status) {
1871*4882a593Smuzhiyun 	case MYRB_STATUS_SUCCESS:
1872*4882a593Smuzhiyun 		break;
1873*4882a593Smuzhiyun 	case MYRB_STATUS_START_DEVICE_FAILED:
1874*4882a593Smuzhiyun 		sdev_printk(KERN_INFO, sdev,
1875*4882a593Smuzhiyun 			     "Failed - Unable to Start Device\n");
1876*4882a593Smuzhiyun 		count = -EAGAIN;
1877*4882a593Smuzhiyun 		break;
1878*4882a593Smuzhiyun 	case MYRB_STATUS_NO_DEVICE:
1879*4882a593Smuzhiyun 		sdev_printk(KERN_INFO, sdev,
1880*4882a593Smuzhiyun 			    "Failed - No Device at Address\n");
1881*4882a593Smuzhiyun 		count = -ENODEV;
1882*4882a593Smuzhiyun 		break;
1883*4882a593Smuzhiyun 	case MYRB_STATUS_INVALID_CHANNEL_OR_TARGET:
1884*4882a593Smuzhiyun 		sdev_printk(KERN_INFO, sdev,
1885*4882a593Smuzhiyun 			 "Failed - Invalid Channel or Target or Modifier\n");
1886*4882a593Smuzhiyun 		count = -EINVAL;
1887*4882a593Smuzhiyun 		break;
1888*4882a593Smuzhiyun 	case MYRB_STATUS_CHANNEL_BUSY:
1889*4882a593Smuzhiyun 		sdev_printk(KERN_INFO, sdev,
1890*4882a593Smuzhiyun 			 "Failed - Channel Busy\n");
1891*4882a593Smuzhiyun 		count = -EBUSY;
1892*4882a593Smuzhiyun 		break;
1893*4882a593Smuzhiyun 	default:
1894*4882a593Smuzhiyun 		sdev_printk(KERN_INFO, sdev,
1895*4882a593Smuzhiyun 			 "Failed - Unexpected Status %04X\n", status);
1896*4882a593Smuzhiyun 		count = -EIO;
1897*4882a593Smuzhiyun 		break;
1898*4882a593Smuzhiyun 	}
1899*4882a593Smuzhiyun 	return count;
1900*4882a593Smuzhiyun }
1901*4882a593Smuzhiyun static DEVICE_ATTR_RW(raid_state);
1902*4882a593Smuzhiyun 
raid_level_show(struct device * dev,struct device_attribute * attr,char * buf)1903*4882a593Smuzhiyun static ssize_t raid_level_show(struct device *dev,
1904*4882a593Smuzhiyun 		struct device_attribute *attr, char *buf)
1905*4882a593Smuzhiyun {
1906*4882a593Smuzhiyun 	struct scsi_device *sdev = to_scsi_device(dev);
1907*4882a593Smuzhiyun 
1908*4882a593Smuzhiyun 	if (sdev->channel == myrb_logical_channel(sdev->host)) {
1909*4882a593Smuzhiyun 		struct myrb_ldev_info *ldev_info = sdev->hostdata;
1910*4882a593Smuzhiyun 		const char *name;
1911*4882a593Smuzhiyun 
1912*4882a593Smuzhiyun 		if (!ldev_info)
1913*4882a593Smuzhiyun 			return -ENXIO;
1914*4882a593Smuzhiyun 
1915*4882a593Smuzhiyun 		name = myrb_raidlevel_name(ldev_info->raid_level);
1916*4882a593Smuzhiyun 		if (!name)
1917*4882a593Smuzhiyun 			return snprintf(buf, 32, "Invalid (%02X)\n",
1918*4882a593Smuzhiyun 					ldev_info->state);
1919*4882a593Smuzhiyun 		return snprintf(buf, 32, "%s\n", name);
1920*4882a593Smuzhiyun 	}
1921*4882a593Smuzhiyun 	return snprintf(buf, 32, "Physical Drive\n");
1922*4882a593Smuzhiyun }
1923*4882a593Smuzhiyun static DEVICE_ATTR_RO(raid_level);
1924*4882a593Smuzhiyun 
rebuild_show(struct device * dev,struct device_attribute * attr,char * buf)1925*4882a593Smuzhiyun static ssize_t rebuild_show(struct device *dev,
1926*4882a593Smuzhiyun 		struct device_attribute *attr, char *buf)
1927*4882a593Smuzhiyun {
1928*4882a593Smuzhiyun 	struct scsi_device *sdev = to_scsi_device(dev);
1929*4882a593Smuzhiyun 	struct myrb_hba *cb = shost_priv(sdev->host);
1930*4882a593Smuzhiyun 	struct myrb_rbld_progress rbld_buf;
1931*4882a593Smuzhiyun 	unsigned char status;
1932*4882a593Smuzhiyun 
1933*4882a593Smuzhiyun 	if (sdev->channel < myrb_logical_channel(sdev->host))
1934*4882a593Smuzhiyun 		return snprintf(buf, 32, "physical device - not rebuilding\n");
1935*4882a593Smuzhiyun 
1936*4882a593Smuzhiyun 	status = myrb_get_rbld_progress(cb, &rbld_buf);
1937*4882a593Smuzhiyun 
1938*4882a593Smuzhiyun 	if (rbld_buf.ldev_num != sdev->id ||
1939*4882a593Smuzhiyun 	    status != MYRB_STATUS_SUCCESS)
1940*4882a593Smuzhiyun 		return snprintf(buf, 32, "not rebuilding\n");
1941*4882a593Smuzhiyun 
1942*4882a593Smuzhiyun 	return snprintf(buf, 32, "rebuilding block %u of %u\n",
1943*4882a593Smuzhiyun 			rbld_buf.ldev_size - rbld_buf.blocks_left,
1944*4882a593Smuzhiyun 			rbld_buf.ldev_size);
1945*4882a593Smuzhiyun }
1946*4882a593Smuzhiyun 
rebuild_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1947*4882a593Smuzhiyun static ssize_t rebuild_store(struct device *dev,
1948*4882a593Smuzhiyun 		struct device_attribute *attr, const char *buf, size_t count)
1949*4882a593Smuzhiyun {
1950*4882a593Smuzhiyun 	struct scsi_device *sdev = to_scsi_device(dev);
1951*4882a593Smuzhiyun 	struct myrb_hba *cb = shost_priv(sdev->host);
1952*4882a593Smuzhiyun 	struct myrb_cmdblk *cmd_blk;
1953*4882a593Smuzhiyun 	union myrb_cmd_mbox *mbox;
1954*4882a593Smuzhiyun 	unsigned short status;
1955*4882a593Smuzhiyun 	int rc, start;
1956*4882a593Smuzhiyun 	const char *msg;
1957*4882a593Smuzhiyun 
1958*4882a593Smuzhiyun 	rc = kstrtoint(buf, 0, &start);
1959*4882a593Smuzhiyun 	if (rc)
1960*4882a593Smuzhiyun 		return rc;
1961*4882a593Smuzhiyun 
1962*4882a593Smuzhiyun 	if (sdev->channel >= myrb_logical_channel(sdev->host))
1963*4882a593Smuzhiyun 		return -ENXIO;
1964*4882a593Smuzhiyun 
1965*4882a593Smuzhiyun 	status = myrb_get_rbld_progress(cb, NULL);
1966*4882a593Smuzhiyun 	if (start) {
1967*4882a593Smuzhiyun 		if (status == MYRB_STATUS_SUCCESS) {
1968*4882a593Smuzhiyun 			sdev_printk(KERN_INFO, sdev,
1969*4882a593Smuzhiyun 				    "Rebuild Not Initiated; already in progress\n");
1970*4882a593Smuzhiyun 			return -EALREADY;
1971*4882a593Smuzhiyun 		}
1972*4882a593Smuzhiyun 		mutex_lock(&cb->dcmd_mutex);
1973*4882a593Smuzhiyun 		cmd_blk = &cb->dcmd_blk;
1974*4882a593Smuzhiyun 		myrb_reset_cmd(cmd_blk);
1975*4882a593Smuzhiyun 		mbox = &cmd_blk->mbox;
1976*4882a593Smuzhiyun 		mbox->type3D.opcode = MYRB_CMD_REBUILD_ASYNC;
1977*4882a593Smuzhiyun 		mbox->type3D.id = MYRB_DCMD_TAG;
1978*4882a593Smuzhiyun 		mbox->type3D.channel = sdev->channel;
1979*4882a593Smuzhiyun 		mbox->type3D.target = sdev->id;
1980*4882a593Smuzhiyun 		status = myrb_exec_cmd(cb, cmd_blk);
1981*4882a593Smuzhiyun 		mutex_unlock(&cb->dcmd_mutex);
1982*4882a593Smuzhiyun 	} else {
1983*4882a593Smuzhiyun 		struct pci_dev *pdev = cb->pdev;
1984*4882a593Smuzhiyun 		unsigned char *rate;
1985*4882a593Smuzhiyun 		dma_addr_t rate_addr;
1986*4882a593Smuzhiyun 
1987*4882a593Smuzhiyun 		if (status != MYRB_STATUS_SUCCESS) {
1988*4882a593Smuzhiyun 			sdev_printk(KERN_INFO, sdev,
1989*4882a593Smuzhiyun 				    "Rebuild Not Cancelled; not in progress\n");
1990*4882a593Smuzhiyun 			return 0;
1991*4882a593Smuzhiyun 		}
1992*4882a593Smuzhiyun 
1993*4882a593Smuzhiyun 		rate = dma_alloc_coherent(&pdev->dev, sizeof(char),
1994*4882a593Smuzhiyun 					  &rate_addr, GFP_KERNEL);
1995*4882a593Smuzhiyun 		if (rate == NULL) {
1996*4882a593Smuzhiyun 			sdev_printk(KERN_INFO, sdev,
1997*4882a593Smuzhiyun 				    "Cancellation of Rebuild Failed - Out of Memory\n");
1998*4882a593Smuzhiyun 			return -ENOMEM;
1999*4882a593Smuzhiyun 		}
2000*4882a593Smuzhiyun 		mutex_lock(&cb->dcmd_mutex);
2001*4882a593Smuzhiyun 		cmd_blk = &cb->dcmd_blk;
2002*4882a593Smuzhiyun 		myrb_reset_cmd(cmd_blk);
2003*4882a593Smuzhiyun 		mbox = &cmd_blk->mbox;
2004*4882a593Smuzhiyun 		mbox->type3R.opcode = MYRB_CMD_REBUILD_CONTROL;
2005*4882a593Smuzhiyun 		mbox->type3R.id = MYRB_DCMD_TAG;
2006*4882a593Smuzhiyun 		mbox->type3R.rbld_rate = 0xFF;
2007*4882a593Smuzhiyun 		mbox->type3R.addr = rate_addr;
2008*4882a593Smuzhiyun 		status = myrb_exec_cmd(cb, cmd_blk);
2009*4882a593Smuzhiyun 		dma_free_coherent(&pdev->dev, sizeof(char), rate, rate_addr);
2010*4882a593Smuzhiyun 		mutex_unlock(&cb->dcmd_mutex);
2011*4882a593Smuzhiyun 	}
2012*4882a593Smuzhiyun 	if (status == MYRB_STATUS_SUCCESS) {
2013*4882a593Smuzhiyun 		sdev_printk(KERN_INFO, sdev, "Rebuild %s\n",
2014*4882a593Smuzhiyun 			    start ? "Initiated" : "Cancelled");
2015*4882a593Smuzhiyun 		return count;
2016*4882a593Smuzhiyun 	}
2017*4882a593Smuzhiyun 	if (!start) {
2018*4882a593Smuzhiyun 		sdev_printk(KERN_INFO, sdev,
2019*4882a593Smuzhiyun 			    "Rebuild Not Cancelled, status 0x%x\n",
2020*4882a593Smuzhiyun 			    status);
2021*4882a593Smuzhiyun 		return -EIO;
2022*4882a593Smuzhiyun 	}
2023*4882a593Smuzhiyun 
2024*4882a593Smuzhiyun 	switch (status) {
2025*4882a593Smuzhiyun 	case MYRB_STATUS_ATTEMPT_TO_RBLD_ONLINE_DRIVE:
2026*4882a593Smuzhiyun 		msg = "Attempt to Rebuild Online or Unresponsive Drive";
2027*4882a593Smuzhiyun 		break;
2028*4882a593Smuzhiyun 	case MYRB_STATUS_RBLD_NEW_DISK_FAILED:
2029*4882a593Smuzhiyun 		msg = "New Disk Failed During Rebuild";
2030*4882a593Smuzhiyun 		break;
2031*4882a593Smuzhiyun 	case MYRB_STATUS_INVALID_ADDRESS:
2032*4882a593Smuzhiyun 		msg = "Invalid Device Address";
2033*4882a593Smuzhiyun 		break;
2034*4882a593Smuzhiyun 	case MYRB_STATUS_RBLD_OR_CHECK_INPROGRESS:
2035*4882a593Smuzhiyun 		msg = "Already in Progress";
2036*4882a593Smuzhiyun 		break;
2037*4882a593Smuzhiyun 	default:
2038*4882a593Smuzhiyun 		msg = NULL;
2039*4882a593Smuzhiyun 		break;
2040*4882a593Smuzhiyun 	}
2041*4882a593Smuzhiyun 	if (msg)
2042*4882a593Smuzhiyun 		sdev_printk(KERN_INFO, sdev,
2043*4882a593Smuzhiyun 			    "Rebuild Failed - %s\n", msg);
2044*4882a593Smuzhiyun 	else
2045*4882a593Smuzhiyun 		sdev_printk(KERN_INFO, sdev,
2046*4882a593Smuzhiyun 			    "Rebuild Failed, status 0x%x\n", status);
2047*4882a593Smuzhiyun 
2048*4882a593Smuzhiyun 	return -EIO;
2049*4882a593Smuzhiyun }
2050*4882a593Smuzhiyun static DEVICE_ATTR_RW(rebuild);
2051*4882a593Smuzhiyun 
consistency_check_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2052*4882a593Smuzhiyun static ssize_t consistency_check_store(struct device *dev,
2053*4882a593Smuzhiyun 		struct device_attribute *attr, const char *buf, size_t count)
2054*4882a593Smuzhiyun {
2055*4882a593Smuzhiyun 	struct scsi_device *sdev = to_scsi_device(dev);
2056*4882a593Smuzhiyun 	struct myrb_hba *cb = shost_priv(sdev->host);
2057*4882a593Smuzhiyun 	struct myrb_rbld_progress rbld_buf;
2058*4882a593Smuzhiyun 	struct myrb_cmdblk *cmd_blk;
2059*4882a593Smuzhiyun 	union myrb_cmd_mbox *mbox;
2060*4882a593Smuzhiyun 	unsigned short ldev_num = 0xFFFF;
2061*4882a593Smuzhiyun 	unsigned short status;
2062*4882a593Smuzhiyun 	int rc, start;
2063*4882a593Smuzhiyun 	const char *msg;
2064*4882a593Smuzhiyun 
2065*4882a593Smuzhiyun 	rc = kstrtoint(buf, 0, &start);
2066*4882a593Smuzhiyun 	if (rc)
2067*4882a593Smuzhiyun 		return rc;
2068*4882a593Smuzhiyun 
2069*4882a593Smuzhiyun 	if (sdev->channel < myrb_logical_channel(sdev->host))
2070*4882a593Smuzhiyun 		return -ENXIO;
2071*4882a593Smuzhiyun 
2072*4882a593Smuzhiyun 	status = myrb_get_rbld_progress(cb, &rbld_buf);
2073*4882a593Smuzhiyun 	if (start) {
2074*4882a593Smuzhiyun 		if (status == MYRB_STATUS_SUCCESS) {
2075*4882a593Smuzhiyun 			sdev_printk(KERN_INFO, sdev,
2076*4882a593Smuzhiyun 				    "Check Consistency Not Initiated; already in progress\n");
2077*4882a593Smuzhiyun 			return -EALREADY;
2078*4882a593Smuzhiyun 		}
2079*4882a593Smuzhiyun 		mutex_lock(&cb->dcmd_mutex);
2080*4882a593Smuzhiyun 		cmd_blk = &cb->dcmd_blk;
2081*4882a593Smuzhiyun 		myrb_reset_cmd(cmd_blk);
2082*4882a593Smuzhiyun 		mbox = &cmd_blk->mbox;
2083*4882a593Smuzhiyun 		mbox->type3C.opcode = MYRB_CMD_CHECK_CONSISTENCY_ASYNC;
2084*4882a593Smuzhiyun 		mbox->type3C.id = MYRB_DCMD_TAG;
2085*4882a593Smuzhiyun 		mbox->type3C.ldev_num = sdev->id;
2086*4882a593Smuzhiyun 		mbox->type3C.auto_restore = true;
2087*4882a593Smuzhiyun 
2088*4882a593Smuzhiyun 		status = myrb_exec_cmd(cb, cmd_blk);
2089*4882a593Smuzhiyun 		mutex_unlock(&cb->dcmd_mutex);
2090*4882a593Smuzhiyun 	} else {
2091*4882a593Smuzhiyun 		struct pci_dev *pdev = cb->pdev;
2092*4882a593Smuzhiyun 		unsigned char *rate;
2093*4882a593Smuzhiyun 		dma_addr_t rate_addr;
2094*4882a593Smuzhiyun 
2095*4882a593Smuzhiyun 		if (ldev_num != sdev->id) {
2096*4882a593Smuzhiyun 			sdev_printk(KERN_INFO, sdev,
2097*4882a593Smuzhiyun 				    "Check Consistency Not Cancelled; not in progress\n");
2098*4882a593Smuzhiyun 			return 0;
2099*4882a593Smuzhiyun 		}
2100*4882a593Smuzhiyun 		rate = dma_alloc_coherent(&pdev->dev, sizeof(char),
2101*4882a593Smuzhiyun 					  &rate_addr, GFP_KERNEL);
2102*4882a593Smuzhiyun 		if (rate == NULL) {
2103*4882a593Smuzhiyun 			sdev_printk(KERN_INFO, sdev,
2104*4882a593Smuzhiyun 				    "Cancellation of Check Consistency Failed - Out of Memory\n");
2105*4882a593Smuzhiyun 			return -ENOMEM;
2106*4882a593Smuzhiyun 		}
2107*4882a593Smuzhiyun 		mutex_lock(&cb->dcmd_mutex);
2108*4882a593Smuzhiyun 		cmd_blk = &cb->dcmd_blk;
2109*4882a593Smuzhiyun 		myrb_reset_cmd(cmd_blk);
2110*4882a593Smuzhiyun 		mbox = &cmd_blk->mbox;
2111*4882a593Smuzhiyun 		mbox->type3R.opcode = MYRB_CMD_REBUILD_CONTROL;
2112*4882a593Smuzhiyun 		mbox->type3R.id = MYRB_DCMD_TAG;
2113*4882a593Smuzhiyun 		mbox->type3R.rbld_rate = 0xFF;
2114*4882a593Smuzhiyun 		mbox->type3R.addr = rate_addr;
2115*4882a593Smuzhiyun 		status = myrb_exec_cmd(cb, cmd_blk);
2116*4882a593Smuzhiyun 		dma_free_coherent(&pdev->dev, sizeof(char), rate, rate_addr);
2117*4882a593Smuzhiyun 		mutex_unlock(&cb->dcmd_mutex);
2118*4882a593Smuzhiyun 	}
2119*4882a593Smuzhiyun 	if (status == MYRB_STATUS_SUCCESS) {
2120*4882a593Smuzhiyun 		sdev_printk(KERN_INFO, sdev, "Check Consistency %s\n",
2121*4882a593Smuzhiyun 			    start ? "Initiated" : "Cancelled");
2122*4882a593Smuzhiyun 		return count;
2123*4882a593Smuzhiyun 	}
2124*4882a593Smuzhiyun 	if (!start) {
2125*4882a593Smuzhiyun 		sdev_printk(KERN_INFO, sdev,
2126*4882a593Smuzhiyun 			    "Check Consistency Not Cancelled, status 0x%x\n",
2127*4882a593Smuzhiyun 			    status);
2128*4882a593Smuzhiyun 		return -EIO;
2129*4882a593Smuzhiyun 	}
2130*4882a593Smuzhiyun 
2131*4882a593Smuzhiyun 	switch (status) {
2132*4882a593Smuzhiyun 	case MYRB_STATUS_ATTEMPT_TO_RBLD_ONLINE_DRIVE:
2133*4882a593Smuzhiyun 		msg = "Dependent Physical Device is DEAD";
2134*4882a593Smuzhiyun 		break;
2135*4882a593Smuzhiyun 	case MYRB_STATUS_RBLD_NEW_DISK_FAILED:
2136*4882a593Smuzhiyun 		msg = "New Disk Failed During Rebuild";
2137*4882a593Smuzhiyun 		break;
2138*4882a593Smuzhiyun 	case MYRB_STATUS_INVALID_ADDRESS:
2139*4882a593Smuzhiyun 		msg = "Invalid or Nonredundant Logical Drive";
2140*4882a593Smuzhiyun 		break;
2141*4882a593Smuzhiyun 	case MYRB_STATUS_RBLD_OR_CHECK_INPROGRESS:
2142*4882a593Smuzhiyun 		msg = "Already in Progress";
2143*4882a593Smuzhiyun 		break;
2144*4882a593Smuzhiyun 	default:
2145*4882a593Smuzhiyun 		msg = NULL;
2146*4882a593Smuzhiyun 		break;
2147*4882a593Smuzhiyun 	}
2148*4882a593Smuzhiyun 	if (msg)
2149*4882a593Smuzhiyun 		sdev_printk(KERN_INFO, sdev,
2150*4882a593Smuzhiyun 			    "Check Consistency Failed - %s\n", msg);
2151*4882a593Smuzhiyun 	else
2152*4882a593Smuzhiyun 		sdev_printk(KERN_INFO, sdev,
2153*4882a593Smuzhiyun 			    "Check Consistency Failed, status 0x%x\n", status);
2154*4882a593Smuzhiyun 
2155*4882a593Smuzhiyun 	return -EIO;
2156*4882a593Smuzhiyun }
2157*4882a593Smuzhiyun 
consistency_check_show(struct device * dev,struct device_attribute * attr,char * buf)2158*4882a593Smuzhiyun static ssize_t consistency_check_show(struct device *dev,
2159*4882a593Smuzhiyun 		struct device_attribute *attr, char *buf)
2160*4882a593Smuzhiyun {
2161*4882a593Smuzhiyun 	return rebuild_show(dev, attr, buf);
2162*4882a593Smuzhiyun }
2163*4882a593Smuzhiyun static DEVICE_ATTR_RW(consistency_check);
2164*4882a593Smuzhiyun 
ctlr_num_show(struct device * dev,struct device_attribute * attr,char * buf)2165*4882a593Smuzhiyun static ssize_t ctlr_num_show(struct device *dev,
2166*4882a593Smuzhiyun 		struct device_attribute *attr, char *buf)
2167*4882a593Smuzhiyun {
2168*4882a593Smuzhiyun 	struct Scsi_Host *shost = class_to_shost(dev);
2169*4882a593Smuzhiyun 	struct myrb_hba *cb = shost_priv(shost);
2170*4882a593Smuzhiyun 
2171*4882a593Smuzhiyun 	return snprintf(buf, 20, "%u\n", cb->ctlr_num);
2172*4882a593Smuzhiyun }
2173*4882a593Smuzhiyun static DEVICE_ATTR_RO(ctlr_num);
2174*4882a593Smuzhiyun 
firmware_show(struct device * dev,struct device_attribute * attr,char * buf)2175*4882a593Smuzhiyun static ssize_t firmware_show(struct device *dev,
2176*4882a593Smuzhiyun 		struct device_attribute *attr, char *buf)
2177*4882a593Smuzhiyun {
2178*4882a593Smuzhiyun 	struct Scsi_Host *shost = class_to_shost(dev);
2179*4882a593Smuzhiyun 	struct myrb_hba *cb = shost_priv(shost);
2180*4882a593Smuzhiyun 
2181*4882a593Smuzhiyun 	return snprintf(buf, 16, "%s\n", cb->fw_version);
2182*4882a593Smuzhiyun }
2183*4882a593Smuzhiyun static DEVICE_ATTR_RO(firmware);
2184*4882a593Smuzhiyun 
model_show(struct device * dev,struct device_attribute * attr,char * buf)2185*4882a593Smuzhiyun static ssize_t model_show(struct device *dev,
2186*4882a593Smuzhiyun 		struct device_attribute *attr, char *buf)
2187*4882a593Smuzhiyun {
2188*4882a593Smuzhiyun 	struct Scsi_Host *shost = class_to_shost(dev);
2189*4882a593Smuzhiyun 	struct myrb_hba *cb = shost_priv(shost);
2190*4882a593Smuzhiyun 
2191*4882a593Smuzhiyun 	return snprintf(buf, 16, "%s\n", cb->model_name);
2192*4882a593Smuzhiyun }
2193*4882a593Smuzhiyun static DEVICE_ATTR_RO(model);
2194*4882a593Smuzhiyun 
flush_cache_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2195*4882a593Smuzhiyun static ssize_t flush_cache_store(struct device *dev,
2196*4882a593Smuzhiyun 		struct device_attribute *attr, const char *buf, size_t count)
2197*4882a593Smuzhiyun {
2198*4882a593Smuzhiyun 	struct Scsi_Host *shost = class_to_shost(dev);
2199*4882a593Smuzhiyun 	struct myrb_hba *cb = shost_priv(shost);
2200*4882a593Smuzhiyun 	unsigned short status;
2201*4882a593Smuzhiyun 
2202*4882a593Smuzhiyun 	status = myrb_exec_type3(cb, MYRB_CMD_FLUSH, 0);
2203*4882a593Smuzhiyun 	if (status == MYRB_STATUS_SUCCESS) {
2204*4882a593Smuzhiyun 		shost_printk(KERN_INFO, shost,
2205*4882a593Smuzhiyun 			     "Cache Flush Completed\n");
2206*4882a593Smuzhiyun 		return count;
2207*4882a593Smuzhiyun 	}
2208*4882a593Smuzhiyun 	shost_printk(KERN_INFO, shost,
2209*4882a593Smuzhiyun 		     "Cache Flush Failed, status %x\n", status);
2210*4882a593Smuzhiyun 	return -EIO;
2211*4882a593Smuzhiyun }
2212*4882a593Smuzhiyun static DEVICE_ATTR_WO(flush_cache);
2213*4882a593Smuzhiyun 
2214*4882a593Smuzhiyun static struct device_attribute *myrb_sdev_attrs[] = {
2215*4882a593Smuzhiyun 	&dev_attr_rebuild,
2216*4882a593Smuzhiyun 	&dev_attr_consistency_check,
2217*4882a593Smuzhiyun 	&dev_attr_raid_state,
2218*4882a593Smuzhiyun 	&dev_attr_raid_level,
2219*4882a593Smuzhiyun 	NULL,
2220*4882a593Smuzhiyun };
2221*4882a593Smuzhiyun 
2222*4882a593Smuzhiyun static struct device_attribute *myrb_shost_attrs[] = {
2223*4882a593Smuzhiyun 	&dev_attr_ctlr_num,
2224*4882a593Smuzhiyun 	&dev_attr_model,
2225*4882a593Smuzhiyun 	&dev_attr_firmware,
2226*4882a593Smuzhiyun 	&dev_attr_flush_cache,
2227*4882a593Smuzhiyun 	NULL,
2228*4882a593Smuzhiyun };
2229*4882a593Smuzhiyun 
2230*4882a593Smuzhiyun static struct scsi_host_template myrb_template = {
2231*4882a593Smuzhiyun 	.module			= THIS_MODULE,
2232*4882a593Smuzhiyun 	.name			= "DAC960",
2233*4882a593Smuzhiyun 	.proc_name		= "myrb",
2234*4882a593Smuzhiyun 	.queuecommand		= myrb_queuecommand,
2235*4882a593Smuzhiyun 	.eh_host_reset_handler	= myrb_host_reset,
2236*4882a593Smuzhiyun 	.slave_alloc		= myrb_slave_alloc,
2237*4882a593Smuzhiyun 	.slave_configure	= myrb_slave_configure,
2238*4882a593Smuzhiyun 	.slave_destroy		= myrb_slave_destroy,
2239*4882a593Smuzhiyun 	.bios_param		= myrb_biosparam,
2240*4882a593Smuzhiyun 	.cmd_size		= sizeof(struct myrb_cmdblk),
2241*4882a593Smuzhiyun 	.shost_attrs		= myrb_shost_attrs,
2242*4882a593Smuzhiyun 	.sdev_attrs		= myrb_sdev_attrs,
2243*4882a593Smuzhiyun 	.this_id		= -1,
2244*4882a593Smuzhiyun };
2245*4882a593Smuzhiyun 
2246*4882a593Smuzhiyun /**
2247*4882a593Smuzhiyun  * myrb_is_raid - return boolean indicating device is raid volume
2248*4882a593Smuzhiyun  * @dev the device struct object
2249*4882a593Smuzhiyun  */
myrb_is_raid(struct device * dev)2250*4882a593Smuzhiyun static int myrb_is_raid(struct device *dev)
2251*4882a593Smuzhiyun {
2252*4882a593Smuzhiyun 	struct scsi_device *sdev = to_scsi_device(dev);
2253*4882a593Smuzhiyun 
2254*4882a593Smuzhiyun 	return sdev->channel == myrb_logical_channel(sdev->host);
2255*4882a593Smuzhiyun }
2256*4882a593Smuzhiyun 
2257*4882a593Smuzhiyun /**
2258*4882a593Smuzhiyun  * myrb_get_resync - get raid volume resync percent complete
2259*4882a593Smuzhiyun  * @dev the device struct object
2260*4882a593Smuzhiyun  */
myrb_get_resync(struct device * dev)2261*4882a593Smuzhiyun static void myrb_get_resync(struct device *dev)
2262*4882a593Smuzhiyun {
2263*4882a593Smuzhiyun 	struct scsi_device *sdev = to_scsi_device(dev);
2264*4882a593Smuzhiyun 	struct myrb_hba *cb = shost_priv(sdev->host);
2265*4882a593Smuzhiyun 	struct myrb_rbld_progress rbld_buf;
2266*4882a593Smuzhiyun 	unsigned int percent_complete = 0;
2267*4882a593Smuzhiyun 	unsigned short status;
2268*4882a593Smuzhiyun 	unsigned int ldev_size = 0, remaining = 0;
2269*4882a593Smuzhiyun 
2270*4882a593Smuzhiyun 	if (sdev->channel < myrb_logical_channel(sdev->host))
2271*4882a593Smuzhiyun 		return;
2272*4882a593Smuzhiyun 	status = myrb_get_rbld_progress(cb, &rbld_buf);
2273*4882a593Smuzhiyun 	if (status == MYRB_STATUS_SUCCESS) {
2274*4882a593Smuzhiyun 		if (rbld_buf.ldev_num == sdev->id) {
2275*4882a593Smuzhiyun 			ldev_size = rbld_buf.ldev_size;
2276*4882a593Smuzhiyun 			remaining = rbld_buf.blocks_left;
2277*4882a593Smuzhiyun 		}
2278*4882a593Smuzhiyun 	}
2279*4882a593Smuzhiyun 	if (remaining && ldev_size)
2280*4882a593Smuzhiyun 		percent_complete = (ldev_size - remaining) * 100 / ldev_size;
2281*4882a593Smuzhiyun 	raid_set_resync(myrb_raid_template, dev, percent_complete);
2282*4882a593Smuzhiyun }
2283*4882a593Smuzhiyun 
2284*4882a593Smuzhiyun /**
2285*4882a593Smuzhiyun  * myrb_get_state - get raid volume status
2286*4882a593Smuzhiyun  * @dev the device struct object
2287*4882a593Smuzhiyun  */
myrb_get_state(struct device * dev)2288*4882a593Smuzhiyun static void myrb_get_state(struct device *dev)
2289*4882a593Smuzhiyun {
2290*4882a593Smuzhiyun 	struct scsi_device *sdev = to_scsi_device(dev);
2291*4882a593Smuzhiyun 	struct myrb_hba *cb = shost_priv(sdev->host);
2292*4882a593Smuzhiyun 	struct myrb_ldev_info *ldev_info = sdev->hostdata;
2293*4882a593Smuzhiyun 	enum raid_state state = RAID_STATE_UNKNOWN;
2294*4882a593Smuzhiyun 	unsigned short status;
2295*4882a593Smuzhiyun 
2296*4882a593Smuzhiyun 	if (sdev->channel < myrb_logical_channel(sdev->host) || !ldev_info)
2297*4882a593Smuzhiyun 		state = RAID_STATE_UNKNOWN;
2298*4882a593Smuzhiyun 	else {
2299*4882a593Smuzhiyun 		status = myrb_get_rbld_progress(cb, NULL);
2300*4882a593Smuzhiyun 		if (status == MYRB_STATUS_SUCCESS)
2301*4882a593Smuzhiyun 			state = RAID_STATE_RESYNCING;
2302*4882a593Smuzhiyun 		else {
2303*4882a593Smuzhiyun 			switch (ldev_info->state) {
2304*4882a593Smuzhiyun 			case MYRB_DEVICE_ONLINE:
2305*4882a593Smuzhiyun 				state = RAID_STATE_ACTIVE;
2306*4882a593Smuzhiyun 				break;
2307*4882a593Smuzhiyun 			case MYRB_DEVICE_WO:
2308*4882a593Smuzhiyun 			case MYRB_DEVICE_CRITICAL:
2309*4882a593Smuzhiyun 				state = RAID_STATE_DEGRADED;
2310*4882a593Smuzhiyun 				break;
2311*4882a593Smuzhiyun 			default:
2312*4882a593Smuzhiyun 				state = RAID_STATE_OFFLINE;
2313*4882a593Smuzhiyun 			}
2314*4882a593Smuzhiyun 		}
2315*4882a593Smuzhiyun 	}
2316*4882a593Smuzhiyun 	raid_set_state(myrb_raid_template, dev, state);
2317*4882a593Smuzhiyun }
2318*4882a593Smuzhiyun 
2319*4882a593Smuzhiyun static struct raid_function_template myrb_raid_functions = {
2320*4882a593Smuzhiyun 	.cookie		= &myrb_template,
2321*4882a593Smuzhiyun 	.is_raid	= myrb_is_raid,
2322*4882a593Smuzhiyun 	.get_resync	= myrb_get_resync,
2323*4882a593Smuzhiyun 	.get_state	= myrb_get_state,
2324*4882a593Smuzhiyun };
2325*4882a593Smuzhiyun 
myrb_handle_scsi(struct myrb_hba * cb,struct myrb_cmdblk * cmd_blk,struct scsi_cmnd * scmd)2326*4882a593Smuzhiyun static void myrb_handle_scsi(struct myrb_hba *cb, struct myrb_cmdblk *cmd_blk,
2327*4882a593Smuzhiyun 		struct scsi_cmnd *scmd)
2328*4882a593Smuzhiyun {
2329*4882a593Smuzhiyun 	unsigned short status;
2330*4882a593Smuzhiyun 
2331*4882a593Smuzhiyun 	if (!cmd_blk)
2332*4882a593Smuzhiyun 		return;
2333*4882a593Smuzhiyun 
2334*4882a593Smuzhiyun 	scsi_dma_unmap(scmd);
2335*4882a593Smuzhiyun 
2336*4882a593Smuzhiyun 	if (cmd_blk->dcdb) {
2337*4882a593Smuzhiyun 		memcpy(scmd->sense_buffer, &cmd_blk->dcdb->sense, 64);
2338*4882a593Smuzhiyun 		dma_pool_free(cb->dcdb_pool, cmd_blk->dcdb,
2339*4882a593Smuzhiyun 			      cmd_blk->dcdb_addr);
2340*4882a593Smuzhiyun 		cmd_blk->dcdb = NULL;
2341*4882a593Smuzhiyun 	}
2342*4882a593Smuzhiyun 	if (cmd_blk->sgl) {
2343*4882a593Smuzhiyun 		dma_pool_free(cb->sg_pool, cmd_blk->sgl, cmd_blk->sgl_addr);
2344*4882a593Smuzhiyun 		cmd_blk->sgl = NULL;
2345*4882a593Smuzhiyun 		cmd_blk->sgl_addr = 0;
2346*4882a593Smuzhiyun 	}
2347*4882a593Smuzhiyun 	status = cmd_blk->status;
2348*4882a593Smuzhiyun 	switch (status) {
2349*4882a593Smuzhiyun 	case MYRB_STATUS_SUCCESS:
2350*4882a593Smuzhiyun 	case MYRB_STATUS_DEVICE_BUSY:
2351*4882a593Smuzhiyun 		scmd->result = (DID_OK << 16) | status;
2352*4882a593Smuzhiyun 		break;
2353*4882a593Smuzhiyun 	case MYRB_STATUS_BAD_DATA:
2354*4882a593Smuzhiyun 		dev_dbg(&scmd->device->sdev_gendev,
2355*4882a593Smuzhiyun 			"Bad Data Encountered\n");
2356*4882a593Smuzhiyun 		if (scmd->sc_data_direction == DMA_FROM_DEVICE)
2357*4882a593Smuzhiyun 			/* Unrecovered read error */
2358*4882a593Smuzhiyun 			scsi_build_sense_buffer(0, scmd->sense_buffer,
2359*4882a593Smuzhiyun 						MEDIUM_ERROR, 0x11, 0);
2360*4882a593Smuzhiyun 		else
2361*4882a593Smuzhiyun 			/* Write error */
2362*4882a593Smuzhiyun 			scsi_build_sense_buffer(0, scmd->sense_buffer,
2363*4882a593Smuzhiyun 						MEDIUM_ERROR, 0x0C, 0);
2364*4882a593Smuzhiyun 		scmd->result = (DID_OK << 16) | SAM_STAT_CHECK_CONDITION;
2365*4882a593Smuzhiyun 		break;
2366*4882a593Smuzhiyun 	case MYRB_STATUS_IRRECOVERABLE_DATA_ERROR:
2367*4882a593Smuzhiyun 		scmd_printk(KERN_ERR, scmd, "Irrecoverable Data Error\n");
2368*4882a593Smuzhiyun 		if (scmd->sc_data_direction == DMA_FROM_DEVICE)
2369*4882a593Smuzhiyun 			/* Unrecovered read error, auto-reallocation failed */
2370*4882a593Smuzhiyun 			scsi_build_sense_buffer(0, scmd->sense_buffer,
2371*4882a593Smuzhiyun 						MEDIUM_ERROR, 0x11, 0x04);
2372*4882a593Smuzhiyun 		else
2373*4882a593Smuzhiyun 			/* Write error, auto-reallocation failed */
2374*4882a593Smuzhiyun 			scsi_build_sense_buffer(0, scmd->sense_buffer,
2375*4882a593Smuzhiyun 						MEDIUM_ERROR, 0x0C, 0x02);
2376*4882a593Smuzhiyun 		scmd->result = (DID_OK << 16) | SAM_STAT_CHECK_CONDITION;
2377*4882a593Smuzhiyun 		break;
2378*4882a593Smuzhiyun 	case MYRB_STATUS_LDRV_NONEXISTENT_OR_OFFLINE:
2379*4882a593Smuzhiyun 		dev_dbg(&scmd->device->sdev_gendev,
2380*4882a593Smuzhiyun 			    "Logical Drive Nonexistent or Offline");
2381*4882a593Smuzhiyun 		scmd->result = (DID_BAD_TARGET << 16);
2382*4882a593Smuzhiyun 		break;
2383*4882a593Smuzhiyun 	case MYRB_STATUS_ACCESS_BEYOND_END_OF_LDRV:
2384*4882a593Smuzhiyun 		dev_dbg(&scmd->device->sdev_gendev,
2385*4882a593Smuzhiyun 			    "Attempt to Access Beyond End of Logical Drive");
2386*4882a593Smuzhiyun 		/* Logical block address out of range */
2387*4882a593Smuzhiyun 		scsi_build_sense_buffer(0, scmd->sense_buffer,
2388*4882a593Smuzhiyun 					NOT_READY, 0x21, 0);
2389*4882a593Smuzhiyun 		break;
2390*4882a593Smuzhiyun 	case MYRB_STATUS_DEVICE_NONRESPONSIVE:
2391*4882a593Smuzhiyun 		dev_dbg(&scmd->device->sdev_gendev, "Device nonresponsive\n");
2392*4882a593Smuzhiyun 		scmd->result = (DID_BAD_TARGET << 16);
2393*4882a593Smuzhiyun 		break;
2394*4882a593Smuzhiyun 	default:
2395*4882a593Smuzhiyun 		scmd_printk(KERN_ERR, scmd,
2396*4882a593Smuzhiyun 			    "Unexpected Error Status %04X", status);
2397*4882a593Smuzhiyun 		scmd->result = (DID_ERROR << 16);
2398*4882a593Smuzhiyun 		break;
2399*4882a593Smuzhiyun 	}
2400*4882a593Smuzhiyun 	scmd->scsi_done(scmd);
2401*4882a593Smuzhiyun }
2402*4882a593Smuzhiyun 
myrb_handle_cmdblk(struct myrb_hba * cb,struct myrb_cmdblk * cmd_blk)2403*4882a593Smuzhiyun static void myrb_handle_cmdblk(struct myrb_hba *cb, struct myrb_cmdblk *cmd_blk)
2404*4882a593Smuzhiyun {
2405*4882a593Smuzhiyun 	if (!cmd_blk)
2406*4882a593Smuzhiyun 		return;
2407*4882a593Smuzhiyun 
2408*4882a593Smuzhiyun 	if (cmd_blk->completion) {
2409*4882a593Smuzhiyun 		complete(cmd_blk->completion);
2410*4882a593Smuzhiyun 		cmd_blk->completion = NULL;
2411*4882a593Smuzhiyun 	}
2412*4882a593Smuzhiyun }
2413*4882a593Smuzhiyun 
myrb_monitor(struct work_struct * work)2414*4882a593Smuzhiyun static void myrb_monitor(struct work_struct *work)
2415*4882a593Smuzhiyun {
2416*4882a593Smuzhiyun 	struct myrb_hba *cb = container_of(work,
2417*4882a593Smuzhiyun 			struct myrb_hba, monitor_work.work);
2418*4882a593Smuzhiyun 	struct Scsi_Host *shost = cb->host;
2419*4882a593Smuzhiyun 	unsigned long interval = MYRB_PRIMARY_MONITOR_INTERVAL;
2420*4882a593Smuzhiyun 
2421*4882a593Smuzhiyun 	dev_dbg(&shost->shost_gendev, "monitor tick\n");
2422*4882a593Smuzhiyun 
2423*4882a593Smuzhiyun 	if (cb->new_ev_seq > cb->old_ev_seq) {
2424*4882a593Smuzhiyun 		int event = cb->old_ev_seq;
2425*4882a593Smuzhiyun 
2426*4882a593Smuzhiyun 		dev_dbg(&shost->shost_gendev,
2427*4882a593Smuzhiyun 			"get event log no %d/%d\n",
2428*4882a593Smuzhiyun 			cb->new_ev_seq, event);
2429*4882a593Smuzhiyun 		myrb_get_event(cb, event);
2430*4882a593Smuzhiyun 		cb->old_ev_seq = event + 1;
2431*4882a593Smuzhiyun 		interval = 10;
2432*4882a593Smuzhiyun 	} else if (cb->need_err_info) {
2433*4882a593Smuzhiyun 		cb->need_err_info = false;
2434*4882a593Smuzhiyun 		dev_dbg(&shost->shost_gendev, "get error table\n");
2435*4882a593Smuzhiyun 		myrb_get_errtable(cb);
2436*4882a593Smuzhiyun 		interval = 10;
2437*4882a593Smuzhiyun 	} else if (cb->need_rbld && cb->rbld_first) {
2438*4882a593Smuzhiyun 		cb->need_rbld = false;
2439*4882a593Smuzhiyun 		dev_dbg(&shost->shost_gendev,
2440*4882a593Smuzhiyun 			"get rebuild progress\n");
2441*4882a593Smuzhiyun 		myrb_update_rbld_progress(cb);
2442*4882a593Smuzhiyun 		interval = 10;
2443*4882a593Smuzhiyun 	} else if (cb->need_ldev_info) {
2444*4882a593Smuzhiyun 		cb->need_ldev_info = false;
2445*4882a593Smuzhiyun 		dev_dbg(&shost->shost_gendev,
2446*4882a593Smuzhiyun 			"get logical drive info\n");
2447*4882a593Smuzhiyun 		myrb_get_ldev_info(cb);
2448*4882a593Smuzhiyun 		interval = 10;
2449*4882a593Smuzhiyun 	} else if (cb->need_rbld) {
2450*4882a593Smuzhiyun 		cb->need_rbld = false;
2451*4882a593Smuzhiyun 		dev_dbg(&shost->shost_gendev,
2452*4882a593Smuzhiyun 			"get rebuild progress\n");
2453*4882a593Smuzhiyun 		myrb_update_rbld_progress(cb);
2454*4882a593Smuzhiyun 		interval = 10;
2455*4882a593Smuzhiyun 	} else if (cb->need_cc_status) {
2456*4882a593Smuzhiyun 		cb->need_cc_status = false;
2457*4882a593Smuzhiyun 		dev_dbg(&shost->shost_gendev,
2458*4882a593Smuzhiyun 			"get consistency check progress\n");
2459*4882a593Smuzhiyun 		myrb_get_cc_progress(cb);
2460*4882a593Smuzhiyun 		interval = 10;
2461*4882a593Smuzhiyun 	} else if (cb->need_bgi_status) {
2462*4882a593Smuzhiyun 		cb->need_bgi_status = false;
2463*4882a593Smuzhiyun 		dev_dbg(&shost->shost_gendev, "get background init status\n");
2464*4882a593Smuzhiyun 		myrb_bgi_control(cb);
2465*4882a593Smuzhiyun 		interval = 10;
2466*4882a593Smuzhiyun 	} else {
2467*4882a593Smuzhiyun 		dev_dbg(&shost->shost_gendev, "new enquiry\n");
2468*4882a593Smuzhiyun 		mutex_lock(&cb->dma_mutex);
2469*4882a593Smuzhiyun 		myrb_hba_enquiry(cb);
2470*4882a593Smuzhiyun 		mutex_unlock(&cb->dma_mutex);
2471*4882a593Smuzhiyun 		if ((cb->new_ev_seq - cb->old_ev_seq > 0) ||
2472*4882a593Smuzhiyun 		    cb->need_err_info || cb->need_rbld ||
2473*4882a593Smuzhiyun 		    cb->need_ldev_info || cb->need_cc_status ||
2474*4882a593Smuzhiyun 		    cb->need_bgi_status) {
2475*4882a593Smuzhiyun 			dev_dbg(&shost->shost_gendev,
2476*4882a593Smuzhiyun 				"reschedule monitor\n");
2477*4882a593Smuzhiyun 			interval = 0;
2478*4882a593Smuzhiyun 		}
2479*4882a593Smuzhiyun 	}
2480*4882a593Smuzhiyun 	if (interval > 1)
2481*4882a593Smuzhiyun 		cb->primary_monitor_time = jiffies;
2482*4882a593Smuzhiyun 	queue_delayed_work(cb->work_q, &cb->monitor_work, interval);
2483*4882a593Smuzhiyun }
2484*4882a593Smuzhiyun 
2485*4882a593Smuzhiyun /**
2486*4882a593Smuzhiyun  * myrb_err_status - reports controller BIOS messages
2487*4882a593Smuzhiyun  *
2488*4882a593Smuzhiyun  * Controller BIOS messages are passed through the Error Status Register
2489*4882a593Smuzhiyun  * when the driver performs the BIOS handshaking.
2490*4882a593Smuzhiyun  *
2491*4882a593Smuzhiyun  * Return: true for fatal errors and false otherwise.
2492*4882a593Smuzhiyun  */
myrb_err_status(struct myrb_hba * cb,unsigned char error,unsigned char parm0,unsigned char parm1)2493*4882a593Smuzhiyun static bool myrb_err_status(struct myrb_hba *cb, unsigned char error,
2494*4882a593Smuzhiyun 		unsigned char parm0, unsigned char parm1)
2495*4882a593Smuzhiyun {
2496*4882a593Smuzhiyun 	struct pci_dev *pdev = cb->pdev;
2497*4882a593Smuzhiyun 
2498*4882a593Smuzhiyun 	switch (error) {
2499*4882a593Smuzhiyun 	case 0x00:
2500*4882a593Smuzhiyun 		dev_info(&pdev->dev,
2501*4882a593Smuzhiyun 			 "Physical Device %d:%d Not Responding\n",
2502*4882a593Smuzhiyun 			 parm1, parm0);
2503*4882a593Smuzhiyun 		break;
2504*4882a593Smuzhiyun 	case 0x08:
2505*4882a593Smuzhiyun 		dev_notice(&pdev->dev, "Spinning Up Drives\n");
2506*4882a593Smuzhiyun 		break;
2507*4882a593Smuzhiyun 	case 0x30:
2508*4882a593Smuzhiyun 		dev_notice(&pdev->dev, "Configuration Checksum Error\n");
2509*4882a593Smuzhiyun 		break;
2510*4882a593Smuzhiyun 	case 0x60:
2511*4882a593Smuzhiyun 		dev_notice(&pdev->dev, "Mirror Race Recovery Failed\n");
2512*4882a593Smuzhiyun 		break;
2513*4882a593Smuzhiyun 	case 0x70:
2514*4882a593Smuzhiyun 		dev_notice(&pdev->dev, "Mirror Race Recovery In Progress\n");
2515*4882a593Smuzhiyun 		break;
2516*4882a593Smuzhiyun 	case 0x90:
2517*4882a593Smuzhiyun 		dev_notice(&pdev->dev, "Physical Device %d:%d COD Mismatch\n",
2518*4882a593Smuzhiyun 			   parm1, parm0);
2519*4882a593Smuzhiyun 		break;
2520*4882a593Smuzhiyun 	case 0xA0:
2521*4882a593Smuzhiyun 		dev_notice(&pdev->dev, "Logical Drive Installation Aborted\n");
2522*4882a593Smuzhiyun 		break;
2523*4882a593Smuzhiyun 	case 0xB0:
2524*4882a593Smuzhiyun 		dev_notice(&pdev->dev, "Mirror Race On A Critical Logical Drive\n");
2525*4882a593Smuzhiyun 		break;
2526*4882a593Smuzhiyun 	case 0xD0:
2527*4882a593Smuzhiyun 		dev_notice(&pdev->dev, "New Controller Configuration Found\n");
2528*4882a593Smuzhiyun 		break;
2529*4882a593Smuzhiyun 	case 0xF0:
2530*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Fatal Memory Parity Error\n");
2531*4882a593Smuzhiyun 		return true;
2532*4882a593Smuzhiyun 	default:
2533*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Unknown Initialization Error %02X\n",
2534*4882a593Smuzhiyun 			error);
2535*4882a593Smuzhiyun 		return true;
2536*4882a593Smuzhiyun 	}
2537*4882a593Smuzhiyun 	return false;
2538*4882a593Smuzhiyun }
2539*4882a593Smuzhiyun 
2540*4882a593Smuzhiyun /*
2541*4882a593Smuzhiyun  * Hardware-specific functions
2542*4882a593Smuzhiyun  */
2543*4882a593Smuzhiyun 
2544*4882a593Smuzhiyun /*
2545*4882a593Smuzhiyun  * DAC960 LA Series Controllers
2546*4882a593Smuzhiyun  */
2547*4882a593Smuzhiyun 
DAC960_LA_hw_mbox_new_cmd(void __iomem * base)2548*4882a593Smuzhiyun static inline void DAC960_LA_hw_mbox_new_cmd(void __iomem *base)
2549*4882a593Smuzhiyun {
2550*4882a593Smuzhiyun 	writeb(DAC960_LA_IDB_HWMBOX_NEW_CMD, base + DAC960_LA_IDB_OFFSET);
2551*4882a593Smuzhiyun }
2552*4882a593Smuzhiyun 
DAC960_LA_ack_hw_mbox_status(void __iomem * base)2553*4882a593Smuzhiyun static inline void DAC960_LA_ack_hw_mbox_status(void __iomem *base)
2554*4882a593Smuzhiyun {
2555*4882a593Smuzhiyun 	writeb(DAC960_LA_IDB_HWMBOX_ACK_STS, base + DAC960_LA_IDB_OFFSET);
2556*4882a593Smuzhiyun }
2557*4882a593Smuzhiyun 
DAC960_LA_gen_intr(void __iomem * base)2558*4882a593Smuzhiyun static inline void DAC960_LA_gen_intr(void __iomem *base)
2559*4882a593Smuzhiyun {
2560*4882a593Smuzhiyun 	writeb(DAC960_LA_IDB_GEN_IRQ, base + DAC960_LA_IDB_OFFSET);
2561*4882a593Smuzhiyun }
2562*4882a593Smuzhiyun 
DAC960_LA_reset_ctrl(void __iomem * base)2563*4882a593Smuzhiyun static inline void DAC960_LA_reset_ctrl(void __iomem *base)
2564*4882a593Smuzhiyun {
2565*4882a593Smuzhiyun 	writeb(DAC960_LA_IDB_CTRL_RESET, base + DAC960_LA_IDB_OFFSET);
2566*4882a593Smuzhiyun }
2567*4882a593Smuzhiyun 
DAC960_LA_mem_mbox_new_cmd(void __iomem * base)2568*4882a593Smuzhiyun static inline void DAC960_LA_mem_mbox_new_cmd(void __iomem *base)
2569*4882a593Smuzhiyun {
2570*4882a593Smuzhiyun 	writeb(DAC960_LA_IDB_MMBOX_NEW_CMD, base + DAC960_LA_IDB_OFFSET);
2571*4882a593Smuzhiyun }
2572*4882a593Smuzhiyun 
DAC960_LA_hw_mbox_is_full(void __iomem * base)2573*4882a593Smuzhiyun static inline bool DAC960_LA_hw_mbox_is_full(void __iomem *base)
2574*4882a593Smuzhiyun {
2575*4882a593Smuzhiyun 	unsigned char idb = readb(base + DAC960_LA_IDB_OFFSET);
2576*4882a593Smuzhiyun 
2577*4882a593Smuzhiyun 	return !(idb & DAC960_LA_IDB_HWMBOX_EMPTY);
2578*4882a593Smuzhiyun }
2579*4882a593Smuzhiyun 
DAC960_LA_init_in_progress(void __iomem * base)2580*4882a593Smuzhiyun static inline bool DAC960_LA_init_in_progress(void __iomem *base)
2581*4882a593Smuzhiyun {
2582*4882a593Smuzhiyun 	unsigned char idb = readb(base + DAC960_LA_IDB_OFFSET);
2583*4882a593Smuzhiyun 
2584*4882a593Smuzhiyun 	return !(idb & DAC960_LA_IDB_INIT_DONE);
2585*4882a593Smuzhiyun }
2586*4882a593Smuzhiyun 
DAC960_LA_ack_hw_mbox_intr(void __iomem * base)2587*4882a593Smuzhiyun static inline void DAC960_LA_ack_hw_mbox_intr(void __iomem *base)
2588*4882a593Smuzhiyun {
2589*4882a593Smuzhiyun 	writeb(DAC960_LA_ODB_HWMBOX_ACK_IRQ, base + DAC960_LA_ODB_OFFSET);
2590*4882a593Smuzhiyun }
2591*4882a593Smuzhiyun 
DAC960_LA_ack_mem_mbox_intr(void __iomem * base)2592*4882a593Smuzhiyun static inline void DAC960_LA_ack_mem_mbox_intr(void __iomem *base)
2593*4882a593Smuzhiyun {
2594*4882a593Smuzhiyun 	writeb(DAC960_LA_ODB_MMBOX_ACK_IRQ, base + DAC960_LA_ODB_OFFSET);
2595*4882a593Smuzhiyun }
2596*4882a593Smuzhiyun 
DAC960_LA_ack_intr(void __iomem * base)2597*4882a593Smuzhiyun static inline void DAC960_LA_ack_intr(void __iomem *base)
2598*4882a593Smuzhiyun {
2599*4882a593Smuzhiyun 	writeb(DAC960_LA_ODB_HWMBOX_ACK_IRQ | DAC960_LA_ODB_MMBOX_ACK_IRQ,
2600*4882a593Smuzhiyun 	       base + DAC960_LA_ODB_OFFSET);
2601*4882a593Smuzhiyun }
2602*4882a593Smuzhiyun 
DAC960_LA_hw_mbox_status_available(void __iomem * base)2603*4882a593Smuzhiyun static inline bool DAC960_LA_hw_mbox_status_available(void __iomem *base)
2604*4882a593Smuzhiyun {
2605*4882a593Smuzhiyun 	unsigned char odb = readb(base + DAC960_LA_ODB_OFFSET);
2606*4882a593Smuzhiyun 
2607*4882a593Smuzhiyun 	return odb & DAC960_LA_ODB_HWMBOX_STS_AVAIL;
2608*4882a593Smuzhiyun }
2609*4882a593Smuzhiyun 
DAC960_LA_mem_mbox_status_available(void __iomem * base)2610*4882a593Smuzhiyun static inline bool DAC960_LA_mem_mbox_status_available(void __iomem *base)
2611*4882a593Smuzhiyun {
2612*4882a593Smuzhiyun 	unsigned char odb = readb(base + DAC960_LA_ODB_OFFSET);
2613*4882a593Smuzhiyun 
2614*4882a593Smuzhiyun 	return odb & DAC960_LA_ODB_MMBOX_STS_AVAIL;
2615*4882a593Smuzhiyun }
2616*4882a593Smuzhiyun 
DAC960_LA_enable_intr(void __iomem * base)2617*4882a593Smuzhiyun static inline void DAC960_LA_enable_intr(void __iomem *base)
2618*4882a593Smuzhiyun {
2619*4882a593Smuzhiyun 	unsigned char odb = 0xFF;
2620*4882a593Smuzhiyun 
2621*4882a593Smuzhiyun 	odb &= ~DAC960_LA_IRQMASK_DISABLE_IRQ;
2622*4882a593Smuzhiyun 	writeb(odb, base + DAC960_LA_IRQMASK_OFFSET);
2623*4882a593Smuzhiyun }
2624*4882a593Smuzhiyun 
DAC960_LA_disable_intr(void __iomem * base)2625*4882a593Smuzhiyun static inline void DAC960_LA_disable_intr(void __iomem *base)
2626*4882a593Smuzhiyun {
2627*4882a593Smuzhiyun 	unsigned char odb = 0xFF;
2628*4882a593Smuzhiyun 
2629*4882a593Smuzhiyun 	odb |= DAC960_LA_IRQMASK_DISABLE_IRQ;
2630*4882a593Smuzhiyun 	writeb(odb, base + DAC960_LA_IRQMASK_OFFSET);
2631*4882a593Smuzhiyun }
2632*4882a593Smuzhiyun 
DAC960_LA_intr_enabled(void __iomem * base)2633*4882a593Smuzhiyun static inline bool DAC960_LA_intr_enabled(void __iomem *base)
2634*4882a593Smuzhiyun {
2635*4882a593Smuzhiyun 	unsigned char imask = readb(base + DAC960_LA_IRQMASK_OFFSET);
2636*4882a593Smuzhiyun 
2637*4882a593Smuzhiyun 	return !(imask & DAC960_LA_IRQMASK_DISABLE_IRQ);
2638*4882a593Smuzhiyun }
2639*4882a593Smuzhiyun 
DAC960_LA_write_cmd_mbox(union myrb_cmd_mbox * mem_mbox,union myrb_cmd_mbox * mbox)2640*4882a593Smuzhiyun static inline void DAC960_LA_write_cmd_mbox(union myrb_cmd_mbox *mem_mbox,
2641*4882a593Smuzhiyun 		union myrb_cmd_mbox *mbox)
2642*4882a593Smuzhiyun {
2643*4882a593Smuzhiyun 	mem_mbox->words[1] = mbox->words[1];
2644*4882a593Smuzhiyun 	mem_mbox->words[2] = mbox->words[2];
2645*4882a593Smuzhiyun 	mem_mbox->words[3] = mbox->words[3];
2646*4882a593Smuzhiyun 	/* Memory barrier to prevent reordering */
2647*4882a593Smuzhiyun 	wmb();
2648*4882a593Smuzhiyun 	mem_mbox->words[0] = mbox->words[0];
2649*4882a593Smuzhiyun 	/* Memory barrier to force PCI access */
2650*4882a593Smuzhiyun 	mb();
2651*4882a593Smuzhiyun }
2652*4882a593Smuzhiyun 
DAC960_LA_write_hw_mbox(void __iomem * base,union myrb_cmd_mbox * mbox)2653*4882a593Smuzhiyun static inline void DAC960_LA_write_hw_mbox(void __iomem *base,
2654*4882a593Smuzhiyun 		union myrb_cmd_mbox *mbox)
2655*4882a593Smuzhiyun {
2656*4882a593Smuzhiyun 	writel(mbox->words[0], base + DAC960_LA_CMDOP_OFFSET);
2657*4882a593Smuzhiyun 	writel(mbox->words[1], base + DAC960_LA_MBOX4_OFFSET);
2658*4882a593Smuzhiyun 	writel(mbox->words[2], base + DAC960_LA_MBOX8_OFFSET);
2659*4882a593Smuzhiyun 	writeb(mbox->bytes[12], base + DAC960_LA_MBOX12_OFFSET);
2660*4882a593Smuzhiyun }
2661*4882a593Smuzhiyun 
DAC960_LA_read_status_cmd_ident(void __iomem * base)2662*4882a593Smuzhiyun static inline unsigned char DAC960_LA_read_status_cmd_ident(void __iomem *base)
2663*4882a593Smuzhiyun {
2664*4882a593Smuzhiyun 	return readb(base + DAC960_LA_STSID_OFFSET);
2665*4882a593Smuzhiyun }
2666*4882a593Smuzhiyun 
DAC960_LA_read_status(void __iomem * base)2667*4882a593Smuzhiyun static inline unsigned short DAC960_LA_read_status(void __iomem *base)
2668*4882a593Smuzhiyun {
2669*4882a593Smuzhiyun 	return readw(base + DAC960_LA_STS_OFFSET);
2670*4882a593Smuzhiyun }
2671*4882a593Smuzhiyun 
2672*4882a593Smuzhiyun static inline bool
DAC960_LA_read_error_status(void __iomem * base,unsigned char * error,unsigned char * param0,unsigned char * param1)2673*4882a593Smuzhiyun DAC960_LA_read_error_status(void __iomem *base, unsigned char *error,
2674*4882a593Smuzhiyun 		unsigned char *param0, unsigned char *param1)
2675*4882a593Smuzhiyun {
2676*4882a593Smuzhiyun 	unsigned char errsts = readb(base + DAC960_LA_ERRSTS_OFFSET);
2677*4882a593Smuzhiyun 
2678*4882a593Smuzhiyun 	if (!(errsts & DAC960_LA_ERRSTS_PENDING))
2679*4882a593Smuzhiyun 		return false;
2680*4882a593Smuzhiyun 	errsts &= ~DAC960_LA_ERRSTS_PENDING;
2681*4882a593Smuzhiyun 
2682*4882a593Smuzhiyun 	*error = errsts;
2683*4882a593Smuzhiyun 	*param0 = readb(base + DAC960_LA_CMDOP_OFFSET);
2684*4882a593Smuzhiyun 	*param1 = readb(base + DAC960_LA_CMDID_OFFSET);
2685*4882a593Smuzhiyun 	writeb(0xFF, base + DAC960_LA_ERRSTS_OFFSET);
2686*4882a593Smuzhiyun 	return true;
2687*4882a593Smuzhiyun }
2688*4882a593Smuzhiyun 
2689*4882a593Smuzhiyun static inline unsigned short
DAC960_LA_mbox_init(struct pci_dev * pdev,void __iomem * base,union myrb_cmd_mbox * mbox)2690*4882a593Smuzhiyun DAC960_LA_mbox_init(struct pci_dev *pdev, void __iomem *base,
2691*4882a593Smuzhiyun 		union myrb_cmd_mbox *mbox)
2692*4882a593Smuzhiyun {
2693*4882a593Smuzhiyun 	unsigned short status;
2694*4882a593Smuzhiyun 	int timeout = 0;
2695*4882a593Smuzhiyun 
2696*4882a593Smuzhiyun 	while (timeout < MYRB_MAILBOX_TIMEOUT) {
2697*4882a593Smuzhiyun 		if (!DAC960_LA_hw_mbox_is_full(base))
2698*4882a593Smuzhiyun 			break;
2699*4882a593Smuzhiyun 		udelay(10);
2700*4882a593Smuzhiyun 		timeout++;
2701*4882a593Smuzhiyun 	}
2702*4882a593Smuzhiyun 	if (DAC960_LA_hw_mbox_is_full(base)) {
2703*4882a593Smuzhiyun 		dev_err(&pdev->dev,
2704*4882a593Smuzhiyun 			"Timeout waiting for empty mailbox\n");
2705*4882a593Smuzhiyun 		return MYRB_STATUS_SUBSYS_TIMEOUT;
2706*4882a593Smuzhiyun 	}
2707*4882a593Smuzhiyun 	DAC960_LA_write_hw_mbox(base, mbox);
2708*4882a593Smuzhiyun 	DAC960_LA_hw_mbox_new_cmd(base);
2709*4882a593Smuzhiyun 	timeout = 0;
2710*4882a593Smuzhiyun 	while (timeout < MYRB_MAILBOX_TIMEOUT) {
2711*4882a593Smuzhiyun 		if (DAC960_LA_hw_mbox_status_available(base))
2712*4882a593Smuzhiyun 			break;
2713*4882a593Smuzhiyun 		udelay(10);
2714*4882a593Smuzhiyun 		timeout++;
2715*4882a593Smuzhiyun 	}
2716*4882a593Smuzhiyun 	if (!DAC960_LA_hw_mbox_status_available(base)) {
2717*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Timeout waiting for mailbox status\n");
2718*4882a593Smuzhiyun 		return MYRB_STATUS_SUBSYS_TIMEOUT;
2719*4882a593Smuzhiyun 	}
2720*4882a593Smuzhiyun 	status = DAC960_LA_read_status(base);
2721*4882a593Smuzhiyun 	DAC960_LA_ack_hw_mbox_intr(base);
2722*4882a593Smuzhiyun 	DAC960_LA_ack_hw_mbox_status(base);
2723*4882a593Smuzhiyun 
2724*4882a593Smuzhiyun 	return status;
2725*4882a593Smuzhiyun }
2726*4882a593Smuzhiyun 
DAC960_LA_hw_init(struct pci_dev * pdev,struct myrb_hba * cb,void __iomem * base)2727*4882a593Smuzhiyun static int DAC960_LA_hw_init(struct pci_dev *pdev,
2728*4882a593Smuzhiyun 		struct myrb_hba *cb, void __iomem *base)
2729*4882a593Smuzhiyun {
2730*4882a593Smuzhiyun 	int timeout = 0;
2731*4882a593Smuzhiyun 	unsigned char error, parm0, parm1;
2732*4882a593Smuzhiyun 
2733*4882a593Smuzhiyun 	DAC960_LA_disable_intr(base);
2734*4882a593Smuzhiyun 	DAC960_LA_ack_hw_mbox_status(base);
2735*4882a593Smuzhiyun 	udelay(1000);
2736*4882a593Smuzhiyun 	while (DAC960_LA_init_in_progress(base) &&
2737*4882a593Smuzhiyun 	       timeout < MYRB_MAILBOX_TIMEOUT) {
2738*4882a593Smuzhiyun 		if (DAC960_LA_read_error_status(base, &error,
2739*4882a593Smuzhiyun 					      &parm0, &parm1) &&
2740*4882a593Smuzhiyun 		    myrb_err_status(cb, error, parm0, parm1))
2741*4882a593Smuzhiyun 			return -ENODEV;
2742*4882a593Smuzhiyun 		udelay(10);
2743*4882a593Smuzhiyun 		timeout++;
2744*4882a593Smuzhiyun 	}
2745*4882a593Smuzhiyun 	if (timeout == MYRB_MAILBOX_TIMEOUT) {
2746*4882a593Smuzhiyun 		dev_err(&pdev->dev,
2747*4882a593Smuzhiyun 			"Timeout waiting for Controller Initialisation\n");
2748*4882a593Smuzhiyun 		return -ETIMEDOUT;
2749*4882a593Smuzhiyun 	}
2750*4882a593Smuzhiyun 	if (!myrb_enable_mmio(cb, DAC960_LA_mbox_init)) {
2751*4882a593Smuzhiyun 		dev_err(&pdev->dev,
2752*4882a593Smuzhiyun 			"Unable to Enable Memory Mailbox Interface\n");
2753*4882a593Smuzhiyun 		DAC960_LA_reset_ctrl(base);
2754*4882a593Smuzhiyun 		return -ENODEV;
2755*4882a593Smuzhiyun 	}
2756*4882a593Smuzhiyun 	DAC960_LA_enable_intr(base);
2757*4882a593Smuzhiyun 	cb->qcmd = myrb_qcmd;
2758*4882a593Smuzhiyun 	cb->write_cmd_mbox = DAC960_LA_write_cmd_mbox;
2759*4882a593Smuzhiyun 	if (cb->dual_mode_interface)
2760*4882a593Smuzhiyun 		cb->get_cmd_mbox = DAC960_LA_mem_mbox_new_cmd;
2761*4882a593Smuzhiyun 	else
2762*4882a593Smuzhiyun 		cb->get_cmd_mbox = DAC960_LA_hw_mbox_new_cmd;
2763*4882a593Smuzhiyun 	cb->disable_intr = DAC960_LA_disable_intr;
2764*4882a593Smuzhiyun 	cb->reset = DAC960_LA_reset_ctrl;
2765*4882a593Smuzhiyun 
2766*4882a593Smuzhiyun 	return 0;
2767*4882a593Smuzhiyun }
2768*4882a593Smuzhiyun 
DAC960_LA_intr_handler(int irq,void * arg)2769*4882a593Smuzhiyun static irqreturn_t DAC960_LA_intr_handler(int irq, void *arg)
2770*4882a593Smuzhiyun {
2771*4882a593Smuzhiyun 	struct myrb_hba *cb = arg;
2772*4882a593Smuzhiyun 	void __iomem *base = cb->io_base;
2773*4882a593Smuzhiyun 	struct myrb_stat_mbox *next_stat_mbox;
2774*4882a593Smuzhiyun 	unsigned long flags;
2775*4882a593Smuzhiyun 
2776*4882a593Smuzhiyun 	spin_lock_irqsave(&cb->queue_lock, flags);
2777*4882a593Smuzhiyun 	DAC960_LA_ack_intr(base);
2778*4882a593Smuzhiyun 	next_stat_mbox = cb->next_stat_mbox;
2779*4882a593Smuzhiyun 	while (next_stat_mbox->valid) {
2780*4882a593Smuzhiyun 		unsigned char id = next_stat_mbox->id;
2781*4882a593Smuzhiyun 		struct scsi_cmnd *scmd = NULL;
2782*4882a593Smuzhiyun 		struct myrb_cmdblk *cmd_blk = NULL;
2783*4882a593Smuzhiyun 
2784*4882a593Smuzhiyun 		if (id == MYRB_DCMD_TAG)
2785*4882a593Smuzhiyun 			cmd_blk = &cb->dcmd_blk;
2786*4882a593Smuzhiyun 		else if (id == MYRB_MCMD_TAG)
2787*4882a593Smuzhiyun 			cmd_blk = &cb->mcmd_blk;
2788*4882a593Smuzhiyun 		else {
2789*4882a593Smuzhiyun 			scmd = scsi_host_find_tag(cb->host, id - 3);
2790*4882a593Smuzhiyun 			if (scmd)
2791*4882a593Smuzhiyun 				cmd_blk = scsi_cmd_priv(scmd);
2792*4882a593Smuzhiyun 		}
2793*4882a593Smuzhiyun 		if (cmd_blk)
2794*4882a593Smuzhiyun 			cmd_blk->status = next_stat_mbox->status;
2795*4882a593Smuzhiyun 		else
2796*4882a593Smuzhiyun 			dev_err(&cb->pdev->dev,
2797*4882a593Smuzhiyun 				"Unhandled command completion %d\n", id);
2798*4882a593Smuzhiyun 
2799*4882a593Smuzhiyun 		memset(next_stat_mbox, 0, sizeof(struct myrb_stat_mbox));
2800*4882a593Smuzhiyun 		if (++next_stat_mbox > cb->last_stat_mbox)
2801*4882a593Smuzhiyun 			next_stat_mbox = cb->first_stat_mbox;
2802*4882a593Smuzhiyun 
2803*4882a593Smuzhiyun 		if (cmd_blk) {
2804*4882a593Smuzhiyun 			if (id < 3)
2805*4882a593Smuzhiyun 				myrb_handle_cmdblk(cb, cmd_blk);
2806*4882a593Smuzhiyun 			else
2807*4882a593Smuzhiyun 				myrb_handle_scsi(cb, cmd_blk, scmd);
2808*4882a593Smuzhiyun 		}
2809*4882a593Smuzhiyun 	}
2810*4882a593Smuzhiyun 	cb->next_stat_mbox = next_stat_mbox;
2811*4882a593Smuzhiyun 	spin_unlock_irqrestore(&cb->queue_lock, flags);
2812*4882a593Smuzhiyun 	return IRQ_HANDLED;
2813*4882a593Smuzhiyun }
2814*4882a593Smuzhiyun 
2815*4882a593Smuzhiyun struct myrb_privdata DAC960_LA_privdata = {
2816*4882a593Smuzhiyun 	.hw_init =	DAC960_LA_hw_init,
2817*4882a593Smuzhiyun 	.irq_handler =	DAC960_LA_intr_handler,
2818*4882a593Smuzhiyun 	.mmio_size =	DAC960_LA_mmio_size,
2819*4882a593Smuzhiyun };
2820*4882a593Smuzhiyun 
2821*4882a593Smuzhiyun /*
2822*4882a593Smuzhiyun  * DAC960 PG Series Controllers
2823*4882a593Smuzhiyun  */
DAC960_PG_hw_mbox_new_cmd(void __iomem * base)2824*4882a593Smuzhiyun static inline void DAC960_PG_hw_mbox_new_cmd(void __iomem *base)
2825*4882a593Smuzhiyun {
2826*4882a593Smuzhiyun 	writel(DAC960_PG_IDB_HWMBOX_NEW_CMD, base + DAC960_PG_IDB_OFFSET);
2827*4882a593Smuzhiyun }
2828*4882a593Smuzhiyun 
DAC960_PG_ack_hw_mbox_status(void __iomem * base)2829*4882a593Smuzhiyun static inline void DAC960_PG_ack_hw_mbox_status(void __iomem *base)
2830*4882a593Smuzhiyun {
2831*4882a593Smuzhiyun 	writel(DAC960_PG_IDB_HWMBOX_ACK_STS, base + DAC960_PG_IDB_OFFSET);
2832*4882a593Smuzhiyun }
2833*4882a593Smuzhiyun 
DAC960_PG_gen_intr(void __iomem * base)2834*4882a593Smuzhiyun static inline void DAC960_PG_gen_intr(void __iomem *base)
2835*4882a593Smuzhiyun {
2836*4882a593Smuzhiyun 	writel(DAC960_PG_IDB_GEN_IRQ, base + DAC960_PG_IDB_OFFSET);
2837*4882a593Smuzhiyun }
2838*4882a593Smuzhiyun 
DAC960_PG_reset_ctrl(void __iomem * base)2839*4882a593Smuzhiyun static inline void DAC960_PG_reset_ctrl(void __iomem *base)
2840*4882a593Smuzhiyun {
2841*4882a593Smuzhiyun 	writel(DAC960_PG_IDB_CTRL_RESET, base + DAC960_PG_IDB_OFFSET);
2842*4882a593Smuzhiyun }
2843*4882a593Smuzhiyun 
DAC960_PG_mem_mbox_new_cmd(void __iomem * base)2844*4882a593Smuzhiyun static inline void DAC960_PG_mem_mbox_new_cmd(void __iomem *base)
2845*4882a593Smuzhiyun {
2846*4882a593Smuzhiyun 	writel(DAC960_PG_IDB_MMBOX_NEW_CMD, base + DAC960_PG_IDB_OFFSET);
2847*4882a593Smuzhiyun }
2848*4882a593Smuzhiyun 
DAC960_PG_hw_mbox_is_full(void __iomem * base)2849*4882a593Smuzhiyun static inline bool DAC960_PG_hw_mbox_is_full(void __iomem *base)
2850*4882a593Smuzhiyun {
2851*4882a593Smuzhiyun 	unsigned char idb = readl(base + DAC960_PG_IDB_OFFSET);
2852*4882a593Smuzhiyun 
2853*4882a593Smuzhiyun 	return idb & DAC960_PG_IDB_HWMBOX_FULL;
2854*4882a593Smuzhiyun }
2855*4882a593Smuzhiyun 
DAC960_PG_init_in_progress(void __iomem * base)2856*4882a593Smuzhiyun static inline bool DAC960_PG_init_in_progress(void __iomem *base)
2857*4882a593Smuzhiyun {
2858*4882a593Smuzhiyun 	unsigned char idb = readl(base + DAC960_PG_IDB_OFFSET);
2859*4882a593Smuzhiyun 
2860*4882a593Smuzhiyun 	return idb & DAC960_PG_IDB_INIT_IN_PROGRESS;
2861*4882a593Smuzhiyun }
2862*4882a593Smuzhiyun 
DAC960_PG_ack_hw_mbox_intr(void __iomem * base)2863*4882a593Smuzhiyun static inline void DAC960_PG_ack_hw_mbox_intr(void __iomem *base)
2864*4882a593Smuzhiyun {
2865*4882a593Smuzhiyun 	writel(DAC960_PG_ODB_HWMBOX_ACK_IRQ, base + DAC960_PG_ODB_OFFSET);
2866*4882a593Smuzhiyun }
2867*4882a593Smuzhiyun 
DAC960_PG_ack_mem_mbox_intr(void __iomem * base)2868*4882a593Smuzhiyun static inline void DAC960_PG_ack_mem_mbox_intr(void __iomem *base)
2869*4882a593Smuzhiyun {
2870*4882a593Smuzhiyun 	writel(DAC960_PG_ODB_MMBOX_ACK_IRQ, base + DAC960_PG_ODB_OFFSET);
2871*4882a593Smuzhiyun }
2872*4882a593Smuzhiyun 
DAC960_PG_ack_intr(void __iomem * base)2873*4882a593Smuzhiyun static inline void DAC960_PG_ack_intr(void __iomem *base)
2874*4882a593Smuzhiyun {
2875*4882a593Smuzhiyun 	writel(DAC960_PG_ODB_HWMBOX_ACK_IRQ | DAC960_PG_ODB_MMBOX_ACK_IRQ,
2876*4882a593Smuzhiyun 	       base + DAC960_PG_ODB_OFFSET);
2877*4882a593Smuzhiyun }
2878*4882a593Smuzhiyun 
DAC960_PG_hw_mbox_status_available(void __iomem * base)2879*4882a593Smuzhiyun static inline bool DAC960_PG_hw_mbox_status_available(void __iomem *base)
2880*4882a593Smuzhiyun {
2881*4882a593Smuzhiyun 	unsigned char odb = readl(base + DAC960_PG_ODB_OFFSET);
2882*4882a593Smuzhiyun 
2883*4882a593Smuzhiyun 	return odb & DAC960_PG_ODB_HWMBOX_STS_AVAIL;
2884*4882a593Smuzhiyun }
2885*4882a593Smuzhiyun 
DAC960_PG_mem_mbox_status_available(void __iomem * base)2886*4882a593Smuzhiyun static inline bool DAC960_PG_mem_mbox_status_available(void __iomem *base)
2887*4882a593Smuzhiyun {
2888*4882a593Smuzhiyun 	unsigned char odb = readl(base + DAC960_PG_ODB_OFFSET);
2889*4882a593Smuzhiyun 
2890*4882a593Smuzhiyun 	return odb & DAC960_PG_ODB_MMBOX_STS_AVAIL;
2891*4882a593Smuzhiyun }
2892*4882a593Smuzhiyun 
DAC960_PG_enable_intr(void __iomem * base)2893*4882a593Smuzhiyun static inline void DAC960_PG_enable_intr(void __iomem *base)
2894*4882a593Smuzhiyun {
2895*4882a593Smuzhiyun 	unsigned int imask = (unsigned int)-1;
2896*4882a593Smuzhiyun 
2897*4882a593Smuzhiyun 	imask &= ~DAC960_PG_IRQMASK_DISABLE_IRQ;
2898*4882a593Smuzhiyun 	writel(imask, base + DAC960_PG_IRQMASK_OFFSET);
2899*4882a593Smuzhiyun }
2900*4882a593Smuzhiyun 
DAC960_PG_disable_intr(void __iomem * base)2901*4882a593Smuzhiyun static inline void DAC960_PG_disable_intr(void __iomem *base)
2902*4882a593Smuzhiyun {
2903*4882a593Smuzhiyun 	unsigned int imask = (unsigned int)-1;
2904*4882a593Smuzhiyun 
2905*4882a593Smuzhiyun 	writel(imask, base + DAC960_PG_IRQMASK_OFFSET);
2906*4882a593Smuzhiyun }
2907*4882a593Smuzhiyun 
DAC960_PG_intr_enabled(void __iomem * base)2908*4882a593Smuzhiyun static inline bool DAC960_PG_intr_enabled(void __iomem *base)
2909*4882a593Smuzhiyun {
2910*4882a593Smuzhiyun 	unsigned int imask = readl(base + DAC960_PG_IRQMASK_OFFSET);
2911*4882a593Smuzhiyun 
2912*4882a593Smuzhiyun 	return !(imask & DAC960_PG_IRQMASK_DISABLE_IRQ);
2913*4882a593Smuzhiyun }
2914*4882a593Smuzhiyun 
DAC960_PG_write_cmd_mbox(union myrb_cmd_mbox * mem_mbox,union myrb_cmd_mbox * mbox)2915*4882a593Smuzhiyun static inline void DAC960_PG_write_cmd_mbox(union myrb_cmd_mbox *mem_mbox,
2916*4882a593Smuzhiyun 		union myrb_cmd_mbox *mbox)
2917*4882a593Smuzhiyun {
2918*4882a593Smuzhiyun 	mem_mbox->words[1] = mbox->words[1];
2919*4882a593Smuzhiyun 	mem_mbox->words[2] = mbox->words[2];
2920*4882a593Smuzhiyun 	mem_mbox->words[3] = mbox->words[3];
2921*4882a593Smuzhiyun 	/* Memory barrier to prevent reordering */
2922*4882a593Smuzhiyun 	wmb();
2923*4882a593Smuzhiyun 	mem_mbox->words[0] = mbox->words[0];
2924*4882a593Smuzhiyun 	/* Memory barrier to force PCI access */
2925*4882a593Smuzhiyun 	mb();
2926*4882a593Smuzhiyun }
2927*4882a593Smuzhiyun 
DAC960_PG_write_hw_mbox(void __iomem * base,union myrb_cmd_mbox * mbox)2928*4882a593Smuzhiyun static inline void DAC960_PG_write_hw_mbox(void __iomem *base,
2929*4882a593Smuzhiyun 		union myrb_cmd_mbox *mbox)
2930*4882a593Smuzhiyun {
2931*4882a593Smuzhiyun 	writel(mbox->words[0], base + DAC960_PG_CMDOP_OFFSET);
2932*4882a593Smuzhiyun 	writel(mbox->words[1], base + DAC960_PG_MBOX4_OFFSET);
2933*4882a593Smuzhiyun 	writel(mbox->words[2], base + DAC960_PG_MBOX8_OFFSET);
2934*4882a593Smuzhiyun 	writeb(mbox->bytes[12], base + DAC960_PG_MBOX12_OFFSET);
2935*4882a593Smuzhiyun }
2936*4882a593Smuzhiyun 
2937*4882a593Smuzhiyun static inline unsigned char
DAC960_PG_read_status_cmd_ident(void __iomem * base)2938*4882a593Smuzhiyun DAC960_PG_read_status_cmd_ident(void __iomem *base)
2939*4882a593Smuzhiyun {
2940*4882a593Smuzhiyun 	return readb(base + DAC960_PG_STSID_OFFSET);
2941*4882a593Smuzhiyun }
2942*4882a593Smuzhiyun 
2943*4882a593Smuzhiyun static inline unsigned short
DAC960_PG_read_status(void __iomem * base)2944*4882a593Smuzhiyun DAC960_PG_read_status(void __iomem *base)
2945*4882a593Smuzhiyun {
2946*4882a593Smuzhiyun 	return readw(base + DAC960_PG_STS_OFFSET);
2947*4882a593Smuzhiyun }
2948*4882a593Smuzhiyun 
2949*4882a593Smuzhiyun static inline bool
DAC960_PG_read_error_status(void __iomem * base,unsigned char * error,unsigned char * param0,unsigned char * param1)2950*4882a593Smuzhiyun DAC960_PG_read_error_status(void __iomem *base, unsigned char *error,
2951*4882a593Smuzhiyun 		unsigned char *param0, unsigned char *param1)
2952*4882a593Smuzhiyun {
2953*4882a593Smuzhiyun 	unsigned char errsts = readb(base + DAC960_PG_ERRSTS_OFFSET);
2954*4882a593Smuzhiyun 
2955*4882a593Smuzhiyun 	if (!(errsts & DAC960_PG_ERRSTS_PENDING))
2956*4882a593Smuzhiyun 		return false;
2957*4882a593Smuzhiyun 	errsts &= ~DAC960_PG_ERRSTS_PENDING;
2958*4882a593Smuzhiyun 	*error = errsts;
2959*4882a593Smuzhiyun 	*param0 = readb(base + DAC960_PG_CMDOP_OFFSET);
2960*4882a593Smuzhiyun 	*param1 = readb(base + DAC960_PG_CMDID_OFFSET);
2961*4882a593Smuzhiyun 	writeb(0, base + DAC960_PG_ERRSTS_OFFSET);
2962*4882a593Smuzhiyun 	return true;
2963*4882a593Smuzhiyun }
2964*4882a593Smuzhiyun 
2965*4882a593Smuzhiyun static inline unsigned short
DAC960_PG_mbox_init(struct pci_dev * pdev,void __iomem * base,union myrb_cmd_mbox * mbox)2966*4882a593Smuzhiyun DAC960_PG_mbox_init(struct pci_dev *pdev, void __iomem *base,
2967*4882a593Smuzhiyun 		union myrb_cmd_mbox *mbox)
2968*4882a593Smuzhiyun {
2969*4882a593Smuzhiyun 	unsigned short status;
2970*4882a593Smuzhiyun 	int timeout = 0;
2971*4882a593Smuzhiyun 
2972*4882a593Smuzhiyun 	while (timeout < MYRB_MAILBOX_TIMEOUT) {
2973*4882a593Smuzhiyun 		if (!DAC960_PG_hw_mbox_is_full(base))
2974*4882a593Smuzhiyun 			break;
2975*4882a593Smuzhiyun 		udelay(10);
2976*4882a593Smuzhiyun 		timeout++;
2977*4882a593Smuzhiyun 	}
2978*4882a593Smuzhiyun 	if (DAC960_PG_hw_mbox_is_full(base)) {
2979*4882a593Smuzhiyun 		dev_err(&pdev->dev,
2980*4882a593Smuzhiyun 			"Timeout waiting for empty mailbox\n");
2981*4882a593Smuzhiyun 		return MYRB_STATUS_SUBSYS_TIMEOUT;
2982*4882a593Smuzhiyun 	}
2983*4882a593Smuzhiyun 	DAC960_PG_write_hw_mbox(base, mbox);
2984*4882a593Smuzhiyun 	DAC960_PG_hw_mbox_new_cmd(base);
2985*4882a593Smuzhiyun 
2986*4882a593Smuzhiyun 	timeout = 0;
2987*4882a593Smuzhiyun 	while (timeout < MYRB_MAILBOX_TIMEOUT) {
2988*4882a593Smuzhiyun 		if (DAC960_PG_hw_mbox_status_available(base))
2989*4882a593Smuzhiyun 			break;
2990*4882a593Smuzhiyun 		udelay(10);
2991*4882a593Smuzhiyun 		timeout++;
2992*4882a593Smuzhiyun 	}
2993*4882a593Smuzhiyun 	if (!DAC960_PG_hw_mbox_status_available(base)) {
2994*4882a593Smuzhiyun 		dev_err(&pdev->dev,
2995*4882a593Smuzhiyun 			"Timeout waiting for mailbox status\n");
2996*4882a593Smuzhiyun 		return MYRB_STATUS_SUBSYS_TIMEOUT;
2997*4882a593Smuzhiyun 	}
2998*4882a593Smuzhiyun 	status = DAC960_PG_read_status(base);
2999*4882a593Smuzhiyun 	DAC960_PG_ack_hw_mbox_intr(base);
3000*4882a593Smuzhiyun 	DAC960_PG_ack_hw_mbox_status(base);
3001*4882a593Smuzhiyun 
3002*4882a593Smuzhiyun 	return status;
3003*4882a593Smuzhiyun }
3004*4882a593Smuzhiyun 
DAC960_PG_hw_init(struct pci_dev * pdev,struct myrb_hba * cb,void __iomem * base)3005*4882a593Smuzhiyun static int DAC960_PG_hw_init(struct pci_dev *pdev,
3006*4882a593Smuzhiyun 		struct myrb_hba *cb, void __iomem *base)
3007*4882a593Smuzhiyun {
3008*4882a593Smuzhiyun 	int timeout = 0;
3009*4882a593Smuzhiyun 	unsigned char error, parm0, parm1;
3010*4882a593Smuzhiyun 
3011*4882a593Smuzhiyun 	DAC960_PG_disable_intr(base);
3012*4882a593Smuzhiyun 	DAC960_PG_ack_hw_mbox_status(base);
3013*4882a593Smuzhiyun 	udelay(1000);
3014*4882a593Smuzhiyun 	while (DAC960_PG_init_in_progress(base) &&
3015*4882a593Smuzhiyun 	       timeout < MYRB_MAILBOX_TIMEOUT) {
3016*4882a593Smuzhiyun 		if (DAC960_PG_read_error_status(base, &error,
3017*4882a593Smuzhiyun 						&parm0, &parm1) &&
3018*4882a593Smuzhiyun 		    myrb_err_status(cb, error, parm0, parm1))
3019*4882a593Smuzhiyun 			return -EIO;
3020*4882a593Smuzhiyun 		udelay(10);
3021*4882a593Smuzhiyun 		timeout++;
3022*4882a593Smuzhiyun 	}
3023*4882a593Smuzhiyun 	if (timeout == MYRB_MAILBOX_TIMEOUT) {
3024*4882a593Smuzhiyun 		dev_err(&pdev->dev,
3025*4882a593Smuzhiyun 			"Timeout waiting for Controller Initialisation\n");
3026*4882a593Smuzhiyun 		return -ETIMEDOUT;
3027*4882a593Smuzhiyun 	}
3028*4882a593Smuzhiyun 	if (!myrb_enable_mmio(cb, DAC960_PG_mbox_init)) {
3029*4882a593Smuzhiyun 		dev_err(&pdev->dev,
3030*4882a593Smuzhiyun 			"Unable to Enable Memory Mailbox Interface\n");
3031*4882a593Smuzhiyun 		DAC960_PG_reset_ctrl(base);
3032*4882a593Smuzhiyun 		return -ENODEV;
3033*4882a593Smuzhiyun 	}
3034*4882a593Smuzhiyun 	DAC960_PG_enable_intr(base);
3035*4882a593Smuzhiyun 	cb->qcmd = myrb_qcmd;
3036*4882a593Smuzhiyun 	cb->write_cmd_mbox = DAC960_PG_write_cmd_mbox;
3037*4882a593Smuzhiyun 	if (cb->dual_mode_interface)
3038*4882a593Smuzhiyun 		cb->get_cmd_mbox = DAC960_PG_mem_mbox_new_cmd;
3039*4882a593Smuzhiyun 	else
3040*4882a593Smuzhiyun 		cb->get_cmd_mbox = DAC960_PG_hw_mbox_new_cmd;
3041*4882a593Smuzhiyun 	cb->disable_intr = DAC960_PG_disable_intr;
3042*4882a593Smuzhiyun 	cb->reset = DAC960_PG_reset_ctrl;
3043*4882a593Smuzhiyun 
3044*4882a593Smuzhiyun 	return 0;
3045*4882a593Smuzhiyun }
3046*4882a593Smuzhiyun 
DAC960_PG_intr_handler(int irq,void * arg)3047*4882a593Smuzhiyun static irqreturn_t DAC960_PG_intr_handler(int irq, void *arg)
3048*4882a593Smuzhiyun {
3049*4882a593Smuzhiyun 	struct myrb_hba *cb = arg;
3050*4882a593Smuzhiyun 	void __iomem *base = cb->io_base;
3051*4882a593Smuzhiyun 	struct myrb_stat_mbox *next_stat_mbox;
3052*4882a593Smuzhiyun 	unsigned long flags;
3053*4882a593Smuzhiyun 
3054*4882a593Smuzhiyun 	spin_lock_irqsave(&cb->queue_lock, flags);
3055*4882a593Smuzhiyun 	DAC960_PG_ack_intr(base);
3056*4882a593Smuzhiyun 	next_stat_mbox = cb->next_stat_mbox;
3057*4882a593Smuzhiyun 	while (next_stat_mbox->valid) {
3058*4882a593Smuzhiyun 		unsigned char id = next_stat_mbox->id;
3059*4882a593Smuzhiyun 		struct scsi_cmnd *scmd = NULL;
3060*4882a593Smuzhiyun 		struct myrb_cmdblk *cmd_blk = NULL;
3061*4882a593Smuzhiyun 
3062*4882a593Smuzhiyun 		if (id == MYRB_DCMD_TAG)
3063*4882a593Smuzhiyun 			cmd_blk = &cb->dcmd_blk;
3064*4882a593Smuzhiyun 		else if (id == MYRB_MCMD_TAG)
3065*4882a593Smuzhiyun 			cmd_blk = &cb->mcmd_blk;
3066*4882a593Smuzhiyun 		else {
3067*4882a593Smuzhiyun 			scmd = scsi_host_find_tag(cb->host, id - 3);
3068*4882a593Smuzhiyun 			if (scmd)
3069*4882a593Smuzhiyun 				cmd_blk = scsi_cmd_priv(scmd);
3070*4882a593Smuzhiyun 		}
3071*4882a593Smuzhiyun 		if (cmd_blk)
3072*4882a593Smuzhiyun 			cmd_blk->status = next_stat_mbox->status;
3073*4882a593Smuzhiyun 		else
3074*4882a593Smuzhiyun 			dev_err(&cb->pdev->dev,
3075*4882a593Smuzhiyun 				"Unhandled command completion %d\n", id);
3076*4882a593Smuzhiyun 
3077*4882a593Smuzhiyun 		memset(next_stat_mbox, 0, sizeof(struct myrb_stat_mbox));
3078*4882a593Smuzhiyun 		if (++next_stat_mbox > cb->last_stat_mbox)
3079*4882a593Smuzhiyun 			next_stat_mbox = cb->first_stat_mbox;
3080*4882a593Smuzhiyun 
3081*4882a593Smuzhiyun 		if (id < 3)
3082*4882a593Smuzhiyun 			myrb_handle_cmdblk(cb, cmd_blk);
3083*4882a593Smuzhiyun 		else
3084*4882a593Smuzhiyun 			myrb_handle_scsi(cb, cmd_blk, scmd);
3085*4882a593Smuzhiyun 	}
3086*4882a593Smuzhiyun 	cb->next_stat_mbox = next_stat_mbox;
3087*4882a593Smuzhiyun 	spin_unlock_irqrestore(&cb->queue_lock, flags);
3088*4882a593Smuzhiyun 	return IRQ_HANDLED;
3089*4882a593Smuzhiyun }
3090*4882a593Smuzhiyun 
3091*4882a593Smuzhiyun struct myrb_privdata DAC960_PG_privdata = {
3092*4882a593Smuzhiyun 	.hw_init =	DAC960_PG_hw_init,
3093*4882a593Smuzhiyun 	.irq_handler =	DAC960_PG_intr_handler,
3094*4882a593Smuzhiyun 	.mmio_size =	DAC960_PG_mmio_size,
3095*4882a593Smuzhiyun };
3096*4882a593Smuzhiyun 
3097*4882a593Smuzhiyun 
3098*4882a593Smuzhiyun /*
3099*4882a593Smuzhiyun  * DAC960 PD Series Controllers
3100*4882a593Smuzhiyun  */
3101*4882a593Smuzhiyun 
DAC960_PD_hw_mbox_new_cmd(void __iomem * base)3102*4882a593Smuzhiyun static inline void DAC960_PD_hw_mbox_new_cmd(void __iomem *base)
3103*4882a593Smuzhiyun {
3104*4882a593Smuzhiyun 	writeb(DAC960_PD_IDB_HWMBOX_NEW_CMD, base + DAC960_PD_IDB_OFFSET);
3105*4882a593Smuzhiyun }
3106*4882a593Smuzhiyun 
DAC960_PD_ack_hw_mbox_status(void __iomem * base)3107*4882a593Smuzhiyun static inline void DAC960_PD_ack_hw_mbox_status(void __iomem *base)
3108*4882a593Smuzhiyun {
3109*4882a593Smuzhiyun 	writeb(DAC960_PD_IDB_HWMBOX_ACK_STS, base + DAC960_PD_IDB_OFFSET);
3110*4882a593Smuzhiyun }
3111*4882a593Smuzhiyun 
DAC960_PD_gen_intr(void __iomem * base)3112*4882a593Smuzhiyun static inline void DAC960_PD_gen_intr(void __iomem *base)
3113*4882a593Smuzhiyun {
3114*4882a593Smuzhiyun 	writeb(DAC960_PD_IDB_GEN_IRQ, base + DAC960_PD_IDB_OFFSET);
3115*4882a593Smuzhiyun }
3116*4882a593Smuzhiyun 
DAC960_PD_reset_ctrl(void __iomem * base)3117*4882a593Smuzhiyun static inline void DAC960_PD_reset_ctrl(void __iomem *base)
3118*4882a593Smuzhiyun {
3119*4882a593Smuzhiyun 	writeb(DAC960_PD_IDB_CTRL_RESET, base + DAC960_PD_IDB_OFFSET);
3120*4882a593Smuzhiyun }
3121*4882a593Smuzhiyun 
DAC960_PD_hw_mbox_is_full(void __iomem * base)3122*4882a593Smuzhiyun static inline bool DAC960_PD_hw_mbox_is_full(void __iomem *base)
3123*4882a593Smuzhiyun {
3124*4882a593Smuzhiyun 	unsigned char idb = readb(base + DAC960_PD_IDB_OFFSET);
3125*4882a593Smuzhiyun 
3126*4882a593Smuzhiyun 	return idb & DAC960_PD_IDB_HWMBOX_FULL;
3127*4882a593Smuzhiyun }
3128*4882a593Smuzhiyun 
DAC960_PD_init_in_progress(void __iomem * base)3129*4882a593Smuzhiyun static inline bool DAC960_PD_init_in_progress(void __iomem *base)
3130*4882a593Smuzhiyun {
3131*4882a593Smuzhiyun 	unsigned char idb = readb(base + DAC960_PD_IDB_OFFSET);
3132*4882a593Smuzhiyun 
3133*4882a593Smuzhiyun 	return idb & DAC960_PD_IDB_INIT_IN_PROGRESS;
3134*4882a593Smuzhiyun }
3135*4882a593Smuzhiyun 
DAC960_PD_ack_intr(void __iomem * base)3136*4882a593Smuzhiyun static inline void DAC960_PD_ack_intr(void __iomem *base)
3137*4882a593Smuzhiyun {
3138*4882a593Smuzhiyun 	writeb(DAC960_PD_ODB_HWMBOX_ACK_IRQ, base + DAC960_PD_ODB_OFFSET);
3139*4882a593Smuzhiyun }
3140*4882a593Smuzhiyun 
DAC960_PD_hw_mbox_status_available(void __iomem * base)3141*4882a593Smuzhiyun static inline bool DAC960_PD_hw_mbox_status_available(void __iomem *base)
3142*4882a593Smuzhiyun {
3143*4882a593Smuzhiyun 	unsigned char odb = readb(base + DAC960_PD_ODB_OFFSET);
3144*4882a593Smuzhiyun 
3145*4882a593Smuzhiyun 	return odb & DAC960_PD_ODB_HWMBOX_STS_AVAIL;
3146*4882a593Smuzhiyun }
3147*4882a593Smuzhiyun 
DAC960_PD_enable_intr(void __iomem * base)3148*4882a593Smuzhiyun static inline void DAC960_PD_enable_intr(void __iomem *base)
3149*4882a593Smuzhiyun {
3150*4882a593Smuzhiyun 	writeb(DAC960_PD_IRQMASK_ENABLE_IRQ, base + DAC960_PD_IRQEN_OFFSET);
3151*4882a593Smuzhiyun }
3152*4882a593Smuzhiyun 
DAC960_PD_disable_intr(void __iomem * base)3153*4882a593Smuzhiyun static inline void DAC960_PD_disable_intr(void __iomem *base)
3154*4882a593Smuzhiyun {
3155*4882a593Smuzhiyun 	writeb(0, base + DAC960_PD_IRQEN_OFFSET);
3156*4882a593Smuzhiyun }
3157*4882a593Smuzhiyun 
DAC960_PD_intr_enabled(void __iomem * base)3158*4882a593Smuzhiyun static inline bool DAC960_PD_intr_enabled(void __iomem *base)
3159*4882a593Smuzhiyun {
3160*4882a593Smuzhiyun 	unsigned char imask = readb(base + DAC960_PD_IRQEN_OFFSET);
3161*4882a593Smuzhiyun 
3162*4882a593Smuzhiyun 	return imask & DAC960_PD_IRQMASK_ENABLE_IRQ;
3163*4882a593Smuzhiyun }
3164*4882a593Smuzhiyun 
DAC960_PD_write_cmd_mbox(void __iomem * base,union myrb_cmd_mbox * mbox)3165*4882a593Smuzhiyun static inline void DAC960_PD_write_cmd_mbox(void __iomem *base,
3166*4882a593Smuzhiyun 		union myrb_cmd_mbox *mbox)
3167*4882a593Smuzhiyun {
3168*4882a593Smuzhiyun 	writel(mbox->words[0], base + DAC960_PD_CMDOP_OFFSET);
3169*4882a593Smuzhiyun 	writel(mbox->words[1], base + DAC960_PD_MBOX4_OFFSET);
3170*4882a593Smuzhiyun 	writel(mbox->words[2], base + DAC960_PD_MBOX8_OFFSET);
3171*4882a593Smuzhiyun 	writeb(mbox->bytes[12], base + DAC960_PD_MBOX12_OFFSET);
3172*4882a593Smuzhiyun }
3173*4882a593Smuzhiyun 
3174*4882a593Smuzhiyun static inline unsigned char
DAC960_PD_read_status_cmd_ident(void __iomem * base)3175*4882a593Smuzhiyun DAC960_PD_read_status_cmd_ident(void __iomem *base)
3176*4882a593Smuzhiyun {
3177*4882a593Smuzhiyun 	return readb(base + DAC960_PD_STSID_OFFSET);
3178*4882a593Smuzhiyun }
3179*4882a593Smuzhiyun 
3180*4882a593Smuzhiyun static inline unsigned short
DAC960_PD_read_status(void __iomem * base)3181*4882a593Smuzhiyun DAC960_PD_read_status(void __iomem *base)
3182*4882a593Smuzhiyun {
3183*4882a593Smuzhiyun 	return readw(base + DAC960_PD_STS_OFFSET);
3184*4882a593Smuzhiyun }
3185*4882a593Smuzhiyun 
3186*4882a593Smuzhiyun static inline bool
DAC960_PD_read_error_status(void __iomem * base,unsigned char * error,unsigned char * param0,unsigned char * param1)3187*4882a593Smuzhiyun DAC960_PD_read_error_status(void __iomem *base, unsigned char *error,
3188*4882a593Smuzhiyun 		unsigned char *param0, unsigned char *param1)
3189*4882a593Smuzhiyun {
3190*4882a593Smuzhiyun 	unsigned char errsts = readb(base + DAC960_PD_ERRSTS_OFFSET);
3191*4882a593Smuzhiyun 
3192*4882a593Smuzhiyun 	if (!(errsts & DAC960_PD_ERRSTS_PENDING))
3193*4882a593Smuzhiyun 		return false;
3194*4882a593Smuzhiyun 	errsts &= ~DAC960_PD_ERRSTS_PENDING;
3195*4882a593Smuzhiyun 	*error = errsts;
3196*4882a593Smuzhiyun 	*param0 = readb(base + DAC960_PD_CMDOP_OFFSET);
3197*4882a593Smuzhiyun 	*param1 = readb(base + DAC960_PD_CMDID_OFFSET);
3198*4882a593Smuzhiyun 	writeb(0, base + DAC960_PD_ERRSTS_OFFSET);
3199*4882a593Smuzhiyun 	return true;
3200*4882a593Smuzhiyun }
3201*4882a593Smuzhiyun 
DAC960_PD_qcmd(struct myrb_hba * cb,struct myrb_cmdblk * cmd_blk)3202*4882a593Smuzhiyun static void DAC960_PD_qcmd(struct myrb_hba *cb, struct myrb_cmdblk *cmd_blk)
3203*4882a593Smuzhiyun {
3204*4882a593Smuzhiyun 	void __iomem *base = cb->io_base;
3205*4882a593Smuzhiyun 	union myrb_cmd_mbox *mbox = &cmd_blk->mbox;
3206*4882a593Smuzhiyun 
3207*4882a593Smuzhiyun 	while (DAC960_PD_hw_mbox_is_full(base))
3208*4882a593Smuzhiyun 		udelay(1);
3209*4882a593Smuzhiyun 	DAC960_PD_write_cmd_mbox(base, mbox);
3210*4882a593Smuzhiyun 	DAC960_PD_hw_mbox_new_cmd(base);
3211*4882a593Smuzhiyun }
3212*4882a593Smuzhiyun 
DAC960_PD_hw_init(struct pci_dev * pdev,struct myrb_hba * cb,void __iomem * base)3213*4882a593Smuzhiyun static int DAC960_PD_hw_init(struct pci_dev *pdev,
3214*4882a593Smuzhiyun 		struct myrb_hba *cb, void __iomem *base)
3215*4882a593Smuzhiyun {
3216*4882a593Smuzhiyun 	int timeout = 0;
3217*4882a593Smuzhiyun 	unsigned char error, parm0, parm1;
3218*4882a593Smuzhiyun 
3219*4882a593Smuzhiyun 	if (!request_region(cb->io_addr, 0x80, "myrb")) {
3220*4882a593Smuzhiyun 		dev_err(&pdev->dev, "IO port 0x%lx busy\n",
3221*4882a593Smuzhiyun 			(unsigned long)cb->io_addr);
3222*4882a593Smuzhiyun 		return -EBUSY;
3223*4882a593Smuzhiyun 	}
3224*4882a593Smuzhiyun 	DAC960_PD_disable_intr(base);
3225*4882a593Smuzhiyun 	DAC960_PD_ack_hw_mbox_status(base);
3226*4882a593Smuzhiyun 	udelay(1000);
3227*4882a593Smuzhiyun 	while (DAC960_PD_init_in_progress(base) &&
3228*4882a593Smuzhiyun 	       timeout < MYRB_MAILBOX_TIMEOUT) {
3229*4882a593Smuzhiyun 		if (DAC960_PD_read_error_status(base, &error,
3230*4882a593Smuzhiyun 					      &parm0, &parm1) &&
3231*4882a593Smuzhiyun 		    myrb_err_status(cb, error, parm0, parm1))
3232*4882a593Smuzhiyun 			return -EIO;
3233*4882a593Smuzhiyun 		udelay(10);
3234*4882a593Smuzhiyun 		timeout++;
3235*4882a593Smuzhiyun 	}
3236*4882a593Smuzhiyun 	if (timeout == MYRB_MAILBOX_TIMEOUT) {
3237*4882a593Smuzhiyun 		dev_err(&pdev->dev,
3238*4882a593Smuzhiyun 			"Timeout waiting for Controller Initialisation\n");
3239*4882a593Smuzhiyun 		return -ETIMEDOUT;
3240*4882a593Smuzhiyun 	}
3241*4882a593Smuzhiyun 	if (!myrb_enable_mmio(cb, NULL)) {
3242*4882a593Smuzhiyun 		dev_err(&pdev->dev,
3243*4882a593Smuzhiyun 			"Unable to Enable Memory Mailbox Interface\n");
3244*4882a593Smuzhiyun 		DAC960_PD_reset_ctrl(base);
3245*4882a593Smuzhiyun 		return -ENODEV;
3246*4882a593Smuzhiyun 	}
3247*4882a593Smuzhiyun 	DAC960_PD_enable_intr(base);
3248*4882a593Smuzhiyun 	cb->qcmd = DAC960_PD_qcmd;
3249*4882a593Smuzhiyun 	cb->disable_intr = DAC960_PD_disable_intr;
3250*4882a593Smuzhiyun 	cb->reset = DAC960_PD_reset_ctrl;
3251*4882a593Smuzhiyun 
3252*4882a593Smuzhiyun 	return 0;
3253*4882a593Smuzhiyun }
3254*4882a593Smuzhiyun 
DAC960_PD_intr_handler(int irq,void * arg)3255*4882a593Smuzhiyun static irqreturn_t DAC960_PD_intr_handler(int irq, void *arg)
3256*4882a593Smuzhiyun {
3257*4882a593Smuzhiyun 	struct myrb_hba *cb = arg;
3258*4882a593Smuzhiyun 	void __iomem *base = cb->io_base;
3259*4882a593Smuzhiyun 	unsigned long flags;
3260*4882a593Smuzhiyun 
3261*4882a593Smuzhiyun 	spin_lock_irqsave(&cb->queue_lock, flags);
3262*4882a593Smuzhiyun 	while (DAC960_PD_hw_mbox_status_available(base)) {
3263*4882a593Smuzhiyun 		unsigned char id = DAC960_PD_read_status_cmd_ident(base);
3264*4882a593Smuzhiyun 		struct scsi_cmnd *scmd = NULL;
3265*4882a593Smuzhiyun 		struct myrb_cmdblk *cmd_blk = NULL;
3266*4882a593Smuzhiyun 
3267*4882a593Smuzhiyun 		if (id == MYRB_DCMD_TAG)
3268*4882a593Smuzhiyun 			cmd_blk = &cb->dcmd_blk;
3269*4882a593Smuzhiyun 		else if (id == MYRB_MCMD_TAG)
3270*4882a593Smuzhiyun 			cmd_blk = &cb->mcmd_blk;
3271*4882a593Smuzhiyun 		else {
3272*4882a593Smuzhiyun 			scmd = scsi_host_find_tag(cb->host, id - 3);
3273*4882a593Smuzhiyun 			if (scmd)
3274*4882a593Smuzhiyun 				cmd_blk = scsi_cmd_priv(scmd);
3275*4882a593Smuzhiyun 		}
3276*4882a593Smuzhiyun 		if (cmd_blk)
3277*4882a593Smuzhiyun 			cmd_blk->status = DAC960_PD_read_status(base);
3278*4882a593Smuzhiyun 		else
3279*4882a593Smuzhiyun 			dev_err(&cb->pdev->dev,
3280*4882a593Smuzhiyun 				"Unhandled command completion %d\n", id);
3281*4882a593Smuzhiyun 
3282*4882a593Smuzhiyun 		DAC960_PD_ack_intr(base);
3283*4882a593Smuzhiyun 		DAC960_PD_ack_hw_mbox_status(base);
3284*4882a593Smuzhiyun 
3285*4882a593Smuzhiyun 		if (id < 3)
3286*4882a593Smuzhiyun 			myrb_handle_cmdblk(cb, cmd_blk);
3287*4882a593Smuzhiyun 		else
3288*4882a593Smuzhiyun 			myrb_handle_scsi(cb, cmd_blk, scmd);
3289*4882a593Smuzhiyun 	}
3290*4882a593Smuzhiyun 	spin_unlock_irqrestore(&cb->queue_lock, flags);
3291*4882a593Smuzhiyun 	return IRQ_HANDLED;
3292*4882a593Smuzhiyun }
3293*4882a593Smuzhiyun 
3294*4882a593Smuzhiyun struct myrb_privdata DAC960_PD_privdata = {
3295*4882a593Smuzhiyun 	.hw_init =	DAC960_PD_hw_init,
3296*4882a593Smuzhiyun 	.irq_handler =	DAC960_PD_intr_handler,
3297*4882a593Smuzhiyun 	.mmio_size =	DAC960_PD_mmio_size,
3298*4882a593Smuzhiyun };
3299*4882a593Smuzhiyun 
3300*4882a593Smuzhiyun 
3301*4882a593Smuzhiyun /*
3302*4882a593Smuzhiyun  * DAC960 P Series Controllers
3303*4882a593Smuzhiyun  *
3304*4882a593Smuzhiyun  * Similar to the DAC960 PD Series Controllers, but some commands have
3305*4882a593Smuzhiyun  * to be translated.
3306*4882a593Smuzhiyun  */
3307*4882a593Smuzhiyun 
myrb_translate_enquiry(void * enq)3308*4882a593Smuzhiyun static inline void myrb_translate_enquiry(void *enq)
3309*4882a593Smuzhiyun {
3310*4882a593Smuzhiyun 	memcpy(enq + 132, enq + 36, 64);
3311*4882a593Smuzhiyun 	memset(enq + 36, 0, 96);
3312*4882a593Smuzhiyun }
3313*4882a593Smuzhiyun 
myrb_translate_devstate(void * state)3314*4882a593Smuzhiyun static inline void myrb_translate_devstate(void *state)
3315*4882a593Smuzhiyun {
3316*4882a593Smuzhiyun 	memcpy(state + 2, state + 3, 1);
3317*4882a593Smuzhiyun 	memmove(state + 4, state + 5, 2);
3318*4882a593Smuzhiyun 	memmove(state + 6, state + 8, 4);
3319*4882a593Smuzhiyun }
3320*4882a593Smuzhiyun 
myrb_translate_to_rw_command(struct myrb_cmdblk * cmd_blk)3321*4882a593Smuzhiyun static inline void myrb_translate_to_rw_command(struct myrb_cmdblk *cmd_blk)
3322*4882a593Smuzhiyun {
3323*4882a593Smuzhiyun 	union myrb_cmd_mbox *mbox = &cmd_blk->mbox;
3324*4882a593Smuzhiyun 	int ldev_num = mbox->type5.ld.ldev_num;
3325*4882a593Smuzhiyun 
3326*4882a593Smuzhiyun 	mbox->bytes[3] &= 0x7;
3327*4882a593Smuzhiyun 	mbox->bytes[3] |= mbox->bytes[7] << 6;
3328*4882a593Smuzhiyun 	mbox->bytes[7] = ldev_num;
3329*4882a593Smuzhiyun }
3330*4882a593Smuzhiyun 
myrb_translate_from_rw_command(struct myrb_cmdblk * cmd_blk)3331*4882a593Smuzhiyun static inline void myrb_translate_from_rw_command(struct myrb_cmdblk *cmd_blk)
3332*4882a593Smuzhiyun {
3333*4882a593Smuzhiyun 	union myrb_cmd_mbox *mbox = &cmd_blk->mbox;
3334*4882a593Smuzhiyun 	int ldev_num = mbox->bytes[7];
3335*4882a593Smuzhiyun 
3336*4882a593Smuzhiyun 	mbox->bytes[7] = mbox->bytes[3] >> 6;
3337*4882a593Smuzhiyun 	mbox->bytes[3] &= 0x7;
3338*4882a593Smuzhiyun 	mbox->bytes[3] |= ldev_num << 3;
3339*4882a593Smuzhiyun }
3340*4882a593Smuzhiyun 
DAC960_P_qcmd(struct myrb_hba * cb,struct myrb_cmdblk * cmd_blk)3341*4882a593Smuzhiyun static void DAC960_P_qcmd(struct myrb_hba *cb, struct myrb_cmdblk *cmd_blk)
3342*4882a593Smuzhiyun {
3343*4882a593Smuzhiyun 	void __iomem *base = cb->io_base;
3344*4882a593Smuzhiyun 	union myrb_cmd_mbox *mbox = &cmd_blk->mbox;
3345*4882a593Smuzhiyun 
3346*4882a593Smuzhiyun 	switch (mbox->common.opcode) {
3347*4882a593Smuzhiyun 	case MYRB_CMD_ENQUIRY:
3348*4882a593Smuzhiyun 		mbox->common.opcode = MYRB_CMD_ENQUIRY_OLD;
3349*4882a593Smuzhiyun 		break;
3350*4882a593Smuzhiyun 	case MYRB_CMD_GET_DEVICE_STATE:
3351*4882a593Smuzhiyun 		mbox->common.opcode = MYRB_CMD_GET_DEVICE_STATE_OLD;
3352*4882a593Smuzhiyun 		break;
3353*4882a593Smuzhiyun 	case MYRB_CMD_READ:
3354*4882a593Smuzhiyun 		mbox->common.opcode = MYRB_CMD_READ_OLD;
3355*4882a593Smuzhiyun 		myrb_translate_to_rw_command(cmd_blk);
3356*4882a593Smuzhiyun 		break;
3357*4882a593Smuzhiyun 	case MYRB_CMD_WRITE:
3358*4882a593Smuzhiyun 		mbox->common.opcode = MYRB_CMD_WRITE_OLD;
3359*4882a593Smuzhiyun 		myrb_translate_to_rw_command(cmd_blk);
3360*4882a593Smuzhiyun 		break;
3361*4882a593Smuzhiyun 	case MYRB_CMD_READ_SG:
3362*4882a593Smuzhiyun 		mbox->common.opcode = MYRB_CMD_READ_SG_OLD;
3363*4882a593Smuzhiyun 		myrb_translate_to_rw_command(cmd_blk);
3364*4882a593Smuzhiyun 		break;
3365*4882a593Smuzhiyun 	case MYRB_CMD_WRITE_SG:
3366*4882a593Smuzhiyun 		mbox->common.opcode = MYRB_CMD_WRITE_SG_OLD;
3367*4882a593Smuzhiyun 		myrb_translate_to_rw_command(cmd_blk);
3368*4882a593Smuzhiyun 		break;
3369*4882a593Smuzhiyun 	default:
3370*4882a593Smuzhiyun 		break;
3371*4882a593Smuzhiyun 	}
3372*4882a593Smuzhiyun 	while (DAC960_PD_hw_mbox_is_full(base))
3373*4882a593Smuzhiyun 		udelay(1);
3374*4882a593Smuzhiyun 	DAC960_PD_write_cmd_mbox(base, mbox);
3375*4882a593Smuzhiyun 	DAC960_PD_hw_mbox_new_cmd(base);
3376*4882a593Smuzhiyun }
3377*4882a593Smuzhiyun 
3378*4882a593Smuzhiyun 
DAC960_P_hw_init(struct pci_dev * pdev,struct myrb_hba * cb,void __iomem * base)3379*4882a593Smuzhiyun static int DAC960_P_hw_init(struct pci_dev *pdev,
3380*4882a593Smuzhiyun 		struct myrb_hba *cb, void __iomem *base)
3381*4882a593Smuzhiyun {
3382*4882a593Smuzhiyun 	int timeout = 0;
3383*4882a593Smuzhiyun 	unsigned char error, parm0, parm1;
3384*4882a593Smuzhiyun 
3385*4882a593Smuzhiyun 	if (!request_region(cb->io_addr, 0x80, "myrb")) {
3386*4882a593Smuzhiyun 		dev_err(&pdev->dev, "IO port 0x%lx busy\n",
3387*4882a593Smuzhiyun 			(unsigned long)cb->io_addr);
3388*4882a593Smuzhiyun 		return -EBUSY;
3389*4882a593Smuzhiyun 	}
3390*4882a593Smuzhiyun 	DAC960_PD_disable_intr(base);
3391*4882a593Smuzhiyun 	DAC960_PD_ack_hw_mbox_status(base);
3392*4882a593Smuzhiyun 	udelay(1000);
3393*4882a593Smuzhiyun 	while (DAC960_PD_init_in_progress(base) &&
3394*4882a593Smuzhiyun 	       timeout < MYRB_MAILBOX_TIMEOUT) {
3395*4882a593Smuzhiyun 		if (DAC960_PD_read_error_status(base, &error,
3396*4882a593Smuzhiyun 						&parm0, &parm1) &&
3397*4882a593Smuzhiyun 		    myrb_err_status(cb, error, parm0, parm1))
3398*4882a593Smuzhiyun 			return -EAGAIN;
3399*4882a593Smuzhiyun 		udelay(10);
3400*4882a593Smuzhiyun 		timeout++;
3401*4882a593Smuzhiyun 	}
3402*4882a593Smuzhiyun 	if (timeout == MYRB_MAILBOX_TIMEOUT) {
3403*4882a593Smuzhiyun 		dev_err(&pdev->dev,
3404*4882a593Smuzhiyun 			"Timeout waiting for Controller Initialisation\n");
3405*4882a593Smuzhiyun 		return -ETIMEDOUT;
3406*4882a593Smuzhiyun 	}
3407*4882a593Smuzhiyun 	if (!myrb_enable_mmio(cb, NULL)) {
3408*4882a593Smuzhiyun 		dev_err(&pdev->dev,
3409*4882a593Smuzhiyun 			"Unable to allocate DMA mapped memory\n");
3410*4882a593Smuzhiyun 		DAC960_PD_reset_ctrl(base);
3411*4882a593Smuzhiyun 		return -ETIMEDOUT;
3412*4882a593Smuzhiyun 	}
3413*4882a593Smuzhiyun 	DAC960_PD_enable_intr(base);
3414*4882a593Smuzhiyun 	cb->qcmd = DAC960_P_qcmd;
3415*4882a593Smuzhiyun 	cb->disable_intr = DAC960_PD_disable_intr;
3416*4882a593Smuzhiyun 	cb->reset = DAC960_PD_reset_ctrl;
3417*4882a593Smuzhiyun 
3418*4882a593Smuzhiyun 	return 0;
3419*4882a593Smuzhiyun }
3420*4882a593Smuzhiyun 
DAC960_P_intr_handler(int irq,void * arg)3421*4882a593Smuzhiyun static irqreturn_t DAC960_P_intr_handler(int irq, void *arg)
3422*4882a593Smuzhiyun {
3423*4882a593Smuzhiyun 	struct myrb_hba *cb = arg;
3424*4882a593Smuzhiyun 	void __iomem *base = cb->io_base;
3425*4882a593Smuzhiyun 	unsigned long flags;
3426*4882a593Smuzhiyun 
3427*4882a593Smuzhiyun 	spin_lock_irqsave(&cb->queue_lock, flags);
3428*4882a593Smuzhiyun 	while (DAC960_PD_hw_mbox_status_available(base)) {
3429*4882a593Smuzhiyun 		unsigned char id = DAC960_PD_read_status_cmd_ident(base);
3430*4882a593Smuzhiyun 		struct scsi_cmnd *scmd = NULL;
3431*4882a593Smuzhiyun 		struct myrb_cmdblk *cmd_blk = NULL;
3432*4882a593Smuzhiyun 		union myrb_cmd_mbox *mbox;
3433*4882a593Smuzhiyun 		enum myrb_cmd_opcode op;
3434*4882a593Smuzhiyun 
3435*4882a593Smuzhiyun 
3436*4882a593Smuzhiyun 		if (id == MYRB_DCMD_TAG)
3437*4882a593Smuzhiyun 			cmd_blk = &cb->dcmd_blk;
3438*4882a593Smuzhiyun 		else if (id == MYRB_MCMD_TAG)
3439*4882a593Smuzhiyun 			cmd_blk = &cb->mcmd_blk;
3440*4882a593Smuzhiyun 		else {
3441*4882a593Smuzhiyun 			scmd = scsi_host_find_tag(cb->host, id - 3);
3442*4882a593Smuzhiyun 			if (scmd)
3443*4882a593Smuzhiyun 				cmd_blk = scsi_cmd_priv(scmd);
3444*4882a593Smuzhiyun 		}
3445*4882a593Smuzhiyun 		if (cmd_blk)
3446*4882a593Smuzhiyun 			cmd_blk->status = DAC960_PD_read_status(base);
3447*4882a593Smuzhiyun 		else
3448*4882a593Smuzhiyun 			dev_err(&cb->pdev->dev,
3449*4882a593Smuzhiyun 				"Unhandled command completion %d\n", id);
3450*4882a593Smuzhiyun 
3451*4882a593Smuzhiyun 		DAC960_PD_ack_intr(base);
3452*4882a593Smuzhiyun 		DAC960_PD_ack_hw_mbox_status(base);
3453*4882a593Smuzhiyun 
3454*4882a593Smuzhiyun 		if (!cmd_blk)
3455*4882a593Smuzhiyun 			continue;
3456*4882a593Smuzhiyun 
3457*4882a593Smuzhiyun 		mbox = &cmd_blk->mbox;
3458*4882a593Smuzhiyun 		op = mbox->common.opcode;
3459*4882a593Smuzhiyun 		switch (op) {
3460*4882a593Smuzhiyun 		case MYRB_CMD_ENQUIRY_OLD:
3461*4882a593Smuzhiyun 			mbox->common.opcode = MYRB_CMD_ENQUIRY;
3462*4882a593Smuzhiyun 			myrb_translate_enquiry(cb->enquiry);
3463*4882a593Smuzhiyun 			break;
3464*4882a593Smuzhiyun 		case MYRB_CMD_READ_OLD:
3465*4882a593Smuzhiyun 			mbox->common.opcode = MYRB_CMD_READ;
3466*4882a593Smuzhiyun 			myrb_translate_from_rw_command(cmd_blk);
3467*4882a593Smuzhiyun 			break;
3468*4882a593Smuzhiyun 		case MYRB_CMD_WRITE_OLD:
3469*4882a593Smuzhiyun 			mbox->common.opcode = MYRB_CMD_WRITE;
3470*4882a593Smuzhiyun 			myrb_translate_from_rw_command(cmd_blk);
3471*4882a593Smuzhiyun 			break;
3472*4882a593Smuzhiyun 		case MYRB_CMD_READ_SG_OLD:
3473*4882a593Smuzhiyun 			mbox->common.opcode = MYRB_CMD_READ_SG;
3474*4882a593Smuzhiyun 			myrb_translate_from_rw_command(cmd_blk);
3475*4882a593Smuzhiyun 			break;
3476*4882a593Smuzhiyun 		case MYRB_CMD_WRITE_SG_OLD:
3477*4882a593Smuzhiyun 			mbox->common.opcode = MYRB_CMD_WRITE_SG;
3478*4882a593Smuzhiyun 			myrb_translate_from_rw_command(cmd_blk);
3479*4882a593Smuzhiyun 			break;
3480*4882a593Smuzhiyun 		default:
3481*4882a593Smuzhiyun 			break;
3482*4882a593Smuzhiyun 		}
3483*4882a593Smuzhiyun 		if (id < 3)
3484*4882a593Smuzhiyun 			myrb_handle_cmdblk(cb, cmd_blk);
3485*4882a593Smuzhiyun 		else
3486*4882a593Smuzhiyun 			myrb_handle_scsi(cb, cmd_blk, scmd);
3487*4882a593Smuzhiyun 	}
3488*4882a593Smuzhiyun 	spin_unlock_irqrestore(&cb->queue_lock, flags);
3489*4882a593Smuzhiyun 	return IRQ_HANDLED;
3490*4882a593Smuzhiyun }
3491*4882a593Smuzhiyun 
3492*4882a593Smuzhiyun struct myrb_privdata DAC960_P_privdata = {
3493*4882a593Smuzhiyun 	.hw_init =	DAC960_P_hw_init,
3494*4882a593Smuzhiyun 	.irq_handler =	DAC960_P_intr_handler,
3495*4882a593Smuzhiyun 	.mmio_size =	DAC960_PD_mmio_size,
3496*4882a593Smuzhiyun };
3497*4882a593Smuzhiyun 
myrb_detect(struct pci_dev * pdev,const struct pci_device_id * entry)3498*4882a593Smuzhiyun static struct myrb_hba *myrb_detect(struct pci_dev *pdev,
3499*4882a593Smuzhiyun 		const struct pci_device_id *entry)
3500*4882a593Smuzhiyun {
3501*4882a593Smuzhiyun 	struct myrb_privdata *privdata =
3502*4882a593Smuzhiyun 		(struct myrb_privdata *)entry->driver_data;
3503*4882a593Smuzhiyun 	irq_handler_t irq_handler = privdata->irq_handler;
3504*4882a593Smuzhiyun 	unsigned int mmio_size = privdata->mmio_size;
3505*4882a593Smuzhiyun 	struct Scsi_Host *shost;
3506*4882a593Smuzhiyun 	struct myrb_hba *cb = NULL;
3507*4882a593Smuzhiyun 
3508*4882a593Smuzhiyun 	shost = scsi_host_alloc(&myrb_template, sizeof(struct myrb_hba));
3509*4882a593Smuzhiyun 	if (!shost) {
3510*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Unable to allocate Controller\n");
3511*4882a593Smuzhiyun 		return NULL;
3512*4882a593Smuzhiyun 	}
3513*4882a593Smuzhiyun 	shost->max_cmd_len = 12;
3514*4882a593Smuzhiyun 	shost->max_lun = 256;
3515*4882a593Smuzhiyun 	cb = shost_priv(shost);
3516*4882a593Smuzhiyun 	mutex_init(&cb->dcmd_mutex);
3517*4882a593Smuzhiyun 	mutex_init(&cb->dma_mutex);
3518*4882a593Smuzhiyun 	cb->pdev = pdev;
3519*4882a593Smuzhiyun 	cb->host = shost;
3520*4882a593Smuzhiyun 
3521*4882a593Smuzhiyun 	if (pci_enable_device(pdev)) {
3522*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Failed to enable PCI device\n");
3523*4882a593Smuzhiyun 		scsi_host_put(shost);
3524*4882a593Smuzhiyun 		return NULL;
3525*4882a593Smuzhiyun 	}
3526*4882a593Smuzhiyun 
3527*4882a593Smuzhiyun 	if (privdata->hw_init == DAC960_PD_hw_init ||
3528*4882a593Smuzhiyun 	    privdata->hw_init == DAC960_P_hw_init) {
3529*4882a593Smuzhiyun 		cb->io_addr = pci_resource_start(pdev, 0);
3530*4882a593Smuzhiyun 		cb->pci_addr = pci_resource_start(pdev, 1);
3531*4882a593Smuzhiyun 	} else
3532*4882a593Smuzhiyun 		cb->pci_addr = pci_resource_start(pdev, 0);
3533*4882a593Smuzhiyun 
3534*4882a593Smuzhiyun 	pci_set_drvdata(pdev, cb);
3535*4882a593Smuzhiyun 	spin_lock_init(&cb->queue_lock);
3536*4882a593Smuzhiyun 	if (mmio_size < PAGE_SIZE)
3537*4882a593Smuzhiyun 		mmio_size = PAGE_SIZE;
3538*4882a593Smuzhiyun 	cb->mmio_base = ioremap(cb->pci_addr & PAGE_MASK, mmio_size);
3539*4882a593Smuzhiyun 	if (cb->mmio_base == NULL) {
3540*4882a593Smuzhiyun 		dev_err(&pdev->dev,
3541*4882a593Smuzhiyun 			"Unable to map Controller Register Window\n");
3542*4882a593Smuzhiyun 		goto failure;
3543*4882a593Smuzhiyun 	}
3544*4882a593Smuzhiyun 
3545*4882a593Smuzhiyun 	cb->io_base = cb->mmio_base + (cb->pci_addr & ~PAGE_MASK);
3546*4882a593Smuzhiyun 	if (privdata->hw_init(pdev, cb, cb->io_base))
3547*4882a593Smuzhiyun 		goto failure;
3548*4882a593Smuzhiyun 
3549*4882a593Smuzhiyun 	if (request_irq(pdev->irq, irq_handler, IRQF_SHARED, "myrb", cb) < 0) {
3550*4882a593Smuzhiyun 		dev_err(&pdev->dev,
3551*4882a593Smuzhiyun 			"Unable to acquire IRQ Channel %d\n", pdev->irq);
3552*4882a593Smuzhiyun 		goto failure;
3553*4882a593Smuzhiyun 	}
3554*4882a593Smuzhiyun 	cb->irq = pdev->irq;
3555*4882a593Smuzhiyun 	return cb;
3556*4882a593Smuzhiyun 
3557*4882a593Smuzhiyun failure:
3558*4882a593Smuzhiyun 	dev_err(&pdev->dev,
3559*4882a593Smuzhiyun 		"Failed to initialize Controller\n");
3560*4882a593Smuzhiyun 	myrb_cleanup(cb);
3561*4882a593Smuzhiyun 	return NULL;
3562*4882a593Smuzhiyun }
3563*4882a593Smuzhiyun 
myrb_probe(struct pci_dev * dev,const struct pci_device_id * entry)3564*4882a593Smuzhiyun static int myrb_probe(struct pci_dev *dev, const struct pci_device_id *entry)
3565*4882a593Smuzhiyun {
3566*4882a593Smuzhiyun 	struct myrb_hba *cb;
3567*4882a593Smuzhiyun 	int ret;
3568*4882a593Smuzhiyun 
3569*4882a593Smuzhiyun 	cb = myrb_detect(dev, entry);
3570*4882a593Smuzhiyun 	if (!cb)
3571*4882a593Smuzhiyun 		return -ENODEV;
3572*4882a593Smuzhiyun 
3573*4882a593Smuzhiyun 	ret = myrb_get_hba_config(cb);
3574*4882a593Smuzhiyun 	if (ret < 0) {
3575*4882a593Smuzhiyun 		myrb_cleanup(cb);
3576*4882a593Smuzhiyun 		return ret;
3577*4882a593Smuzhiyun 	}
3578*4882a593Smuzhiyun 
3579*4882a593Smuzhiyun 	if (!myrb_create_mempools(dev, cb)) {
3580*4882a593Smuzhiyun 		ret = -ENOMEM;
3581*4882a593Smuzhiyun 		goto failed;
3582*4882a593Smuzhiyun 	}
3583*4882a593Smuzhiyun 
3584*4882a593Smuzhiyun 	ret = scsi_add_host(cb->host, &dev->dev);
3585*4882a593Smuzhiyun 	if (ret) {
3586*4882a593Smuzhiyun 		dev_err(&dev->dev, "scsi_add_host failed with %d\n", ret);
3587*4882a593Smuzhiyun 		myrb_destroy_mempools(cb);
3588*4882a593Smuzhiyun 		goto failed;
3589*4882a593Smuzhiyun 	}
3590*4882a593Smuzhiyun 	scsi_scan_host(cb->host);
3591*4882a593Smuzhiyun 	return 0;
3592*4882a593Smuzhiyun failed:
3593*4882a593Smuzhiyun 	myrb_cleanup(cb);
3594*4882a593Smuzhiyun 	return ret;
3595*4882a593Smuzhiyun }
3596*4882a593Smuzhiyun 
3597*4882a593Smuzhiyun 
myrb_remove(struct pci_dev * pdev)3598*4882a593Smuzhiyun static void myrb_remove(struct pci_dev *pdev)
3599*4882a593Smuzhiyun {
3600*4882a593Smuzhiyun 	struct myrb_hba *cb = pci_get_drvdata(pdev);
3601*4882a593Smuzhiyun 
3602*4882a593Smuzhiyun 	shost_printk(KERN_NOTICE, cb->host, "Flushing Cache...");
3603*4882a593Smuzhiyun 	myrb_exec_type3(cb, MYRB_CMD_FLUSH, 0);
3604*4882a593Smuzhiyun 	myrb_cleanup(cb);
3605*4882a593Smuzhiyun 	myrb_destroy_mempools(cb);
3606*4882a593Smuzhiyun }
3607*4882a593Smuzhiyun 
3608*4882a593Smuzhiyun 
3609*4882a593Smuzhiyun static const struct pci_device_id myrb_id_table[] = {
3610*4882a593Smuzhiyun 	{
3611*4882a593Smuzhiyun 		PCI_DEVICE_SUB(PCI_VENDOR_ID_DEC,
3612*4882a593Smuzhiyun 			       PCI_DEVICE_ID_DEC_21285,
3613*4882a593Smuzhiyun 			       PCI_VENDOR_ID_MYLEX,
3614*4882a593Smuzhiyun 			       PCI_DEVICE_ID_MYLEX_DAC960_LA),
3615*4882a593Smuzhiyun 		.driver_data	= (unsigned long) &DAC960_LA_privdata,
3616*4882a593Smuzhiyun 	},
3617*4882a593Smuzhiyun 	{
3618*4882a593Smuzhiyun 		PCI_DEVICE_DATA(MYLEX, DAC960_PG, &DAC960_PG_privdata),
3619*4882a593Smuzhiyun 	},
3620*4882a593Smuzhiyun 	{
3621*4882a593Smuzhiyun 		PCI_DEVICE_DATA(MYLEX, DAC960_PD, &DAC960_PD_privdata),
3622*4882a593Smuzhiyun 	},
3623*4882a593Smuzhiyun 	{
3624*4882a593Smuzhiyun 		PCI_DEVICE_DATA(MYLEX, DAC960_P, &DAC960_P_privdata),
3625*4882a593Smuzhiyun 	},
3626*4882a593Smuzhiyun 	{0, },
3627*4882a593Smuzhiyun };
3628*4882a593Smuzhiyun 
3629*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, myrb_id_table);
3630*4882a593Smuzhiyun 
3631*4882a593Smuzhiyun static struct pci_driver myrb_pci_driver = {
3632*4882a593Smuzhiyun 	.name		= "myrb",
3633*4882a593Smuzhiyun 	.id_table	= myrb_id_table,
3634*4882a593Smuzhiyun 	.probe		= myrb_probe,
3635*4882a593Smuzhiyun 	.remove		= myrb_remove,
3636*4882a593Smuzhiyun };
3637*4882a593Smuzhiyun 
myrb_init_module(void)3638*4882a593Smuzhiyun static int __init myrb_init_module(void)
3639*4882a593Smuzhiyun {
3640*4882a593Smuzhiyun 	int ret;
3641*4882a593Smuzhiyun 
3642*4882a593Smuzhiyun 	myrb_raid_template = raid_class_attach(&myrb_raid_functions);
3643*4882a593Smuzhiyun 	if (!myrb_raid_template)
3644*4882a593Smuzhiyun 		return -ENODEV;
3645*4882a593Smuzhiyun 
3646*4882a593Smuzhiyun 	ret = pci_register_driver(&myrb_pci_driver);
3647*4882a593Smuzhiyun 	if (ret)
3648*4882a593Smuzhiyun 		raid_class_release(myrb_raid_template);
3649*4882a593Smuzhiyun 
3650*4882a593Smuzhiyun 	return ret;
3651*4882a593Smuzhiyun }
3652*4882a593Smuzhiyun 
myrb_cleanup_module(void)3653*4882a593Smuzhiyun static void __exit myrb_cleanup_module(void)
3654*4882a593Smuzhiyun {
3655*4882a593Smuzhiyun 	pci_unregister_driver(&myrb_pci_driver);
3656*4882a593Smuzhiyun 	raid_class_release(myrb_raid_template);
3657*4882a593Smuzhiyun }
3658*4882a593Smuzhiyun 
3659*4882a593Smuzhiyun module_init(myrb_init_module);
3660*4882a593Smuzhiyun module_exit(myrb_cleanup_module);
3661*4882a593Smuzhiyun 
3662*4882a593Smuzhiyun MODULE_DESCRIPTION("Mylex DAC960/AcceleRAID/eXtremeRAID driver (Block interface)");
3663*4882a593Smuzhiyun MODULE_AUTHOR("Hannes Reinecke <hare@suse.com>");
3664*4882a593Smuzhiyun MODULE_LICENSE("GPL");
3665