1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Marvell 88SE64xx hardware specific head file 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2007 Red Hat, Inc. 6*4882a593Smuzhiyun * Copyright 2008 Marvell. <kewei@marvell.com> 7*4882a593Smuzhiyun * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _MVS64XX_REG_H_ 11*4882a593Smuzhiyun #define _MVS64XX_REG_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/types.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define MAX_LINK_RATE SAS_LINK_RATE_3_0_GBPS 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* enhanced mode registers (BAR4) */ 18*4882a593Smuzhiyun enum hw_registers { 19*4882a593Smuzhiyun MVS_GBL_CTL = 0x04, /* global control */ 20*4882a593Smuzhiyun MVS_GBL_INT_STAT = 0x08, /* global irq status */ 21*4882a593Smuzhiyun MVS_GBL_PI = 0x0C, /* ports implemented bitmask */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun MVS_PHY_CTL = 0x40, /* SOC PHY Control */ 24*4882a593Smuzhiyun MVS_PORTS_IMP = 0x9C, /* SOC Port Implemented */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun MVS_GBL_PORT_TYPE = 0xa0, /* port type */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun MVS_CTL = 0x100, /* SAS/SATA port configuration */ 29*4882a593Smuzhiyun MVS_PCS = 0x104, /* SAS/SATA port control/status */ 30*4882a593Smuzhiyun MVS_CMD_LIST_LO = 0x108, /* cmd list addr */ 31*4882a593Smuzhiyun MVS_CMD_LIST_HI = 0x10C, 32*4882a593Smuzhiyun MVS_RX_FIS_LO = 0x110, /* RX FIS list addr */ 33*4882a593Smuzhiyun MVS_RX_FIS_HI = 0x114, 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun MVS_TX_CFG = 0x120, /* TX configuration */ 36*4882a593Smuzhiyun MVS_TX_LO = 0x124, /* TX (delivery) ring addr */ 37*4882a593Smuzhiyun MVS_TX_HI = 0x128, 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun MVS_TX_PROD_IDX = 0x12C, /* TX producer pointer */ 40*4882a593Smuzhiyun MVS_TX_CONS_IDX = 0x130, /* TX consumer pointer (RO) */ 41*4882a593Smuzhiyun MVS_RX_CFG = 0x134, /* RX configuration */ 42*4882a593Smuzhiyun MVS_RX_LO = 0x138, /* RX (completion) ring addr */ 43*4882a593Smuzhiyun MVS_RX_HI = 0x13C, 44*4882a593Smuzhiyun MVS_RX_CONS_IDX = 0x140, /* RX consumer pointer (RO) */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun MVS_INT_COAL = 0x148, /* Int coalescing config */ 47*4882a593Smuzhiyun MVS_INT_COAL_TMOUT = 0x14C, /* Int coalescing timeout */ 48*4882a593Smuzhiyun MVS_INT_STAT = 0x150, /* Central int status */ 49*4882a593Smuzhiyun MVS_INT_MASK = 0x154, /* Central int enable */ 50*4882a593Smuzhiyun MVS_INT_STAT_SRS_0 = 0x158, /* SATA register set status */ 51*4882a593Smuzhiyun MVS_INT_MASK_SRS_0 = 0x15C, 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* ports 1-3 follow after this */ 54*4882a593Smuzhiyun MVS_P0_INT_STAT = 0x160, /* port0 interrupt status */ 55*4882a593Smuzhiyun MVS_P0_INT_MASK = 0x164, /* port0 interrupt mask */ 56*4882a593Smuzhiyun /* ports 5-7 follow after this */ 57*4882a593Smuzhiyun MVS_P4_INT_STAT = 0x200, /* Port4 interrupt status */ 58*4882a593Smuzhiyun MVS_P4_INT_MASK = 0x204, /* Port4 interrupt enable mask */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* ports 1-3 follow after this */ 61*4882a593Smuzhiyun MVS_P0_SER_CTLSTAT = 0x180, /* port0 serial control/status */ 62*4882a593Smuzhiyun /* ports 5-7 follow after this */ 63*4882a593Smuzhiyun MVS_P4_SER_CTLSTAT = 0x220, /* port4 serial control/status */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun MVS_CMD_ADDR = 0x1B8, /* Command register port (addr) */ 66*4882a593Smuzhiyun MVS_CMD_DATA = 0x1BC, /* Command register port (data) */ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* ports 1-3 follow after this */ 69*4882a593Smuzhiyun MVS_P0_CFG_ADDR = 0x1C0, /* port0 phy register address */ 70*4882a593Smuzhiyun MVS_P0_CFG_DATA = 0x1C4, /* port0 phy register data */ 71*4882a593Smuzhiyun /* ports 5-7 follow after this */ 72*4882a593Smuzhiyun MVS_P4_CFG_ADDR = 0x230, /* Port4 config address */ 73*4882a593Smuzhiyun MVS_P4_CFG_DATA = 0x234, /* Port4 config data */ 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* ports 1-3 follow after this */ 76*4882a593Smuzhiyun MVS_P0_VSR_ADDR = 0x1E0, /* port0 VSR address */ 77*4882a593Smuzhiyun MVS_P0_VSR_DATA = 0x1E4, /* port0 VSR data */ 78*4882a593Smuzhiyun /* ports 5-7 follow after this */ 79*4882a593Smuzhiyun MVS_P4_VSR_ADDR = 0x250, /* port4 VSR addr */ 80*4882a593Smuzhiyun MVS_P4_VSR_DATA = 0x254, /* port4 VSR data */ 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun enum pci_cfg_registers { 84*4882a593Smuzhiyun PCR_PHY_CTL = 0x40, 85*4882a593Smuzhiyun PCR_PHY_CTL2 = 0x90, 86*4882a593Smuzhiyun PCR_DEV_CTRL = 0xE8, 87*4882a593Smuzhiyun PCR_LINK_STAT = 0xF2, 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* SAS/SATA Vendor Specific Port Registers */ 91*4882a593Smuzhiyun enum sas_sata_vsp_regs { 92*4882a593Smuzhiyun VSR_PHY_STAT = 0x00, /* Phy Status */ 93*4882a593Smuzhiyun VSR_PHY_MODE1 = 0x01, /* phy tx */ 94*4882a593Smuzhiyun VSR_PHY_MODE2 = 0x02, /* tx scc */ 95*4882a593Smuzhiyun VSR_PHY_MODE3 = 0x03, /* pll */ 96*4882a593Smuzhiyun VSR_PHY_MODE4 = 0x04, /* VCO */ 97*4882a593Smuzhiyun VSR_PHY_MODE5 = 0x05, /* Rx */ 98*4882a593Smuzhiyun VSR_PHY_MODE6 = 0x06, /* CDR */ 99*4882a593Smuzhiyun VSR_PHY_MODE7 = 0x07, /* Impedance */ 100*4882a593Smuzhiyun VSR_PHY_MODE8 = 0x08, /* Voltage */ 101*4882a593Smuzhiyun VSR_PHY_MODE9 = 0x09, /* Test */ 102*4882a593Smuzhiyun VSR_PHY_MODE10 = 0x0A, /* Power */ 103*4882a593Smuzhiyun VSR_PHY_MODE11 = 0x0B, /* Phy Mode */ 104*4882a593Smuzhiyun VSR_PHY_VS0 = 0x0C, /* Vednor Specific 0 */ 105*4882a593Smuzhiyun VSR_PHY_VS1 = 0x0D, /* Vednor Specific 1 */ 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun enum chip_register_bits { 109*4882a593Smuzhiyun PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0xF << 8), 110*4882a593Smuzhiyun PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0xF << 12), 111*4882a593Smuzhiyun PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16), 112*4882a593Smuzhiyun PHY_NEG_SPP_PHYS_LINK_RATE_MASK = 113*4882a593Smuzhiyun (0xF << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET), 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #define MAX_SG_ENTRY 64 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun struct mvs_prd { 119*4882a593Smuzhiyun __le64 addr; /* 64-bit buffer address */ 120*4882a593Smuzhiyun __le32 reserved; 121*4882a593Smuzhiyun __le32 len; /* 16-bit length */ 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define SPI_CTRL_REG 0xc0 125*4882a593Smuzhiyun #define SPI_CTRL_VENDOR_ENABLE (1U<<29) 126*4882a593Smuzhiyun #define SPI_CTRL_SPIRDY (1U<<22) 127*4882a593Smuzhiyun #define SPI_CTRL_SPISTART (1U<<20) 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define SPI_CMD_REG 0xc4 130*4882a593Smuzhiyun #define SPI_DATA_REG 0xc8 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define SPI_CTRL_REG_64XX 0x10 133*4882a593Smuzhiyun #define SPI_CMD_REG_64XX 0x14 134*4882a593Smuzhiyun #define SPI_DATA_REG_64XX 0x18 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #endif 137