1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2000-2020 Broadcom Inc. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Name: mpi2_pci.h 6*4882a593Smuzhiyun * Title: MPI PCIe Attached Devices structures and definitions. 7*4882a593Smuzhiyun * Creation Date: October 9, 2012 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * mpi2_pci.h Version: 02.00.04 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 12*4882a593Smuzhiyun * prefix are for use only on MPI v2.5 products, and must not be used 13*4882a593Smuzhiyun * with MPI v2.0 products. Unless otherwise noted, names beginning with 14*4882a593Smuzhiyun * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * Version History 17*4882a593Smuzhiyun * --------------- 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * Date Version Description 20*4882a593Smuzhiyun * -------- -------- ------------------------------------------------------ 21*4882a593Smuzhiyun * 03-16-15 02.00.00 Initial version. 22*4882a593Smuzhiyun * 02-17-16 02.00.01 Removed AHCI support. 23*4882a593Smuzhiyun * Removed SOP support. 24*4882a593Smuzhiyun * 07-01-16 02.00.02 Added MPI26_NVME_FLAGS_FORCE_ADMIN_ERR_RESP to 25*4882a593Smuzhiyun * NVME Encapsulated Request. 26*4882a593Smuzhiyun * 07-22-18 02.00.03 Updted flags field for NVME Encapsulated req 27*4882a593Smuzhiyun * 12-17-18 02.00.04 Added MPI26_PCIE_DEVINFO_SCSI 28*4882a593Smuzhiyun * Shortten some defines to be compatible with DOS 29*4882a593Smuzhiyun * -------------------------------------------------------------------------- 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #ifndef MPI2_PCI_H 33*4882a593Smuzhiyun #define MPI2_PCI_H 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* 37*4882a593Smuzhiyun *Values for the PCIe DeviceInfo field used in PCIe Device Status Change Event 38*4882a593Smuzhiyun *data and PCIe Configuration pages. 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun #define MPI26_PCIE_DEVINFO_DIRECT_ATTACH (0x00000010) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define MPI26_PCIE_DEVINFO_MASK_DEVICE_TYPE (0x0000000F) 43*4882a593Smuzhiyun #define MPI26_PCIE_DEVINFO_NO_DEVICE (0x00000000) 44*4882a593Smuzhiyun #define MPI26_PCIE_DEVINFO_PCI_SWITCH (0x00000001) 45*4882a593Smuzhiyun #define MPI26_PCIE_DEVINFO_NVME (0x00000003) 46*4882a593Smuzhiyun #define MPI26_PCIE_DEVINFO_SCSI (0x00000004) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /**************************************************************************** 49*4882a593Smuzhiyun * NVMe Encapsulated message 50*4882a593Smuzhiyun ****************************************************************************/ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /*NVME Encapsulated Request Message */ 53*4882a593Smuzhiyun typedef struct _MPI26_NVME_ENCAPSULATED_REQUEST { 54*4882a593Smuzhiyun U16 DevHandle; /*0x00 */ 55*4882a593Smuzhiyun U8 ChainOffset; /*0x02 */ 56*4882a593Smuzhiyun U8 Function; /*0x03 */ 57*4882a593Smuzhiyun U16 EncapsulatedCommandLength; /*0x04 */ 58*4882a593Smuzhiyun U8 Reserved1; /*0x06 */ 59*4882a593Smuzhiyun U8 MsgFlags; /*0x07 */ 60*4882a593Smuzhiyun U8 VP_ID; /*0x08 */ 61*4882a593Smuzhiyun U8 VF_ID; /*0x09 */ 62*4882a593Smuzhiyun U16 Reserved2; /*0x0A */ 63*4882a593Smuzhiyun U32 Reserved3; /*0x0C */ 64*4882a593Smuzhiyun U64 ErrorResponseBaseAddress; /*0x10 */ 65*4882a593Smuzhiyun U16 ErrorResponseAllocationLength; /*0x18 */ 66*4882a593Smuzhiyun U16 Flags; /*0x1A */ 67*4882a593Smuzhiyun U32 DataLength; /*0x1C */ 68*4882a593Smuzhiyun U8 NVMe_Command[4]; /*0x20 */ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun } MPI26_NVME_ENCAPSULATED_REQUEST, *PTR_MPI26_NVME_ENCAPSULATED_REQUEST, 71*4882a593Smuzhiyun Mpi26NVMeEncapsulatedRequest_t, *pMpi26NVMeEncapsulatedRequest_t; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /*defines for the Flags field */ 74*4882a593Smuzhiyun #define MPI26_NVME_FLAGS_FORCE_ADMIN_ERR_RESP (0x0020) 75*4882a593Smuzhiyun /*Submission Queue Type*/ 76*4882a593Smuzhiyun #define MPI26_NVME_FLAGS_SUBMISSIONQ_MASK (0x0010) 77*4882a593Smuzhiyun #define MPI26_NVME_FLAGS_SUBMISSIONQ_IO (0x0000) 78*4882a593Smuzhiyun #define MPI26_NVME_FLAGS_SUBMISSIONQ_ADMIN (0x0010) 79*4882a593Smuzhiyun /*Error Response Address Space */ 80*4882a593Smuzhiyun #define MPI26_NVME_FLAGS_ERR_RSP_ADDR_MASK (0x000C) 81*4882a593Smuzhiyun #define MPI26_NVME_FLAGS_ERR_RSP_ADDR_SYSTEM (0x0000) 82*4882a593Smuzhiyun #define MPI26_NVME_FLAGS_ERR_RSP_ADDR_IOCTL (0x0008) 83*4882a593Smuzhiyun /* Data Direction*/ 84*4882a593Smuzhiyun #define MPI26_NVME_FLAGS_DATADIRECTION_MASK (0x0003) 85*4882a593Smuzhiyun #define MPI26_NVME_FLAGS_NODATATRANSFER (0x0000) 86*4882a593Smuzhiyun #define MPI26_NVME_FLAGS_WRITE (0x0001) 87*4882a593Smuzhiyun #define MPI26_NVME_FLAGS_READ (0x0002) 88*4882a593Smuzhiyun #define MPI26_NVME_FLAGS_BIDIRECTIONAL (0x0003) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /*NVMe Encapuslated Reply Message */ 92*4882a593Smuzhiyun typedef struct _MPI26_NVME_ENCAPSULATED_ERROR_REPLY { 93*4882a593Smuzhiyun U16 DevHandle; /*0x00 */ 94*4882a593Smuzhiyun U8 MsgLength; /*0x02 */ 95*4882a593Smuzhiyun U8 Function; /*0x03 */ 96*4882a593Smuzhiyun U16 EncapsulatedCommandLength; /*0x04 */ 97*4882a593Smuzhiyun U8 Reserved1; /*0x06 */ 98*4882a593Smuzhiyun U8 MsgFlags; /*0x07 */ 99*4882a593Smuzhiyun U8 VP_ID; /*0x08 */ 100*4882a593Smuzhiyun U8 VF_ID; /*0x09 */ 101*4882a593Smuzhiyun U16 Reserved2; /*0x0A */ 102*4882a593Smuzhiyun U16 Reserved3; /*0x0C */ 103*4882a593Smuzhiyun U16 IOCStatus; /*0x0E */ 104*4882a593Smuzhiyun U32 IOCLogInfo; /*0x10 */ 105*4882a593Smuzhiyun U16 ErrorResponseCount; /*0x14 */ 106*4882a593Smuzhiyun U16 Reserved4; /*0x16 */ 107*4882a593Smuzhiyun } MPI26_NVME_ENCAPSULATED_ERROR_REPLY, 108*4882a593Smuzhiyun *PTR_MPI26_NVME_ENCAPSULATED_ERROR_REPLY, 109*4882a593Smuzhiyun Mpi26NVMeEncapsulatedErrorReply_t, 110*4882a593Smuzhiyun *pMpi26NVMeEncapsulatedErrorReply_t; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #endif 114