1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * mesh.h: definitions for the driver for the MESH SCSI bus adaptor 4*4882a593Smuzhiyun * (Macintosh Enhanced SCSI Hardware) found on Power Macintosh computers. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 1996 Paul Mackerras. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef _MESH_H 9*4882a593Smuzhiyun #define _MESH_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Registers in the MESH controller. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct mesh_regs { 16*4882a593Smuzhiyun unsigned char count_lo; 17*4882a593Smuzhiyun char pad0[15]; 18*4882a593Smuzhiyun unsigned char count_hi; 19*4882a593Smuzhiyun char pad1[15]; 20*4882a593Smuzhiyun unsigned char fifo; 21*4882a593Smuzhiyun char pad2[15]; 22*4882a593Smuzhiyun unsigned char sequence; 23*4882a593Smuzhiyun char pad3[15]; 24*4882a593Smuzhiyun unsigned char bus_status0; 25*4882a593Smuzhiyun char pad4[15]; 26*4882a593Smuzhiyun unsigned char bus_status1; 27*4882a593Smuzhiyun char pad5[15]; 28*4882a593Smuzhiyun unsigned char fifo_count; 29*4882a593Smuzhiyun char pad6[15]; 30*4882a593Smuzhiyun unsigned char exception; 31*4882a593Smuzhiyun char pad7[15]; 32*4882a593Smuzhiyun unsigned char error; 33*4882a593Smuzhiyun char pad8[15]; 34*4882a593Smuzhiyun unsigned char intr_mask; 35*4882a593Smuzhiyun char pad9[15]; 36*4882a593Smuzhiyun unsigned char interrupt; 37*4882a593Smuzhiyun char pad10[15]; 38*4882a593Smuzhiyun unsigned char source_id; 39*4882a593Smuzhiyun char pad11[15]; 40*4882a593Smuzhiyun unsigned char dest_id; 41*4882a593Smuzhiyun char pad12[15]; 42*4882a593Smuzhiyun unsigned char sync_params; 43*4882a593Smuzhiyun char pad13[15]; 44*4882a593Smuzhiyun unsigned char mesh_id; 45*4882a593Smuzhiyun char pad14[15]; 46*4882a593Smuzhiyun unsigned char sel_timeout; 47*4882a593Smuzhiyun char pad15[15]; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* Bits in the sequence register. */ 51*4882a593Smuzhiyun #define SEQ_DMA_MODE 0x80 /* use DMA for data transfer */ 52*4882a593Smuzhiyun #define SEQ_TARGET 0x40 /* put the controller into target mode */ 53*4882a593Smuzhiyun #define SEQ_ATN 0x20 /* assert ATN signal */ 54*4882a593Smuzhiyun #define SEQ_ACTIVE_NEG 0x10 /* use active negation on REQ/ACK */ 55*4882a593Smuzhiyun #define SEQ_CMD 0x0f /* command bits: */ 56*4882a593Smuzhiyun #define SEQ_ARBITRATE 1 /* get the bus */ 57*4882a593Smuzhiyun #define SEQ_SELECT 2 /* select a target */ 58*4882a593Smuzhiyun #define SEQ_COMMAND 3 /* send a command */ 59*4882a593Smuzhiyun #define SEQ_STATUS 4 /* receive status */ 60*4882a593Smuzhiyun #define SEQ_DATAOUT 5 /* send data */ 61*4882a593Smuzhiyun #define SEQ_DATAIN 6 /* receive data */ 62*4882a593Smuzhiyun #define SEQ_MSGOUT 7 /* send a message */ 63*4882a593Smuzhiyun #define SEQ_MSGIN 8 /* receive a message */ 64*4882a593Smuzhiyun #define SEQ_BUSFREE 9 /* look for bus free */ 65*4882a593Smuzhiyun #define SEQ_ENBPARITY 0x0a /* enable parity checking */ 66*4882a593Smuzhiyun #define SEQ_DISPARITY 0x0b /* disable parity checking */ 67*4882a593Smuzhiyun #define SEQ_ENBRESEL 0x0c /* enable reselection */ 68*4882a593Smuzhiyun #define SEQ_DISRESEL 0x0d /* disable reselection */ 69*4882a593Smuzhiyun #define SEQ_RESETMESH 0x0e /* reset the controller */ 70*4882a593Smuzhiyun #define SEQ_FLUSHFIFO 0x0f /* clear out the FIFO */ 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* Bits in the bus_status0 and bus_status1 registers: 73*4882a593Smuzhiyun these correspond directly to the SCSI bus control signals. */ 74*4882a593Smuzhiyun #define BS0_REQ 0x20 75*4882a593Smuzhiyun #define BS0_ACK 0x10 76*4882a593Smuzhiyun #define BS0_ATN 0x08 77*4882a593Smuzhiyun #define BS0_MSG 0x04 78*4882a593Smuzhiyun #define BS0_CD 0x02 79*4882a593Smuzhiyun #define BS0_IO 0x01 80*4882a593Smuzhiyun #define BS1_RST 0x80 81*4882a593Smuzhiyun #define BS1_BSY 0x40 82*4882a593Smuzhiyun #define BS1_SEL 0x20 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* Bus phases defined by the bits in bus_status0 */ 85*4882a593Smuzhiyun #define BS0_PHASE (BS0_MSG+BS0_CD+BS0_IO) 86*4882a593Smuzhiyun #define BP_DATAOUT 0 87*4882a593Smuzhiyun #define BP_DATAIN BS0_IO 88*4882a593Smuzhiyun #define BP_COMMAND BS0_CD 89*4882a593Smuzhiyun #define BP_STATUS (BS0_CD+BS0_IO) 90*4882a593Smuzhiyun #define BP_MSGOUT (BS0_MSG+BS0_CD) 91*4882a593Smuzhiyun #define BP_MSGIN (BS0_MSG+BS0_CD+BS0_IO) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* Bits in the exception register. */ 94*4882a593Smuzhiyun #define EXC_SELWATN 0x20 /* (as target) we were selected with ATN */ 95*4882a593Smuzhiyun #define EXC_SELECTED 0x10 /* (as target) we were selected w/o ATN */ 96*4882a593Smuzhiyun #define EXC_RESELECTED 0x08 /* (as initiator) we were reselected */ 97*4882a593Smuzhiyun #define EXC_ARBLOST 0x04 /* we lost arbitration */ 98*4882a593Smuzhiyun #define EXC_PHASEMM 0x02 /* SCSI phase mismatch */ 99*4882a593Smuzhiyun #define EXC_SELTO 0x01 /* selection timeout */ 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* Bits in the error register */ 102*4882a593Smuzhiyun #define ERR_UNEXPDISC 0x40 /* target unexpectedly disconnected */ 103*4882a593Smuzhiyun #define ERR_SCSIRESET 0x20 /* SCSI bus got reset on us */ 104*4882a593Smuzhiyun #define ERR_SEQERR 0x10 /* we did something the chip didn't like */ 105*4882a593Smuzhiyun #define ERR_PARITY 0x01 /* parity error was detected */ 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* Bits in the interrupt and intr_mask registers */ 108*4882a593Smuzhiyun #define INT_ERROR 0x04 /* error interrupt */ 109*4882a593Smuzhiyun #define INT_EXCEPTION 0x02 /* exception interrupt */ 110*4882a593Smuzhiyun #define INT_CMDDONE 0x01 /* command done interrupt */ 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* Fields in the sync_params register */ 113*4882a593Smuzhiyun #define SYNC_OFF(x) ((x) >> 4) /* offset field */ 114*4882a593Smuzhiyun #define SYNC_PER(x) ((x) & 0xf) /* period field */ 115*4882a593Smuzhiyun #define SYNC_PARAMS(o, p) (((o) << 4) | (p)) 116*4882a593Smuzhiyun #define ASYNC_PARAMS 2 /* sync_params value for async xfers */ 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* 119*4882a593Smuzhiyun * Assuming a clock frequency of 50MHz: 120*4882a593Smuzhiyun * 121*4882a593Smuzhiyun * The transfer period with SYNC_PER(sync_params) == x 122*4882a593Smuzhiyun * is (x + 2) * 40ns, except that x == 0 gives 100ns. 123*4882a593Smuzhiyun * 124*4882a593Smuzhiyun * The units of the sel_timeout register are 10ms. 125*4882a593Smuzhiyun */ 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #endif /* _MESH_H */ 129