1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Linux MegaRAID driver for SAS based RAID controllers
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2009-2013 LSI Corporation
6*4882a593Smuzhiyun * Copyright (c) 2013-2016 Avago Technologies
7*4882a593Smuzhiyun * Copyright (c) 2016-2018 Broadcom Inc.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * FILE: megaraid_sas_fp.c
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Authors: Broadcom Inc.
12*4882a593Smuzhiyun * Sumant Patro
13*4882a593Smuzhiyun * Varad Talamacki
14*4882a593Smuzhiyun * Manoj Jose
15*4882a593Smuzhiyun * Kashyap Desai <kashyap.desai@broadcom.com>
16*4882a593Smuzhiyun * Sumit Saxena <sumit.saxena@broadcom.com>
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * Send feedback to: megaraidlinux.pdl@broadcom.com
19*4882a593Smuzhiyun */
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <linux/kernel.h>
22*4882a593Smuzhiyun #include <linux/types.h>
23*4882a593Smuzhiyun #include <linux/pci.h>
24*4882a593Smuzhiyun #include <linux/list.h>
25*4882a593Smuzhiyun #include <linux/moduleparam.h>
26*4882a593Smuzhiyun #include <linux/module.h>
27*4882a593Smuzhiyun #include <linux/spinlock.h>
28*4882a593Smuzhiyun #include <linux/interrupt.h>
29*4882a593Smuzhiyun #include <linux/delay.h>
30*4882a593Smuzhiyun #include <linux/uio.h>
31*4882a593Smuzhiyun #include <linux/uaccess.h>
32*4882a593Smuzhiyun #include <linux/fs.h>
33*4882a593Smuzhiyun #include <linux/compat.h>
34*4882a593Smuzhiyun #include <linux/blkdev.h>
35*4882a593Smuzhiyun #include <linux/poll.h>
36*4882a593Smuzhiyun #include <linux/irq_poll.h>
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #include <scsi/scsi.h>
39*4882a593Smuzhiyun #include <scsi/scsi_cmnd.h>
40*4882a593Smuzhiyun #include <scsi/scsi_device.h>
41*4882a593Smuzhiyun #include <scsi/scsi_host.h>
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #include "megaraid_sas_fusion.h"
44*4882a593Smuzhiyun #include "megaraid_sas.h"
45*4882a593Smuzhiyun #include <asm/div64.h>
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define LB_PENDING_CMDS_DEFAULT 4
48*4882a593Smuzhiyun static unsigned int lb_pending_cmds = LB_PENDING_CMDS_DEFAULT;
49*4882a593Smuzhiyun module_param(lb_pending_cmds, int, 0444);
50*4882a593Smuzhiyun MODULE_PARM_DESC(lb_pending_cmds, "Change raid-1 load balancing outstanding "
51*4882a593Smuzhiyun "threshold. Valid Values are 1-128. Default: 4");
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define ABS_DIFF(a, b) (((a) > (b)) ? ((a) - (b)) : ((b) - (a)))
55*4882a593Smuzhiyun #define MR_LD_STATE_OPTIMAL 3
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #define SPAN_ROW_SIZE(map, ld, index_) (MR_LdSpanPtrGet(ld, index_, map)->spanRowSize)
58*4882a593Smuzhiyun #define SPAN_ROW_DATA_SIZE(map_, ld, index_) (MR_LdSpanPtrGet(ld, index_, map)->spanRowDataSize)
59*4882a593Smuzhiyun #define SPAN_INVALID 0xff
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* Prototypes */
62*4882a593Smuzhiyun static void mr_update_span_set(struct MR_DRV_RAID_MAP_ALL *map,
63*4882a593Smuzhiyun PLD_SPAN_INFO ldSpanInfo);
64*4882a593Smuzhiyun static u8 mr_spanset_get_phy_params(struct megasas_instance *instance, u32 ld,
65*4882a593Smuzhiyun u64 stripRow, u16 stripRef, struct IO_REQUEST_INFO *io_info,
66*4882a593Smuzhiyun struct RAID_CONTEXT *pRAID_Context, struct MR_DRV_RAID_MAP_ALL *map);
67*4882a593Smuzhiyun static u64 get_row_from_strip(struct megasas_instance *instance, u32 ld,
68*4882a593Smuzhiyun u64 strip, struct MR_DRV_RAID_MAP_ALL *map);
69*4882a593Smuzhiyun
mega_mod64(u64 dividend,u32 divisor)70*4882a593Smuzhiyun u32 mega_mod64(u64 dividend, u32 divisor)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun u64 d;
73*4882a593Smuzhiyun u32 remainder;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun if (!divisor)
76*4882a593Smuzhiyun printk(KERN_ERR "megasas : DIVISOR is zero, in div fn\n");
77*4882a593Smuzhiyun d = dividend;
78*4882a593Smuzhiyun remainder = do_div(d, divisor);
79*4882a593Smuzhiyun return remainder;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /**
83*4882a593Smuzhiyun * mega_div64_32 - Do a 64-bit division
84*4882a593Smuzhiyun * @dividend: Dividend
85*4882a593Smuzhiyun * @divisor: Divisor
86*4882a593Smuzhiyun *
87*4882a593Smuzhiyun * @return quotient
88*4882a593Smuzhiyun **/
mega_div64_32(uint64_t dividend,uint32_t divisor)89*4882a593Smuzhiyun static u64 mega_div64_32(uint64_t dividend, uint32_t divisor)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun u64 d = dividend;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun if (!divisor)
94*4882a593Smuzhiyun printk(KERN_ERR "megasas : DIVISOR is zero in mod fn\n");
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun do_div(d, divisor);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun return d;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
MR_LdRaidGet(u32 ld,struct MR_DRV_RAID_MAP_ALL * map)101*4882a593Smuzhiyun struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun return &map->raidMap.ldSpanMap[ld].ldRaid;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
MR_LdSpanInfoGet(u32 ld,struct MR_DRV_RAID_MAP_ALL * map)106*4882a593Smuzhiyun static struct MR_SPAN_BLOCK_INFO *MR_LdSpanInfoGet(u32 ld,
107*4882a593Smuzhiyun struct MR_DRV_RAID_MAP_ALL
108*4882a593Smuzhiyun *map)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun return &map->raidMap.ldSpanMap[ld].spanBlock[0];
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
MR_LdDataArmGet(u32 ld,u32 armIdx,struct MR_DRV_RAID_MAP_ALL * map)113*4882a593Smuzhiyun static u8 MR_LdDataArmGet(u32 ld, u32 armIdx, struct MR_DRV_RAID_MAP_ALL *map)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun return map->raidMap.ldSpanMap[ld].dataArmMap[armIdx];
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
MR_ArPdGet(u32 ar,u32 arm,struct MR_DRV_RAID_MAP_ALL * map)118*4882a593Smuzhiyun u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun return le16_to_cpu(map->raidMap.arMapInfo[ar].pd[arm]);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
MR_LdSpanArrayGet(u32 ld,u32 span,struct MR_DRV_RAID_MAP_ALL * map)123*4882a593Smuzhiyun u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun return le16_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span].span.arrayRef);
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
MR_PdDevHandleGet(u32 pd,struct MR_DRV_RAID_MAP_ALL * map)128*4882a593Smuzhiyun __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun return map->raidMap.devHndlInfo[pd].curDevHdl;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
MR_PdInterfaceTypeGet(u32 pd,struct MR_DRV_RAID_MAP_ALL * map)133*4882a593Smuzhiyun static u8 MR_PdInterfaceTypeGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun return map->raidMap.devHndlInfo[pd].interfaceType;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
MR_GetLDTgtId(u32 ld,struct MR_DRV_RAID_MAP_ALL * map)138*4882a593Smuzhiyun u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun return le16_to_cpu(map->raidMap.ldSpanMap[ld].ldRaid.targetId);
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
MR_TargetIdToLdGet(u32 ldTgtId,struct MR_DRV_RAID_MAP_ALL * map)143*4882a593Smuzhiyun u16 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun return map->raidMap.ldTgtIdToLd[ldTgtId];
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
MR_LdSpanPtrGet(u32 ld,u32 span,struct MR_DRV_RAID_MAP_ALL * map)148*4882a593Smuzhiyun static struct MR_LD_SPAN *MR_LdSpanPtrGet(u32 ld, u32 span,
149*4882a593Smuzhiyun struct MR_DRV_RAID_MAP_ALL *map)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun return &map->raidMap.ldSpanMap[ld].spanBlock[span].span;
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun /*
155*4882a593Smuzhiyun * This function will Populate Driver Map using firmware raid map
156*4882a593Smuzhiyun */
MR_PopulateDrvRaidMap(struct megasas_instance * instance,u64 map_id)157*4882a593Smuzhiyun static int MR_PopulateDrvRaidMap(struct megasas_instance *instance, u64 map_id)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun struct fusion_context *fusion = instance->ctrl_context;
160*4882a593Smuzhiyun struct MR_FW_RAID_MAP_ALL *fw_map_old = NULL;
161*4882a593Smuzhiyun struct MR_FW_RAID_MAP *pFwRaidMap = NULL;
162*4882a593Smuzhiyun int i, j;
163*4882a593Smuzhiyun u16 ld_count;
164*4882a593Smuzhiyun struct MR_FW_RAID_MAP_DYNAMIC *fw_map_dyn;
165*4882a593Smuzhiyun struct MR_FW_RAID_MAP_EXT *fw_map_ext;
166*4882a593Smuzhiyun struct MR_RAID_MAP_DESC_TABLE *desc_table;
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun struct MR_DRV_RAID_MAP_ALL *drv_map =
170*4882a593Smuzhiyun fusion->ld_drv_map[(map_id & 1)];
171*4882a593Smuzhiyun struct MR_DRV_RAID_MAP *pDrvRaidMap = &drv_map->raidMap;
172*4882a593Smuzhiyun void *raid_map_data = NULL;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun memset(drv_map, 0, fusion->drv_map_sz);
175*4882a593Smuzhiyun memset(pDrvRaidMap->ldTgtIdToLd,
176*4882a593Smuzhiyun 0xff, (sizeof(u16) * MAX_LOGICAL_DRIVES_DYN));
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun if (instance->max_raid_mapsize) {
179*4882a593Smuzhiyun fw_map_dyn = fusion->ld_map[(map_id & 1)];
180*4882a593Smuzhiyun desc_table =
181*4882a593Smuzhiyun (struct MR_RAID_MAP_DESC_TABLE *)((void *)fw_map_dyn + le32_to_cpu(fw_map_dyn->desc_table_offset));
182*4882a593Smuzhiyun if (desc_table != fw_map_dyn->raid_map_desc_table)
183*4882a593Smuzhiyun dev_dbg(&instance->pdev->dev, "offsets of desc table are not matching desc %p original %p\n",
184*4882a593Smuzhiyun desc_table, fw_map_dyn->raid_map_desc_table);
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun ld_count = (u16)le16_to_cpu(fw_map_dyn->ld_count);
187*4882a593Smuzhiyun pDrvRaidMap->ldCount = (__le16)cpu_to_le16(ld_count);
188*4882a593Smuzhiyun pDrvRaidMap->fpPdIoTimeoutSec =
189*4882a593Smuzhiyun fw_map_dyn->fp_pd_io_timeout_sec;
190*4882a593Smuzhiyun pDrvRaidMap->totalSize =
191*4882a593Smuzhiyun cpu_to_le32(sizeof(struct MR_DRV_RAID_MAP_ALL));
192*4882a593Smuzhiyun /* point to actual data starting point*/
193*4882a593Smuzhiyun raid_map_data = (void *)fw_map_dyn +
194*4882a593Smuzhiyun le32_to_cpu(fw_map_dyn->desc_table_offset) +
195*4882a593Smuzhiyun le32_to_cpu(fw_map_dyn->desc_table_size);
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun for (i = 0; i < le32_to_cpu(fw_map_dyn->desc_table_num_elements); ++i) {
198*4882a593Smuzhiyun switch (le32_to_cpu(desc_table->raid_map_desc_type)) {
199*4882a593Smuzhiyun case RAID_MAP_DESC_TYPE_DEVHDL_INFO:
200*4882a593Smuzhiyun fw_map_dyn->dev_hndl_info =
201*4882a593Smuzhiyun (struct MR_DEV_HANDLE_INFO *)(raid_map_data + le32_to_cpu(desc_table->raid_map_desc_offset));
202*4882a593Smuzhiyun memcpy(pDrvRaidMap->devHndlInfo,
203*4882a593Smuzhiyun fw_map_dyn->dev_hndl_info,
204*4882a593Smuzhiyun sizeof(struct MR_DEV_HANDLE_INFO) *
205*4882a593Smuzhiyun le32_to_cpu(desc_table->raid_map_desc_elements));
206*4882a593Smuzhiyun break;
207*4882a593Smuzhiyun case RAID_MAP_DESC_TYPE_TGTID_INFO:
208*4882a593Smuzhiyun fw_map_dyn->ld_tgt_id_to_ld =
209*4882a593Smuzhiyun (u16 *)(raid_map_data +
210*4882a593Smuzhiyun le32_to_cpu(desc_table->raid_map_desc_offset));
211*4882a593Smuzhiyun for (j = 0; j < le32_to_cpu(desc_table->raid_map_desc_elements); j++) {
212*4882a593Smuzhiyun pDrvRaidMap->ldTgtIdToLd[j] =
213*4882a593Smuzhiyun le16_to_cpu(fw_map_dyn->ld_tgt_id_to_ld[j]);
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun break;
216*4882a593Smuzhiyun case RAID_MAP_DESC_TYPE_ARRAY_INFO:
217*4882a593Smuzhiyun fw_map_dyn->ar_map_info =
218*4882a593Smuzhiyun (struct MR_ARRAY_INFO *)
219*4882a593Smuzhiyun (raid_map_data + le32_to_cpu(desc_table->raid_map_desc_offset));
220*4882a593Smuzhiyun memcpy(pDrvRaidMap->arMapInfo,
221*4882a593Smuzhiyun fw_map_dyn->ar_map_info,
222*4882a593Smuzhiyun sizeof(struct MR_ARRAY_INFO) *
223*4882a593Smuzhiyun le32_to_cpu(desc_table->raid_map_desc_elements));
224*4882a593Smuzhiyun break;
225*4882a593Smuzhiyun case RAID_MAP_DESC_TYPE_SPAN_INFO:
226*4882a593Smuzhiyun fw_map_dyn->ld_span_map =
227*4882a593Smuzhiyun (struct MR_LD_SPAN_MAP *)
228*4882a593Smuzhiyun (raid_map_data +
229*4882a593Smuzhiyun le32_to_cpu(desc_table->raid_map_desc_offset));
230*4882a593Smuzhiyun memcpy(pDrvRaidMap->ldSpanMap,
231*4882a593Smuzhiyun fw_map_dyn->ld_span_map,
232*4882a593Smuzhiyun sizeof(struct MR_LD_SPAN_MAP) *
233*4882a593Smuzhiyun le32_to_cpu(desc_table->raid_map_desc_elements));
234*4882a593Smuzhiyun break;
235*4882a593Smuzhiyun default:
236*4882a593Smuzhiyun dev_dbg(&instance->pdev->dev, "wrong number of desctableElements %d\n",
237*4882a593Smuzhiyun fw_map_dyn->desc_table_num_elements);
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun ++desc_table;
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun } else if (instance->supportmax256vd) {
243*4882a593Smuzhiyun fw_map_ext =
244*4882a593Smuzhiyun (struct MR_FW_RAID_MAP_EXT *)fusion->ld_map[(map_id & 1)];
245*4882a593Smuzhiyun ld_count = (u16)le16_to_cpu(fw_map_ext->ldCount);
246*4882a593Smuzhiyun if (ld_count > MAX_LOGICAL_DRIVES_EXT) {
247*4882a593Smuzhiyun dev_dbg(&instance->pdev->dev, "megaraid_sas: LD count exposed in RAID map in not valid\n");
248*4882a593Smuzhiyun return 1;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun pDrvRaidMap->ldCount = (__le16)cpu_to_le16(ld_count);
252*4882a593Smuzhiyun pDrvRaidMap->fpPdIoTimeoutSec = fw_map_ext->fpPdIoTimeoutSec;
253*4882a593Smuzhiyun for (i = 0; i < (MAX_LOGICAL_DRIVES_EXT); i++)
254*4882a593Smuzhiyun pDrvRaidMap->ldTgtIdToLd[i] =
255*4882a593Smuzhiyun (u16)fw_map_ext->ldTgtIdToLd[i];
256*4882a593Smuzhiyun memcpy(pDrvRaidMap->ldSpanMap, fw_map_ext->ldSpanMap,
257*4882a593Smuzhiyun sizeof(struct MR_LD_SPAN_MAP) * ld_count);
258*4882a593Smuzhiyun memcpy(pDrvRaidMap->arMapInfo, fw_map_ext->arMapInfo,
259*4882a593Smuzhiyun sizeof(struct MR_ARRAY_INFO) * MAX_API_ARRAYS_EXT);
260*4882a593Smuzhiyun memcpy(pDrvRaidMap->devHndlInfo, fw_map_ext->devHndlInfo,
261*4882a593Smuzhiyun sizeof(struct MR_DEV_HANDLE_INFO) *
262*4882a593Smuzhiyun MAX_RAIDMAP_PHYSICAL_DEVICES);
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun /* New Raid map will not set totalSize, so keep expected value
265*4882a593Smuzhiyun * for legacy code in ValidateMapInfo
266*4882a593Smuzhiyun */
267*4882a593Smuzhiyun pDrvRaidMap->totalSize =
268*4882a593Smuzhiyun cpu_to_le32(sizeof(struct MR_FW_RAID_MAP_EXT));
269*4882a593Smuzhiyun } else {
270*4882a593Smuzhiyun fw_map_old = (struct MR_FW_RAID_MAP_ALL *)
271*4882a593Smuzhiyun fusion->ld_map[(map_id & 1)];
272*4882a593Smuzhiyun pFwRaidMap = &fw_map_old->raidMap;
273*4882a593Smuzhiyun ld_count = (u16)le32_to_cpu(pFwRaidMap->ldCount);
274*4882a593Smuzhiyun if (ld_count > MAX_LOGICAL_DRIVES) {
275*4882a593Smuzhiyun dev_dbg(&instance->pdev->dev,
276*4882a593Smuzhiyun "LD count exposed in RAID map in not valid\n");
277*4882a593Smuzhiyun return 1;
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun pDrvRaidMap->totalSize = pFwRaidMap->totalSize;
281*4882a593Smuzhiyun pDrvRaidMap->ldCount = (__le16)cpu_to_le16(ld_count);
282*4882a593Smuzhiyun pDrvRaidMap->fpPdIoTimeoutSec = pFwRaidMap->fpPdIoTimeoutSec;
283*4882a593Smuzhiyun for (i = 0; i < MAX_RAIDMAP_LOGICAL_DRIVES + MAX_RAIDMAP_VIEWS; i++)
284*4882a593Smuzhiyun pDrvRaidMap->ldTgtIdToLd[i] =
285*4882a593Smuzhiyun (u8)pFwRaidMap->ldTgtIdToLd[i];
286*4882a593Smuzhiyun for (i = 0; i < ld_count; i++) {
287*4882a593Smuzhiyun pDrvRaidMap->ldSpanMap[i] = pFwRaidMap->ldSpanMap[i];
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun memcpy(pDrvRaidMap->arMapInfo, pFwRaidMap->arMapInfo,
290*4882a593Smuzhiyun sizeof(struct MR_ARRAY_INFO) * MAX_RAIDMAP_ARRAYS);
291*4882a593Smuzhiyun memcpy(pDrvRaidMap->devHndlInfo, pFwRaidMap->devHndlInfo,
292*4882a593Smuzhiyun sizeof(struct MR_DEV_HANDLE_INFO) *
293*4882a593Smuzhiyun MAX_RAIDMAP_PHYSICAL_DEVICES);
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun return 0;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun /*
300*4882a593Smuzhiyun * This function will validate Map info data provided by FW
301*4882a593Smuzhiyun */
MR_ValidateMapInfo(struct megasas_instance * instance,u64 map_id)302*4882a593Smuzhiyun u8 MR_ValidateMapInfo(struct megasas_instance *instance, u64 map_id)
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun struct fusion_context *fusion;
305*4882a593Smuzhiyun struct MR_DRV_RAID_MAP_ALL *drv_map;
306*4882a593Smuzhiyun struct MR_DRV_RAID_MAP *pDrvRaidMap;
307*4882a593Smuzhiyun struct LD_LOAD_BALANCE_INFO *lbInfo;
308*4882a593Smuzhiyun PLD_SPAN_INFO ldSpanInfo;
309*4882a593Smuzhiyun struct MR_LD_RAID *raid;
310*4882a593Smuzhiyun u16 num_lds, i;
311*4882a593Smuzhiyun u16 ld;
312*4882a593Smuzhiyun u32 expected_size;
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun if (MR_PopulateDrvRaidMap(instance, map_id))
315*4882a593Smuzhiyun return 0;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun fusion = instance->ctrl_context;
318*4882a593Smuzhiyun drv_map = fusion->ld_drv_map[(map_id & 1)];
319*4882a593Smuzhiyun pDrvRaidMap = &drv_map->raidMap;
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun lbInfo = fusion->load_balance_info;
322*4882a593Smuzhiyun ldSpanInfo = fusion->log_to_span;
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun if (instance->max_raid_mapsize)
325*4882a593Smuzhiyun expected_size = sizeof(struct MR_DRV_RAID_MAP_ALL);
326*4882a593Smuzhiyun else if (instance->supportmax256vd)
327*4882a593Smuzhiyun expected_size = sizeof(struct MR_FW_RAID_MAP_EXT);
328*4882a593Smuzhiyun else
329*4882a593Smuzhiyun expected_size =
330*4882a593Smuzhiyun (sizeof(struct MR_FW_RAID_MAP) - sizeof(struct MR_LD_SPAN_MAP) +
331*4882a593Smuzhiyun (sizeof(struct MR_LD_SPAN_MAP) * le16_to_cpu(pDrvRaidMap->ldCount)));
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun if (le32_to_cpu(pDrvRaidMap->totalSize) != expected_size) {
334*4882a593Smuzhiyun dev_dbg(&instance->pdev->dev, "megasas: map info structure size 0x%x",
335*4882a593Smuzhiyun le32_to_cpu(pDrvRaidMap->totalSize));
336*4882a593Smuzhiyun dev_dbg(&instance->pdev->dev, "is not matching expected size 0x%x\n",
337*4882a593Smuzhiyun (unsigned int)expected_size);
338*4882a593Smuzhiyun dev_err(&instance->pdev->dev, "megasas: span map %x, pDrvRaidMap->totalSize : %x\n",
339*4882a593Smuzhiyun (unsigned int)sizeof(struct MR_LD_SPAN_MAP),
340*4882a593Smuzhiyun le32_to_cpu(pDrvRaidMap->totalSize));
341*4882a593Smuzhiyun return 0;
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun if (instance->UnevenSpanSupport)
345*4882a593Smuzhiyun mr_update_span_set(drv_map, ldSpanInfo);
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun if (lbInfo)
348*4882a593Smuzhiyun mr_update_load_balance_params(drv_map, lbInfo);
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun num_lds = le16_to_cpu(drv_map->raidMap.ldCount);
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun memcpy(instance->ld_ids_prev,
353*4882a593Smuzhiyun instance->ld_ids_from_raidmap,
354*4882a593Smuzhiyun sizeof(instance->ld_ids_from_raidmap));
355*4882a593Smuzhiyun memset(instance->ld_ids_from_raidmap, 0xff, MEGASAS_MAX_LD_IDS);
356*4882a593Smuzhiyun /*Convert Raid capability values to CPU arch */
357*4882a593Smuzhiyun for (i = 0; (num_lds > 0) && (i < MAX_LOGICAL_DRIVES_EXT); i++) {
358*4882a593Smuzhiyun ld = MR_TargetIdToLdGet(i, drv_map);
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun /* For non existing VDs, iterate to next VD*/
361*4882a593Smuzhiyun if (ld >= (MAX_LOGICAL_DRIVES_EXT - 1))
362*4882a593Smuzhiyun continue;
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun raid = MR_LdRaidGet(ld, drv_map);
365*4882a593Smuzhiyun le32_to_cpus((u32 *)&raid->capability);
366*4882a593Smuzhiyun instance->ld_ids_from_raidmap[i] = i;
367*4882a593Smuzhiyun num_lds--;
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun return 1;
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun
MR_GetSpanBlock(u32 ld,u64 row,u64 * span_blk,struct MR_DRV_RAID_MAP_ALL * map)373*4882a593Smuzhiyun static u32 MR_GetSpanBlock(u32 ld, u64 row, u64 *span_blk,
374*4882a593Smuzhiyun struct MR_DRV_RAID_MAP_ALL *map)
375*4882a593Smuzhiyun {
376*4882a593Smuzhiyun struct MR_SPAN_BLOCK_INFO *pSpanBlock = MR_LdSpanInfoGet(ld, map);
377*4882a593Smuzhiyun struct MR_QUAD_ELEMENT *quad;
378*4882a593Smuzhiyun struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
379*4882a593Smuzhiyun u32 span, j;
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun for (span = 0; span < raid->spanDepth; span++, pSpanBlock++) {
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun for (j = 0; j < le32_to_cpu(pSpanBlock->block_span_info.noElements); j++) {
384*4882a593Smuzhiyun quad = &pSpanBlock->block_span_info.quad[j];
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun if (le32_to_cpu(quad->diff) == 0)
387*4882a593Smuzhiyun return SPAN_INVALID;
388*4882a593Smuzhiyun if (le64_to_cpu(quad->logStart) <= row && row <=
389*4882a593Smuzhiyun le64_to_cpu(quad->logEnd) && (mega_mod64(row - le64_to_cpu(quad->logStart),
390*4882a593Smuzhiyun le32_to_cpu(quad->diff))) == 0) {
391*4882a593Smuzhiyun if (span_blk != NULL) {
392*4882a593Smuzhiyun u64 blk;
393*4882a593Smuzhiyun blk = mega_div64_32((row-le64_to_cpu(quad->logStart)), le32_to_cpu(quad->diff));
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun blk = (blk + le64_to_cpu(quad->offsetInSpan)) << raid->stripeShift;
396*4882a593Smuzhiyun *span_blk = blk;
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun return span;
399*4882a593Smuzhiyun }
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun return SPAN_INVALID;
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun /*
406*4882a593Smuzhiyun ******************************************************************************
407*4882a593Smuzhiyun *
408*4882a593Smuzhiyun * This routine calculates the Span block for given row using spanset.
409*4882a593Smuzhiyun *
410*4882a593Smuzhiyun * Inputs :
411*4882a593Smuzhiyun * instance - HBA instance
412*4882a593Smuzhiyun * ld - Logical drive number
413*4882a593Smuzhiyun * row - Row number
414*4882a593Smuzhiyun * map - LD map
415*4882a593Smuzhiyun *
416*4882a593Smuzhiyun * Outputs :
417*4882a593Smuzhiyun *
418*4882a593Smuzhiyun * span - Span number
419*4882a593Smuzhiyun * block - Absolute Block number in the physical disk
420*4882a593Smuzhiyun * div_error - Devide error code.
421*4882a593Smuzhiyun */
422*4882a593Smuzhiyun
mr_spanset_get_span_block(struct megasas_instance * instance,u32 ld,u64 row,u64 * span_blk,struct MR_DRV_RAID_MAP_ALL * map)423*4882a593Smuzhiyun static u32 mr_spanset_get_span_block(struct megasas_instance *instance,
424*4882a593Smuzhiyun u32 ld, u64 row, u64 *span_blk, struct MR_DRV_RAID_MAP_ALL *map)
425*4882a593Smuzhiyun {
426*4882a593Smuzhiyun struct fusion_context *fusion = instance->ctrl_context;
427*4882a593Smuzhiyun struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
428*4882a593Smuzhiyun LD_SPAN_SET *span_set;
429*4882a593Smuzhiyun struct MR_QUAD_ELEMENT *quad;
430*4882a593Smuzhiyun u32 span, info;
431*4882a593Smuzhiyun PLD_SPAN_INFO ldSpanInfo = fusion->log_to_span;
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun for (info = 0; info < MAX_QUAD_DEPTH; info++) {
434*4882a593Smuzhiyun span_set = &(ldSpanInfo[ld].span_set[info]);
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun if (span_set->span_row_data_width == 0)
437*4882a593Smuzhiyun break;
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun if (row > span_set->data_row_end)
440*4882a593Smuzhiyun continue;
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun for (span = 0; span < raid->spanDepth; span++)
443*4882a593Smuzhiyun if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span].
444*4882a593Smuzhiyun block_span_info.noElements) >= info+1) {
445*4882a593Smuzhiyun quad = &map->raidMap.ldSpanMap[ld].
446*4882a593Smuzhiyun spanBlock[span].
447*4882a593Smuzhiyun block_span_info.quad[info];
448*4882a593Smuzhiyun if (le32_to_cpu(quad->diff) == 0)
449*4882a593Smuzhiyun return SPAN_INVALID;
450*4882a593Smuzhiyun if (le64_to_cpu(quad->logStart) <= row &&
451*4882a593Smuzhiyun row <= le64_to_cpu(quad->logEnd) &&
452*4882a593Smuzhiyun (mega_mod64(row - le64_to_cpu(quad->logStart),
453*4882a593Smuzhiyun le32_to_cpu(quad->diff))) == 0) {
454*4882a593Smuzhiyun if (span_blk != NULL) {
455*4882a593Smuzhiyun u64 blk;
456*4882a593Smuzhiyun blk = mega_div64_32
457*4882a593Smuzhiyun ((row - le64_to_cpu(quad->logStart)),
458*4882a593Smuzhiyun le32_to_cpu(quad->diff));
459*4882a593Smuzhiyun blk = (blk + le64_to_cpu(quad->offsetInSpan))
460*4882a593Smuzhiyun << raid->stripeShift;
461*4882a593Smuzhiyun *span_blk = blk;
462*4882a593Smuzhiyun }
463*4882a593Smuzhiyun return span;
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun return SPAN_INVALID;
468*4882a593Smuzhiyun }
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun /*
471*4882a593Smuzhiyun ******************************************************************************
472*4882a593Smuzhiyun *
473*4882a593Smuzhiyun * This routine calculates the row for given strip using spanset.
474*4882a593Smuzhiyun *
475*4882a593Smuzhiyun * Inputs :
476*4882a593Smuzhiyun * instance - HBA instance
477*4882a593Smuzhiyun * ld - Logical drive number
478*4882a593Smuzhiyun * Strip - Strip
479*4882a593Smuzhiyun * map - LD map
480*4882a593Smuzhiyun *
481*4882a593Smuzhiyun * Outputs :
482*4882a593Smuzhiyun *
483*4882a593Smuzhiyun * row - row associated with strip
484*4882a593Smuzhiyun */
485*4882a593Smuzhiyun
get_row_from_strip(struct megasas_instance * instance,u32 ld,u64 strip,struct MR_DRV_RAID_MAP_ALL * map)486*4882a593Smuzhiyun static u64 get_row_from_strip(struct megasas_instance *instance,
487*4882a593Smuzhiyun u32 ld, u64 strip, struct MR_DRV_RAID_MAP_ALL *map)
488*4882a593Smuzhiyun {
489*4882a593Smuzhiyun struct fusion_context *fusion = instance->ctrl_context;
490*4882a593Smuzhiyun struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
491*4882a593Smuzhiyun LD_SPAN_SET *span_set;
492*4882a593Smuzhiyun PLD_SPAN_INFO ldSpanInfo = fusion->log_to_span;
493*4882a593Smuzhiyun u32 info, strip_offset, span, span_offset;
494*4882a593Smuzhiyun u64 span_set_Strip, span_set_Row, retval;
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun for (info = 0; info < MAX_QUAD_DEPTH; info++) {
497*4882a593Smuzhiyun span_set = &(ldSpanInfo[ld].span_set[info]);
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun if (span_set->span_row_data_width == 0)
500*4882a593Smuzhiyun break;
501*4882a593Smuzhiyun if (strip > span_set->data_strip_end)
502*4882a593Smuzhiyun continue;
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun span_set_Strip = strip - span_set->data_strip_start;
505*4882a593Smuzhiyun strip_offset = mega_mod64(span_set_Strip,
506*4882a593Smuzhiyun span_set->span_row_data_width);
507*4882a593Smuzhiyun span_set_Row = mega_div64_32(span_set_Strip,
508*4882a593Smuzhiyun span_set->span_row_data_width) * span_set->diff;
509*4882a593Smuzhiyun for (span = 0, span_offset = 0; span < raid->spanDepth; span++)
510*4882a593Smuzhiyun if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span].
511*4882a593Smuzhiyun block_span_info.noElements) >= info+1) {
512*4882a593Smuzhiyun if (strip_offset >=
513*4882a593Smuzhiyun span_set->strip_offset[span])
514*4882a593Smuzhiyun span_offset++;
515*4882a593Smuzhiyun else
516*4882a593Smuzhiyun break;
517*4882a593Smuzhiyun }
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun retval = (span_set->data_row_start + span_set_Row +
520*4882a593Smuzhiyun (span_offset - 1));
521*4882a593Smuzhiyun return retval;
522*4882a593Smuzhiyun }
523*4882a593Smuzhiyun return -1LLU;
524*4882a593Smuzhiyun }
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun /*
528*4882a593Smuzhiyun ******************************************************************************
529*4882a593Smuzhiyun *
530*4882a593Smuzhiyun * This routine calculates the Start Strip for given row using spanset.
531*4882a593Smuzhiyun *
532*4882a593Smuzhiyun * Inputs :
533*4882a593Smuzhiyun * instance - HBA instance
534*4882a593Smuzhiyun * ld - Logical drive number
535*4882a593Smuzhiyun * row - Row number
536*4882a593Smuzhiyun * map - LD map
537*4882a593Smuzhiyun *
538*4882a593Smuzhiyun * Outputs :
539*4882a593Smuzhiyun *
540*4882a593Smuzhiyun * Strip - Start strip associated with row
541*4882a593Smuzhiyun */
542*4882a593Smuzhiyun
get_strip_from_row(struct megasas_instance * instance,u32 ld,u64 row,struct MR_DRV_RAID_MAP_ALL * map)543*4882a593Smuzhiyun static u64 get_strip_from_row(struct megasas_instance *instance,
544*4882a593Smuzhiyun u32 ld, u64 row, struct MR_DRV_RAID_MAP_ALL *map)
545*4882a593Smuzhiyun {
546*4882a593Smuzhiyun struct fusion_context *fusion = instance->ctrl_context;
547*4882a593Smuzhiyun struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
548*4882a593Smuzhiyun LD_SPAN_SET *span_set;
549*4882a593Smuzhiyun struct MR_QUAD_ELEMENT *quad;
550*4882a593Smuzhiyun PLD_SPAN_INFO ldSpanInfo = fusion->log_to_span;
551*4882a593Smuzhiyun u32 span, info;
552*4882a593Smuzhiyun u64 strip;
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun for (info = 0; info < MAX_QUAD_DEPTH; info++) {
555*4882a593Smuzhiyun span_set = &(ldSpanInfo[ld].span_set[info]);
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun if (span_set->span_row_data_width == 0)
558*4882a593Smuzhiyun break;
559*4882a593Smuzhiyun if (row > span_set->data_row_end)
560*4882a593Smuzhiyun continue;
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun for (span = 0; span < raid->spanDepth; span++)
563*4882a593Smuzhiyun if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span].
564*4882a593Smuzhiyun block_span_info.noElements) >= info+1) {
565*4882a593Smuzhiyun quad = &map->raidMap.ldSpanMap[ld].
566*4882a593Smuzhiyun spanBlock[span].block_span_info.quad[info];
567*4882a593Smuzhiyun if (le64_to_cpu(quad->logStart) <= row &&
568*4882a593Smuzhiyun row <= le64_to_cpu(quad->logEnd) &&
569*4882a593Smuzhiyun mega_mod64((row - le64_to_cpu(quad->logStart)),
570*4882a593Smuzhiyun le32_to_cpu(quad->diff)) == 0) {
571*4882a593Smuzhiyun strip = mega_div64_32
572*4882a593Smuzhiyun (((row - span_set->data_row_start)
573*4882a593Smuzhiyun - le64_to_cpu(quad->logStart)),
574*4882a593Smuzhiyun le32_to_cpu(quad->diff));
575*4882a593Smuzhiyun strip *= span_set->span_row_data_width;
576*4882a593Smuzhiyun strip += span_set->data_strip_start;
577*4882a593Smuzhiyun strip += span_set->strip_offset[span];
578*4882a593Smuzhiyun return strip;
579*4882a593Smuzhiyun }
580*4882a593Smuzhiyun }
581*4882a593Smuzhiyun }
582*4882a593Smuzhiyun dev_err(&instance->pdev->dev, "get_strip_from_row"
583*4882a593Smuzhiyun "returns invalid strip for ld=%x, row=%lx\n",
584*4882a593Smuzhiyun ld, (long unsigned int)row);
585*4882a593Smuzhiyun return -1;
586*4882a593Smuzhiyun }
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun /*
589*4882a593Smuzhiyun ******************************************************************************
590*4882a593Smuzhiyun *
591*4882a593Smuzhiyun * This routine calculates the Physical Arm for given strip using spanset.
592*4882a593Smuzhiyun *
593*4882a593Smuzhiyun * Inputs :
594*4882a593Smuzhiyun * instance - HBA instance
595*4882a593Smuzhiyun * ld - Logical drive number
596*4882a593Smuzhiyun * strip - Strip
597*4882a593Smuzhiyun * map - LD map
598*4882a593Smuzhiyun *
599*4882a593Smuzhiyun * Outputs :
600*4882a593Smuzhiyun *
601*4882a593Smuzhiyun * Phys Arm - Phys Arm associated with strip
602*4882a593Smuzhiyun */
603*4882a593Smuzhiyun
get_arm_from_strip(struct megasas_instance * instance,u32 ld,u64 strip,struct MR_DRV_RAID_MAP_ALL * map)604*4882a593Smuzhiyun static u32 get_arm_from_strip(struct megasas_instance *instance,
605*4882a593Smuzhiyun u32 ld, u64 strip, struct MR_DRV_RAID_MAP_ALL *map)
606*4882a593Smuzhiyun {
607*4882a593Smuzhiyun struct fusion_context *fusion = instance->ctrl_context;
608*4882a593Smuzhiyun struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
609*4882a593Smuzhiyun LD_SPAN_SET *span_set;
610*4882a593Smuzhiyun PLD_SPAN_INFO ldSpanInfo = fusion->log_to_span;
611*4882a593Smuzhiyun u32 info, strip_offset, span, span_offset, retval;
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun for (info = 0 ; info < MAX_QUAD_DEPTH; info++) {
614*4882a593Smuzhiyun span_set = &(ldSpanInfo[ld].span_set[info]);
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun if (span_set->span_row_data_width == 0)
617*4882a593Smuzhiyun break;
618*4882a593Smuzhiyun if (strip > span_set->data_strip_end)
619*4882a593Smuzhiyun continue;
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun strip_offset = (uint)mega_mod64
622*4882a593Smuzhiyun ((strip - span_set->data_strip_start),
623*4882a593Smuzhiyun span_set->span_row_data_width);
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun for (span = 0, span_offset = 0; span < raid->spanDepth; span++)
626*4882a593Smuzhiyun if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span].
627*4882a593Smuzhiyun block_span_info.noElements) >= info+1) {
628*4882a593Smuzhiyun if (strip_offset >=
629*4882a593Smuzhiyun span_set->strip_offset[span])
630*4882a593Smuzhiyun span_offset =
631*4882a593Smuzhiyun span_set->strip_offset[span];
632*4882a593Smuzhiyun else
633*4882a593Smuzhiyun break;
634*4882a593Smuzhiyun }
635*4882a593Smuzhiyun
636*4882a593Smuzhiyun retval = (strip_offset - span_offset);
637*4882a593Smuzhiyun return retval;
638*4882a593Smuzhiyun }
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun dev_err(&instance->pdev->dev, "get_arm_from_strip"
641*4882a593Smuzhiyun "returns invalid arm for ld=%x strip=%lx\n",
642*4882a593Smuzhiyun ld, (long unsigned int)strip);
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun return -1;
645*4882a593Smuzhiyun }
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun /* This Function will return Phys arm */
get_arm(struct megasas_instance * instance,u32 ld,u8 span,u64 stripe,struct MR_DRV_RAID_MAP_ALL * map)648*4882a593Smuzhiyun static u8 get_arm(struct megasas_instance *instance, u32 ld, u8 span, u64 stripe,
649*4882a593Smuzhiyun struct MR_DRV_RAID_MAP_ALL *map)
650*4882a593Smuzhiyun {
651*4882a593Smuzhiyun struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
652*4882a593Smuzhiyun /* Need to check correct default value */
653*4882a593Smuzhiyun u32 arm = 0;
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun switch (raid->level) {
656*4882a593Smuzhiyun case 0:
657*4882a593Smuzhiyun case 5:
658*4882a593Smuzhiyun case 6:
659*4882a593Smuzhiyun arm = mega_mod64(stripe, SPAN_ROW_SIZE(map, ld, span));
660*4882a593Smuzhiyun break;
661*4882a593Smuzhiyun case 1:
662*4882a593Smuzhiyun /* start with logical arm */
663*4882a593Smuzhiyun arm = get_arm_from_strip(instance, ld, stripe, map);
664*4882a593Smuzhiyun if (arm != -1U)
665*4882a593Smuzhiyun arm *= 2;
666*4882a593Smuzhiyun break;
667*4882a593Smuzhiyun }
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun return arm;
670*4882a593Smuzhiyun }
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun /*
674*4882a593Smuzhiyun ******************************************************************************
675*4882a593Smuzhiyun *
676*4882a593Smuzhiyun * This routine calculates the arm, span and block for the specified stripe and
677*4882a593Smuzhiyun * reference in stripe using spanset
678*4882a593Smuzhiyun *
679*4882a593Smuzhiyun * Inputs :
680*4882a593Smuzhiyun *
681*4882a593Smuzhiyun * ld - Logical drive number
682*4882a593Smuzhiyun * stripRow - Stripe number
683*4882a593Smuzhiyun * stripRef - Reference in stripe
684*4882a593Smuzhiyun *
685*4882a593Smuzhiyun * Outputs :
686*4882a593Smuzhiyun *
687*4882a593Smuzhiyun * span - Span number
688*4882a593Smuzhiyun * block - Absolute Block number in the physical disk
689*4882a593Smuzhiyun */
mr_spanset_get_phy_params(struct megasas_instance * instance,u32 ld,u64 stripRow,u16 stripRef,struct IO_REQUEST_INFO * io_info,struct RAID_CONTEXT * pRAID_Context,struct MR_DRV_RAID_MAP_ALL * map)690*4882a593Smuzhiyun static u8 mr_spanset_get_phy_params(struct megasas_instance *instance, u32 ld,
691*4882a593Smuzhiyun u64 stripRow, u16 stripRef, struct IO_REQUEST_INFO *io_info,
692*4882a593Smuzhiyun struct RAID_CONTEXT *pRAID_Context,
693*4882a593Smuzhiyun struct MR_DRV_RAID_MAP_ALL *map)
694*4882a593Smuzhiyun {
695*4882a593Smuzhiyun struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
696*4882a593Smuzhiyun u32 pd, arRef, r1_alt_pd;
697*4882a593Smuzhiyun u8 physArm, span;
698*4882a593Smuzhiyun u64 row;
699*4882a593Smuzhiyun u8 retval = true;
700*4882a593Smuzhiyun u64 *pdBlock = &io_info->pdBlock;
701*4882a593Smuzhiyun __le16 *pDevHandle = &io_info->devHandle;
702*4882a593Smuzhiyun u8 *pPdInterface = &io_info->pd_interface;
703*4882a593Smuzhiyun u32 logArm, rowMod, armQ, arm;
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun *pDevHandle = cpu_to_le16(MR_DEVHANDLE_INVALID);
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun /*Get row and span from io_info for Uneven Span IO.*/
708*4882a593Smuzhiyun row = io_info->start_row;
709*4882a593Smuzhiyun span = io_info->start_span;
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun if (raid->level == 6) {
713*4882a593Smuzhiyun logArm = get_arm_from_strip(instance, ld, stripRow, map);
714*4882a593Smuzhiyun if (logArm == -1U)
715*4882a593Smuzhiyun return false;
716*4882a593Smuzhiyun rowMod = mega_mod64(row, SPAN_ROW_SIZE(map, ld, span));
717*4882a593Smuzhiyun armQ = SPAN_ROW_SIZE(map, ld, span) - 1 - rowMod;
718*4882a593Smuzhiyun arm = armQ + 1 + logArm;
719*4882a593Smuzhiyun if (arm >= SPAN_ROW_SIZE(map, ld, span))
720*4882a593Smuzhiyun arm -= SPAN_ROW_SIZE(map, ld, span);
721*4882a593Smuzhiyun physArm = (u8)arm;
722*4882a593Smuzhiyun } else
723*4882a593Smuzhiyun /* Calculate the arm */
724*4882a593Smuzhiyun physArm = get_arm(instance, ld, span, stripRow, map);
725*4882a593Smuzhiyun if (physArm == 0xFF)
726*4882a593Smuzhiyun return false;
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun arRef = MR_LdSpanArrayGet(ld, span, map);
729*4882a593Smuzhiyun pd = MR_ArPdGet(arRef, physArm, map);
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun if (pd != MR_PD_INVALID) {
732*4882a593Smuzhiyun *pDevHandle = MR_PdDevHandleGet(pd, map);
733*4882a593Smuzhiyun *pPdInterface = MR_PdInterfaceTypeGet(pd, map);
734*4882a593Smuzhiyun /* get second pd also for raid 1/10 fast path writes*/
735*4882a593Smuzhiyun if ((instance->adapter_type >= VENTURA_SERIES) &&
736*4882a593Smuzhiyun (raid->level == 1) &&
737*4882a593Smuzhiyun !io_info->isRead) {
738*4882a593Smuzhiyun r1_alt_pd = MR_ArPdGet(arRef, physArm + 1, map);
739*4882a593Smuzhiyun if (r1_alt_pd != MR_PD_INVALID)
740*4882a593Smuzhiyun io_info->r1_alt_dev_handle =
741*4882a593Smuzhiyun MR_PdDevHandleGet(r1_alt_pd, map);
742*4882a593Smuzhiyun }
743*4882a593Smuzhiyun } else {
744*4882a593Smuzhiyun if ((raid->level >= 5) &&
745*4882a593Smuzhiyun ((instance->adapter_type == THUNDERBOLT_SERIES) ||
746*4882a593Smuzhiyun ((instance->adapter_type == INVADER_SERIES) &&
747*4882a593Smuzhiyun (raid->regTypeReqOnRead != REGION_TYPE_UNUSED))))
748*4882a593Smuzhiyun pRAID_Context->reg_lock_flags = REGION_TYPE_EXCLUSIVE;
749*4882a593Smuzhiyun else if (raid->level == 1) {
750*4882a593Smuzhiyun physArm = physArm + 1;
751*4882a593Smuzhiyun pd = MR_ArPdGet(arRef, physArm, map);
752*4882a593Smuzhiyun if (pd != MR_PD_INVALID) {
753*4882a593Smuzhiyun *pDevHandle = MR_PdDevHandleGet(pd, map);
754*4882a593Smuzhiyun *pPdInterface = MR_PdInterfaceTypeGet(pd, map);
755*4882a593Smuzhiyun }
756*4882a593Smuzhiyun }
757*4882a593Smuzhiyun }
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun *pdBlock += stripRef + le64_to_cpu(MR_LdSpanPtrGet(ld, span, map)->startBlk);
760*4882a593Smuzhiyun if (instance->adapter_type >= VENTURA_SERIES) {
761*4882a593Smuzhiyun ((struct RAID_CONTEXT_G35 *)pRAID_Context)->span_arm =
762*4882a593Smuzhiyun (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm;
763*4882a593Smuzhiyun io_info->span_arm =
764*4882a593Smuzhiyun (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm;
765*4882a593Smuzhiyun } else {
766*4882a593Smuzhiyun pRAID_Context->span_arm =
767*4882a593Smuzhiyun (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm;
768*4882a593Smuzhiyun io_info->span_arm = pRAID_Context->span_arm;
769*4882a593Smuzhiyun }
770*4882a593Smuzhiyun io_info->pd_after_lb = pd;
771*4882a593Smuzhiyun return retval;
772*4882a593Smuzhiyun }
773*4882a593Smuzhiyun
774*4882a593Smuzhiyun /*
775*4882a593Smuzhiyun ******************************************************************************
776*4882a593Smuzhiyun *
777*4882a593Smuzhiyun * This routine calculates the arm, span and block for the specified stripe and
778*4882a593Smuzhiyun * reference in stripe.
779*4882a593Smuzhiyun *
780*4882a593Smuzhiyun * Inputs :
781*4882a593Smuzhiyun *
782*4882a593Smuzhiyun * ld - Logical drive number
783*4882a593Smuzhiyun * stripRow - Stripe number
784*4882a593Smuzhiyun * stripRef - Reference in stripe
785*4882a593Smuzhiyun *
786*4882a593Smuzhiyun * Outputs :
787*4882a593Smuzhiyun *
788*4882a593Smuzhiyun * span - Span number
789*4882a593Smuzhiyun * block - Absolute Block number in the physical disk
790*4882a593Smuzhiyun */
MR_GetPhyParams(struct megasas_instance * instance,u32 ld,u64 stripRow,u16 stripRef,struct IO_REQUEST_INFO * io_info,struct RAID_CONTEXT * pRAID_Context,struct MR_DRV_RAID_MAP_ALL * map)791*4882a593Smuzhiyun static u8 MR_GetPhyParams(struct megasas_instance *instance, u32 ld, u64 stripRow,
792*4882a593Smuzhiyun u16 stripRef, struct IO_REQUEST_INFO *io_info,
793*4882a593Smuzhiyun struct RAID_CONTEXT *pRAID_Context,
794*4882a593Smuzhiyun struct MR_DRV_RAID_MAP_ALL *map)
795*4882a593Smuzhiyun {
796*4882a593Smuzhiyun struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
797*4882a593Smuzhiyun u32 pd, arRef, r1_alt_pd;
798*4882a593Smuzhiyun u8 physArm, span;
799*4882a593Smuzhiyun u64 row;
800*4882a593Smuzhiyun u8 retval = true;
801*4882a593Smuzhiyun u64 *pdBlock = &io_info->pdBlock;
802*4882a593Smuzhiyun __le16 *pDevHandle = &io_info->devHandle;
803*4882a593Smuzhiyun u8 *pPdInterface = &io_info->pd_interface;
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun *pDevHandle = cpu_to_le16(MR_DEVHANDLE_INVALID);
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun row = mega_div64_32(stripRow, raid->rowDataSize);
808*4882a593Smuzhiyun
809*4882a593Smuzhiyun if (raid->level == 6) {
810*4882a593Smuzhiyun /* logical arm within row */
811*4882a593Smuzhiyun u32 logArm = mega_mod64(stripRow, raid->rowDataSize);
812*4882a593Smuzhiyun u32 rowMod, armQ, arm;
813*4882a593Smuzhiyun
814*4882a593Smuzhiyun if (raid->rowSize == 0)
815*4882a593Smuzhiyun return false;
816*4882a593Smuzhiyun /* get logical row mod */
817*4882a593Smuzhiyun rowMod = mega_mod64(row, raid->rowSize);
818*4882a593Smuzhiyun armQ = raid->rowSize-1-rowMod; /* index of Q drive */
819*4882a593Smuzhiyun arm = armQ+1+logArm; /* data always logically follows Q */
820*4882a593Smuzhiyun if (arm >= raid->rowSize) /* handle wrap condition */
821*4882a593Smuzhiyun arm -= raid->rowSize;
822*4882a593Smuzhiyun physArm = (u8)arm;
823*4882a593Smuzhiyun } else {
824*4882a593Smuzhiyun if (raid->modFactor == 0)
825*4882a593Smuzhiyun return false;
826*4882a593Smuzhiyun physArm = MR_LdDataArmGet(ld, mega_mod64(stripRow,
827*4882a593Smuzhiyun raid->modFactor),
828*4882a593Smuzhiyun map);
829*4882a593Smuzhiyun }
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun if (raid->spanDepth == 1) {
832*4882a593Smuzhiyun span = 0;
833*4882a593Smuzhiyun *pdBlock = row << raid->stripeShift;
834*4882a593Smuzhiyun } else {
835*4882a593Smuzhiyun span = (u8)MR_GetSpanBlock(ld, row, pdBlock, map);
836*4882a593Smuzhiyun if (span == SPAN_INVALID)
837*4882a593Smuzhiyun return false;
838*4882a593Smuzhiyun }
839*4882a593Smuzhiyun
840*4882a593Smuzhiyun /* Get the array on which this span is present */
841*4882a593Smuzhiyun arRef = MR_LdSpanArrayGet(ld, span, map);
842*4882a593Smuzhiyun pd = MR_ArPdGet(arRef, physArm, map); /* Get the pd */
843*4882a593Smuzhiyun
844*4882a593Smuzhiyun if (pd != MR_PD_INVALID) {
845*4882a593Smuzhiyun /* Get dev handle from Pd. */
846*4882a593Smuzhiyun *pDevHandle = MR_PdDevHandleGet(pd, map);
847*4882a593Smuzhiyun *pPdInterface = MR_PdInterfaceTypeGet(pd, map);
848*4882a593Smuzhiyun /* get second pd also for raid 1/10 fast path writes*/
849*4882a593Smuzhiyun if ((instance->adapter_type >= VENTURA_SERIES) &&
850*4882a593Smuzhiyun (raid->level == 1) &&
851*4882a593Smuzhiyun !io_info->isRead) {
852*4882a593Smuzhiyun r1_alt_pd = MR_ArPdGet(arRef, physArm + 1, map);
853*4882a593Smuzhiyun if (r1_alt_pd != MR_PD_INVALID)
854*4882a593Smuzhiyun io_info->r1_alt_dev_handle =
855*4882a593Smuzhiyun MR_PdDevHandleGet(r1_alt_pd, map);
856*4882a593Smuzhiyun }
857*4882a593Smuzhiyun } else {
858*4882a593Smuzhiyun if ((raid->level >= 5) &&
859*4882a593Smuzhiyun ((instance->adapter_type == THUNDERBOLT_SERIES) ||
860*4882a593Smuzhiyun ((instance->adapter_type == INVADER_SERIES) &&
861*4882a593Smuzhiyun (raid->regTypeReqOnRead != REGION_TYPE_UNUSED))))
862*4882a593Smuzhiyun pRAID_Context->reg_lock_flags = REGION_TYPE_EXCLUSIVE;
863*4882a593Smuzhiyun else if (raid->level == 1) {
864*4882a593Smuzhiyun /* Get alternate Pd. */
865*4882a593Smuzhiyun physArm = physArm + 1;
866*4882a593Smuzhiyun pd = MR_ArPdGet(arRef, physArm, map);
867*4882a593Smuzhiyun if (pd != MR_PD_INVALID) {
868*4882a593Smuzhiyun /* Get dev handle from Pd */
869*4882a593Smuzhiyun *pDevHandle = MR_PdDevHandleGet(pd, map);
870*4882a593Smuzhiyun *pPdInterface = MR_PdInterfaceTypeGet(pd, map);
871*4882a593Smuzhiyun }
872*4882a593Smuzhiyun }
873*4882a593Smuzhiyun }
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun *pdBlock += stripRef + le64_to_cpu(MR_LdSpanPtrGet(ld, span, map)->startBlk);
876*4882a593Smuzhiyun if (instance->adapter_type >= VENTURA_SERIES) {
877*4882a593Smuzhiyun ((struct RAID_CONTEXT_G35 *)pRAID_Context)->span_arm =
878*4882a593Smuzhiyun (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm;
879*4882a593Smuzhiyun io_info->span_arm =
880*4882a593Smuzhiyun (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm;
881*4882a593Smuzhiyun } else {
882*4882a593Smuzhiyun pRAID_Context->span_arm =
883*4882a593Smuzhiyun (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm;
884*4882a593Smuzhiyun io_info->span_arm = pRAID_Context->span_arm;
885*4882a593Smuzhiyun }
886*4882a593Smuzhiyun io_info->pd_after_lb = pd;
887*4882a593Smuzhiyun return retval;
888*4882a593Smuzhiyun }
889*4882a593Smuzhiyun
890*4882a593Smuzhiyun /*
891*4882a593Smuzhiyun * mr_get_phy_params_r56_rmw - Calculate parameters for R56 CTIO write operation
892*4882a593Smuzhiyun * @instance: Adapter soft state
893*4882a593Smuzhiyun * @ld: LD index
894*4882a593Smuzhiyun * @stripNo: Strip Number
895*4882a593Smuzhiyun * @io_info: IO info structure pointer
896*4882a593Smuzhiyun * pRAID_Context: RAID context pointer
897*4882a593Smuzhiyun * map: RAID map pointer
898*4882a593Smuzhiyun *
899*4882a593Smuzhiyun * This routine calculates the logical arm, data Arm, row number and parity arm
900*4882a593Smuzhiyun * for R56 CTIO write operation.
901*4882a593Smuzhiyun */
mr_get_phy_params_r56_rmw(struct megasas_instance * instance,u32 ld,u64 stripNo,struct IO_REQUEST_INFO * io_info,struct RAID_CONTEXT_G35 * pRAID_Context,struct MR_DRV_RAID_MAP_ALL * map)902*4882a593Smuzhiyun static void mr_get_phy_params_r56_rmw(struct megasas_instance *instance,
903*4882a593Smuzhiyun u32 ld, u64 stripNo,
904*4882a593Smuzhiyun struct IO_REQUEST_INFO *io_info,
905*4882a593Smuzhiyun struct RAID_CONTEXT_G35 *pRAID_Context,
906*4882a593Smuzhiyun struct MR_DRV_RAID_MAP_ALL *map)
907*4882a593Smuzhiyun {
908*4882a593Smuzhiyun struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
909*4882a593Smuzhiyun u8 span, dataArms, arms, dataArm, logArm;
910*4882a593Smuzhiyun s8 rightmostParityArm, PParityArm;
911*4882a593Smuzhiyun u64 rowNum;
912*4882a593Smuzhiyun u64 *pdBlock = &io_info->pdBlock;
913*4882a593Smuzhiyun
914*4882a593Smuzhiyun dataArms = raid->rowDataSize;
915*4882a593Smuzhiyun arms = raid->rowSize;
916*4882a593Smuzhiyun
917*4882a593Smuzhiyun rowNum = mega_div64_32(stripNo, dataArms);
918*4882a593Smuzhiyun /* parity disk arm, first arm is 0 */
919*4882a593Smuzhiyun rightmostParityArm = (arms - 1) - mega_mod64(rowNum, arms);
920*4882a593Smuzhiyun
921*4882a593Smuzhiyun /* logical arm within row */
922*4882a593Smuzhiyun logArm = mega_mod64(stripNo, dataArms);
923*4882a593Smuzhiyun /* physical arm for data */
924*4882a593Smuzhiyun dataArm = mega_mod64((rightmostParityArm + 1 + logArm), arms);
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun if (raid->spanDepth == 1) {
927*4882a593Smuzhiyun span = 0;
928*4882a593Smuzhiyun } else {
929*4882a593Smuzhiyun span = (u8)MR_GetSpanBlock(ld, rowNum, pdBlock, map);
930*4882a593Smuzhiyun if (span == SPAN_INVALID)
931*4882a593Smuzhiyun return;
932*4882a593Smuzhiyun }
933*4882a593Smuzhiyun
934*4882a593Smuzhiyun if (raid->level == 6) {
935*4882a593Smuzhiyun /* P Parity arm, note this can go negative adjust if negative */
936*4882a593Smuzhiyun PParityArm = (arms - 2) - mega_mod64(rowNum, arms);
937*4882a593Smuzhiyun
938*4882a593Smuzhiyun if (PParityArm < 0)
939*4882a593Smuzhiyun PParityArm += arms;
940*4882a593Smuzhiyun
941*4882a593Smuzhiyun /* rightmostParityArm is P-Parity for RAID 5 and Q-Parity for RAID */
942*4882a593Smuzhiyun pRAID_Context->flow_specific.r56_arm_map = rightmostParityArm;
943*4882a593Smuzhiyun pRAID_Context->flow_specific.r56_arm_map |=
944*4882a593Smuzhiyun (u16)(PParityArm << RAID_CTX_R56_P_ARM_SHIFT);
945*4882a593Smuzhiyun } else {
946*4882a593Smuzhiyun pRAID_Context->flow_specific.r56_arm_map |=
947*4882a593Smuzhiyun (u16)(rightmostParityArm << RAID_CTX_R56_P_ARM_SHIFT);
948*4882a593Smuzhiyun }
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun pRAID_Context->reg_lock_row_lba = cpu_to_le64(rowNum);
951*4882a593Smuzhiyun pRAID_Context->flow_specific.r56_arm_map |=
952*4882a593Smuzhiyun (u16)(logArm << RAID_CTX_R56_LOG_ARM_SHIFT);
953*4882a593Smuzhiyun cpu_to_le16s(&pRAID_Context->flow_specific.r56_arm_map);
954*4882a593Smuzhiyun pRAID_Context->span_arm = (span << RAID_CTX_SPANARM_SPAN_SHIFT) | dataArm;
955*4882a593Smuzhiyun pRAID_Context->raid_flags = (MR_RAID_FLAGS_IO_SUB_TYPE_R56_DIV_OFFLOAD <<
956*4882a593Smuzhiyun MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT);
957*4882a593Smuzhiyun
958*4882a593Smuzhiyun return;
959*4882a593Smuzhiyun }
960*4882a593Smuzhiyun
961*4882a593Smuzhiyun /*
962*4882a593Smuzhiyun ******************************************************************************
963*4882a593Smuzhiyun *
964*4882a593Smuzhiyun * MR_BuildRaidContext function
965*4882a593Smuzhiyun *
966*4882a593Smuzhiyun * This function will initiate command processing. The start/end row and strip
967*4882a593Smuzhiyun * information is calculated then the lock is acquired.
968*4882a593Smuzhiyun * This function will return 0 if region lock was acquired OR return num strips
969*4882a593Smuzhiyun */
970*4882a593Smuzhiyun u8
MR_BuildRaidContext(struct megasas_instance * instance,struct IO_REQUEST_INFO * io_info,struct RAID_CONTEXT * pRAID_Context,struct MR_DRV_RAID_MAP_ALL * map,u8 ** raidLUN)971*4882a593Smuzhiyun MR_BuildRaidContext(struct megasas_instance *instance,
972*4882a593Smuzhiyun struct IO_REQUEST_INFO *io_info,
973*4882a593Smuzhiyun struct RAID_CONTEXT *pRAID_Context,
974*4882a593Smuzhiyun struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN)
975*4882a593Smuzhiyun {
976*4882a593Smuzhiyun struct fusion_context *fusion;
977*4882a593Smuzhiyun struct MR_LD_RAID *raid;
978*4882a593Smuzhiyun u32 stripSize, stripe_mask;
979*4882a593Smuzhiyun u64 endLba, endStrip, endRow, start_row, start_strip;
980*4882a593Smuzhiyun u64 regStart;
981*4882a593Smuzhiyun u32 regSize;
982*4882a593Smuzhiyun u8 num_strips, numRows;
983*4882a593Smuzhiyun u16 ref_in_start_stripe, ref_in_end_stripe;
984*4882a593Smuzhiyun u64 ldStartBlock;
985*4882a593Smuzhiyun u32 numBlocks, ldTgtId;
986*4882a593Smuzhiyun u8 isRead;
987*4882a593Smuzhiyun u8 retval = 0;
988*4882a593Smuzhiyun u8 startlba_span = SPAN_INVALID;
989*4882a593Smuzhiyun u64 *pdBlock = &io_info->pdBlock;
990*4882a593Smuzhiyun u16 ld;
991*4882a593Smuzhiyun
992*4882a593Smuzhiyun ldStartBlock = io_info->ldStartBlock;
993*4882a593Smuzhiyun numBlocks = io_info->numBlocks;
994*4882a593Smuzhiyun ldTgtId = io_info->ldTgtId;
995*4882a593Smuzhiyun isRead = io_info->isRead;
996*4882a593Smuzhiyun io_info->IoforUnevenSpan = 0;
997*4882a593Smuzhiyun io_info->start_span = SPAN_INVALID;
998*4882a593Smuzhiyun fusion = instance->ctrl_context;
999*4882a593Smuzhiyun
1000*4882a593Smuzhiyun ld = MR_TargetIdToLdGet(ldTgtId, map);
1001*4882a593Smuzhiyun raid = MR_LdRaidGet(ld, map);
1002*4882a593Smuzhiyun /*check read ahead bit*/
1003*4882a593Smuzhiyun io_info->ra_capable = raid->capability.ra_capable;
1004*4882a593Smuzhiyun
1005*4882a593Smuzhiyun /*
1006*4882a593Smuzhiyun * if rowDataSize @RAID map and spanRowDataSize @SPAN INFO are zero
1007*4882a593Smuzhiyun * return FALSE
1008*4882a593Smuzhiyun */
1009*4882a593Smuzhiyun if (raid->rowDataSize == 0) {
1010*4882a593Smuzhiyun if (MR_LdSpanPtrGet(ld, 0, map)->spanRowDataSize == 0)
1011*4882a593Smuzhiyun return false;
1012*4882a593Smuzhiyun else if (instance->UnevenSpanSupport) {
1013*4882a593Smuzhiyun io_info->IoforUnevenSpan = 1;
1014*4882a593Smuzhiyun } else {
1015*4882a593Smuzhiyun dev_info(&instance->pdev->dev,
1016*4882a593Smuzhiyun "raid->rowDataSize is 0, but has SPAN[0]"
1017*4882a593Smuzhiyun "rowDataSize = 0x%0x,"
1018*4882a593Smuzhiyun "but there is _NO_ UnevenSpanSupport\n",
1019*4882a593Smuzhiyun MR_LdSpanPtrGet(ld, 0, map)->spanRowDataSize);
1020*4882a593Smuzhiyun return false;
1021*4882a593Smuzhiyun }
1022*4882a593Smuzhiyun }
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun stripSize = 1 << raid->stripeShift;
1025*4882a593Smuzhiyun stripe_mask = stripSize-1;
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun io_info->data_arms = raid->rowDataSize;
1028*4882a593Smuzhiyun
1029*4882a593Smuzhiyun /*
1030*4882a593Smuzhiyun * calculate starting row and stripe, and number of strips and rows
1031*4882a593Smuzhiyun */
1032*4882a593Smuzhiyun start_strip = ldStartBlock >> raid->stripeShift;
1033*4882a593Smuzhiyun ref_in_start_stripe = (u16)(ldStartBlock & stripe_mask);
1034*4882a593Smuzhiyun endLba = ldStartBlock + numBlocks - 1;
1035*4882a593Smuzhiyun ref_in_end_stripe = (u16)(endLba & stripe_mask);
1036*4882a593Smuzhiyun endStrip = endLba >> raid->stripeShift;
1037*4882a593Smuzhiyun num_strips = (u8)(endStrip - start_strip + 1); /* End strip */
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun if (io_info->IoforUnevenSpan) {
1040*4882a593Smuzhiyun start_row = get_row_from_strip(instance, ld, start_strip, map);
1041*4882a593Smuzhiyun endRow = get_row_from_strip(instance, ld, endStrip, map);
1042*4882a593Smuzhiyun if (start_row == -1ULL || endRow == -1ULL) {
1043*4882a593Smuzhiyun dev_info(&instance->pdev->dev, "return from %s %d."
1044*4882a593Smuzhiyun "Send IO w/o region lock.\n",
1045*4882a593Smuzhiyun __func__, __LINE__);
1046*4882a593Smuzhiyun return false;
1047*4882a593Smuzhiyun }
1048*4882a593Smuzhiyun
1049*4882a593Smuzhiyun if (raid->spanDepth == 1) {
1050*4882a593Smuzhiyun startlba_span = 0;
1051*4882a593Smuzhiyun *pdBlock = start_row << raid->stripeShift;
1052*4882a593Smuzhiyun } else
1053*4882a593Smuzhiyun startlba_span = (u8)mr_spanset_get_span_block(instance,
1054*4882a593Smuzhiyun ld, start_row, pdBlock, map);
1055*4882a593Smuzhiyun if (startlba_span == SPAN_INVALID) {
1056*4882a593Smuzhiyun dev_info(&instance->pdev->dev, "return from %s %d"
1057*4882a593Smuzhiyun "for row 0x%llx,start strip %llx"
1058*4882a593Smuzhiyun "endSrip %llx\n", __func__, __LINE__,
1059*4882a593Smuzhiyun (unsigned long long)start_row,
1060*4882a593Smuzhiyun (unsigned long long)start_strip,
1061*4882a593Smuzhiyun (unsigned long long)endStrip);
1062*4882a593Smuzhiyun return false;
1063*4882a593Smuzhiyun }
1064*4882a593Smuzhiyun io_info->start_span = startlba_span;
1065*4882a593Smuzhiyun io_info->start_row = start_row;
1066*4882a593Smuzhiyun } else {
1067*4882a593Smuzhiyun start_row = mega_div64_32(start_strip, raid->rowDataSize);
1068*4882a593Smuzhiyun endRow = mega_div64_32(endStrip, raid->rowDataSize);
1069*4882a593Smuzhiyun }
1070*4882a593Smuzhiyun numRows = (u8)(endRow - start_row + 1);
1071*4882a593Smuzhiyun
1072*4882a593Smuzhiyun /*
1073*4882a593Smuzhiyun * calculate region info.
1074*4882a593Smuzhiyun */
1075*4882a593Smuzhiyun
1076*4882a593Smuzhiyun /* assume region is at the start of the first row */
1077*4882a593Smuzhiyun regStart = start_row << raid->stripeShift;
1078*4882a593Smuzhiyun /* assume this IO needs the full row - we'll adjust if not true */
1079*4882a593Smuzhiyun regSize = stripSize;
1080*4882a593Smuzhiyun
1081*4882a593Smuzhiyun io_info->do_fp_rlbypass = raid->capability.fpBypassRegionLock;
1082*4882a593Smuzhiyun
1083*4882a593Smuzhiyun /* Check if we can send this I/O via FastPath */
1084*4882a593Smuzhiyun if (raid->capability.fpCapable) {
1085*4882a593Smuzhiyun if (isRead)
1086*4882a593Smuzhiyun io_info->fpOkForIo = (raid->capability.fpReadCapable &&
1087*4882a593Smuzhiyun ((num_strips == 1) ||
1088*4882a593Smuzhiyun raid->capability.
1089*4882a593Smuzhiyun fpReadAcrossStripe));
1090*4882a593Smuzhiyun else
1091*4882a593Smuzhiyun io_info->fpOkForIo = (raid->capability.fpWriteCapable &&
1092*4882a593Smuzhiyun ((num_strips == 1) ||
1093*4882a593Smuzhiyun raid->capability.
1094*4882a593Smuzhiyun fpWriteAcrossStripe));
1095*4882a593Smuzhiyun } else
1096*4882a593Smuzhiyun io_info->fpOkForIo = false;
1097*4882a593Smuzhiyun
1098*4882a593Smuzhiyun if (numRows == 1) {
1099*4882a593Smuzhiyun /* single-strip IOs can always lock only the data needed */
1100*4882a593Smuzhiyun if (num_strips == 1) {
1101*4882a593Smuzhiyun regStart += ref_in_start_stripe;
1102*4882a593Smuzhiyun regSize = numBlocks;
1103*4882a593Smuzhiyun }
1104*4882a593Smuzhiyun /* multi-strip IOs always need to full stripe locked */
1105*4882a593Smuzhiyun } else if (io_info->IoforUnevenSpan == 0) {
1106*4882a593Smuzhiyun /*
1107*4882a593Smuzhiyun * For Even span region lock optimization.
1108*4882a593Smuzhiyun * If the start strip is the last in the start row
1109*4882a593Smuzhiyun */
1110*4882a593Smuzhiyun if (start_strip == (start_row + 1) * raid->rowDataSize - 1) {
1111*4882a593Smuzhiyun regStart += ref_in_start_stripe;
1112*4882a593Smuzhiyun /* initialize count to sectors from startref to end
1113*4882a593Smuzhiyun of strip */
1114*4882a593Smuzhiyun regSize = stripSize - ref_in_start_stripe;
1115*4882a593Smuzhiyun }
1116*4882a593Smuzhiyun
1117*4882a593Smuzhiyun /* add complete rows in the middle of the transfer */
1118*4882a593Smuzhiyun if (numRows > 2)
1119*4882a593Smuzhiyun regSize += (numRows-2) << raid->stripeShift;
1120*4882a593Smuzhiyun
1121*4882a593Smuzhiyun /* if IO ends within first strip of last row*/
1122*4882a593Smuzhiyun if (endStrip == endRow*raid->rowDataSize)
1123*4882a593Smuzhiyun regSize += ref_in_end_stripe+1;
1124*4882a593Smuzhiyun else
1125*4882a593Smuzhiyun regSize += stripSize;
1126*4882a593Smuzhiyun } else {
1127*4882a593Smuzhiyun /*
1128*4882a593Smuzhiyun * For Uneven span region lock optimization.
1129*4882a593Smuzhiyun * If the start strip is the last in the start row
1130*4882a593Smuzhiyun */
1131*4882a593Smuzhiyun if (start_strip == (get_strip_from_row(instance, ld, start_row, map) +
1132*4882a593Smuzhiyun SPAN_ROW_DATA_SIZE(map, ld, startlba_span) - 1)) {
1133*4882a593Smuzhiyun regStart += ref_in_start_stripe;
1134*4882a593Smuzhiyun /* initialize count to sectors from
1135*4882a593Smuzhiyun * startRef to end of strip
1136*4882a593Smuzhiyun */
1137*4882a593Smuzhiyun regSize = stripSize - ref_in_start_stripe;
1138*4882a593Smuzhiyun }
1139*4882a593Smuzhiyun /* Add complete rows in the middle of the transfer*/
1140*4882a593Smuzhiyun
1141*4882a593Smuzhiyun if (numRows > 2)
1142*4882a593Smuzhiyun /* Add complete rows in the middle of the transfer*/
1143*4882a593Smuzhiyun regSize += (numRows-2) << raid->stripeShift;
1144*4882a593Smuzhiyun
1145*4882a593Smuzhiyun /* if IO ends within first strip of last row */
1146*4882a593Smuzhiyun if (endStrip == get_strip_from_row(instance, ld, endRow, map))
1147*4882a593Smuzhiyun regSize += ref_in_end_stripe + 1;
1148*4882a593Smuzhiyun else
1149*4882a593Smuzhiyun regSize += stripSize;
1150*4882a593Smuzhiyun }
1151*4882a593Smuzhiyun
1152*4882a593Smuzhiyun pRAID_Context->timeout_value =
1153*4882a593Smuzhiyun cpu_to_le16(raid->fpIoTimeoutForLd ?
1154*4882a593Smuzhiyun raid->fpIoTimeoutForLd :
1155*4882a593Smuzhiyun map->raidMap.fpPdIoTimeoutSec);
1156*4882a593Smuzhiyun if (instance->adapter_type == INVADER_SERIES)
1157*4882a593Smuzhiyun pRAID_Context->reg_lock_flags = (isRead) ?
1158*4882a593Smuzhiyun raid->regTypeReqOnRead : raid->regTypeReqOnWrite;
1159*4882a593Smuzhiyun else if (instance->adapter_type == THUNDERBOLT_SERIES)
1160*4882a593Smuzhiyun pRAID_Context->reg_lock_flags = (isRead) ?
1161*4882a593Smuzhiyun REGION_TYPE_SHARED_READ : raid->regTypeReqOnWrite;
1162*4882a593Smuzhiyun pRAID_Context->virtual_disk_tgt_id = raid->targetId;
1163*4882a593Smuzhiyun pRAID_Context->reg_lock_row_lba = cpu_to_le64(regStart);
1164*4882a593Smuzhiyun pRAID_Context->reg_lock_length = cpu_to_le32(regSize);
1165*4882a593Smuzhiyun pRAID_Context->config_seq_num = raid->seqNum;
1166*4882a593Smuzhiyun /* save pointer to raid->LUN array */
1167*4882a593Smuzhiyun *raidLUN = raid->LUN;
1168*4882a593Smuzhiyun
1169*4882a593Smuzhiyun /* Aero R5/6 Division Offload for WRITE */
1170*4882a593Smuzhiyun if (fusion->r56_div_offload && (raid->level >= 5) && !isRead) {
1171*4882a593Smuzhiyun mr_get_phy_params_r56_rmw(instance, ld, start_strip, io_info,
1172*4882a593Smuzhiyun (struct RAID_CONTEXT_G35 *)pRAID_Context,
1173*4882a593Smuzhiyun map);
1174*4882a593Smuzhiyun return true;
1175*4882a593Smuzhiyun }
1176*4882a593Smuzhiyun
1177*4882a593Smuzhiyun /*Get Phy Params only if FP capable, or else leave it to MR firmware
1178*4882a593Smuzhiyun to do the calculation.*/
1179*4882a593Smuzhiyun if (io_info->fpOkForIo) {
1180*4882a593Smuzhiyun retval = io_info->IoforUnevenSpan ?
1181*4882a593Smuzhiyun mr_spanset_get_phy_params(instance, ld,
1182*4882a593Smuzhiyun start_strip, ref_in_start_stripe,
1183*4882a593Smuzhiyun io_info, pRAID_Context, map) :
1184*4882a593Smuzhiyun MR_GetPhyParams(instance, ld, start_strip,
1185*4882a593Smuzhiyun ref_in_start_stripe, io_info,
1186*4882a593Smuzhiyun pRAID_Context, map);
1187*4882a593Smuzhiyun /* If IO on an invalid Pd, then FP is not possible.*/
1188*4882a593Smuzhiyun if (io_info->devHandle == MR_DEVHANDLE_INVALID)
1189*4882a593Smuzhiyun io_info->fpOkForIo = false;
1190*4882a593Smuzhiyun return retval;
1191*4882a593Smuzhiyun } else if (isRead) {
1192*4882a593Smuzhiyun uint stripIdx;
1193*4882a593Smuzhiyun for (stripIdx = 0; stripIdx < num_strips; stripIdx++) {
1194*4882a593Smuzhiyun retval = io_info->IoforUnevenSpan ?
1195*4882a593Smuzhiyun mr_spanset_get_phy_params(instance, ld,
1196*4882a593Smuzhiyun start_strip + stripIdx,
1197*4882a593Smuzhiyun ref_in_start_stripe, io_info,
1198*4882a593Smuzhiyun pRAID_Context, map) :
1199*4882a593Smuzhiyun MR_GetPhyParams(instance, ld,
1200*4882a593Smuzhiyun start_strip + stripIdx, ref_in_start_stripe,
1201*4882a593Smuzhiyun io_info, pRAID_Context, map);
1202*4882a593Smuzhiyun if (!retval)
1203*4882a593Smuzhiyun return true;
1204*4882a593Smuzhiyun }
1205*4882a593Smuzhiyun }
1206*4882a593Smuzhiyun return true;
1207*4882a593Smuzhiyun }
1208*4882a593Smuzhiyun
1209*4882a593Smuzhiyun /*
1210*4882a593Smuzhiyun ******************************************************************************
1211*4882a593Smuzhiyun *
1212*4882a593Smuzhiyun * This routine pepare spanset info from Valid Raid map and store it into
1213*4882a593Smuzhiyun * local copy of ldSpanInfo per instance data structure.
1214*4882a593Smuzhiyun *
1215*4882a593Smuzhiyun * Inputs :
1216*4882a593Smuzhiyun * map - LD map
1217*4882a593Smuzhiyun * ldSpanInfo - ldSpanInfo per HBA instance
1218*4882a593Smuzhiyun *
1219*4882a593Smuzhiyun */
mr_update_span_set(struct MR_DRV_RAID_MAP_ALL * map,PLD_SPAN_INFO ldSpanInfo)1220*4882a593Smuzhiyun void mr_update_span_set(struct MR_DRV_RAID_MAP_ALL *map,
1221*4882a593Smuzhiyun PLD_SPAN_INFO ldSpanInfo)
1222*4882a593Smuzhiyun {
1223*4882a593Smuzhiyun u8 span, count;
1224*4882a593Smuzhiyun u32 element, span_row_width;
1225*4882a593Smuzhiyun u64 span_row;
1226*4882a593Smuzhiyun struct MR_LD_RAID *raid;
1227*4882a593Smuzhiyun LD_SPAN_SET *span_set, *span_set_prev;
1228*4882a593Smuzhiyun struct MR_QUAD_ELEMENT *quad;
1229*4882a593Smuzhiyun int ldCount;
1230*4882a593Smuzhiyun u16 ld;
1231*4882a593Smuzhiyun
1232*4882a593Smuzhiyun
1233*4882a593Smuzhiyun for (ldCount = 0; ldCount < MAX_LOGICAL_DRIVES_EXT; ldCount++) {
1234*4882a593Smuzhiyun ld = MR_TargetIdToLdGet(ldCount, map);
1235*4882a593Smuzhiyun if (ld >= (MAX_LOGICAL_DRIVES_EXT - 1))
1236*4882a593Smuzhiyun continue;
1237*4882a593Smuzhiyun raid = MR_LdRaidGet(ld, map);
1238*4882a593Smuzhiyun for (element = 0; element < MAX_QUAD_DEPTH; element++) {
1239*4882a593Smuzhiyun for (span = 0; span < raid->spanDepth; span++) {
1240*4882a593Smuzhiyun if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span].
1241*4882a593Smuzhiyun block_span_info.noElements) <
1242*4882a593Smuzhiyun element + 1)
1243*4882a593Smuzhiyun continue;
1244*4882a593Smuzhiyun span_set = &(ldSpanInfo[ld].span_set[element]);
1245*4882a593Smuzhiyun quad = &map->raidMap.ldSpanMap[ld].
1246*4882a593Smuzhiyun spanBlock[span].block_span_info.
1247*4882a593Smuzhiyun quad[element];
1248*4882a593Smuzhiyun
1249*4882a593Smuzhiyun span_set->diff = le32_to_cpu(quad->diff);
1250*4882a593Smuzhiyun
1251*4882a593Smuzhiyun for (count = 0, span_row_width = 0;
1252*4882a593Smuzhiyun count < raid->spanDepth; count++) {
1253*4882a593Smuzhiyun if (le32_to_cpu(map->raidMap.ldSpanMap[ld].
1254*4882a593Smuzhiyun spanBlock[count].
1255*4882a593Smuzhiyun block_span_info.
1256*4882a593Smuzhiyun noElements) >= element + 1) {
1257*4882a593Smuzhiyun span_set->strip_offset[count] =
1258*4882a593Smuzhiyun span_row_width;
1259*4882a593Smuzhiyun span_row_width +=
1260*4882a593Smuzhiyun MR_LdSpanPtrGet
1261*4882a593Smuzhiyun (ld, count, map)->spanRowDataSize;
1262*4882a593Smuzhiyun }
1263*4882a593Smuzhiyun }
1264*4882a593Smuzhiyun
1265*4882a593Smuzhiyun span_set->span_row_data_width = span_row_width;
1266*4882a593Smuzhiyun span_row = mega_div64_32(((le64_to_cpu(quad->logEnd) -
1267*4882a593Smuzhiyun le64_to_cpu(quad->logStart)) + le32_to_cpu(quad->diff)),
1268*4882a593Smuzhiyun le32_to_cpu(quad->diff));
1269*4882a593Smuzhiyun
1270*4882a593Smuzhiyun if (element == 0) {
1271*4882a593Smuzhiyun span_set->log_start_lba = 0;
1272*4882a593Smuzhiyun span_set->log_end_lba =
1273*4882a593Smuzhiyun ((span_row << raid->stripeShift)
1274*4882a593Smuzhiyun * span_row_width) - 1;
1275*4882a593Smuzhiyun
1276*4882a593Smuzhiyun span_set->span_row_start = 0;
1277*4882a593Smuzhiyun span_set->span_row_end = span_row - 1;
1278*4882a593Smuzhiyun
1279*4882a593Smuzhiyun span_set->data_strip_start = 0;
1280*4882a593Smuzhiyun span_set->data_strip_end =
1281*4882a593Smuzhiyun (span_row * span_row_width) - 1;
1282*4882a593Smuzhiyun
1283*4882a593Smuzhiyun span_set->data_row_start = 0;
1284*4882a593Smuzhiyun span_set->data_row_end =
1285*4882a593Smuzhiyun (span_row * le32_to_cpu(quad->diff)) - 1;
1286*4882a593Smuzhiyun } else {
1287*4882a593Smuzhiyun span_set_prev = &(ldSpanInfo[ld].
1288*4882a593Smuzhiyun span_set[element - 1]);
1289*4882a593Smuzhiyun span_set->log_start_lba =
1290*4882a593Smuzhiyun span_set_prev->log_end_lba + 1;
1291*4882a593Smuzhiyun span_set->log_end_lba =
1292*4882a593Smuzhiyun span_set->log_start_lba +
1293*4882a593Smuzhiyun ((span_row << raid->stripeShift)
1294*4882a593Smuzhiyun * span_row_width) - 1;
1295*4882a593Smuzhiyun
1296*4882a593Smuzhiyun span_set->span_row_start =
1297*4882a593Smuzhiyun span_set_prev->span_row_end + 1;
1298*4882a593Smuzhiyun span_set->span_row_end =
1299*4882a593Smuzhiyun span_set->span_row_start + span_row - 1;
1300*4882a593Smuzhiyun
1301*4882a593Smuzhiyun span_set->data_strip_start =
1302*4882a593Smuzhiyun span_set_prev->data_strip_end + 1;
1303*4882a593Smuzhiyun span_set->data_strip_end =
1304*4882a593Smuzhiyun span_set->data_strip_start +
1305*4882a593Smuzhiyun (span_row * span_row_width) - 1;
1306*4882a593Smuzhiyun
1307*4882a593Smuzhiyun span_set->data_row_start =
1308*4882a593Smuzhiyun span_set_prev->data_row_end + 1;
1309*4882a593Smuzhiyun span_set->data_row_end =
1310*4882a593Smuzhiyun span_set->data_row_start +
1311*4882a593Smuzhiyun (span_row * le32_to_cpu(quad->diff)) - 1;
1312*4882a593Smuzhiyun }
1313*4882a593Smuzhiyun break;
1314*4882a593Smuzhiyun }
1315*4882a593Smuzhiyun if (span == raid->spanDepth)
1316*4882a593Smuzhiyun break;
1317*4882a593Smuzhiyun }
1318*4882a593Smuzhiyun }
1319*4882a593Smuzhiyun }
1320*4882a593Smuzhiyun
mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL * drv_map,struct LD_LOAD_BALANCE_INFO * lbInfo)1321*4882a593Smuzhiyun void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *drv_map,
1322*4882a593Smuzhiyun struct LD_LOAD_BALANCE_INFO *lbInfo)
1323*4882a593Smuzhiyun {
1324*4882a593Smuzhiyun int ldCount;
1325*4882a593Smuzhiyun u16 ld;
1326*4882a593Smuzhiyun struct MR_LD_RAID *raid;
1327*4882a593Smuzhiyun
1328*4882a593Smuzhiyun if (lb_pending_cmds > 128 || lb_pending_cmds < 1)
1329*4882a593Smuzhiyun lb_pending_cmds = LB_PENDING_CMDS_DEFAULT;
1330*4882a593Smuzhiyun
1331*4882a593Smuzhiyun for (ldCount = 0; ldCount < MAX_LOGICAL_DRIVES_EXT; ldCount++) {
1332*4882a593Smuzhiyun ld = MR_TargetIdToLdGet(ldCount, drv_map);
1333*4882a593Smuzhiyun if (ld >= MAX_LOGICAL_DRIVES_EXT - 1) {
1334*4882a593Smuzhiyun lbInfo[ldCount].loadBalanceFlag = 0;
1335*4882a593Smuzhiyun continue;
1336*4882a593Smuzhiyun }
1337*4882a593Smuzhiyun
1338*4882a593Smuzhiyun raid = MR_LdRaidGet(ld, drv_map);
1339*4882a593Smuzhiyun if ((raid->level != 1) ||
1340*4882a593Smuzhiyun (raid->ldState != MR_LD_STATE_OPTIMAL)) {
1341*4882a593Smuzhiyun lbInfo[ldCount].loadBalanceFlag = 0;
1342*4882a593Smuzhiyun continue;
1343*4882a593Smuzhiyun }
1344*4882a593Smuzhiyun lbInfo[ldCount].loadBalanceFlag = 1;
1345*4882a593Smuzhiyun }
1346*4882a593Smuzhiyun }
1347*4882a593Smuzhiyun
megasas_get_best_arm_pd(struct megasas_instance * instance,struct LD_LOAD_BALANCE_INFO * lbInfo,struct IO_REQUEST_INFO * io_info,struct MR_DRV_RAID_MAP_ALL * drv_map)1348*4882a593Smuzhiyun static u8 megasas_get_best_arm_pd(struct megasas_instance *instance,
1349*4882a593Smuzhiyun struct LD_LOAD_BALANCE_INFO *lbInfo,
1350*4882a593Smuzhiyun struct IO_REQUEST_INFO *io_info,
1351*4882a593Smuzhiyun struct MR_DRV_RAID_MAP_ALL *drv_map)
1352*4882a593Smuzhiyun {
1353*4882a593Smuzhiyun struct MR_LD_RAID *raid;
1354*4882a593Smuzhiyun u16 pd1_dev_handle;
1355*4882a593Smuzhiyun u16 pend0, pend1, ld;
1356*4882a593Smuzhiyun u64 diff0, diff1;
1357*4882a593Smuzhiyun u8 bestArm, pd0, pd1, span, arm;
1358*4882a593Smuzhiyun u32 arRef, span_row_size;
1359*4882a593Smuzhiyun
1360*4882a593Smuzhiyun u64 block = io_info->ldStartBlock;
1361*4882a593Smuzhiyun u32 count = io_info->numBlocks;
1362*4882a593Smuzhiyun
1363*4882a593Smuzhiyun span = ((io_info->span_arm & RAID_CTX_SPANARM_SPAN_MASK)
1364*4882a593Smuzhiyun >> RAID_CTX_SPANARM_SPAN_SHIFT);
1365*4882a593Smuzhiyun arm = (io_info->span_arm & RAID_CTX_SPANARM_ARM_MASK);
1366*4882a593Smuzhiyun
1367*4882a593Smuzhiyun ld = MR_TargetIdToLdGet(io_info->ldTgtId, drv_map);
1368*4882a593Smuzhiyun raid = MR_LdRaidGet(ld, drv_map);
1369*4882a593Smuzhiyun span_row_size = instance->UnevenSpanSupport ?
1370*4882a593Smuzhiyun SPAN_ROW_SIZE(drv_map, ld, span) : raid->rowSize;
1371*4882a593Smuzhiyun
1372*4882a593Smuzhiyun arRef = MR_LdSpanArrayGet(ld, span, drv_map);
1373*4882a593Smuzhiyun pd0 = MR_ArPdGet(arRef, arm, drv_map);
1374*4882a593Smuzhiyun pd1 = MR_ArPdGet(arRef, (arm + 1) >= span_row_size ?
1375*4882a593Smuzhiyun (arm + 1 - span_row_size) : arm + 1, drv_map);
1376*4882a593Smuzhiyun
1377*4882a593Smuzhiyun /* Get PD1 Dev Handle */
1378*4882a593Smuzhiyun
1379*4882a593Smuzhiyun pd1_dev_handle = MR_PdDevHandleGet(pd1, drv_map);
1380*4882a593Smuzhiyun
1381*4882a593Smuzhiyun if (pd1_dev_handle == MR_DEVHANDLE_INVALID) {
1382*4882a593Smuzhiyun bestArm = arm;
1383*4882a593Smuzhiyun } else {
1384*4882a593Smuzhiyun /* get the pending cmds for the data and mirror arms */
1385*4882a593Smuzhiyun pend0 = atomic_read(&lbInfo->scsi_pending_cmds[pd0]);
1386*4882a593Smuzhiyun pend1 = atomic_read(&lbInfo->scsi_pending_cmds[pd1]);
1387*4882a593Smuzhiyun
1388*4882a593Smuzhiyun /* Determine the disk whose head is nearer to the req. block */
1389*4882a593Smuzhiyun diff0 = ABS_DIFF(block, lbInfo->last_accessed_block[pd0]);
1390*4882a593Smuzhiyun diff1 = ABS_DIFF(block, lbInfo->last_accessed_block[pd1]);
1391*4882a593Smuzhiyun bestArm = (diff0 <= diff1 ? arm : arm ^ 1);
1392*4882a593Smuzhiyun
1393*4882a593Smuzhiyun /* Make balance count from 16 to 4 to
1394*4882a593Smuzhiyun * keep driver in sync with Firmware
1395*4882a593Smuzhiyun */
1396*4882a593Smuzhiyun if ((bestArm == arm && pend0 > pend1 + lb_pending_cmds) ||
1397*4882a593Smuzhiyun (bestArm != arm && pend1 > pend0 + lb_pending_cmds))
1398*4882a593Smuzhiyun bestArm ^= 1;
1399*4882a593Smuzhiyun
1400*4882a593Smuzhiyun /* Update the last accessed block on the correct pd */
1401*4882a593Smuzhiyun io_info->span_arm =
1402*4882a593Smuzhiyun (span << RAID_CTX_SPANARM_SPAN_SHIFT) | bestArm;
1403*4882a593Smuzhiyun io_info->pd_after_lb = (bestArm == arm) ? pd0 : pd1;
1404*4882a593Smuzhiyun }
1405*4882a593Smuzhiyun
1406*4882a593Smuzhiyun lbInfo->last_accessed_block[io_info->pd_after_lb] = block + count - 1;
1407*4882a593Smuzhiyun return io_info->pd_after_lb;
1408*4882a593Smuzhiyun }
1409*4882a593Smuzhiyun
get_updated_dev_handle(struct megasas_instance * instance,struct LD_LOAD_BALANCE_INFO * lbInfo,struct IO_REQUEST_INFO * io_info,struct MR_DRV_RAID_MAP_ALL * drv_map)1410*4882a593Smuzhiyun __le16 get_updated_dev_handle(struct megasas_instance *instance,
1411*4882a593Smuzhiyun struct LD_LOAD_BALANCE_INFO *lbInfo,
1412*4882a593Smuzhiyun struct IO_REQUEST_INFO *io_info,
1413*4882a593Smuzhiyun struct MR_DRV_RAID_MAP_ALL *drv_map)
1414*4882a593Smuzhiyun {
1415*4882a593Smuzhiyun u8 arm_pd;
1416*4882a593Smuzhiyun __le16 devHandle;
1417*4882a593Smuzhiyun
1418*4882a593Smuzhiyun /* get best new arm (PD ID) */
1419*4882a593Smuzhiyun arm_pd = megasas_get_best_arm_pd(instance, lbInfo, io_info, drv_map);
1420*4882a593Smuzhiyun devHandle = MR_PdDevHandleGet(arm_pd, drv_map);
1421*4882a593Smuzhiyun io_info->pd_interface = MR_PdInterfaceTypeGet(arm_pd, drv_map);
1422*4882a593Smuzhiyun atomic_inc(&lbInfo->scsi_pending_cmds[arm_pd]);
1423*4882a593Smuzhiyun
1424*4882a593Smuzhiyun return devHandle;
1425*4882a593Smuzhiyun }
1426