1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * mac53c94.h: definitions for the driver for the 53c94 SCSI bus adaptor 4*4882a593Smuzhiyun * found on Power Macintosh computers, controlling the external SCSI chain. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 1996 Paul Mackerras. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef _MAC53C94_H 9*4882a593Smuzhiyun #define _MAC53C94_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Registers in the 53C94 controller. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct mac53c94_regs { 16*4882a593Smuzhiyun unsigned char count_lo; 17*4882a593Smuzhiyun char pad0[15]; 18*4882a593Smuzhiyun unsigned char count_mid; 19*4882a593Smuzhiyun char pad1[15]; 20*4882a593Smuzhiyun unsigned char fifo; 21*4882a593Smuzhiyun char pad2[15]; 22*4882a593Smuzhiyun unsigned char command; 23*4882a593Smuzhiyun char pad3[15]; 24*4882a593Smuzhiyun unsigned char status; 25*4882a593Smuzhiyun char pad4[15]; 26*4882a593Smuzhiyun unsigned char interrupt; 27*4882a593Smuzhiyun char pad5[15]; 28*4882a593Smuzhiyun unsigned char seqstep; 29*4882a593Smuzhiyun char pad6[15]; 30*4882a593Smuzhiyun unsigned char flags; 31*4882a593Smuzhiyun char pad7[15]; 32*4882a593Smuzhiyun unsigned char config1; 33*4882a593Smuzhiyun char pad8[15]; 34*4882a593Smuzhiyun unsigned char clk_factor; 35*4882a593Smuzhiyun char pad9[15]; 36*4882a593Smuzhiyun unsigned char test; 37*4882a593Smuzhiyun char pad10[15]; 38*4882a593Smuzhiyun unsigned char config2; 39*4882a593Smuzhiyun char pad11[15]; 40*4882a593Smuzhiyun unsigned char config3; 41*4882a593Smuzhiyun char pad12[15]; 42*4882a593Smuzhiyun unsigned char config4; 43*4882a593Smuzhiyun char pad13[15]; 44*4882a593Smuzhiyun unsigned char count_hi; 45*4882a593Smuzhiyun char pad14[15]; 46*4882a593Smuzhiyun unsigned char fifo_res; 47*4882a593Smuzhiyun char pad15[15]; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* 51*4882a593Smuzhiyun * Alternate functions for some registers. 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun #define dest_id status 54*4882a593Smuzhiyun #define sel_timeout interrupt 55*4882a593Smuzhiyun #define sync_period seqstep 56*4882a593Smuzhiyun #define sync_offset flags 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* 59*4882a593Smuzhiyun * Bits in command register. 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun #define CMD_DMA_MODE 0x80 62*4882a593Smuzhiyun #define CMD_MODE_MASK 0x70 63*4882a593Smuzhiyun #define CMD_MODE_INIT 0x10 64*4882a593Smuzhiyun #define CMD_MODE_TARG 0x20 65*4882a593Smuzhiyun #define CMD_MODE_DISC 0x40 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define CMD_NOP 0 68*4882a593Smuzhiyun #define CMD_FLUSH 1 69*4882a593Smuzhiyun #define CMD_RESET 2 70*4882a593Smuzhiyun #define CMD_SCSI_RESET 3 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define CMD_XFER_DATA 0x10 73*4882a593Smuzhiyun #define CMD_I_COMPLETE 0x11 74*4882a593Smuzhiyun #define CMD_ACCEPT_MSG 0x12 75*4882a593Smuzhiyun #define CMD_XFER_PAD 0x18 76*4882a593Smuzhiyun #define CMD_SET_ATN 0x1a 77*4882a593Smuzhiyun #define CMD_CLR_ATN 0x1b 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define CMD_SEND_MSG 0x20 80*4882a593Smuzhiyun #define CMD_SEND_STATUS 0x21 81*4882a593Smuzhiyun #define CMD_SEND_DATA 0x22 82*4882a593Smuzhiyun #define CMD_DISC_SEQ 0x23 83*4882a593Smuzhiyun #define CMD_TERMINATE 0x24 84*4882a593Smuzhiyun #define CMD_T_COMPLETE 0x25 85*4882a593Smuzhiyun #define CMD_DISCONNECT 0x27 86*4882a593Smuzhiyun #define CMD_RECV_MSG 0x28 87*4882a593Smuzhiyun #define CMD_RECV_CDB 0x29 88*4882a593Smuzhiyun #define CMD_RECV_DATA 0x2a 89*4882a593Smuzhiyun #define CMD_RECV_CMD 0x2b 90*4882a593Smuzhiyun #define CMD_ABORT_DMA 0x04 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define CMD_RESELECT 0x40 93*4882a593Smuzhiyun #define CMD_SELECT 0x41 94*4882a593Smuzhiyun #define CMD_SELECT_ATN 0x42 95*4882a593Smuzhiyun #define CMD_SELATN_STOP 0x43 96*4882a593Smuzhiyun #define CMD_ENABLE_SEL 0x44 97*4882a593Smuzhiyun #define CMD_DISABLE_SEL 0x45 98*4882a593Smuzhiyun #define CMD_SEL_ATN3 0x46 99*4882a593Smuzhiyun #define CMD_RESEL_ATN3 0x47 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* 102*4882a593Smuzhiyun * Bits in status register. 103*4882a593Smuzhiyun */ 104*4882a593Smuzhiyun #define STAT_IRQ 0x80 105*4882a593Smuzhiyun #define STAT_ERROR 0x40 106*4882a593Smuzhiyun #define STAT_PARITY 0x20 107*4882a593Smuzhiyun #define STAT_TC_ZERO 0x10 108*4882a593Smuzhiyun #define STAT_DONE 0x08 109*4882a593Smuzhiyun #define STAT_PHASE 0x07 110*4882a593Smuzhiyun #define STAT_MSG 0x04 111*4882a593Smuzhiyun #define STAT_CD 0x02 112*4882a593Smuzhiyun #define STAT_IO 0x01 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* 115*4882a593Smuzhiyun * Bits in interrupt register. 116*4882a593Smuzhiyun */ 117*4882a593Smuzhiyun #define INTR_RESET 0x80 /* SCSI bus was reset */ 118*4882a593Smuzhiyun #define INTR_ILL_CMD 0x40 /* illegal command */ 119*4882a593Smuzhiyun #define INTR_DISCONNECT 0x20 /* we got disconnected */ 120*4882a593Smuzhiyun #define INTR_BUS_SERV 0x10 /* bus service requested */ 121*4882a593Smuzhiyun #define INTR_DONE 0x08 /* function completed */ 122*4882a593Smuzhiyun #define INTR_RESELECTED 0x04 /* we were reselected */ 123*4882a593Smuzhiyun #define INTR_SEL_ATN 0x02 /* we were selected, ATN asserted */ 124*4882a593Smuzhiyun #define INTR_SELECT 0x01 /* we were selected, ATN negated */ 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* 127*4882a593Smuzhiyun * Encoding for the select timeout. 128*4882a593Smuzhiyun */ 129*4882a593Smuzhiyun #define TIMO_VAL(x) ((x) * 5000 / 7682) 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* 132*4882a593Smuzhiyun * Bits in sequence step register. 133*4882a593Smuzhiyun */ 134*4882a593Smuzhiyun #define SS_MASK 7 135*4882a593Smuzhiyun #define SS_ARB_SEL 0 /* Selection & arbitration complete */ 136*4882a593Smuzhiyun #define SS_MSG_SENT 1 /* One message byte sent */ 137*4882a593Smuzhiyun #define SS_NOT_CMD 2 /* Not in command phase */ 138*4882a593Smuzhiyun #define SS_PHASE_CHG 3 /* Early phase change, cmd bytes lost */ 139*4882a593Smuzhiyun #define SS_DONE 4 /* Command was sent OK */ 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /* 142*4882a593Smuzhiyun * Encoding for sync transfer period. 143*4882a593Smuzhiyun */ 144*4882a593Smuzhiyun #define SYNCP_MASK 0x1f 145*4882a593Smuzhiyun #define SYNCP_MIN 4 146*4882a593Smuzhiyun #define SYNCP_MAX 31 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* 149*4882a593Smuzhiyun * Bits in flags register. 150*4882a593Smuzhiyun */ 151*4882a593Smuzhiyun #define FLAGS_FIFO_LEV 0x1f 152*4882a593Smuzhiyun #define FLAGS_SEQ_STEP 0xe0 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* 155*4882a593Smuzhiyun * Encoding for sync offset. 156*4882a593Smuzhiyun */ 157*4882a593Smuzhiyun #define SYNCO_MASK 0x0f 158*4882a593Smuzhiyun #define SYNCO_ASS_CTRL 0x30 /* REQ/ACK assertion control */ 159*4882a593Smuzhiyun #define SYNCO_NEG_CTRL 0xc0 /* REQ/ACK negation control */ 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* 162*4882a593Smuzhiyun * Bits in config1 register. 163*4882a593Smuzhiyun */ 164*4882a593Smuzhiyun #define CF1_SLOW_CABLE 0x80 /* Slow cable mode */ 165*4882a593Smuzhiyun #define CF1_NO_RES_REP 0x40 /* Disable SCSI reset reports */ 166*4882a593Smuzhiyun #define CF1_PAR_TEST 0x20 /* Parity test mode enable */ 167*4882a593Smuzhiyun #define CF1_PAR_ENABLE 0x10 /* Enable parity checks */ 168*4882a593Smuzhiyun #define CF1_TEST 0x08 /* Chip tests */ 169*4882a593Smuzhiyun #define CF1_MY_ID 0x07 /* Controller's address on bus */ 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* 172*4882a593Smuzhiyun * Encoding for clk_factor register. 173*4882a593Smuzhiyun */ 174*4882a593Smuzhiyun #define CLKF_MASK 7 175*4882a593Smuzhiyun #define CLKF_VAL(freq) ((((freq) + 4999999) / 5000000) & CLKF_MASK) 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun /* 178*4882a593Smuzhiyun * Bits in test mode register. 179*4882a593Smuzhiyun */ 180*4882a593Smuzhiyun #define TEST_TARGET 1 /* target test mode */ 181*4882a593Smuzhiyun #define TEST_INITIATOR 2 /* initiator test mode */ 182*4882a593Smuzhiyun #define TEST_TRISTATE 4 /* tristate (hi-z) test mode */ 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun /* 185*4882a593Smuzhiyun * Bits in config2 register. 186*4882a593Smuzhiyun */ 187*4882a593Smuzhiyun #define CF2_RFB 0x80 188*4882a593Smuzhiyun #define CF2_FEATURE_EN 0x40 /* enable features / phase latch */ 189*4882a593Smuzhiyun #define CF2_BYTECTRL 0x20 190*4882a593Smuzhiyun #define CF2_DREQ_HIZ 0x10 191*4882a593Smuzhiyun #define CF2_SCSI2 0x08 192*4882a593Smuzhiyun #define CF2_PAR_ABORT 0x04 /* bad parity target abort */ 193*4882a593Smuzhiyun #define CF2_REG_PARERR 0x02 /* register parity error */ 194*4882a593Smuzhiyun #define CF2_DMA_PARERR 0x01 /* DMA parity error */ 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun /* 197*4882a593Smuzhiyun * Bits in the config3 register. 198*4882a593Smuzhiyun */ 199*4882a593Smuzhiyun #define CF3_ID_MSG_CHK 0x80 200*4882a593Smuzhiyun #define CF3_3B_MSGS 0x40 201*4882a593Smuzhiyun #define CF3_CDB10 0x20 202*4882a593Smuzhiyun #define CF3_FASTSCSI 0x10 /* enable fast SCSI support */ 203*4882a593Smuzhiyun #define CF3_FASTCLOCK 0x08 204*4882a593Smuzhiyun #define CF3_SAVERESID 0x04 205*4882a593Smuzhiyun #define CF3_ALT_DMA 0x02 206*4882a593Smuzhiyun #define CF3_THRESH_8 0x01 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun /* 209*4882a593Smuzhiyun * Bits in the config4 register. 210*4882a593Smuzhiyun */ 211*4882a593Smuzhiyun #define CF4_EAN 0x04 212*4882a593Smuzhiyun #define CF4_TEST 0x02 213*4882a593Smuzhiyun #define CF4_BBTE 0x01 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun #endif /* _MAC53C94_H */ 216