xref: /OK3568_Linux_fs/kernel/drivers/scsi/fnic/vnic_wq.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright 2008 Cisco Systems, Inc.  All rights reserved.
3*4882a593Smuzhiyun  * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * This program is free software; you may redistribute it and/or modify
6*4882a593Smuzhiyun  * it under the terms of the GNU General Public License as published by
7*4882a593Smuzhiyun  * the Free Software Foundation; version 2 of the License.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
10*4882a593Smuzhiyun  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11*4882a593Smuzhiyun  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
12*4882a593Smuzhiyun  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
13*4882a593Smuzhiyun  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
14*4882a593Smuzhiyun  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
15*4882a593Smuzhiyun  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
16*4882a593Smuzhiyun  * SOFTWARE.
17*4882a593Smuzhiyun  */
18*4882a593Smuzhiyun #ifndef _VNIC_WQ_H_
19*4882a593Smuzhiyun #define _VNIC_WQ_H_
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #include <linux/pci.h>
22*4882a593Smuzhiyun #include "vnic_dev.h"
23*4882a593Smuzhiyun #include "vnic_cq.h"
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun /*
26*4882a593Smuzhiyun  * These defines avoid symbol clash between fnic and enic (Cisco 10G Eth
27*4882a593Smuzhiyun  * Driver) when both are built with CONFIG options =y
28*4882a593Smuzhiyun  */
29*4882a593Smuzhiyun #define vnic_wq_desc_avail fnic_wq_desc_avail
30*4882a593Smuzhiyun #define vnic_wq_desc_used fnic_wq_desc_used
31*4882a593Smuzhiyun #define vnic_wq_next_desc fni_cwq_next_desc
32*4882a593Smuzhiyun #define vnic_wq_post fnic_wq_post
33*4882a593Smuzhiyun #define vnic_wq_service fnic_wq_service
34*4882a593Smuzhiyun #define vnic_wq_free fnic_wq_free
35*4882a593Smuzhiyun #define vnic_wq_alloc fnic_wq_alloc
36*4882a593Smuzhiyun #define vnic_wq_devcmd2_alloc fnic_wq_devcmd2_alloc
37*4882a593Smuzhiyun #define vnic_wq_init_start fnic_wq_init_start
38*4882a593Smuzhiyun #define vnic_wq_init fnic_wq_init
39*4882a593Smuzhiyun #define vnic_wq_error_status fnic_wq_error_status
40*4882a593Smuzhiyun #define vnic_wq_enable fnic_wq_enable
41*4882a593Smuzhiyun #define vnic_wq_disable fnic_wq_disable
42*4882a593Smuzhiyun #define vnic_wq_clean fnic_wq_clean
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun /* Work queue control */
45*4882a593Smuzhiyun struct vnic_wq_ctrl {
46*4882a593Smuzhiyun 	u64 ring_base;			/* 0x00 */
47*4882a593Smuzhiyun 	u32 ring_size;			/* 0x08 */
48*4882a593Smuzhiyun 	u32 pad0;
49*4882a593Smuzhiyun 	u32 posted_index;		/* 0x10 */
50*4882a593Smuzhiyun 	u32 pad1;
51*4882a593Smuzhiyun 	u32 cq_index;			/* 0x18 */
52*4882a593Smuzhiyun 	u32 pad2;
53*4882a593Smuzhiyun 	u32 enable;			/* 0x20 */
54*4882a593Smuzhiyun 	u32 pad3;
55*4882a593Smuzhiyun 	u32 running;			/* 0x28 */
56*4882a593Smuzhiyun 	u32 pad4;
57*4882a593Smuzhiyun 	u32 fetch_index;		/* 0x30 */
58*4882a593Smuzhiyun 	u32 pad5;
59*4882a593Smuzhiyun 	u32 dca_value;			/* 0x38 */
60*4882a593Smuzhiyun 	u32 pad6;
61*4882a593Smuzhiyun 	u32 error_interrupt_enable;	/* 0x40 */
62*4882a593Smuzhiyun 	u32 pad7;
63*4882a593Smuzhiyun 	u32 error_interrupt_offset;	/* 0x48 */
64*4882a593Smuzhiyun 	u32 pad8;
65*4882a593Smuzhiyun 	u32 error_status;		/* 0x50 */
66*4882a593Smuzhiyun 	u32 pad9;
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun struct vnic_wq_buf {
70*4882a593Smuzhiyun 	struct vnic_wq_buf *next;
71*4882a593Smuzhiyun 	dma_addr_t dma_addr;
72*4882a593Smuzhiyun 	void *os_buf;
73*4882a593Smuzhiyun 	unsigned int len;
74*4882a593Smuzhiyun 	unsigned int index;
75*4882a593Smuzhiyun 	int sop;
76*4882a593Smuzhiyun 	void *desc;
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun /* Break the vnic_wq_buf allocations into blocks of 64 entries */
80*4882a593Smuzhiyun #define VNIC_WQ_BUF_BLK_ENTRIES 64
81*4882a593Smuzhiyun #define VNIC_WQ_BUF_BLK_SZ \
82*4882a593Smuzhiyun 	(VNIC_WQ_BUF_BLK_ENTRIES * sizeof(struct vnic_wq_buf))
83*4882a593Smuzhiyun #define VNIC_WQ_BUF_BLKS_NEEDED(entries) \
84*4882a593Smuzhiyun 	DIV_ROUND_UP(entries, VNIC_WQ_BUF_BLK_ENTRIES)
85*4882a593Smuzhiyun #define VNIC_WQ_BUF_BLKS_MAX VNIC_WQ_BUF_BLKS_NEEDED(4096)
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun struct vnic_wq {
88*4882a593Smuzhiyun 	unsigned int index;
89*4882a593Smuzhiyun 	struct vnic_dev *vdev;
90*4882a593Smuzhiyun 	struct vnic_wq_ctrl __iomem *ctrl;	/* memory-mapped */
91*4882a593Smuzhiyun 	struct vnic_dev_ring ring;
92*4882a593Smuzhiyun 	struct vnic_wq_buf *bufs[VNIC_WQ_BUF_BLKS_MAX];
93*4882a593Smuzhiyun 	struct vnic_wq_buf *to_use;
94*4882a593Smuzhiyun 	struct vnic_wq_buf *to_clean;
95*4882a593Smuzhiyun 	unsigned int pkts_outstanding;
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun 
vnic_wq_desc_avail(struct vnic_wq * wq)98*4882a593Smuzhiyun static inline unsigned int vnic_wq_desc_avail(struct vnic_wq *wq)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun 	/* how many does SW own? */
101*4882a593Smuzhiyun 	return wq->ring.desc_avail;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun 
vnic_wq_desc_used(struct vnic_wq * wq)104*4882a593Smuzhiyun static inline unsigned int vnic_wq_desc_used(struct vnic_wq *wq)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun 	/* how many does HW own? */
107*4882a593Smuzhiyun 	return wq->ring.desc_count - wq->ring.desc_avail - 1;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun 
vnic_wq_next_desc(struct vnic_wq * wq)110*4882a593Smuzhiyun static inline void *vnic_wq_next_desc(struct vnic_wq *wq)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun 	return wq->to_use->desc;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun 
vnic_wq_post(struct vnic_wq * wq,void * os_buf,dma_addr_t dma_addr,unsigned int len,int sop,int eop)115*4882a593Smuzhiyun static inline void vnic_wq_post(struct vnic_wq *wq,
116*4882a593Smuzhiyun 	void *os_buf, dma_addr_t dma_addr,
117*4882a593Smuzhiyun 	unsigned int len, int sop, int eop)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun 	struct vnic_wq_buf *buf = wq->to_use;
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	buf->sop = sop;
122*4882a593Smuzhiyun 	buf->os_buf = eop ? os_buf : NULL;
123*4882a593Smuzhiyun 	buf->dma_addr = dma_addr;
124*4882a593Smuzhiyun 	buf->len = len;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	buf = buf->next;
127*4882a593Smuzhiyun 	if (eop) {
128*4882a593Smuzhiyun 		/* Adding write memory barrier prevents compiler and/or CPU
129*4882a593Smuzhiyun 		 * reordering, thus avoiding descriptor posting before
130*4882a593Smuzhiyun 		 * descriptor is initialized. Otherwise, hardware can read
131*4882a593Smuzhiyun 		 * stale descriptor fields.
132*4882a593Smuzhiyun 		 */
133*4882a593Smuzhiyun 		wmb();
134*4882a593Smuzhiyun 		iowrite32(buf->index, &wq->ctrl->posted_index);
135*4882a593Smuzhiyun 	}
136*4882a593Smuzhiyun 	wq->to_use = buf;
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	wq->ring.desc_avail--;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun 
vnic_wq_service(struct vnic_wq * wq,struct cq_desc * cq_desc,u16 completed_index,void (* buf_service)(struct vnic_wq * wq,struct cq_desc * cq_desc,struct vnic_wq_buf * buf,void * opaque),void * opaque)141*4882a593Smuzhiyun static inline void vnic_wq_service(struct vnic_wq *wq,
142*4882a593Smuzhiyun 	struct cq_desc *cq_desc, u16 completed_index,
143*4882a593Smuzhiyun 	void (*buf_service)(struct vnic_wq *wq,
144*4882a593Smuzhiyun 	struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque),
145*4882a593Smuzhiyun 	void *opaque)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun 	struct vnic_wq_buf *buf;
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	buf = wq->to_clean;
150*4882a593Smuzhiyun 	while (1) {
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 		(*buf_service)(wq, cq_desc, buf, opaque);
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 		wq->ring.desc_avail++;
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 		wq->to_clean = buf->next;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 		if (buf->index == completed_index)
159*4882a593Smuzhiyun 			break;
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 		buf = wq->to_clean;
162*4882a593Smuzhiyun 	}
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun void vnic_wq_free(struct vnic_wq *wq);
166*4882a593Smuzhiyun int vnic_wq_alloc(struct vnic_dev *vdev, struct vnic_wq *wq, unsigned int index,
167*4882a593Smuzhiyun 	unsigned int desc_count, unsigned int desc_size);
168*4882a593Smuzhiyun int vnic_wq_devcmd2_alloc(struct vnic_dev *vdev, struct vnic_wq *wq,
169*4882a593Smuzhiyun 		unsigned int desc_count, unsigned int desc_size);
170*4882a593Smuzhiyun void vnic_wq_init_start(struct vnic_wq *wq, unsigned int cq_index,
171*4882a593Smuzhiyun 		unsigned int fetch_index, unsigned int posted_index,
172*4882a593Smuzhiyun 		unsigned int error_interrupt_enable,
173*4882a593Smuzhiyun 		unsigned int error_interrupt_offset);
174*4882a593Smuzhiyun void vnic_wq_init(struct vnic_wq *wq, unsigned int cq_index,
175*4882a593Smuzhiyun 	unsigned int error_interrupt_enable,
176*4882a593Smuzhiyun 	unsigned int error_interrupt_offset);
177*4882a593Smuzhiyun unsigned int vnic_wq_error_status(struct vnic_wq *wq);
178*4882a593Smuzhiyun void vnic_wq_enable(struct vnic_wq *wq);
179*4882a593Smuzhiyun int vnic_wq_disable(struct vnic_wq *wq);
180*4882a593Smuzhiyun void vnic_wq_clean(struct vnic_wq *wq,
181*4882a593Smuzhiyun 	void (*buf_clean)(struct vnic_wq *wq, struct vnic_wq_buf *buf));
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun #endif /* _VNIC_WQ_H_ */
184