1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2008 Cisco Systems, Inc. All rights reserved. 3*4882a593Smuzhiyun * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you may redistribute it and/or modify 6*4882a593Smuzhiyun * it under the terms of the GNU General Public License as published by 7*4882a593Smuzhiyun * the Free Software Foundation; version 2 of the License. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 10*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 11*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 12*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 13*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 14*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 15*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 16*4882a593Smuzhiyun * SOFTWARE. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #ifndef _FNIC_IO_H_ 19*4882a593Smuzhiyun #define _FNIC_IO_H_ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #include <scsi/fc/fc_fcp.h> 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define FNIC_DFLT_SG_DESC_CNT 32 24*4882a593Smuzhiyun #define FNIC_MAX_SG_DESC_CNT 256 /* Maximum descriptors per sgl */ 25*4882a593Smuzhiyun #define FNIC_SG_DESC_ALIGN 16 /* Descriptor address alignment */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun struct host_sg_desc { 28*4882a593Smuzhiyun __le64 addr; 29*4882a593Smuzhiyun __le32 len; 30*4882a593Smuzhiyun u32 _resvd; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun struct fnic_dflt_sgl_list { 34*4882a593Smuzhiyun struct host_sg_desc sg_desc[FNIC_DFLT_SG_DESC_CNT]; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun struct fnic_sgl_list { 38*4882a593Smuzhiyun struct host_sg_desc sg_desc[FNIC_MAX_SG_DESC_CNT]; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun enum fnic_sgl_list_type { 42*4882a593Smuzhiyun FNIC_SGL_CACHE_DFLT = 0, /* cache with default size sgl */ 43*4882a593Smuzhiyun FNIC_SGL_CACHE_MAX, /* cache with max size sgl */ 44*4882a593Smuzhiyun FNIC_SGL_NUM_CACHES /* number of sgl caches */ 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun enum fnic_ioreq_state { 48*4882a593Smuzhiyun FNIC_IOREQ_NOT_INITED = 0, 49*4882a593Smuzhiyun FNIC_IOREQ_CMD_PENDING, 50*4882a593Smuzhiyun FNIC_IOREQ_ABTS_PENDING, 51*4882a593Smuzhiyun FNIC_IOREQ_ABTS_COMPLETE, 52*4882a593Smuzhiyun FNIC_IOREQ_CMD_COMPLETE, 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun struct fnic_io_req { 56*4882a593Smuzhiyun struct host_sg_desc *sgl_list; /* sgl list */ 57*4882a593Smuzhiyun void *sgl_list_alloc; /* sgl list address used for free */ 58*4882a593Smuzhiyun dma_addr_t sense_buf_pa; /* dma address for sense buffer*/ 59*4882a593Smuzhiyun dma_addr_t sgl_list_pa; /* dma address for sgl list */ 60*4882a593Smuzhiyun u16 sgl_cnt; 61*4882a593Smuzhiyun u8 sgl_type; /* device DMA descriptor list type */ 62*4882a593Smuzhiyun u8 io_completed:1; /* set to 1 when fw completes IO */ 63*4882a593Smuzhiyun u32 port_id; /* remote port DID */ 64*4882a593Smuzhiyun unsigned long start_time; /* in jiffies */ 65*4882a593Smuzhiyun struct completion *abts_done; /* completion for abts */ 66*4882a593Smuzhiyun struct completion *dr_done; /* completion for device reset */ 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun enum fnic_port_speeds { 70*4882a593Smuzhiyun DCEM_PORTSPEED_NONE = 0, 71*4882a593Smuzhiyun DCEM_PORTSPEED_1G = 1000, 72*4882a593Smuzhiyun DCEM_PORTSPEED_10G = 10000, 73*4882a593Smuzhiyun DCEM_PORTSPEED_20G = 20000, 74*4882a593Smuzhiyun DCEM_PORTSPEED_25G = 25000, 75*4882a593Smuzhiyun DCEM_PORTSPEED_40G = 40000, 76*4882a593Smuzhiyun DCEM_PORTSPEED_4x10G = 41000, 77*4882a593Smuzhiyun DCEM_PORTSPEED_100G = 100000, 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun #endif /* _FNIC_IO_H_ */ 80