1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /*************************************************************************** 3*4882a593Smuzhiyun dpti_ioctl.h - description 4*4882a593Smuzhiyun ------------------- 5*4882a593Smuzhiyun begin : Thu Sep 7 2000 6*4882a593Smuzhiyun copyright : (C) 2001 by Adaptec 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun See Documentation/scsi/dpti.rst for history, notes, license info 9*4882a593Smuzhiyun and credits 10*4882a593Smuzhiyun ***************************************************************************/ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /*************************************************************************** 13*4882a593Smuzhiyun * * 14*4882a593Smuzhiyun * * 15*4882a593Smuzhiyun ***************************************************************************/ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /*************************************************************************** 18*4882a593Smuzhiyun * This file is generated from osd_unix.h * 19*4882a593Smuzhiyun * *************************************************************************/ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #ifndef _dpti_ioctl_h 22*4882a593Smuzhiyun #define _dpti_ioctl_h 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun // IOCTL interface commands 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #ifndef _IOWR 27*4882a593Smuzhiyun # define _IOWR(x,y,z) (((x)<<8)|y) 28*4882a593Smuzhiyun #endif 29*4882a593Smuzhiyun #ifndef _IOW 30*4882a593Smuzhiyun # define _IOW(x,y,z) (((x)<<8)|y) 31*4882a593Smuzhiyun #endif 32*4882a593Smuzhiyun #ifndef _IOR 33*4882a593Smuzhiyun # define _IOR(x,y,z) (((x)<<8)|y) 34*4882a593Smuzhiyun #endif 35*4882a593Smuzhiyun #ifndef _IO 36*4882a593Smuzhiyun # define _IO(x,y) (((x)<<8)|y) 37*4882a593Smuzhiyun #endif 38*4882a593Smuzhiyun /* EATA PassThrough Command */ 39*4882a593Smuzhiyun #define EATAUSRCMD _IOWR('D',65,EATA_CP) 40*4882a593Smuzhiyun /* Set Debug Level If Enabled */ 41*4882a593Smuzhiyun #define DPT_DEBUG _IOW('D',66,int) 42*4882a593Smuzhiyun /* Get Signature Structure */ 43*4882a593Smuzhiyun #define DPT_SIGNATURE _IOR('D',67,dpt_sig_S) 44*4882a593Smuzhiyun #if defined __bsdi__ 45*4882a593Smuzhiyun #define DPT_SIGNATURE_PACKED _IOR('D',67,dpt_sig_S_Packed) 46*4882a593Smuzhiyun #endif 47*4882a593Smuzhiyun /* Get Number Of DPT Adapters */ 48*4882a593Smuzhiyun #define DPT_NUMCTRLS _IOR('D',68,int) 49*4882a593Smuzhiyun /* Get Adapter Info Structure */ 50*4882a593Smuzhiyun #define DPT_CTRLINFO _IOR('D',69,CtrlInfo) 51*4882a593Smuzhiyun /* Get Statistics If Enabled */ 52*4882a593Smuzhiyun #define DPT_STATINFO _IO('D',70) 53*4882a593Smuzhiyun /* Clear Stats If Enabled */ 54*4882a593Smuzhiyun #define DPT_CLRSTAT _IO('D',71) 55*4882a593Smuzhiyun /* Get System Info Structure */ 56*4882a593Smuzhiyun #define DPT_SYSINFO _IOR('D',72,sysInfo_S) 57*4882a593Smuzhiyun /* Set Timeout Value */ 58*4882a593Smuzhiyun #define DPT_TIMEOUT _IO('D',73) 59*4882a593Smuzhiyun /* Get config Data */ 60*4882a593Smuzhiyun #define DPT_CONFIG _IO('D',74) 61*4882a593Smuzhiyun /* Get Blink LED Code */ 62*4882a593Smuzhiyun #define DPT_BLINKLED _IOR('D',75,int) 63*4882a593Smuzhiyun /* Get Statistical information (if available) */ 64*4882a593Smuzhiyun #define DPT_STATS_INFO _IOR('D',80,STATS_DATA) 65*4882a593Smuzhiyun /* Clear the statistical information */ 66*4882a593Smuzhiyun #define DPT_STATS_CLEAR _IO('D',81) 67*4882a593Smuzhiyun /* Get Performance metrics */ 68*4882a593Smuzhiyun #define DPT_PERF_INFO _IOR('D',82,dpt_perf_t) 69*4882a593Smuzhiyun /* Send an I2O command */ 70*4882a593Smuzhiyun #define I2OUSRCMD _IO('D',76) 71*4882a593Smuzhiyun /* Inform driver to re-acquire LCT information */ 72*4882a593Smuzhiyun #define I2ORESCANCMD _IO('D',77) 73*4882a593Smuzhiyun /* Inform driver to reset adapter */ 74*4882a593Smuzhiyun #define I2ORESETCMD _IO('D',78) 75*4882a593Smuzhiyun /* See if the target is mounted */ 76*4882a593Smuzhiyun #define DPT_TARGET_BUSY _IOR('D',79, TARGET_BUSY_T) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* Structure Returned From Get Controller Info */ 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun typedef struct { 82*4882a593Smuzhiyun uCHAR state; /* Operational state */ 83*4882a593Smuzhiyun uCHAR id; /* Host adapter SCSI id */ 84*4882a593Smuzhiyun int vect; /* Interrupt vector number */ 85*4882a593Smuzhiyun int base; /* Base I/O address */ 86*4882a593Smuzhiyun int njobs; /* # of jobs sent to HA */ 87*4882a593Smuzhiyun int qdepth; /* Controller queue depth. */ 88*4882a593Smuzhiyun int wakebase; /* mpx wakeup base index. */ 89*4882a593Smuzhiyun uINT SGsize; /* Scatter/Gather list size. */ 90*4882a593Smuzhiyun unsigned heads; /* heads for drives on cntlr. */ 91*4882a593Smuzhiyun unsigned sectors; /* sectors for drives on cntlr. */ 92*4882a593Smuzhiyun uCHAR do_drive32; /* Flag for Above 16 MB Ability */ 93*4882a593Smuzhiyun uCHAR BusQuiet; /* SCSI Bus Quiet Flag */ 94*4882a593Smuzhiyun char idPAL[4]; /* 4 Bytes Of The ID Pal */ 95*4882a593Smuzhiyun uCHAR primary; /* 1 For Primary, 0 For Secondary */ 96*4882a593Smuzhiyun uCHAR eataVersion; /* EATA Version */ 97*4882a593Smuzhiyun uINT cpLength; /* EATA Command Packet Length */ 98*4882a593Smuzhiyun uINT spLength; /* EATA Status Packet Length */ 99*4882a593Smuzhiyun uCHAR drqNum; /* DRQ Index (0,5,6,7) */ 100*4882a593Smuzhiyun uCHAR flag1; /* EATA Flags 1 (Byte 9) */ 101*4882a593Smuzhiyun uCHAR flag2; /* EATA Flags 2 (Byte 30) */ 102*4882a593Smuzhiyun } CtrlInfo; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun typedef struct { 105*4882a593Smuzhiyun uSHORT length; // Remaining length of this 106*4882a593Smuzhiyun uSHORT drvrHBAnum; // Relative HBA # used by the driver 107*4882a593Smuzhiyun uINT baseAddr; // Base I/O address 108*4882a593Smuzhiyun uSHORT blinkState; // Blink LED state (0=Not in blink LED) 109*4882a593Smuzhiyun uCHAR pciBusNum; // PCI Bus # (Optional) 110*4882a593Smuzhiyun uCHAR pciDeviceNum; // PCI Device # (Optional) 111*4882a593Smuzhiyun uSHORT hbaFlags; // Miscellaneous HBA flags 112*4882a593Smuzhiyun uSHORT Interrupt; // Interrupt set for this device. 113*4882a593Smuzhiyun # if (defined(_DPT_ARC)) 114*4882a593Smuzhiyun uINT baseLength; 115*4882a593Smuzhiyun ADAPTER_OBJECT *AdapterObject; 116*4882a593Smuzhiyun LARGE_INTEGER DmaLogicalAddress; 117*4882a593Smuzhiyun PVOID DmaVirtualAddress; 118*4882a593Smuzhiyun LARGE_INTEGER ReplyLogicalAddress; 119*4882a593Smuzhiyun PVOID ReplyVirtualAddress; 120*4882a593Smuzhiyun # else 121*4882a593Smuzhiyun uINT reserved1; // Reserved for future expansion 122*4882a593Smuzhiyun uINT reserved2; // Reserved for future expansion 123*4882a593Smuzhiyun uINT reserved3; // Reserved for future expansion 124*4882a593Smuzhiyun # endif 125*4882a593Smuzhiyun } drvrHBAinfo_S; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun typedef struct TARGET_BUSY 128*4882a593Smuzhiyun { 129*4882a593Smuzhiyun uLONG channel; 130*4882a593Smuzhiyun uLONG id; 131*4882a593Smuzhiyun uLONG lun; 132*4882a593Smuzhiyun uLONG isBusy; 133*4882a593Smuzhiyun } TARGET_BUSY_T; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #endif 136*4882a593Smuzhiyun 137