1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * CXL Flash Device Driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Written by: Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation 6*4882a593Smuzhiyun * Uma Krishnan <ukrishn@linux.vnet.ibm.com>, IBM Corporation 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2018 IBM Corporation 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define OCXL_MAX_IRQS 4 /* Max interrupts per process */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct ocxlflash_irqs { 14*4882a593Smuzhiyun int hwirq; 15*4882a593Smuzhiyun u32 virq; 16*4882a593Smuzhiyun void __iomem *vtrig; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* OCXL hardware AFU associated with the host */ 20*4882a593Smuzhiyun struct ocxl_hw_afu { 21*4882a593Smuzhiyun struct ocxlflash_context *ocxl_ctx; /* Host context */ 22*4882a593Smuzhiyun struct pci_dev *pdev; /* PCI device */ 23*4882a593Smuzhiyun struct device *dev; /* Generic device */ 24*4882a593Smuzhiyun bool perst_same_image; /* Same image loaded on perst */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun struct ocxl_fn_config fcfg; /* DVSEC config of the function */ 27*4882a593Smuzhiyun struct ocxl_afu_config acfg; /* AFU configuration data */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun int fn_actag_base; /* Function acTag base */ 30*4882a593Smuzhiyun int fn_actag_enabled; /* Function acTag number enabled */ 31*4882a593Smuzhiyun int afu_actag_base; /* AFU acTag base */ 32*4882a593Smuzhiyun int afu_actag_enabled; /* AFU acTag number enabled */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun phys_addr_t ppmmio_phys; /* Per process MMIO space */ 35*4882a593Smuzhiyun phys_addr_t gmmio_phys; /* Global AFU MMIO space */ 36*4882a593Smuzhiyun void __iomem *gmmio_virt; /* Global MMIO map */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun void *link_token; /* Link token for the SPA */ 39*4882a593Smuzhiyun struct idr idr; /* IDR to manage contexts */ 40*4882a593Smuzhiyun int max_pasid; /* Maximum number of contexts */ 41*4882a593Smuzhiyun bool is_present; /* Function has AFUs defined */ 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun enum ocxlflash_ctx_state { 45*4882a593Smuzhiyun CLOSED, 46*4882a593Smuzhiyun OPENED, 47*4882a593Smuzhiyun STARTED 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun struct ocxlflash_context { 51*4882a593Smuzhiyun struct ocxl_hw_afu *hw_afu; /* HW AFU back pointer */ 52*4882a593Smuzhiyun struct address_space *mapping; /* Mapping for pseudo filesystem */ 53*4882a593Smuzhiyun bool master; /* Whether this is a master context */ 54*4882a593Smuzhiyun int pe; /* Process element */ 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun phys_addr_t psn_phys; /* Process mapping */ 57*4882a593Smuzhiyun u64 psn_size; /* Process mapping size */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun spinlock_t slock; /* Protects irq/fault/event updates */ 60*4882a593Smuzhiyun wait_queue_head_t wq; /* Wait queue for poll and interrupts */ 61*4882a593Smuzhiyun struct mutex state_mutex; /* Mutex to update context state */ 62*4882a593Smuzhiyun enum ocxlflash_ctx_state state; /* Context state */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun struct ocxlflash_irqs *irqs; /* Pointer to array of structures */ 65*4882a593Smuzhiyun int num_irqs; /* Number of interrupts */ 66*4882a593Smuzhiyun bool pending_irq; /* Pending interrupt on the context */ 67*4882a593Smuzhiyun ulong irq_bitmap; /* Bits indicating pending irq num */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun u64 fault_addr; /* Address that triggered the fault */ 70*4882a593Smuzhiyun u64 fault_dsisr; /* Value of dsisr register at fault */ 71*4882a593Smuzhiyun bool pending_fault; /* Pending translation fault */ 72*4882a593Smuzhiyun }; 73