1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * CXL Flash Device Driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation 6*4882a593Smuzhiyun * Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2015 IBM Corporation 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _CXLFLASH_MAIN_H 12*4882a593Smuzhiyun #define _CXLFLASH_MAIN_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <linux/list.h> 15*4882a593Smuzhiyun #include <linux/types.h> 16*4882a593Smuzhiyun #include <scsi/scsi.h> 17*4882a593Smuzhiyun #include <scsi/scsi_device.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #include "backend.h" 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define CXLFLASH_NAME "cxlflash" 22*4882a593Smuzhiyun #define CXLFLASH_ADAPTER_NAME "IBM POWER CXL Flash Adapter" 23*4882a593Smuzhiyun #define CXLFLASH_MAX_ADAPTERS 32 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define PCI_DEVICE_ID_IBM_CORSA 0x04F0 26*4882a593Smuzhiyun #define PCI_DEVICE_ID_IBM_FLASH_GT 0x0600 27*4882a593Smuzhiyun #define PCI_DEVICE_ID_IBM_BRIARD 0x0624 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Since there is only one target, make it 0 */ 30*4882a593Smuzhiyun #define CXLFLASH_TARGET 0 31*4882a593Smuzhiyun #define CXLFLASH_MAX_CDB_LEN 16 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Really only one target per bus since the Texan is directly attached */ 34*4882a593Smuzhiyun #define CXLFLASH_MAX_NUM_TARGETS_PER_BUS 1 35*4882a593Smuzhiyun #define CXLFLASH_MAX_NUM_LUNS_PER_TARGET 65536 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define CXLFLASH_PCI_ERROR_RECOVERY_TIMEOUT (120 * HZ) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* FC defines */ 40*4882a593Smuzhiyun #define FC_MTIP_CMDCONFIG 0x010 41*4882a593Smuzhiyun #define FC_MTIP_STATUS 0x018 42*4882a593Smuzhiyun #define FC_MAX_NUM_LUNS 0x080 /* Max LUNs host can provision for port */ 43*4882a593Smuzhiyun #define FC_CUR_NUM_LUNS 0x088 /* Cur number LUNs provisioned for port */ 44*4882a593Smuzhiyun #define FC_MAX_CAP_PORT 0x090 /* Max capacity all LUNs for port (4K blocks) */ 45*4882a593Smuzhiyun #define FC_CUR_CAP_PORT 0x098 /* Cur capacity all LUNs for port (4K blocks) */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define FC_PNAME 0x300 48*4882a593Smuzhiyun #define FC_CONFIG 0x320 49*4882a593Smuzhiyun #define FC_CONFIG2 0x328 50*4882a593Smuzhiyun #define FC_STATUS 0x330 51*4882a593Smuzhiyun #define FC_ERROR 0x380 52*4882a593Smuzhiyun #define FC_ERRCAP 0x388 53*4882a593Smuzhiyun #define FC_ERRMSK 0x390 54*4882a593Smuzhiyun #define FC_CNT_CRCERR 0x538 55*4882a593Smuzhiyun #define FC_CRC_THRESH 0x580 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define FC_MTIP_CMDCONFIG_ONLINE 0x20ULL 58*4882a593Smuzhiyun #define FC_MTIP_CMDCONFIG_OFFLINE 0x40ULL 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define FC_MTIP_STATUS_MASK 0x30ULL 61*4882a593Smuzhiyun #define FC_MTIP_STATUS_ONLINE 0x20ULL 62*4882a593Smuzhiyun #define FC_MTIP_STATUS_OFFLINE 0x10ULL 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* TIMEOUT and RETRY definitions */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* AFU command timeout values */ 67*4882a593Smuzhiyun #define MC_AFU_SYNC_TIMEOUT 5 /* 5 secs */ 68*4882a593Smuzhiyun #define MC_LUN_PROV_TIMEOUT 5 /* 5 secs */ 69*4882a593Smuzhiyun #define MC_AFU_DEBUG_TIMEOUT 5 /* 5 secs */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* AFU command room retry limit */ 72*4882a593Smuzhiyun #define MC_ROOM_RETRY_CNT 10 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* FC CRC clear periodic timer */ 75*4882a593Smuzhiyun #define MC_CRC_THRESH 100 /* threshold in 5 mins */ 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define FC_PORT_STATUS_RETRY_CNT 100 /* 100 100ms retries = 10 seconds */ 78*4882a593Smuzhiyun #define FC_PORT_STATUS_RETRY_INTERVAL_US 100000 /* microseconds */ 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* VPD defines */ 81*4882a593Smuzhiyun #define CXLFLASH_VPD_LEN 256 82*4882a593Smuzhiyun #define WWPN_LEN 16 83*4882a593Smuzhiyun #define WWPN_BUF_LEN (WWPN_LEN + 1) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun enum undo_level { 86*4882a593Smuzhiyun UNDO_NOOP = 0, 87*4882a593Smuzhiyun FREE_IRQ, 88*4882a593Smuzhiyun UNMAP_ONE, 89*4882a593Smuzhiyun UNMAP_TWO, 90*4882a593Smuzhiyun UNMAP_THREE 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun struct dev_dependent_vals { 94*4882a593Smuzhiyun u64 max_sectors; 95*4882a593Smuzhiyun u64 flags; 96*4882a593Smuzhiyun #define CXLFLASH_NOTIFY_SHUTDOWN 0x0000000000000001ULL 97*4882a593Smuzhiyun #define CXLFLASH_WWPN_VPD_REQUIRED 0x0000000000000002ULL 98*4882a593Smuzhiyun #define CXLFLASH_OCXL_DEV 0x0000000000000004ULL 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun static inline const struct cxlflash_backend_ops * cxlflash_assign_ops(struct dev_dependent_vals * ddv)102*4882a593Smuzhiyuncxlflash_assign_ops(struct dev_dependent_vals *ddv) 103*4882a593Smuzhiyun { 104*4882a593Smuzhiyun const struct cxlflash_backend_ops *ops = NULL; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #ifdef CONFIG_OCXL_BASE 107*4882a593Smuzhiyun if (ddv->flags & CXLFLASH_OCXL_DEV) 108*4882a593Smuzhiyun ops = &cxlflash_ocxl_ops; 109*4882a593Smuzhiyun #endif 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #ifdef CONFIG_CXL_BASE 112*4882a593Smuzhiyun if (!(ddv->flags & CXLFLASH_OCXL_DEV)) 113*4882a593Smuzhiyun ops = &cxlflash_cxl_ops; 114*4882a593Smuzhiyun #endif 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun return ops; 117*4882a593Smuzhiyun } 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun struct asyc_intr_info { 120*4882a593Smuzhiyun u64 status; 121*4882a593Smuzhiyun char *desc; 122*4882a593Smuzhiyun u8 port; 123*4882a593Smuzhiyun u8 action; 124*4882a593Smuzhiyun #define CLR_FC_ERROR 0x01 125*4882a593Smuzhiyun #define LINK_RESET 0x02 126*4882a593Smuzhiyun #define SCAN_HOST 0x04 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #endif /* _CXLFLASH_MAIN_H */ 130