xref: /OK3568_Linux_fs/kernel/drivers/scsi/bnx2i/bnx2i.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* bnx2i.h: QLogic NetXtreme II iSCSI driver.
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * Copyright (c) 2006 - 2013 Broadcom Corporation
4*4882a593Smuzhiyun  * Copyright (c) 2007, 2008 Red Hat, Inc.  All rights reserved.
5*4882a593Smuzhiyun  * Copyright (c) 2007, 2008 Mike Christie
6*4882a593Smuzhiyun  * Copyright (c) 2014, QLogic Corporation
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify
9*4882a593Smuzhiyun  * it under the terms of the GNU General Public License as published by
10*4882a593Smuzhiyun  * the Free Software Foundation.
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * Written by: Anil Veerabhadrappa (anilgv@broadcom.com)
13*4882a593Smuzhiyun  * Previously Maintained by: Eddie Wai (eddie.wai@broadcom.com)
14*4882a593Smuzhiyun  * Maintained by: QLogic-Storage-Upstream@qlogic.com
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #ifndef _BNX2I_H_
18*4882a593Smuzhiyun #define _BNX2I_H_
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include <linux/module.h>
21*4882a593Smuzhiyun #include <linux/moduleparam.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #include <linux/errno.h>
24*4882a593Smuzhiyun #include <linux/pci.h>
25*4882a593Smuzhiyun #include <linux/spinlock.h>
26*4882a593Smuzhiyun #include <linux/interrupt.h>
27*4882a593Smuzhiyun #include <linux/delay.h>
28*4882a593Smuzhiyun #include <linux/sched/signal.h>
29*4882a593Smuzhiyun #include <linux/in.h>
30*4882a593Smuzhiyun #include <linux/kfifo.h>
31*4882a593Smuzhiyun #include <linux/netdevice.h>
32*4882a593Smuzhiyun #include <linux/completion.h>
33*4882a593Smuzhiyun #include <linux/kthread.h>
34*4882a593Smuzhiyun #include <linux/cpu.h>
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #include <scsi/scsi_cmnd.h>
37*4882a593Smuzhiyun #include <scsi/scsi_device.h>
38*4882a593Smuzhiyun #include <scsi/scsi_eh.h>
39*4882a593Smuzhiyun #include <scsi/scsi_host.h>
40*4882a593Smuzhiyun #include <scsi/scsi.h>
41*4882a593Smuzhiyun #include <scsi/iscsi_proto.h>
42*4882a593Smuzhiyun #include <scsi/libiscsi.h>
43*4882a593Smuzhiyun #include <scsi/scsi_transport_iscsi.h>
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #include "../../net/ethernet/broadcom/cnic_if.h"
46*4882a593Smuzhiyun #include "57xx_iscsi_hsi.h"
47*4882a593Smuzhiyun #include "57xx_iscsi_constants.h"
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun #include "../../net/ethernet/broadcom/bnx2x/bnx2x_mfw_req.h"
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun #define BNX2_ISCSI_DRIVER_NAME		"bnx2i"
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun #define BNX2I_MAX_ADAPTERS		8
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun #define ISCSI_MAX_CONNS_PER_HBA		128
56*4882a593Smuzhiyun #define ISCSI_MAX_SESS_PER_HBA		ISCSI_MAX_CONNS_PER_HBA
57*4882a593Smuzhiyun #define ISCSI_MAX_CMDS_PER_SESS		128
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun /* Total active commands across all connections supported by devices */
60*4882a593Smuzhiyun #define ISCSI_MAX_CMDS_PER_HBA_5708	(28 * (ISCSI_MAX_CMDS_PER_SESS - 1))
61*4882a593Smuzhiyun #define ISCSI_MAX_CMDS_PER_HBA_5709	(128 * (ISCSI_MAX_CMDS_PER_SESS - 1))
62*4882a593Smuzhiyun #define ISCSI_MAX_CMDS_PER_HBA_57710	(256 * (ISCSI_MAX_CMDS_PER_SESS - 1))
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun #define ISCSI_MAX_BDS_PER_CMD		32
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun #define MAX_PAGES_PER_CTRL_STRUCT_POOL	8
67*4882a593Smuzhiyun #define BNX2I_RESERVED_SLOW_PATH_CMD_SLOTS	4
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun #define BNX2X_DB_SHIFT			3
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun /* 5706/08 hardware has limit on maximum buffer size per BD it can handle */
72*4882a593Smuzhiyun #define MAX_BD_LENGTH			65535
73*4882a593Smuzhiyun #define BD_SPLIT_SIZE			32768
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun /* min, max & default values for SQ/RQ/CQ size, configurable via' modparam */
76*4882a593Smuzhiyun #define BNX2I_SQ_WQES_MIN		16
77*4882a593Smuzhiyun #define BNX2I_570X_SQ_WQES_MAX		128
78*4882a593Smuzhiyun #define BNX2I_5770X_SQ_WQES_MAX		512
79*4882a593Smuzhiyun #define BNX2I_570X_SQ_WQES_DEFAULT	128
80*4882a593Smuzhiyun #define BNX2I_5770X_SQ_WQES_DEFAULT	128
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun #define BNX2I_570X_CQ_WQES_MAX 		128
83*4882a593Smuzhiyun #define BNX2I_5770X_CQ_WQES_MAX 	512
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun #define BNX2I_RQ_WQES_MIN 		16
86*4882a593Smuzhiyun #define BNX2I_RQ_WQES_MAX 		32
87*4882a593Smuzhiyun #define BNX2I_RQ_WQES_DEFAULT 		16
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun /* CCELLs per conn */
90*4882a593Smuzhiyun #define BNX2I_CCELLS_MIN		16
91*4882a593Smuzhiyun #define BNX2I_CCELLS_MAX		96
92*4882a593Smuzhiyun #define BNX2I_CCELLS_DEFAULT		64
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun #define ITT_INVALID_SIGNATURE		0xFFFF
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun #define ISCSI_CMD_CLEANUP_TIMEOUT	100
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun #define BNX2I_CONN_CTX_BUF_SIZE		16384
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun #define BNX2I_SQ_WQE_SIZE		64
101*4882a593Smuzhiyun #define BNX2I_RQ_WQE_SIZE		256
102*4882a593Smuzhiyun #define BNX2I_CQE_SIZE			64
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun #define MB_KERNEL_CTX_SHIFT		8
105*4882a593Smuzhiyun #define MB_KERNEL_CTX_SIZE		(1 << MB_KERNEL_CTX_SHIFT)
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun #define CTX_SHIFT			7
108*4882a593Smuzhiyun #define GET_CID_NUM(cid_addr)		((cid_addr) >> CTX_SHIFT)
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun #define CTX_OFFSET 			0x10000
111*4882a593Smuzhiyun #define MAX_CID_CNT			0x4000
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun #define BNX2I_570X_PAGE_SIZE_DEFAULT	4096
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun /* 5709 context registers */
116*4882a593Smuzhiyun #define BNX2_MQ_CONFIG2			0x00003d00
117*4882a593Smuzhiyun #define BNX2_MQ_CONFIG2_CONT_SZ		(0x7L<<4)
118*4882a593Smuzhiyun #define BNX2_MQ_CONFIG2_FIRST_L4L5	(0x1fL<<8)
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun /* 57710's BAR2 is mapped to doorbell registers */
121*4882a593Smuzhiyun #define BNX2X_DOORBELL_PCI_BAR		2
122*4882a593Smuzhiyun #define BNX2X_MAX_CQS			8
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun #define CNIC_ARM_CQE			1
125*4882a593Smuzhiyun #define CNIC_ARM_CQE_FP			2
126*4882a593Smuzhiyun #define CNIC_DISARM_CQE			0
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun #define REG_RD(__hba, offset)				\
129*4882a593Smuzhiyun 		readl(__hba->regview + offset)
130*4882a593Smuzhiyun #define REG_WR(__hba, offset, val)			\
131*4882a593Smuzhiyun 		writel(val, __hba->regview + offset)
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun #ifdef CONFIG_32BIT
134*4882a593Smuzhiyun #define GET_STATS_64(__hba, dst, field)				\
135*4882a593Smuzhiyun 	do {							\
136*4882a593Smuzhiyun 		spin_lock_bh(&__hba->stat_lock);		\
137*4882a593Smuzhiyun 		dst->field##_lo = __hba->stats.field##_lo;	\
138*4882a593Smuzhiyun 		dst->field##_hi = __hba->stats.field##_hi;	\
139*4882a593Smuzhiyun 		spin_unlock_bh(&__hba->stat_lock);		\
140*4882a593Smuzhiyun 	} while (0)
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun #define ADD_STATS_64(__hba, field, len)				\
143*4882a593Smuzhiyun 	do {							\
144*4882a593Smuzhiyun 		if (spin_trylock(&__hba->stat_lock)) {		\
145*4882a593Smuzhiyun 			if (__hba->stats.field##_lo + len <	\
146*4882a593Smuzhiyun 			    __hba->stats.field##_lo)		\
147*4882a593Smuzhiyun 				__hba->stats.field##_hi++;	\
148*4882a593Smuzhiyun 			__hba->stats.field##_lo += len;		\
149*4882a593Smuzhiyun 			spin_unlock(&__hba->stat_lock);		\
150*4882a593Smuzhiyun 		}						\
151*4882a593Smuzhiyun 	} while (0)
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun #else
154*4882a593Smuzhiyun #define GET_STATS_64(__hba, dst, field)				\
155*4882a593Smuzhiyun 	do {							\
156*4882a593Smuzhiyun 		u64 val, *out;					\
157*4882a593Smuzhiyun 								\
158*4882a593Smuzhiyun 		val = __hba->bnx2i_stats.field;			\
159*4882a593Smuzhiyun 		out = (u64 *)&__hba->stats.field##_lo;		\
160*4882a593Smuzhiyun 		*out = cpu_to_le64(val);			\
161*4882a593Smuzhiyun 		out = (u64 *)&dst->field##_lo;			\
162*4882a593Smuzhiyun 		*out = cpu_to_le64(val);			\
163*4882a593Smuzhiyun 	} while (0)
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun #define ADD_STATS_64(__hba, field, len)				\
166*4882a593Smuzhiyun 	do {							\
167*4882a593Smuzhiyun 		__hba->bnx2i_stats.field += len;		\
168*4882a593Smuzhiyun 	} while (0)
169*4882a593Smuzhiyun #endif
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun /**
172*4882a593Smuzhiyun  * struct generic_pdu_resc - login pdu resource structure
173*4882a593Smuzhiyun  *
174*4882a593Smuzhiyun  * @req_buf:            driver buffer used to stage payload associated with
175*4882a593Smuzhiyun  *                      the login request
176*4882a593Smuzhiyun  * @req_dma_addr:       dma address for iscsi login request payload buffer
177*4882a593Smuzhiyun  * @req_buf_size:       actual login request payload length
178*4882a593Smuzhiyun  * @req_wr_ptr:         pointer into login request buffer when next data is
179*4882a593Smuzhiyun  *                      to be written
180*4882a593Smuzhiyun  * @resp_hdr:           iscsi header where iscsi login response header is to
181*4882a593Smuzhiyun  *                      be recreated
182*4882a593Smuzhiyun  * @resp_buf:           buffer to stage login response payload
183*4882a593Smuzhiyun  * @resp_dma_addr:      login response payload buffer dma address
184*4882a593Smuzhiyun  * @resp_buf_size:      login response paylod length
185*4882a593Smuzhiyun  * @resp_wr_ptr:        pointer into login response buffer when next data is
186*4882a593Smuzhiyun  *                      to be written
187*4882a593Smuzhiyun  * @req_bd_tbl:         iscsi login request payload BD table
188*4882a593Smuzhiyun  * @req_bd_dma:         login request BD table dma address
189*4882a593Smuzhiyun  * @resp_bd_tbl:        iscsi login response payload BD table
190*4882a593Smuzhiyun  * @resp_bd_dma:        login request BD table dma address
191*4882a593Smuzhiyun  *
192*4882a593Smuzhiyun  * following structure defines buffer info for generic pdus such as iSCSI Login,
193*4882a593Smuzhiyun  *	Logout and NOP
194*4882a593Smuzhiyun  */
195*4882a593Smuzhiyun struct generic_pdu_resc {
196*4882a593Smuzhiyun 	char *req_buf;
197*4882a593Smuzhiyun 	dma_addr_t req_dma_addr;
198*4882a593Smuzhiyun 	u32 req_buf_size;
199*4882a593Smuzhiyun 	char *req_wr_ptr;
200*4882a593Smuzhiyun 	struct iscsi_hdr resp_hdr;
201*4882a593Smuzhiyun 	char *resp_buf;
202*4882a593Smuzhiyun 	dma_addr_t resp_dma_addr;
203*4882a593Smuzhiyun 	u32 resp_buf_size;
204*4882a593Smuzhiyun 	char *resp_wr_ptr;
205*4882a593Smuzhiyun 	char *req_bd_tbl;
206*4882a593Smuzhiyun 	dma_addr_t req_bd_dma;
207*4882a593Smuzhiyun 	char *resp_bd_tbl;
208*4882a593Smuzhiyun 	dma_addr_t resp_bd_dma;
209*4882a593Smuzhiyun };
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun /**
213*4882a593Smuzhiyun  * struct bd_resc_page - tracks DMA'able memory allocated for BD tables
214*4882a593Smuzhiyun  *
215*4882a593Smuzhiyun  * @link:               list head to link elements
216*4882a593Smuzhiyun  * @max_ptrs:           maximun pointers that can be stored in this page
217*4882a593Smuzhiyun  * @num_valid:          number of pointer valid in this page
218*4882a593Smuzhiyun  * @page:               base addess for page pointer array
219*4882a593Smuzhiyun  *
220*4882a593Smuzhiyun  * structure to track DMA'able memory allocated for command BD tables
221*4882a593Smuzhiyun  */
222*4882a593Smuzhiyun struct bd_resc_page {
223*4882a593Smuzhiyun 	struct list_head link;
224*4882a593Smuzhiyun 	u32 max_ptrs;
225*4882a593Smuzhiyun 	u32 num_valid;
226*4882a593Smuzhiyun 	void *page[1];
227*4882a593Smuzhiyun };
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun /**
231*4882a593Smuzhiyun  * struct io_bdt - I/O buffer destricptor table
232*4882a593Smuzhiyun  *
233*4882a593Smuzhiyun  * @bd_tbl:             BD table's virtual address
234*4882a593Smuzhiyun  * @bd_tbl_dma:         BD table's dma address
235*4882a593Smuzhiyun  * @bd_valid:           num valid BD entries
236*4882a593Smuzhiyun  *
237*4882a593Smuzhiyun  * IO BD table
238*4882a593Smuzhiyun  */
239*4882a593Smuzhiyun struct io_bdt {
240*4882a593Smuzhiyun 	struct iscsi_bd *bd_tbl;
241*4882a593Smuzhiyun 	dma_addr_t bd_tbl_dma;
242*4882a593Smuzhiyun 	u16 bd_valid;
243*4882a593Smuzhiyun };
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun /**
247*4882a593Smuzhiyun  * bnx2i_cmd - iscsi command structure
248*4882a593Smuzhiyun  *
249*4882a593Smuzhiyun  * @hdr:                iSCSI header
250*4882a593Smuzhiyun  * @conn:               iscsi_conn pointer
251*4882a593Smuzhiyun  * @scsi_cmd:           SCSI-ML task pointer corresponding to this iscsi cmd
252*4882a593Smuzhiyun  * @sg:                 SG list
253*4882a593Smuzhiyun  * @io_tbl:             buffer descriptor (BD) table
254*4882a593Smuzhiyun  * @bd_tbl_dma:         buffer descriptor (BD) table's dma address
255*4882a593Smuzhiyun  * @req:                bnx2i specific command request struct
256*4882a593Smuzhiyun  */
257*4882a593Smuzhiyun struct bnx2i_cmd {
258*4882a593Smuzhiyun 	struct iscsi_hdr hdr;
259*4882a593Smuzhiyun 	struct bnx2i_conn *conn;
260*4882a593Smuzhiyun 	struct scsi_cmnd *scsi_cmd;
261*4882a593Smuzhiyun 	struct scatterlist *sg;
262*4882a593Smuzhiyun 	struct io_bdt io_tbl;
263*4882a593Smuzhiyun 	dma_addr_t bd_tbl_dma;
264*4882a593Smuzhiyun 	struct bnx2i_cmd_request req;
265*4882a593Smuzhiyun };
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun /**
269*4882a593Smuzhiyun  * struct bnx2i_conn - iscsi connection structure
270*4882a593Smuzhiyun  *
271*4882a593Smuzhiyun  * @cls_conn:              pointer to iscsi cls conn
272*4882a593Smuzhiyun  * @hba:                   adapter structure pointer
273*4882a593Smuzhiyun  * @iscsi_conn_cid:        iscsi conn id
274*4882a593Smuzhiyun  * @fw_cid:                firmware iscsi context id
275*4882a593Smuzhiyun  * @ep:                    endpoint structure pointer
276*4882a593Smuzhiyun  * @gen_pdu:               login/nopout/logout pdu resources
277*4882a593Smuzhiyun  * @violation_notified:    bit mask used to track iscsi error/warning messages
278*4882a593Smuzhiyun  *                         already printed out
279*4882a593Smuzhiyun  * @work_cnt:              keeps track of the number of outstanding work
280*4882a593Smuzhiyun  *
281*4882a593Smuzhiyun  * iSCSI connection structure
282*4882a593Smuzhiyun  */
283*4882a593Smuzhiyun struct bnx2i_conn {
284*4882a593Smuzhiyun 	struct iscsi_cls_conn *cls_conn;
285*4882a593Smuzhiyun 	struct bnx2i_hba *hba;
286*4882a593Smuzhiyun 	struct completion cmd_cleanup_cmpl;
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun 	u32 iscsi_conn_cid;
289*4882a593Smuzhiyun #define BNX2I_CID_RESERVED	0x5AFF
290*4882a593Smuzhiyun 	u32 fw_cid;
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	struct timer_list poll_timer;
293*4882a593Smuzhiyun 	/*
294*4882a593Smuzhiyun 	 * Queue Pair (QP) related structure elements.
295*4882a593Smuzhiyun 	 */
296*4882a593Smuzhiyun 	struct bnx2i_endpoint *ep;
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	/*
299*4882a593Smuzhiyun 	 * Buffer for login negotiation process
300*4882a593Smuzhiyun 	 */
301*4882a593Smuzhiyun 	struct generic_pdu_resc gen_pdu;
302*4882a593Smuzhiyun 	u64 violation_notified;
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	atomic_t work_cnt;
305*4882a593Smuzhiyun };
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun /**
310*4882a593Smuzhiyun  * struct iscsi_cid_queue - Per adapter iscsi cid queue
311*4882a593Smuzhiyun  *
312*4882a593Smuzhiyun  * @cid_que_base:           queue base memory
313*4882a593Smuzhiyun  * @cid_que:                queue memory pointer
314*4882a593Smuzhiyun  * @cid_q_prod_idx:         produce index
315*4882a593Smuzhiyun  * @cid_q_cons_idx:         consumer index
316*4882a593Smuzhiyun  * @cid_q_max_idx:          max index. used to detect wrap around condition
317*4882a593Smuzhiyun  * @cid_free_cnt:           queue size
318*4882a593Smuzhiyun  * @conn_cid_tbl:           iscsi cid to conn structure mapping table
319*4882a593Smuzhiyun  *
320*4882a593Smuzhiyun  * Per adapter iSCSI CID Queue
321*4882a593Smuzhiyun  */
322*4882a593Smuzhiyun struct iscsi_cid_queue {
323*4882a593Smuzhiyun 	void *cid_que_base;
324*4882a593Smuzhiyun 	u32 *cid_que;
325*4882a593Smuzhiyun 	u32 cid_q_prod_idx;
326*4882a593Smuzhiyun 	u32 cid_q_cons_idx;
327*4882a593Smuzhiyun 	u32 cid_q_max_idx;
328*4882a593Smuzhiyun 	u32 cid_free_cnt;
329*4882a593Smuzhiyun 	struct bnx2i_conn **conn_cid_tbl;
330*4882a593Smuzhiyun };
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun struct bnx2i_stats_info {
334*4882a593Smuzhiyun 	u64 rx_pdus;
335*4882a593Smuzhiyun 	u64 rx_bytes;
336*4882a593Smuzhiyun 	u64 tx_pdus;
337*4882a593Smuzhiyun 	u64 tx_bytes;
338*4882a593Smuzhiyun };
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun /**
342*4882a593Smuzhiyun  * struct bnx2i_hba - bnx2i adapter structure
343*4882a593Smuzhiyun  *
344*4882a593Smuzhiyun  * @link:                  list head to link elements
345*4882a593Smuzhiyun  * @cnic:                  pointer to cnic device
346*4882a593Smuzhiyun  * @pcidev:                pointer to pci dev
347*4882a593Smuzhiyun  * @netdev:                pointer to netdev structure
348*4882a593Smuzhiyun  * @regview:               mapped PCI register space
349*4882a593Smuzhiyun  * @age:                   age, incremented by every recovery
350*4882a593Smuzhiyun  * @cnic_dev_type:         cnic device type, 5706/5708/5709/57710
351*4882a593Smuzhiyun  * @mail_queue_access:     mailbox queue access mode, applicable to 5709 only
352*4882a593Smuzhiyun  * @reg_with_cnic:         indicates whether the device is register with CNIC
353*4882a593Smuzhiyun  * @adapter_state:         adapter state, UP, GOING_DOWN, LINK_DOWN
354*4882a593Smuzhiyun  * @mtu_supported:         Ethernet MTU supported
355*4882a593Smuzhiyun  * @shost:                 scsi host pointer
356*4882a593Smuzhiyun  * @max_sqes:              SQ size
357*4882a593Smuzhiyun  * @max_rqes:              RQ size
358*4882a593Smuzhiyun  * @max_cqes:              CQ size
359*4882a593Smuzhiyun  * @num_ccell:             number of command cells per connection
360*4882a593Smuzhiyun  * @ofld_conns_active:     active connection list
361*4882a593Smuzhiyun  * @eh_wait:               wait queue for the endpoint to shutdown
362*4882a593Smuzhiyun  * @max_active_conns:      max offload connections supported by this device
363*4882a593Smuzhiyun  * @cid_que:               iscsi cid queue
364*4882a593Smuzhiyun  * @ep_rdwr_lock:          read / write lock to synchronize various ep lists
365*4882a593Smuzhiyun  * @ep_ofld_list:          connection list for pending offload completion
366*4882a593Smuzhiyun  * @ep_active_list:        connection list for active offload endpoints
367*4882a593Smuzhiyun  * @ep_destroy_list:       connection list for pending offload completion
368*4882a593Smuzhiyun  * @mp_bd_tbl:             BD table to be used with middle path requests
369*4882a593Smuzhiyun  * @mp_bd_dma:             DMA address of 'mp_bd_tbl' memory buffer
370*4882a593Smuzhiyun  * @dummy_buffer:          Dummy buffer to be used with zero length scsicmd reqs
371*4882a593Smuzhiyun  * @dummy_buf_dma:         DMA address of 'dummy_buffer' memory buffer
372*4882a593Smuzhiyun  * @lock:              	   lock to synchonize access to hba structure
373*4882a593Smuzhiyun  * @hba_shutdown_tmo:      Timeout value to shutdown each connection
374*4882a593Smuzhiyun  * @conn_teardown_tmo:     Timeout value to tear down each connection
375*4882a593Smuzhiyun  * @conn_ctx_destroy_tmo:  Timeout value to destroy context of each connection
376*4882a593Smuzhiyun  * @pci_did:               PCI device ID
377*4882a593Smuzhiyun  * @pci_vid:               PCI vendor ID
378*4882a593Smuzhiyun  * @pci_sdid:              PCI subsystem device ID
379*4882a593Smuzhiyun  * @pci_svid:              PCI subsystem vendor ID
380*4882a593Smuzhiyun  * @pci_func:              PCI function number in system pci tree
381*4882a593Smuzhiyun  * @pci_devno:             PCI device number in system pci tree
382*4882a593Smuzhiyun  * @num_wqe_sent:          statistic counter, total wqe's sent
383*4882a593Smuzhiyun  * @num_cqe_rcvd:          statistic counter, total cqe's received
384*4882a593Smuzhiyun  * @num_intr_claimed:      statistic counter, total interrupts claimed
385*4882a593Smuzhiyun  * @link_changed_count:    statistic counter, num of link change notifications
386*4882a593Smuzhiyun  *                         received
387*4882a593Smuzhiyun  * @ipaddr_changed_count:  statistic counter, num times IP address changed while
388*4882a593Smuzhiyun  *                         at least one connection is offloaded
389*4882a593Smuzhiyun  * @num_sess_opened:       statistic counter, total num sessions opened
390*4882a593Smuzhiyun  * @num_conn_opened:       statistic counter, total num conns opened on this hba
391*4882a593Smuzhiyun  * @ctx_ccell_tasks:       captures number of ccells and tasks supported by
392*4882a593Smuzhiyun  *                         currently offloaded connection, used to decode
393*4882a593Smuzhiyun  *                         context memory
394*4882a593Smuzhiyun  * @stat_lock:		   spin lock used by the statistic collector (32 bit)
395*4882a593Smuzhiyun  * @stats:		   local iSCSI statistic collection place holder
396*4882a593Smuzhiyun  *
397*4882a593Smuzhiyun  * Adapter Data Structure
398*4882a593Smuzhiyun  */
399*4882a593Smuzhiyun struct bnx2i_hba {
400*4882a593Smuzhiyun 	struct list_head link;
401*4882a593Smuzhiyun 	struct cnic_dev *cnic;
402*4882a593Smuzhiyun 	struct pci_dev *pcidev;
403*4882a593Smuzhiyun 	struct net_device *netdev;
404*4882a593Smuzhiyun 	void __iomem *regview;
405*4882a593Smuzhiyun 	resource_size_t reg_base;
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun 	u32 age;
408*4882a593Smuzhiyun 	unsigned long cnic_dev_type;
409*4882a593Smuzhiyun 		#define BNX2I_NX2_DEV_5706		0x0
410*4882a593Smuzhiyun 		#define BNX2I_NX2_DEV_5708		0x1
411*4882a593Smuzhiyun 		#define BNX2I_NX2_DEV_5709		0x2
412*4882a593Smuzhiyun 		#define BNX2I_NX2_DEV_57710		0x3
413*4882a593Smuzhiyun 	u32 mail_queue_access;
414*4882a593Smuzhiyun 		#define BNX2I_MQ_KERNEL_MODE		0x0
415*4882a593Smuzhiyun 		#define BNX2I_MQ_KERNEL_BYPASS_MODE	0x1
416*4882a593Smuzhiyun 		#define BNX2I_MQ_BIN_MODE		0x2
417*4882a593Smuzhiyun 	unsigned long  reg_with_cnic;
418*4882a593Smuzhiyun 		#define BNX2I_CNIC_REGISTERED		1
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun 	unsigned long  adapter_state;
421*4882a593Smuzhiyun 		#define ADAPTER_STATE_UP		0
422*4882a593Smuzhiyun 		#define ADAPTER_STATE_GOING_DOWN	1
423*4882a593Smuzhiyun 		#define ADAPTER_STATE_LINK_DOWN		2
424*4882a593Smuzhiyun 		#define ADAPTER_STATE_INIT_FAILED	31
425*4882a593Smuzhiyun 	unsigned int mtu_supported;
426*4882a593Smuzhiyun 		#define BNX2I_MAX_MTU_SUPPORTED		9000
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 	struct Scsi_Host *shost;
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun 	u32 max_sqes;
431*4882a593Smuzhiyun 	u32 max_rqes;
432*4882a593Smuzhiyun 	u32 max_cqes;
433*4882a593Smuzhiyun 	u32 num_ccell;
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 	int ofld_conns_active;
436*4882a593Smuzhiyun 	wait_queue_head_t eh_wait;
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun 	int max_active_conns;
439*4882a593Smuzhiyun 	struct iscsi_cid_queue cid_que;
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun 	rwlock_t ep_rdwr_lock;
442*4882a593Smuzhiyun 	struct list_head ep_ofld_list;
443*4882a593Smuzhiyun 	struct list_head ep_active_list;
444*4882a593Smuzhiyun 	struct list_head ep_destroy_list;
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun 	/*
447*4882a593Smuzhiyun 	 * BD table to be used with MP (Middle Path requests.
448*4882a593Smuzhiyun 	 */
449*4882a593Smuzhiyun 	char *mp_bd_tbl;
450*4882a593Smuzhiyun 	dma_addr_t mp_bd_dma;
451*4882a593Smuzhiyun 	char *dummy_buffer;
452*4882a593Smuzhiyun 	dma_addr_t dummy_buf_dma;
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun 	spinlock_t lock;	/* protects hba structure access */
455*4882a593Smuzhiyun 	struct mutex net_dev_lock;/* sync net device access */
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun 	int hba_shutdown_tmo;
458*4882a593Smuzhiyun 	int conn_teardown_tmo;
459*4882a593Smuzhiyun 	int conn_ctx_destroy_tmo;
460*4882a593Smuzhiyun 	/*
461*4882a593Smuzhiyun 	 * PCI related info.
462*4882a593Smuzhiyun 	 */
463*4882a593Smuzhiyun 	u16 pci_did;
464*4882a593Smuzhiyun 	u16 pci_vid;
465*4882a593Smuzhiyun 	u16 pci_sdid;
466*4882a593Smuzhiyun 	u16 pci_svid;
467*4882a593Smuzhiyun 	u16 pci_func;
468*4882a593Smuzhiyun 	u16 pci_devno;
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun 	/*
471*4882a593Smuzhiyun 	 * Following are a bunch of statistics useful during development
472*4882a593Smuzhiyun 	 * and later stage for score boarding.
473*4882a593Smuzhiyun 	 */
474*4882a593Smuzhiyun 	u32 num_wqe_sent;
475*4882a593Smuzhiyun 	u32 num_cqe_rcvd;
476*4882a593Smuzhiyun 	u32 num_intr_claimed;
477*4882a593Smuzhiyun 	u32 link_changed_count;
478*4882a593Smuzhiyun 	u32 ipaddr_changed_count;
479*4882a593Smuzhiyun 	u32 num_sess_opened;
480*4882a593Smuzhiyun 	u32 num_conn_opened;
481*4882a593Smuzhiyun 	unsigned int ctx_ccell_tasks;
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun #ifdef CONFIG_32BIT
484*4882a593Smuzhiyun 	spinlock_t stat_lock;
485*4882a593Smuzhiyun #endif
486*4882a593Smuzhiyun 	struct bnx2i_stats_info bnx2i_stats;
487*4882a593Smuzhiyun 	struct iscsi_stats_info stats;
488*4882a593Smuzhiyun };
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun /*******************************************************************************
492*4882a593Smuzhiyun  * 	QP [ SQ / RQ / CQ ] info.
493*4882a593Smuzhiyun  ******************************************************************************/
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun /*
496*4882a593Smuzhiyun  * SQ/RQ/CQ generic structure definition
497*4882a593Smuzhiyun  */
498*4882a593Smuzhiyun struct 	sqe {
499*4882a593Smuzhiyun 	u8 sqe_byte[BNX2I_SQ_WQE_SIZE];
500*4882a593Smuzhiyun };
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun struct 	rqe {
503*4882a593Smuzhiyun 	u8 rqe_byte[BNX2I_RQ_WQE_SIZE];
504*4882a593Smuzhiyun };
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun struct 	cqe {
507*4882a593Smuzhiyun 	u8 cqe_byte[BNX2I_CQE_SIZE];
508*4882a593Smuzhiyun };
509*4882a593Smuzhiyun 
510*4882a593Smuzhiyun 
511*4882a593Smuzhiyun enum {
512*4882a593Smuzhiyun #if defined(__LITTLE_ENDIAN)
513*4882a593Smuzhiyun 	CNIC_EVENT_COAL_INDEX	= 0x0,
514*4882a593Smuzhiyun 	CNIC_SEND_DOORBELL	= 0x4,
515*4882a593Smuzhiyun 	CNIC_EVENT_CQ_ARM	= 0x7,
516*4882a593Smuzhiyun 	CNIC_RECV_DOORBELL	= 0x8
517*4882a593Smuzhiyun #elif defined(__BIG_ENDIAN)
518*4882a593Smuzhiyun 	CNIC_EVENT_COAL_INDEX	= 0x2,
519*4882a593Smuzhiyun 	CNIC_SEND_DOORBELL	= 0x6,
520*4882a593Smuzhiyun 	CNIC_EVENT_CQ_ARM	= 0x4,
521*4882a593Smuzhiyun 	CNIC_RECV_DOORBELL	= 0xa
522*4882a593Smuzhiyun #endif
523*4882a593Smuzhiyun };
524*4882a593Smuzhiyun 
525*4882a593Smuzhiyun 
526*4882a593Smuzhiyun /*
527*4882a593Smuzhiyun  * CQ DB
528*4882a593Smuzhiyun  */
529*4882a593Smuzhiyun struct bnx2x_iscsi_cq_pend_cmpl {
530*4882a593Smuzhiyun 	/* CQ producer, updated by Ustorm */
531*4882a593Smuzhiyun 	u16 ustrom_prod;
532*4882a593Smuzhiyun 	/* CQ pending completion counter */
533*4882a593Smuzhiyun 	u16 pend_cntr;
534*4882a593Smuzhiyun };
535*4882a593Smuzhiyun 
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun struct bnx2i_5771x_cq_db {
538*4882a593Smuzhiyun 	struct bnx2x_iscsi_cq_pend_cmpl qp_pend_cmpl[BNX2X_MAX_CQS];
539*4882a593Smuzhiyun 	/* CQ pending completion ITT array */
540*4882a593Smuzhiyun 	u16 itt[BNX2X_MAX_CQS];
541*4882a593Smuzhiyun 	/* Cstorm CQ sequence to notify array, updated by driver */;
542*4882a593Smuzhiyun 	u16 sqn[BNX2X_MAX_CQS];
543*4882a593Smuzhiyun 	u32 reserved[4] /* 16 byte allignment */;
544*4882a593Smuzhiyun };
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun 
547*4882a593Smuzhiyun struct bnx2i_5771x_sq_rq_db {
548*4882a593Smuzhiyun 	u16 prod_idx;
549*4882a593Smuzhiyun 	u8 reserved0[62]; /* Pad structure size to 64 bytes */
550*4882a593Smuzhiyun };
551*4882a593Smuzhiyun 
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun struct bnx2i_5771x_dbell_hdr {
554*4882a593Smuzhiyun 	u8 header;
555*4882a593Smuzhiyun 	/* 1 for rx doorbell, 0 for tx doorbell */
556*4882a593Smuzhiyun #define B577XX_DOORBELL_HDR_RX				(0x1<<0)
557*4882a593Smuzhiyun #define B577XX_DOORBELL_HDR_RX_SHIFT			0
558*4882a593Smuzhiyun 	/* 0 for normal doorbell, 1 for advertise wnd doorbell */
559*4882a593Smuzhiyun #define B577XX_DOORBELL_HDR_DB_TYPE			(0x1<<1)
560*4882a593Smuzhiyun #define B577XX_DOORBELL_HDR_DB_TYPE_SHIFT		1
561*4882a593Smuzhiyun 	/* rdma tx only: DPM transaction size specifier (64/128/256/512B) */
562*4882a593Smuzhiyun #define B577XX_DOORBELL_HDR_DPM_SIZE			(0x3<<2)
563*4882a593Smuzhiyun #define B577XX_DOORBELL_HDR_DPM_SIZE_SHIFT		2
564*4882a593Smuzhiyun 	/* connection type */
565*4882a593Smuzhiyun #define B577XX_DOORBELL_HDR_CONN_TYPE			(0xF<<4)
566*4882a593Smuzhiyun #define B577XX_DOORBELL_HDR_CONN_TYPE_SHIFT		4
567*4882a593Smuzhiyun };
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun struct bnx2i_5771x_dbell {
570*4882a593Smuzhiyun 	struct bnx2i_5771x_dbell_hdr dbell;
571*4882a593Smuzhiyun 	u8 pad[3];
572*4882a593Smuzhiyun 
573*4882a593Smuzhiyun };
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun /**
576*4882a593Smuzhiyun  * struct qp_info - QP (share queue region) atrributes structure
577*4882a593Smuzhiyun  *
578*4882a593Smuzhiyun  * @ctx_base:           ioremapped pci register base to access doorbell register
579*4882a593Smuzhiyun  *                      pertaining to this offloaded connection
580*4882a593Smuzhiyun  * @sq_virt:            virtual address of send queue (SQ) region
581*4882a593Smuzhiyun  * @sq_phys:            DMA address of SQ memory region
582*4882a593Smuzhiyun  * @sq_mem_size:        SQ size
583*4882a593Smuzhiyun  * @sq_prod_qe:         SQ producer entry pointer
584*4882a593Smuzhiyun  * @sq_cons_qe:         SQ consumer entry pointer
585*4882a593Smuzhiyun  * @sq_first_qe:        virtual address of first entry in SQ
586*4882a593Smuzhiyun  * @sq_last_qe:         virtual address of last entry in SQ
587*4882a593Smuzhiyun  * @sq_prod_idx:        SQ producer index
588*4882a593Smuzhiyun  * @sq_cons_idx:        SQ consumer index
589*4882a593Smuzhiyun  * @sqe_left:           number sq entry left
590*4882a593Smuzhiyun  * @sq_pgtbl_virt:      page table describing buffer consituting SQ region
591*4882a593Smuzhiyun  * @sq_pgtbl_phys:      dma address of 'sq_pgtbl_virt'
592*4882a593Smuzhiyun  * @sq_pgtbl_size:      SQ page table size
593*4882a593Smuzhiyun  * @cq_virt:            virtual address of completion queue (CQ) region
594*4882a593Smuzhiyun  * @cq_phys:            DMA address of RQ memory region
595*4882a593Smuzhiyun  * @cq_mem_size:        CQ size
596*4882a593Smuzhiyun  * @cq_prod_qe:         CQ producer entry pointer
597*4882a593Smuzhiyun  * @cq_cons_qe:         CQ consumer entry pointer
598*4882a593Smuzhiyun  * @cq_first_qe:        virtual address of first entry in CQ
599*4882a593Smuzhiyun  * @cq_last_qe:         virtual address of last entry in CQ
600*4882a593Smuzhiyun  * @cq_prod_idx:        CQ producer index
601*4882a593Smuzhiyun  * @cq_cons_idx:        CQ consumer index
602*4882a593Smuzhiyun  * @cqe_left:           number cq entry left
603*4882a593Smuzhiyun  * @cqe_size:           size of each CQ entry
604*4882a593Smuzhiyun  * @cqe_exp_seq_sn:     next expected CQE sequence number
605*4882a593Smuzhiyun  * @cq_pgtbl_virt:      page table describing buffer consituting CQ region
606*4882a593Smuzhiyun  * @cq_pgtbl_phys:      dma address of 'cq_pgtbl_virt'
607*4882a593Smuzhiyun  * @cq_pgtbl_size:    	CQ page table size
608*4882a593Smuzhiyun  * @rq_virt:            virtual address of receive queue (RQ) region
609*4882a593Smuzhiyun  * @rq_phys:            DMA address of RQ memory region
610*4882a593Smuzhiyun  * @rq_mem_size:        RQ size
611*4882a593Smuzhiyun  * @rq_prod_qe:         RQ producer entry pointer
612*4882a593Smuzhiyun  * @rq_cons_qe:         RQ consumer entry pointer
613*4882a593Smuzhiyun  * @rq_first_qe:        virtual address of first entry in RQ
614*4882a593Smuzhiyun  * @rq_last_qe:         virtual address of last entry in RQ
615*4882a593Smuzhiyun  * @rq_prod_idx:        RQ producer index
616*4882a593Smuzhiyun  * @rq_cons_idx:        RQ consumer index
617*4882a593Smuzhiyun  * @rqe_left:           number rq entry left
618*4882a593Smuzhiyun  * @rq_pgtbl_virt:      page table describing buffer consituting RQ region
619*4882a593Smuzhiyun  * @rq_pgtbl_phys:      dma address of 'rq_pgtbl_virt'
620*4882a593Smuzhiyun  * @rq_pgtbl_size:      RQ page table size
621*4882a593Smuzhiyun  *
622*4882a593Smuzhiyun  * queue pair (QP) is a per connection shared data structure which is used
623*4882a593Smuzhiyun  *	to send work requests (SQ), receive completion notifications (CQ)
624*4882a593Smuzhiyun  *	and receive asynchoronous / scsi sense info (RQ). 'qp_info' structure
625*4882a593Smuzhiyun  *	below holds queue memory, consumer/producer indexes and page table
626*4882a593Smuzhiyun  *	information
627*4882a593Smuzhiyun  */
628*4882a593Smuzhiyun struct qp_info {
629*4882a593Smuzhiyun 	void __iomem *ctx_base;
630*4882a593Smuzhiyun #define DPM_TRIGER_TYPE			0x40
631*4882a593Smuzhiyun 
632*4882a593Smuzhiyun #define BNX2I_570x_QUE_DB_SIZE		0
633*4882a593Smuzhiyun #define BNX2I_5771x_QUE_DB_SIZE		16
634*4882a593Smuzhiyun 	struct sqe *sq_virt;
635*4882a593Smuzhiyun 	dma_addr_t sq_phys;
636*4882a593Smuzhiyun 	u32 sq_mem_size;
637*4882a593Smuzhiyun 
638*4882a593Smuzhiyun 	struct sqe *sq_prod_qe;
639*4882a593Smuzhiyun 	struct sqe *sq_cons_qe;
640*4882a593Smuzhiyun 	struct sqe *sq_first_qe;
641*4882a593Smuzhiyun 	struct sqe *sq_last_qe;
642*4882a593Smuzhiyun 	u16 sq_prod_idx;
643*4882a593Smuzhiyun 	u16 sq_cons_idx;
644*4882a593Smuzhiyun 	u32 sqe_left;
645*4882a593Smuzhiyun 
646*4882a593Smuzhiyun 	void *sq_pgtbl_virt;
647*4882a593Smuzhiyun 	dma_addr_t sq_pgtbl_phys;
648*4882a593Smuzhiyun 	u32 sq_pgtbl_size;	/* set to PAGE_SIZE for 5708 & 5709 */
649*4882a593Smuzhiyun 
650*4882a593Smuzhiyun 	struct cqe *cq_virt;
651*4882a593Smuzhiyun 	dma_addr_t cq_phys;
652*4882a593Smuzhiyun 	u32 cq_mem_size;
653*4882a593Smuzhiyun 
654*4882a593Smuzhiyun 	struct cqe *cq_prod_qe;
655*4882a593Smuzhiyun 	struct cqe *cq_cons_qe;
656*4882a593Smuzhiyun 	struct cqe *cq_first_qe;
657*4882a593Smuzhiyun 	struct cqe *cq_last_qe;
658*4882a593Smuzhiyun 	u16 cq_prod_idx;
659*4882a593Smuzhiyun 	u16 cq_cons_idx;
660*4882a593Smuzhiyun 	u32 cqe_left;
661*4882a593Smuzhiyun 	u32 cqe_size;
662*4882a593Smuzhiyun 	u32 cqe_exp_seq_sn;
663*4882a593Smuzhiyun 
664*4882a593Smuzhiyun 	void *cq_pgtbl_virt;
665*4882a593Smuzhiyun 	dma_addr_t cq_pgtbl_phys;
666*4882a593Smuzhiyun 	u32 cq_pgtbl_size;	/* set to PAGE_SIZE for 5708 & 5709 */
667*4882a593Smuzhiyun 
668*4882a593Smuzhiyun 	struct rqe *rq_virt;
669*4882a593Smuzhiyun 	dma_addr_t rq_phys;
670*4882a593Smuzhiyun 	u32 rq_mem_size;
671*4882a593Smuzhiyun 
672*4882a593Smuzhiyun 	struct rqe *rq_prod_qe;
673*4882a593Smuzhiyun 	struct rqe *rq_cons_qe;
674*4882a593Smuzhiyun 	struct rqe *rq_first_qe;
675*4882a593Smuzhiyun 	struct rqe *rq_last_qe;
676*4882a593Smuzhiyun 	u16 rq_prod_idx;
677*4882a593Smuzhiyun 	u16 rq_cons_idx;
678*4882a593Smuzhiyun 	u32 rqe_left;
679*4882a593Smuzhiyun 
680*4882a593Smuzhiyun 	void *rq_pgtbl_virt;
681*4882a593Smuzhiyun 	dma_addr_t rq_pgtbl_phys;
682*4882a593Smuzhiyun 	u32 rq_pgtbl_size;	/* set to PAGE_SIZE for 5708 & 5709 */
683*4882a593Smuzhiyun };
684*4882a593Smuzhiyun 
685*4882a593Smuzhiyun 
686*4882a593Smuzhiyun 
687*4882a593Smuzhiyun /*
688*4882a593Smuzhiyun  * CID handles
689*4882a593Smuzhiyun  */
690*4882a593Smuzhiyun struct ep_handles {
691*4882a593Smuzhiyun 	u32 fw_cid;
692*4882a593Smuzhiyun 	u32 drv_iscsi_cid;
693*4882a593Smuzhiyun 	u16 pg_cid;
694*4882a593Smuzhiyun 	u16 rsvd;
695*4882a593Smuzhiyun };
696*4882a593Smuzhiyun 
697*4882a593Smuzhiyun 
698*4882a593Smuzhiyun enum {
699*4882a593Smuzhiyun 	EP_STATE_IDLE                   = 0x0,
700*4882a593Smuzhiyun 	EP_STATE_PG_OFLD_START          = 0x1,
701*4882a593Smuzhiyun 	EP_STATE_PG_OFLD_COMPL          = 0x2,
702*4882a593Smuzhiyun 	EP_STATE_OFLD_START             = 0x4,
703*4882a593Smuzhiyun 	EP_STATE_OFLD_COMPL             = 0x8,
704*4882a593Smuzhiyun 	EP_STATE_CONNECT_START          = 0x10,
705*4882a593Smuzhiyun 	EP_STATE_CONNECT_COMPL          = 0x20,
706*4882a593Smuzhiyun 	EP_STATE_ULP_UPDATE_START       = 0x40,
707*4882a593Smuzhiyun 	EP_STATE_ULP_UPDATE_COMPL       = 0x80,
708*4882a593Smuzhiyun 	EP_STATE_DISCONN_START          = 0x100,
709*4882a593Smuzhiyun 	EP_STATE_DISCONN_COMPL          = 0x200,
710*4882a593Smuzhiyun 	EP_STATE_CLEANUP_START          = 0x400,
711*4882a593Smuzhiyun 	EP_STATE_CLEANUP_CMPL           = 0x800,
712*4882a593Smuzhiyun 	EP_STATE_TCP_FIN_RCVD           = 0x1000,
713*4882a593Smuzhiyun 	EP_STATE_TCP_RST_RCVD           = 0x2000,
714*4882a593Smuzhiyun 	EP_STATE_LOGOUT_SENT            = 0x4000,
715*4882a593Smuzhiyun 	EP_STATE_LOGOUT_RESP_RCVD       = 0x8000,
716*4882a593Smuzhiyun 	EP_STATE_PG_OFLD_FAILED         = 0x1000000,
717*4882a593Smuzhiyun 	EP_STATE_ULP_UPDATE_FAILED      = 0x2000000,
718*4882a593Smuzhiyun 	EP_STATE_CLEANUP_FAILED         = 0x4000000,
719*4882a593Smuzhiyun 	EP_STATE_OFLD_FAILED            = 0x8000000,
720*4882a593Smuzhiyun 	EP_STATE_CONNECT_FAILED         = 0x10000000,
721*4882a593Smuzhiyun 	EP_STATE_DISCONN_TIMEDOUT       = 0x20000000,
722*4882a593Smuzhiyun 	EP_STATE_OFLD_FAILED_CID_BUSY   = 0x80000000,
723*4882a593Smuzhiyun };
724*4882a593Smuzhiyun 
725*4882a593Smuzhiyun /**
726*4882a593Smuzhiyun  * struct bnx2i_endpoint - representation of tcp connection in NX2 world
727*4882a593Smuzhiyun  *
728*4882a593Smuzhiyun  * @link:               list head to link elements
729*4882a593Smuzhiyun  * @hba:                adapter to which this connection belongs
730*4882a593Smuzhiyun  * @conn:               iscsi connection this EP is linked to
731*4882a593Smuzhiyun  * @cls_ep:             associated iSCSI endpoint pointer
732*4882a593Smuzhiyun  * @cm_sk:              cnic sock struct
733*4882a593Smuzhiyun  * @hba_age:            age to detect if 'iscsid' issues ep_disconnect()
734*4882a593Smuzhiyun  *                      after HBA reset is completed by bnx2i/cnic/bnx2
735*4882a593Smuzhiyun  *                      modules
736*4882a593Smuzhiyun  * @state:              tracks offload connection state machine
737*4882a593Smuzhiyun  * @timestamp:          tracks the start time when the ep begins to connect
738*4882a593Smuzhiyun  * @num_active_cmds:    tracks the number of outstanding commands for this ep
739*4882a593Smuzhiyun  * @ec_shift:           the amount of shift as part of the event coal calc
740*4882a593Smuzhiyun  * @qp:                 QP information
741*4882a593Smuzhiyun  * @ids:                contains chip allocated *context id* & driver assigned
742*4882a593Smuzhiyun  *                      *iscsi cid*
743*4882a593Smuzhiyun  * @ofld_timer:         offload timer to detect timeout
744*4882a593Smuzhiyun  * @ofld_wait:          wait queue
745*4882a593Smuzhiyun  *
746*4882a593Smuzhiyun  * Endpoint Structure - equivalent of tcp socket structure
747*4882a593Smuzhiyun  */
748*4882a593Smuzhiyun struct bnx2i_endpoint {
749*4882a593Smuzhiyun 	struct list_head link;
750*4882a593Smuzhiyun 	struct bnx2i_hba *hba;
751*4882a593Smuzhiyun 	struct bnx2i_conn *conn;
752*4882a593Smuzhiyun 	struct iscsi_endpoint *cls_ep;
753*4882a593Smuzhiyun 	struct cnic_sock *cm_sk;
754*4882a593Smuzhiyun 	u32 hba_age;
755*4882a593Smuzhiyun 	u32 state;
756*4882a593Smuzhiyun 	unsigned long timestamp;
757*4882a593Smuzhiyun 	atomic_t num_active_cmds;
758*4882a593Smuzhiyun 	u32 ec_shift;
759*4882a593Smuzhiyun 
760*4882a593Smuzhiyun 	struct qp_info qp;
761*4882a593Smuzhiyun 	struct ep_handles ids;
762*4882a593Smuzhiyun 		#define ep_iscsi_cid	ids.drv_iscsi_cid
763*4882a593Smuzhiyun 		#define ep_cid		ids.fw_cid
764*4882a593Smuzhiyun 		#define ep_pg_cid	ids.pg_cid
765*4882a593Smuzhiyun 	struct timer_list ofld_timer;
766*4882a593Smuzhiyun 	wait_queue_head_t ofld_wait;
767*4882a593Smuzhiyun };
768*4882a593Smuzhiyun 
769*4882a593Smuzhiyun 
770*4882a593Smuzhiyun struct bnx2i_work {
771*4882a593Smuzhiyun 	struct list_head list;
772*4882a593Smuzhiyun 	struct iscsi_session *session;
773*4882a593Smuzhiyun 	struct bnx2i_conn *bnx2i_conn;
774*4882a593Smuzhiyun 	struct cqe cqe;
775*4882a593Smuzhiyun };
776*4882a593Smuzhiyun 
777*4882a593Smuzhiyun struct bnx2i_percpu_s {
778*4882a593Smuzhiyun 	struct task_struct *iothread;
779*4882a593Smuzhiyun 	struct list_head work_list;
780*4882a593Smuzhiyun 	spinlock_t p_work_lock;
781*4882a593Smuzhiyun };
782*4882a593Smuzhiyun 
783*4882a593Smuzhiyun 
784*4882a593Smuzhiyun /* Global variables */
785*4882a593Smuzhiyun extern unsigned int error_mask1, error_mask2;
786*4882a593Smuzhiyun extern u64 iscsi_error_mask;
787*4882a593Smuzhiyun extern unsigned int en_tcp_dack;
788*4882a593Smuzhiyun extern unsigned int event_coal_div;
789*4882a593Smuzhiyun extern unsigned int event_coal_min;
790*4882a593Smuzhiyun 
791*4882a593Smuzhiyun extern struct scsi_transport_template *bnx2i_scsi_xport_template;
792*4882a593Smuzhiyun extern struct iscsi_transport bnx2i_iscsi_transport;
793*4882a593Smuzhiyun extern struct cnic_ulp_ops bnx2i_cnic_cb;
794*4882a593Smuzhiyun 
795*4882a593Smuzhiyun extern unsigned int sq_size;
796*4882a593Smuzhiyun extern unsigned int rq_size;
797*4882a593Smuzhiyun 
798*4882a593Smuzhiyun extern struct device_attribute *bnx2i_dev_attributes[];
799*4882a593Smuzhiyun 
800*4882a593Smuzhiyun 
801*4882a593Smuzhiyun 
802*4882a593Smuzhiyun /*
803*4882a593Smuzhiyun  * Function Prototypes
804*4882a593Smuzhiyun  */
805*4882a593Smuzhiyun extern void bnx2i_identify_device(struct bnx2i_hba *hba, struct cnic_dev *dev);
806*4882a593Smuzhiyun 
807*4882a593Smuzhiyun extern void bnx2i_ulp_init(struct cnic_dev *dev);
808*4882a593Smuzhiyun extern void bnx2i_ulp_exit(struct cnic_dev *dev);
809*4882a593Smuzhiyun extern void bnx2i_start(void *handle);
810*4882a593Smuzhiyun extern void bnx2i_stop(void *handle);
811*4882a593Smuzhiyun extern int bnx2i_get_stats(void *handle);
812*4882a593Smuzhiyun 
813*4882a593Smuzhiyun extern struct bnx2i_hba *get_adapter_list_head(void);
814*4882a593Smuzhiyun 
815*4882a593Smuzhiyun struct bnx2i_conn *bnx2i_get_conn_from_id(struct bnx2i_hba *hba,
816*4882a593Smuzhiyun 					  u16 iscsi_cid);
817*4882a593Smuzhiyun 
818*4882a593Smuzhiyun int bnx2i_alloc_ep_pool(void);
819*4882a593Smuzhiyun void bnx2i_release_ep_pool(void);
820*4882a593Smuzhiyun struct bnx2i_endpoint *bnx2i_ep_ofld_list_next(struct bnx2i_hba *hba);
821*4882a593Smuzhiyun struct bnx2i_endpoint *bnx2i_ep_destroy_list_next(struct bnx2i_hba *hba);
822*4882a593Smuzhiyun 
823*4882a593Smuzhiyun struct bnx2i_hba *bnx2i_find_hba_for_cnic(struct cnic_dev *cnic);
824*4882a593Smuzhiyun 
825*4882a593Smuzhiyun struct bnx2i_hba *bnx2i_alloc_hba(struct cnic_dev *cnic);
826*4882a593Smuzhiyun void bnx2i_free_hba(struct bnx2i_hba *hba);
827*4882a593Smuzhiyun 
828*4882a593Smuzhiyun void bnx2i_get_rq_buf(struct bnx2i_conn *conn, char *ptr, int len);
829*4882a593Smuzhiyun void bnx2i_put_rq_buf(struct bnx2i_conn *conn, int count);
830*4882a593Smuzhiyun 
831*4882a593Smuzhiyun void bnx2i_iscsi_unmap_sg_list(struct bnx2i_cmd *cmd);
832*4882a593Smuzhiyun 
833*4882a593Smuzhiyun void bnx2i_drop_session(struct iscsi_cls_session *session);
834*4882a593Smuzhiyun 
835*4882a593Smuzhiyun extern int bnx2i_send_fw_iscsi_init_msg(struct bnx2i_hba *hba);
836*4882a593Smuzhiyun extern int bnx2i_send_iscsi_login(struct bnx2i_conn *conn,
837*4882a593Smuzhiyun 				  struct iscsi_task *mtask);
838*4882a593Smuzhiyun extern int bnx2i_send_iscsi_tmf(struct bnx2i_conn *conn,
839*4882a593Smuzhiyun 				  struct iscsi_task *mtask);
840*4882a593Smuzhiyun extern int bnx2i_send_iscsi_text(struct bnx2i_conn *conn,
841*4882a593Smuzhiyun 				 struct iscsi_task *mtask);
842*4882a593Smuzhiyun extern int bnx2i_send_iscsi_scsicmd(struct bnx2i_conn *conn,
843*4882a593Smuzhiyun 				    struct bnx2i_cmd *cmnd);
844*4882a593Smuzhiyun extern int bnx2i_send_iscsi_nopout(struct bnx2i_conn *conn,
845*4882a593Smuzhiyun 				   struct iscsi_task *mtask,
846*4882a593Smuzhiyun 				   char *datap, int data_len, int unsol);
847*4882a593Smuzhiyun extern int bnx2i_send_iscsi_logout(struct bnx2i_conn *conn,
848*4882a593Smuzhiyun 				   struct iscsi_task *mtask);
849*4882a593Smuzhiyun extern void bnx2i_send_cmd_cleanup_req(struct bnx2i_hba *hba,
850*4882a593Smuzhiyun 				       struct bnx2i_cmd *cmd);
851*4882a593Smuzhiyun extern int bnx2i_send_conn_ofld_req(struct bnx2i_hba *hba,
852*4882a593Smuzhiyun 				    struct bnx2i_endpoint *ep);
853*4882a593Smuzhiyun extern void bnx2i_update_iscsi_conn(struct iscsi_conn *conn);
854*4882a593Smuzhiyun extern int bnx2i_send_conn_destroy(struct bnx2i_hba *hba,
855*4882a593Smuzhiyun 				   struct bnx2i_endpoint *ep);
856*4882a593Smuzhiyun 
857*4882a593Smuzhiyun extern int bnx2i_alloc_qp_resc(struct bnx2i_hba *hba,
858*4882a593Smuzhiyun 			       struct bnx2i_endpoint *ep);
859*4882a593Smuzhiyun extern void bnx2i_free_qp_resc(struct bnx2i_hba *hba,
860*4882a593Smuzhiyun 			       struct bnx2i_endpoint *ep);
861*4882a593Smuzhiyun extern void bnx2i_ep_ofld_timer(struct timer_list *t);
862*4882a593Smuzhiyun extern struct bnx2i_endpoint *bnx2i_find_ep_in_ofld_list(
863*4882a593Smuzhiyun 		struct bnx2i_hba *hba, u32 iscsi_cid);
864*4882a593Smuzhiyun extern struct bnx2i_endpoint *bnx2i_find_ep_in_destroy_list(
865*4882a593Smuzhiyun 		struct bnx2i_hba *hba, u32 iscsi_cid);
866*4882a593Smuzhiyun 
867*4882a593Smuzhiyun extern int bnx2i_map_ep_dbell_regs(struct bnx2i_endpoint *ep);
868*4882a593Smuzhiyun extern int bnx2i_arm_cq_event_coalescing(struct bnx2i_endpoint *ep, u8 action);
869*4882a593Smuzhiyun 
870*4882a593Smuzhiyun extern int bnx2i_hw_ep_disconnect(struct bnx2i_endpoint *bnx2i_ep);
871*4882a593Smuzhiyun 
872*4882a593Smuzhiyun /* Debug related function prototypes */
873*4882a593Smuzhiyun extern void bnx2i_print_pend_cmd_queue(struct bnx2i_conn *conn);
874*4882a593Smuzhiyun extern void bnx2i_print_active_cmd_queue(struct bnx2i_conn *conn);
875*4882a593Smuzhiyun extern void bnx2i_print_xmit_pdu_queue(struct bnx2i_conn *conn);
876*4882a593Smuzhiyun extern void bnx2i_print_recv_state(struct bnx2i_conn *conn);
877*4882a593Smuzhiyun 
878*4882a593Smuzhiyun extern int bnx2i_percpu_io_thread(void *arg);
879*4882a593Smuzhiyun extern int bnx2i_process_scsi_cmd_resp(struct iscsi_session *session,
880*4882a593Smuzhiyun 				       struct bnx2i_conn *bnx2i_conn,
881*4882a593Smuzhiyun 				       struct cqe *cqe);
882*4882a593Smuzhiyun #endif
883