1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Aic94xx SAS/SATA driver hardware interface header file. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2005 Adaptec, Inc. All rights reserved. 6*4882a593Smuzhiyun * Copyright (C) 2005 Gilbert Wu <gilbert_wu@adaptec.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef _AIC94XX_SDS_H_ 9*4882a593Smuzhiyun #define _AIC94XX_SDS_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun enum { 12*4882a593Smuzhiyun FLASH_METHOD_UNKNOWN, 13*4882a593Smuzhiyun FLASH_METHOD_A, 14*4882a593Smuzhiyun FLASH_METHOD_B 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define FLASH_MANUF_ID_AMD 0x01 18*4882a593Smuzhiyun #define FLASH_MANUF_ID_ST 0x20 19*4882a593Smuzhiyun #define FLASH_MANUF_ID_FUJITSU 0x04 20*4882a593Smuzhiyun #define FLASH_MANUF_ID_MACRONIX 0xC2 21*4882a593Smuzhiyun #define FLASH_MANUF_ID_INTEL 0x89 22*4882a593Smuzhiyun #define FLASH_MANUF_ID_UNKNOWN 0xFF 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define FLASH_DEV_ID_AM29LV008BT 0x3E 25*4882a593Smuzhiyun #define FLASH_DEV_ID_AM29LV800DT 0xDA 26*4882a593Smuzhiyun #define FLASH_DEV_ID_STM29W800DT 0xD7 27*4882a593Smuzhiyun #define FLASH_DEV_ID_STM29LV640 0xDE 28*4882a593Smuzhiyun #define FLASH_DEV_ID_STM29008 0xEA 29*4882a593Smuzhiyun #define FLASH_DEV_ID_MBM29LV800TE 0xDA 30*4882a593Smuzhiyun #define FLASH_DEV_ID_MBM29DL800TA 0x4A 31*4882a593Smuzhiyun #define FLASH_DEV_ID_MBM29LV008TA 0x3E 32*4882a593Smuzhiyun #define FLASH_DEV_ID_AM29LV640MT 0x7E 33*4882a593Smuzhiyun #define FLASH_DEV_ID_AM29F800B 0xD6 34*4882a593Smuzhiyun #define FLASH_DEV_ID_MX29LV800BT 0xDA 35*4882a593Smuzhiyun #define FLASH_DEV_ID_MX29LV008CT 0xDA 36*4882a593Smuzhiyun #define FLASH_DEV_ID_I28LV00TAT 0x3E 37*4882a593Smuzhiyun #define FLASH_DEV_ID_UNKNOWN 0xFF 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* status bit mask values */ 40*4882a593Smuzhiyun #define FLASH_STATUS_BIT_MASK_DQ6 0x40 41*4882a593Smuzhiyun #define FLASH_STATUS_BIT_MASK_DQ5 0x20 42*4882a593Smuzhiyun #define FLASH_STATUS_BIT_MASK_DQ2 0x04 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* minimum value in micro seconds needed for checking status */ 45*4882a593Smuzhiyun #define FLASH_STATUS_ERASE_DELAY_COUNT 50 46*4882a593Smuzhiyun #define FLASH_STATUS_WRITE_DELAY_COUNT 25 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define FLASH_SECTOR_SIZE 0x010000 49*4882a593Smuzhiyun #define FLASH_SECTOR_SIZE_MASK 0xffff0000 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define FLASH_OK 0x000000 52*4882a593Smuzhiyun #define FAIL_OPEN_BIOS_FILE 0x000100 53*4882a593Smuzhiyun #define FAIL_CHECK_PCI_ID 0x000200 54*4882a593Smuzhiyun #define FAIL_CHECK_SUM 0x000300 55*4882a593Smuzhiyun #define FAIL_UNKNOWN 0x000400 56*4882a593Smuzhiyun #define FAIL_VERIFY 0x000500 57*4882a593Smuzhiyun #define FAIL_RESET_FLASH 0x000600 58*4882a593Smuzhiyun #define FAIL_FIND_FLASH_ID 0x000700 59*4882a593Smuzhiyun #define FAIL_ERASE_FLASH 0x000800 60*4882a593Smuzhiyun #define FAIL_WRITE_FLASH 0x000900 61*4882a593Smuzhiyun #define FAIL_FILE_SIZE 0x000a00 62*4882a593Smuzhiyun #define FAIL_PARAMETERS 0x000b00 63*4882a593Smuzhiyun #define FAIL_OUT_MEMORY 0x000c00 64*4882a593Smuzhiyun #define FLASH_IN_PROGRESS 0x001000 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun struct controller_id { 67*4882a593Smuzhiyun u32 vendor; /* PCI Vendor ID */ 68*4882a593Smuzhiyun u32 device; /* PCI Device ID */ 69*4882a593Smuzhiyun u32 sub_vendor; /* PCI Subvendor ID */ 70*4882a593Smuzhiyun u32 sub_device; /* PCI Subdevice ID */ 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun struct image_info { 74*4882a593Smuzhiyun u32 ImageId; /* Identifies the image */ 75*4882a593Smuzhiyun u32 ImageOffset; /* Offset the beginning of the file */ 76*4882a593Smuzhiyun u32 ImageLength; /* length of the image */ 77*4882a593Smuzhiyun u32 ImageChecksum; /* Image checksum */ 78*4882a593Smuzhiyun u32 ImageVersion; /* Version of the image, could be build number */ 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun struct bios_file_header { 82*4882a593Smuzhiyun u8 signature[32]; /* Signature/Cookie to identify the file */ 83*4882a593Smuzhiyun u32 checksum; /*Entire file checksum with this field zero */ 84*4882a593Smuzhiyun u32 antidote; /* Entire file checksum with this field 0xFFFFFFFF */ 85*4882a593Smuzhiyun struct controller_id contrl_id; /*PCI id to identify the controller */ 86*4882a593Smuzhiyun u32 filelen; /*Length of the entire file*/ 87*4882a593Smuzhiyun u32 chunk_num; /*The chunk/part number for multiple Image files */ 88*4882a593Smuzhiyun u32 total_chunks; /*Total number of chunks/parts in the image file */ 89*4882a593Smuzhiyun u32 num_images; /* Number of images in the file */ 90*4882a593Smuzhiyun u32 build_num; /* Build number of this image */ 91*4882a593Smuzhiyun struct image_info image_header; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun int asd_verify_flash_seg(struct asd_ha_struct *asd_ha, 95*4882a593Smuzhiyun const void *src, u32 dest_offset, u32 bytes_to_verify); 96*4882a593Smuzhiyun int asd_write_flash_seg(struct asd_ha_struct *asd_ha, 97*4882a593Smuzhiyun const void *src, u32 dest_offset, u32 bytes_to_write); 98*4882a593Smuzhiyun int asd_chk_write_status(struct asd_ha_struct *asd_ha, 99*4882a593Smuzhiyun u32 sector_addr, u8 erase_flag); 100*4882a593Smuzhiyun int asd_check_flash_type(struct asd_ha_struct *asd_ha); 101*4882a593Smuzhiyun int asd_erase_nv_sector(struct asd_ha_struct *asd_ha, 102*4882a593Smuzhiyun u32 flash_addr, u32 size); 103*4882a593Smuzhiyun #endif 104