1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Aic94xx SAS/SATA driver hardware registers definitions.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2005 Adaptec, Inc. All rights reserved.
6*4882a593Smuzhiyun * Copyright (C) 2005 Luben Tuikov <luben_tuikov@adaptec.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef _AIC94XX_REG_H_
10*4882a593Smuzhiyun #define _AIC94XX_REG_H_
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include "aic94xx_hwi.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /* Values */
16*4882a593Smuzhiyun #define AIC9410_DEV_REV_B0 0x8
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* MBAR0, SWA, SWB, SWC, internal memory space addresses */
19*4882a593Smuzhiyun #define REG_BASE_ADDR 0xB8000000
20*4882a593Smuzhiyun #define REG_BASE_ADDR_CSEQCIO 0xB8002000
21*4882a593Smuzhiyun #define REG_BASE_ADDR_EXSI 0xB8042800
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define MBAR0_SWA_SIZE 0x58
24*4882a593Smuzhiyun extern u32 MBAR0_SWB_SIZE;
25*4882a593Smuzhiyun #define MBAR0_SWC_SIZE 0x8
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* MBAR1, points to On Chip Memory */
28*4882a593Smuzhiyun #define OCM_BASE_ADDR 0xA0000000
29*4882a593Smuzhiyun #define OCM_MAX_SIZE 0x20000
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* Smallest address possible to reference */
32*4882a593Smuzhiyun #define ALL_BASE_ADDR OCM_BASE_ADDR
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* PCI configuration space registers */
35*4882a593Smuzhiyun #define PCI_IOBAR_OFFSET 4
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define PCI_CONF_MBAR1 0x6C
38*4882a593Smuzhiyun #define PCI_CONF_MBAR0_SWA 0x70
39*4882a593Smuzhiyun #define PCI_CONF_MBAR0_SWB 0x74
40*4882a593Smuzhiyun #define PCI_CONF_MBAR0_SWC 0x78
41*4882a593Smuzhiyun #define PCI_CONF_MBAR_KEY 0x7C
42*4882a593Smuzhiyun #define PCI_CONF_FLSH_BAR 0xB8
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #include "aic94xx_reg_def.h"
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun u8 asd_read_reg_byte(struct asd_ha_struct *asd_ha, u32 reg);
47*4882a593Smuzhiyun u16 asd_read_reg_word(struct asd_ha_struct *asd_ha, u32 reg);
48*4882a593Smuzhiyun u32 asd_read_reg_dword(struct asd_ha_struct *asd_ha, u32 reg);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun void asd_write_reg_byte(struct asd_ha_struct *asd_ha, u32 reg, u8 val);
51*4882a593Smuzhiyun void asd_write_reg_word(struct asd_ha_struct *asd_ha, u32 reg, u16 val);
52*4882a593Smuzhiyun void asd_write_reg_dword(struct asd_ha_struct *asd_ha, u32 reg, u32 val);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun void asd_read_reg_string(struct asd_ha_struct *asd_ha, void *dst,
55*4882a593Smuzhiyun u32 offs, int count);
56*4882a593Smuzhiyun void asd_write_reg_string(struct asd_ha_struct *asd_ha, void *src,
57*4882a593Smuzhiyun u32 offs, int count);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun #define ASD_READ_OCM(type, ord, S) \
60*4882a593Smuzhiyun static inline type asd_read_ocm_##ord (struct asd_ha_struct *asd_ha, \
61*4882a593Smuzhiyun u32 offs) \
62*4882a593Smuzhiyun { \
63*4882a593Smuzhiyun struct asd_ha_addrspace *io_handle = &asd_ha->io_handle[1]; \
64*4882a593Smuzhiyun type val = read##S (io_handle->addr + (unsigned long) offs); \
65*4882a593Smuzhiyun rmb(); \
66*4882a593Smuzhiyun return val; \
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun ASD_READ_OCM(u8, byte, b);
70*4882a593Smuzhiyun ASD_READ_OCM(u16,word, w);
71*4882a593Smuzhiyun ASD_READ_OCM(u32,dword,l);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun #define ASD_WRITE_OCM(type, ord, S) \
74*4882a593Smuzhiyun static inline void asd_write_ocm_##ord (struct asd_ha_struct *asd_ha, \
75*4882a593Smuzhiyun u32 offs, type val) \
76*4882a593Smuzhiyun { \
77*4882a593Smuzhiyun struct asd_ha_addrspace *io_handle = &asd_ha->io_handle[1]; \
78*4882a593Smuzhiyun write##S (val, io_handle->addr + (unsigned long) offs); \
79*4882a593Smuzhiyun return; \
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun ASD_WRITE_OCM(u8, byte, b);
83*4882a593Smuzhiyun ASD_WRITE_OCM(u16,word, w);
84*4882a593Smuzhiyun ASD_WRITE_OCM(u32,dword,l);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun #define ASD_DDBSITE_READ(type, ord) \
87*4882a593Smuzhiyun static inline type asd_ddbsite_read_##ord (struct asd_ha_struct *asd_ha, \
88*4882a593Smuzhiyun u16 ddb_site_no, \
89*4882a593Smuzhiyun u16 offs) \
90*4882a593Smuzhiyun { \
91*4882a593Smuzhiyun asd_write_reg_word(asd_ha, ALTCIOADR, MnDDB_SITE + offs); \
92*4882a593Smuzhiyun asd_write_reg_word(asd_ha, ADDBPTR, ddb_site_no); \
93*4882a593Smuzhiyun return asd_read_reg_##ord (asd_ha, CTXACCESS); \
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun ASD_DDBSITE_READ(u32, dword);
97*4882a593Smuzhiyun ASD_DDBSITE_READ(u16, word);
98*4882a593Smuzhiyun
asd_ddbsite_read_byte(struct asd_ha_struct * asd_ha,u16 ddb_site_no,u16 offs)99*4882a593Smuzhiyun static inline u8 asd_ddbsite_read_byte(struct asd_ha_struct *asd_ha,
100*4882a593Smuzhiyun u16 ddb_site_no,
101*4882a593Smuzhiyun u16 offs)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun if (offs & 1)
104*4882a593Smuzhiyun return asd_ddbsite_read_word(asd_ha, ddb_site_no,
105*4882a593Smuzhiyun offs & ~1) >> 8;
106*4882a593Smuzhiyun else
107*4882a593Smuzhiyun return asd_ddbsite_read_word(asd_ha, ddb_site_no,
108*4882a593Smuzhiyun offs) & 0xFF;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun #define ASD_DDBSITE_WRITE(type, ord) \
113*4882a593Smuzhiyun static inline void asd_ddbsite_write_##ord (struct asd_ha_struct *asd_ha, \
114*4882a593Smuzhiyun u16 ddb_site_no, \
115*4882a593Smuzhiyun u16 offs, type val) \
116*4882a593Smuzhiyun { \
117*4882a593Smuzhiyun asd_write_reg_word(asd_ha, ALTCIOADR, MnDDB_SITE + offs); \
118*4882a593Smuzhiyun asd_write_reg_word(asd_ha, ADDBPTR, ddb_site_no); \
119*4882a593Smuzhiyun asd_write_reg_##ord (asd_ha, CTXACCESS, val); \
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun ASD_DDBSITE_WRITE(u32, dword);
123*4882a593Smuzhiyun ASD_DDBSITE_WRITE(u16, word);
124*4882a593Smuzhiyun
asd_ddbsite_write_byte(struct asd_ha_struct * asd_ha,u16 ddb_site_no,u16 offs,u8 val)125*4882a593Smuzhiyun static inline void asd_ddbsite_write_byte(struct asd_ha_struct *asd_ha,
126*4882a593Smuzhiyun u16 ddb_site_no,
127*4882a593Smuzhiyun u16 offs, u8 val)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun u16 base = offs & ~1;
130*4882a593Smuzhiyun u16 rval = asd_ddbsite_read_word(asd_ha, ddb_site_no, base);
131*4882a593Smuzhiyun if (offs & 1)
132*4882a593Smuzhiyun rval = (val << 8) | (rval & 0xFF);
133*4882a593Smuzhiyun else
134*4882a593Smuzhiyun rval = (rval & 0xFF00) | val;
135*4882a593Smuzhiyun asd_ddbsite_write_word(asd_ha, ddb_site_no, base, rval);
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun #define ASD_SCBSITE_READ(type, ord) \
140*4882a593Smuzhiyun static inline type asd_scbsite_read_##ord (struct asd_ha_struct *asd_ha, \
141*4882a593Smuzhiyun u16 scb_site_no, \
142*4882a593Smuzhiyun u16 offs) \
143*4882a593Smuzhiyun { \
144*4882a593Smuzhiyun asd_write_reg_word(asd_ha, ALTCIOADR, MnSCB_SITE + offs); \
145*4882a593Smuzhiyun asd_write_reg_word(asd_ha, ASCBPTR, scb_site_no); \
146*4882a593Smuzhiyun return asd_read_reg_##ord (asd_ha, CTXACCESS); \
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun ASD_SCBSITE_READ(u32, dword);
150*4882a593Smuzhiyun ASD_SCBSITE_READ(u16, word);
151*4882a593Smuzhiyun
asd_scbsite_read_byte(struct asd_ha_struct * asd_ha,u16 scb_site_no,u16 offs)152*4882a593Smuzhiyun static inline u8 asd_scbsite_read_byte(struct asd_ha_struct *asd_ha,
153*4882a593Smuzhiyun u16 scb_site_no,
154*4882a593Smuzhiyun u16 offs)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun if (offs & 1)
157*4882a593Smuzhiyun return asd_scbsite_read_word(asd_ha, scb_site_no,
158*4882a593Smuzhiyun offs & ~1) >> 8;
159*4882a593Smuzhiyun else
160*4882a593Smuzhiyun return asd_scbsite_read_word(asd_ha, scb_site_no,
161*4882a593Smuzhiyun offs) & 0xFF;
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun #define ASD_SCBSITE_WRITE(type, ord) \
166*4882a593Smuzhiyun static inline void asd_scbsite_write_##ord (struct asd_ha_struct *asd_ha, \
167*4882a593Smuzhiyun u16 scb_site_no, \
168*4882a593Smuzhiyun u16 offs, type val) \
169*4882a593Smuzhiyun { \
170*4882a593Smuzhiyun asd_write_reg_word(asd_ha, ALTCIOADR, MnSCB_SITE + offs); \
171*4882a593Smuzhiyun asd_write_reg_word(asd_ha, ASCBPTR, scb_site_no); \
172*4882a593Smuzhiyun asd_write_reg_##ord (asd_ha, CTXACCESS, val); \
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun ASD_SCBSITE_WRITE(u32, dword);
176*4882a593Smuzhiyun ASD_SCBSITE_WRITE(u16, word);
177*4882a593Smuzhiyun
asd_scbsite_write_byte(struct asd_ha_struct * asd_ha,u16 scb_site_no,u16 offs,u8 val)178*4882a593Smuzhiyun static inline void asd_scbsite_write_byte(struct asd_ha_struct *asd_ha,
179*4882a593Smuzhiyun u16 scb_site_no,
180*4882a593Smuzhiyun u16 offs, u8 val)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun u16 base = offs & ~1;
183*4882a593Smuzhiyun u16 rval = asd_scbsite_read_word(asd_ha, scb_site_no, base);
184*4882a593Smuzhiyun if (offs & 1)
185*4882a593Smuzhiyun rval = (val << 8) | (rval & 0xFF);
186*4882a593Smuzhiyun else
187*4882a593Smuzhiyun rval = (rval & 0xFF00) | val;
188*4882a593Smuzhiyun asd_scbsite_write_word(asd_ha, scb_site_no, base, rval);
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun /**
192*4882a593Smuzhiyun * asd_ddbsite_update_word -- atomically update a word in a ddb site
193*4882a593Smuzhiyun * @asd_ha: pointer to host adapter structure
194*4882a593Smuzhiyun * @ddb_site_no: the DDB site number
195*4882a593Smuzhiyun * @offs: the offset into the DDB
196*4882a593Smuzhiyun * @oldval: old value found in that offset
197*4882a593Smuzhiyun * @newval: the new value to replace it
198*4882a593Smuzhiyun *
199*4882a593Smuzhiyun * This function is used when the sequencers are running and we need to
200*4882a593Smuzhiyun * update a DDB site atomically without expensive pausing and upausing
201*4882a593Smuzhiyun * of the sequencers and accessing the DDB site through the CIO bus.
202*4882a593Smuzhiyun *
203*4882a593Smuzhiyun * Return 0 on success; -EFAULT on parity error; -EAGAIN if the old value
204*4882a593Smuzhiyun * is different than the current value at that offset.
205*4882a593Smuzhiyun */
asd_ddbsite_update_word(struct asd_ha_struct * asd_ha,u16 ddb_site_no,u16 offs,u16 oldval,u16 newval)206*4882a593Smuzhiyun static inline int asd_ddbsite_update_word(struct asd_ha_struct *asd_ha,
207*4882a593Smuzhiyun u16 ddb_site_no, u16 offs,
208*4882a593Smuzhiyun u16 oldval, u16 newval)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun u8 done;
211*4882a593Smuzhiyun u16 oval = asd_ddbsite_read_word(asd_ha, ddb_site_no, offs);
212*4882a593Smuzhiyun if (oval != oldval)
213*4882a593Smuzhiyun return -EAGAIN;
214*4882a593Smuzhiyun asd_write_reg_word(asd_ha, AOLDDATA, oldval);
215*4882a593Smuzhiyun asd_write_reg_word(asd_ha, ANEWDATA, newval);
216*4882a593Smuzhiyun do {
217*4882a593Smuzhiyun done = asd_read_reg_byte(asd_ha, ATOMICSTATCTL);
218*4882a593Smuzhiyun } while (!(done & ATOMICDONE));
219*4882a593Smuzhiyun if (done & ATOMICERR)
220*4882a593Smuzhiyun return -EFAULT; /* parity error */
221*4882a593Smuzhiyun else if (done & ATOMICWIN)
222*4882a593Smuzhiyun return 0; /* success */
223*4882a593Smuzhiyun else
224*4882a593Smuzhiyun return -EAGAIN; /* oldval different than current value */
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun
asd_ddbsite_update_byte(struct asd_ha_struct * asd_ha,u16 ddb_site_no,u16 offs,u8 _oldval,u8 _newval)227*4882a593Smuzhiyun static inline int asd_ddbsite_update_byte(struct asd_ha_struct *asd_ha,
228*4882a593Smuzhiyun u16 ddb_site_no, u16 offs,
229*4882a593Smuzhiyun u8 _oldval, u8 _newval)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun u16 base = offs & ~1;
232*4882a593Smuzhiyun u16 oval;
233*4882a593Smuzhiyun u16 nval = asd_ddbsite_read_word(asd_ha, ddb_site_no, base);
234*4882a593Smuzhiyun if (offs & 1) {
235*4882a593Smuzhiyun if ((nval >> 8) != _oldval)
236*4882a593Smuzhiyun return -EAGAIN;
237*4882a593Smuzhiyun nval = (_newval << 8) | (nval & 0xFF);
238*4882a593Smuzhiyun oval = (_oldval << 8) | (nval & 0xFF);
239*4882a593Smuzhiyun } else {
240*4882a593Smuzhiyun if ((nval & 0xFF) != _oldval)
241*4882a593Smuzhiyun return -EAGAIN;
242*4882a593Smuzhiyun nval = (nval & 0xFF00) | _newval;
243*4882a593Smuzhiyun oval = (nval & 0xFF00) | _oldval;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun return asd_ddbsite_update_word(asd_ha, ddb_site_no, base, oval, nval);
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
asd_write_reg_addr(struct asd_ha_struct * asd_ha,u32 reg,dma_addr_t dma_handle)248*4882a593Smuzhiyun static inline void asd_write_reg_addr(struct asd_ha_struct *asd_ha, u32 reg,
249*4882a593Smuzhiyun dma_addr_t dma_handle)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun asd_write_reg_dword(asd_ha, reg, ASD_BUSADDR_LO(dma_handle));
252*4882a593Smuzhiyun asd_write_reg_dword(asd_ha, reg+4, ASD_BUSADDR_HI(dma_handle));
253*4882a593Smuzhiyun }
254*4882a593Smuzhiyun
asd_get_cmdctx_size(struct asd_ha_struct * asd_ha)255*4882a593Smuzhiyun static inline u32 asd_get_cmdctx_size(struct asd_ha_struct *asd_ha)
256*4882a593Smuzhiyun {
257*4882a593Smuzhiyun /* DCHREVISION returns 0, possibly broken */
258*4882a593Smuzhiyun u32 ctxmemsize = asd_read_reg_dword(asd_ha, LmMnINT(0,0)) & CTXMEMSIZE;
259*4882a593Smuzhiyun return ctxmemsize ? 65536 : 32768;
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
asd_get_devctx_size(struct asd_ha_struct * asd_ha)262*4882a593Smuzhiyun static inline u32 asd_get_devctx_size(struct asd_ha_struct *asd_ha)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun u32 ctxmemsize = asd_read_reg_dword(asd_ha, LmMnINT(0,0)) & CTXMEMSIZE;
265*4882a593Smuzhiyun return ctxmemsize ? 8192 : 4096;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
asd_disable_ints(struct asd_ha_struct * asd_ha)268*4882a593Smuzhiyun static inline void asd_disable_ints(struct asd_ha_struct *asd_ha)
269*4882a593Smuzhiyun {
270*4882a593Smuzhiyun asd_write_reg_dword(asd_ha, CHIMINTEN, RST_CHIMINTEN);
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
asd_enable_ints(struct asd_ha_struct * asd_ha)273*4882a593Smuzhiyun static inline void asd_enable_ints(struct asd_ha_struct *asd_ha)
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun /* Enable COM SAS interrupt on errors, COMSTAT */
276*4882a593Smuzhiyun asd_write_reg_dword(asd_ha, COMSTATEN,
277*4882a593Smuzhiyun EN_CSBUFPERR | EN_CSERR | EN_OVLYERR);
278*4882a593Smuzhiyun /* Enable DCH SAS CFIFTOERR */
279*4882a593Smuzhiyun asd_write_reg_dword(asd_ha, DCHSTATUS, EN_CFIFTOERR);
280*4882a593Smuzhiyun /* Enable Host Device interrupts */
281*4882a593Smuzhiyun asd_write_reg_dword(asd_ha, CHIMINTEN, SET_CHIMINTEN);
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun #endif
285