xref: /OK3568_Linux_fs/kernel/drivers/scsi/aacraid/rx.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *	Adaptec AAC series RAID controller driver
4*4882a593Smuzhiyun  *	(c) Copyright 2001 Red Hat Inc.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * based on the old aacraid driver that is..
7*4882a593Smuzhiyun  * Adaptec aacraid device driver for Linux.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Copyright (c) 2000-2010 Adaptec, Inc.
10*4882a593Smuzhiyun  *               2010-2015 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
11*4882a593Smuzhiyun  *		 2016-2017 Microsemi Corp. (aacraid@microsemi.com)
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * Module Name:
14*4882a593Smuzhiyun  *  rx.c
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  * Abstract: Hardware miniport for Drawbridge specific hardware functions.
17*4882a593Smuzhiyun  */
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include <linux/kernel.h>
20*4882a593Smuzhiyun #include <linux/init.h>
21*4882a593Smuzhiyun #include <linux/types.h>
22*4882a593Smuzhiyun #include <linux/pci.h>
23*4882a593Smuzhiyun #include <linux/spinlock.h>
24*4882a593Smuzhiyun #include <linux/blkdev.h>
25*4882a593Smuzhiyun #include <linux/delay.h>
26*4882a593Smuzhiyun #include <linux/completion.h>
27*4882a593Smuzhiyun #include <linux/time.h>
28*4882a593Smuzhiyun #include <linux/interrupt.h>
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #include <scsi/scsi_host.h>
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #include "aacraid.h"
33*4882a593Smuzhiyun 
aac_rx_intr_producer(int irq,void * dev_id)34*4882a593Smuzhiyun static irqreturn_t aac_rx_intr_producer(int irq, void *dev_id)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun 	struct aac_dev *dev = dev_id;
37*4882a593Smuzhiyun 	unsigned long bellbits;
38*4882a593Smuzhiyun 	u8 intstat = rx_readb(dev, MUnit.OISR);
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun 	/*
41*4882a593Smuzhiyun 	 *	Read mask and invert because drawbridge is reversed.
42*4882a593Smuzhiyun 	 *	This allows us to only service interrupts that have
43*4882a593Smuzhiyun 	 *	been enabled.
44*4882a593Smuzhiyun 	 *	Check to see if this is our interrupt.  If it isn't just return
45*4882a593Smuzhiyun 	 */
46*4882a593Smuzhiyun 	if (likely(intstat & ~(dev->OIMR))) {
47*4882a593Smuzhiyun 		bellbits = rx_readl(dev, OutboundDoorbellReg);
48*4882a593Smuzhiyun 		if (unlikely(bellbits & DoorBellPrintfReady)) {
49*4882a593Smuzhiyun 			aac_printf(dev, readl (&dev->IndexRegs->Mailbox[5]));
50*4882a593Smuzhiyun 			rx_writel(dev, MUnit.ODR,DoorBellPrintfReady);
51*4882a593Smuzhiyun 			rx_writel(dev, InboundDoorbellReg,DoorBellPrintfDone);
52*4882a593Smuzhiyun 		}
53*4882a593Smuzhiyun 		else if (unlikely(bellbits & DoorBellAdapterNormCmdReady)) {
54*4882a593Smuzhiyun 			rx_writel(dev, MUnit.ODR, DoorBellAdapterNormCmdReady);
55*4882a593Smuzhiyun 			aac_command_normal(&dev->queues->queue[HostNormCmdQueue]);
56*4882a593Smuzhiyun 		}
57*4882a593Smuzhiyun 		else if (likely(bellbits & DoorBellAdapterNormRespReady)) {
58*4882a593Smuzhiyun 			rx_writel(dev, MUnit.ODR,DoorBellAdapterNormRespReady);
59*4882a593Smuzhiyun 			aac_response_normal(&dev->queues->queue[HostNormRespQueue]);
60*4882a593Smuzhiyun 		}
61*4882a593Smuzhiyun 		else if (unlikely(bellbits & DoorBellAdapterNormCmdNotFull)) {
62*4882a593Smuzhiyun 			rx_writel(dev, MUnit.ODR, DoorBellAdapterNormCmdNotFull);
63*4882a593Smuzhiyun 		}
64*4882a593Smuzhiyun 		else if (unlikely(bellbits & DoorBellAdapterNormRespNotFull)) {
65*4882a593Smuzhiyun 			rx_writel(dev, MUnit.ODR, DoorBellAdapterNormCmdNotFull);
66*4882a593Smuzhiyun 			rx_writel(dev, MUnit.ODR, DoorBellAdapterNormRespNotFull);
67*4882a593Smuzhiyun 		}
68*4882a593Smuzhiyun 		return IRQ_HANDLED;
69*4882a593Smuzhiyun 	}
70*4882a593Smuzhiyun 	return IRQ_NONE;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun 
aac_rx_intr_message(int irq,void * dev_id)73*4882a593Smuzhiyun static irqreturn_t aac_rx_intr_message(int irq, void *dev_id)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun 	int isAif, isFastResponse, isSpecial;
76*4882a593Smuzhiyun 	struct aac_dev *dev = dev_id;
77*4882a593Smuzhiyun 	u32 Index = rx_readl(dev, MUnit.OutboundQueue);
78*4882a593Smuzhiyun 	if (unlikely(Index == 0xFFFFFFFFL))
79*4882a593Smuzhiyun 		Index = rx_readl(dev, MUnit.OutboundQueue);
80*4882a593Smuzhiyun 	if (likely(Index != 0xFFFFFFFFL)) {
81*4882a593Smuzhiyun 		do {
82*4882a593Smuzhiyun 			isAif = isFastResponse = isSpecial = 0;
83*4882a593Smuzhiyun 			if (Index & 0x00000002L) {
84*4882a593Smuzhiyun 				isAif = 1;
85*4882a593Smuzhiyun 				if (Index == 0xFFFFFFFEL)
86*4882a593Smuzhiyun 					isSpecial = 1;
87*4882a593Smuzhiyun 				Index &= ~0x00000002L;
88*4882a593Smuzhiyun 			} else {
89*4882a593Smuzhiyun 				if (Index & 0x00000001L)
90*4882a593Smuzhiyun 					isFastResponse = 1;
91*4882a593Smuzhiyun 				Index >>= 2;
92*4882a593Smuzhiyun 			}
93*4882a593Smuzhiyun 			if (!isSpecial) {
94*4882a593Smuzhiyun 				if (unlikely(aac_intr_normal(dev,
95*4882a593Smuzhiyun 						Index, isAif,
96*4882a593Smuzhiyun 						isFastResponse, NULL))) {
97*4882a593Smuzhiyun 					rx_writel(dev,
98*4882a593Smuzhiyun 						MUnit.OutboundQueue,
99*4882a593Smuzhiyun 						Index);
100*4882a593Smuzhiyun 					rx_writel(dev,
101*4882a593Smuzhiyun 						MUnit.ODR,
102*4882a593Smuzhiyun 						DoorBellAdapterNormRespReady);
103*4882a593Smuzhiyun 				}
104*4882a593Smuzhiyun 			}
105*4882a593Smuzhiyun 			Index = rx_readl(dev, MUnit.OutboundQueue);
106*4882a593Smuzhiyun 		} while (Index != 0xFFFFFFFFL);
107*4882a593Smuzhiyun 		return IRQ_HANDLED;
108*4882a593Smuzhiyun 	}
109*4882a593Smuzhiyun 	return IRQ_NONE;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun /**
113*4882a593Smuzhiyun  *	aac_rx_disable_interrupt	-	Disable interrupts
114*4882a593Smuzhiyun  *	@dev: Adapter
115*4882a593Smuzhiyun  */
116*4882a593Smuzhiyun 
aac_rx_disable_interrupt(struct aac_dev * dev)117*4882a593Smuzhiyun static void aac_rx_disable_interrupt(struct aac_dev *dev)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun 	rx_writeb(dev, MUnit.OIMR, dev->OIMR = 0xff);
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun /**
123*4882a593Smuzhiyun  *	aac_rx_enable_interrupt_producer	-	Enable interrupts
124*4882a593Smuzhiyun  *	@dev: Adapter
125*4882a593Smuzhiyun  */
126*4882a593Smuzhiyun 
aac_rx_enable_interrupt_producer(struct aac_dev * dev)127*4882a593Smuzhiyun static void aac_rx_enable_interrupt_producer(struct aac_dev *dev)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun 	rx_writeb(dev, MUnit.OIMR, dev->OIMR = 0xfb);
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun /**
133*4882a593Smuzhiyun  *	aac_rx_enable_interrupt_message	-	Enable interrupts
134*4882a593Smuzhiyun  *	@dev: Adapter
135*4882a593Smuzhiyun  */
136*4882a593Smuzhiyun 
aac_rx_enable_interrupt_message(struct aac_dev * dev)137*4882a593Smuzhiyun static void aac_rx_enable_interrupt_message(struct aac_dev *dev)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	rx_writeb(dev, MUnit.OIMR, dev->OIMR = 0xf7);
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun /**
143*4882a593Smuzhiyun  *	rx_sync_cmd	-	send a command and wait
144*4882a593Smuzhiyun  *	@dev: Adapter
145*4882a593Smuzhiyun  *	@command: Command to execute
146*4882a593Smuzhiyun  *	@p1: first parameter
147*4882a593Smuzhiyun  *	@p2: second parameter
148*4882a593Smuzhiyun  *	@p3: third parameter
149*4882a593Smuzhiyun  *	@p4: forth parameter
150*4882a593Smuzhiyun  *	@p5: fifth parameter
151*4882a593Smuzhiyun  *	@p6: sixth parameter
152*4882a593Smuzhiyun  *	@status: adapter status
153*4882a593Smuzhiyun  *	@r1: first return value
154*4882a593Smuzhiyun  *	@r2: second return value
155*4882a593Smuzhiyun  *	@r3: third return value
156*4882a593Smuzhiyun  *	@r4: forth return value
157*4882a593Smuzhiyun  *
158*4882a593Smuzhiyun  *	This routine will send a synchronous command to the adapter and wait
159*4882a593Smuzhiyun  *	for its	completion.
160*4882a593Smuzhiyun  */
161*4882a593Smuzhiyun 
rx_sync_cmd(struct aac_dev * dev,u32 command,u32 p1,u32 p2,u32 p3,u32 p4,u32 p5,u32 p6,u32 * status,u32 * r1,u32 * r2,u32 * r3,u32 * r4)162*4882a593Smuzhiyun static int rx_sync_cmd(struct aac_dev *dev, u32 command,
163*4882a593Smuzhiyun 	u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6,
164*4882a593Smuzhiyun 	u32 *status, u32 * r1, u32 * r2, u32 * r3, u32 * r4)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun 	unsigned long start;
167*4882a593Smuzhiyun 	int ok;
168*4882a593Smuzhiyun 	/*
169*4882a593Smuzhiyun 	 *	Write the command into Mailbox 0
170*4882a593Smuzhiyun 	 */
171*4882a593Smuzhiyun 	writel(command, &dev->IndexRegs->Mailbox[0]);
172*4882a593Smuzhiyun 	/*
173*4882a593Smuzhiyun 	 *	Write the parameters into Mailboxes 1 - 6
174*4882a593Smuzhiyun 	 */
175*4882a593Smuzhiyun 	writel(p1, &dev->IndexRegs->Mailbox[1]);
176*4882a593Smuzhiyun 	writel(p2, &dev->IndexRegs->Mailbox[2]);
177*4882a593Smuzhiyun 	writel(p3, &dev->IndexRegs->Mailbox[3]);
178*4882a593Smuzhiyun 	writel(p4, &dev->IndexRegs->Mailbox[4]);
179*4882a593Smuzhiyun 	/*
180*4882a593Smuzhiyun 	 *	Clear the synch command doorbell to start on a clean slate.
181*4882a593Smuzhiyun 	 */
182*4882a593Smuzhiyun 	rx_writel(dev, OutboundDoorbellReg, OUTBOUNDDOORBELL_0);
183*4882a593Smuzhiyun 	/*
184*4882a593Smuzhiyun 	 *	Disable doorbell interrupts
185*4882a593Smuzhiyun 	 */
186*4882a593Smuzhiyun 	rx_writeb(dev, MUnit.OIMR, dev->OIMR = 0xff);
187*4882a593Smuzhiyun 	/*
188*4882a593Smuzhiyun 	 *	Force the completion of the mask register write before issuing
189*4882a593Smuzhiyun 	 *	the interrupt.
190*4882a593Smuzhiyun 	 */
191*4882a593Smuzhiyun 	rx_readb (dev, MUnit.OIMR);
192*4882a593Smuzhiyun 	/*
193*4882a593Smuzhiyun 	 *	Signal that there is a new synch command
194*4882a593Smuzhiyun 	 */
195*4882a593Smuzhiyun 	rx_writel(dev, InboundDoorbellReg, INBOUNDDOORBELL_0);
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	ok = 0;
198*4882a593Smuzhiyun 	start = jiffies;
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	/*
201*4882a593Smuzhiyun 	 *	Wait up to 30 seconds
202*4882a593Smuzhiyun 	 */
203*4882a593Smuzhiyun 	while (time_before(jiffies, start+30*HZ))
204*4882a593Smuzhiyun 	{
205*4882a593Smuzhiyun 		udelay(5);	/* Delay 5 microseconds to let Mon960 get info. */
206*4882a593Smuzhiyun 		/*
207*4882a593Smuzhiyun 		 *	Mon960 will set doorbell0 bit when it has completed the command.
208*4882a593Smuzhiyun 		 */
209*4882a593Smuzhiyun 		if (rx_readl(dev, OutboundDoorbellReg) & OUTBOUNDDOORBELL_0) {
210*4882a593Smuzhiyun 			/*
211*4882a593Smuzhiyun 			 *	Clear the doorbell.
212*4882a593Smuzhiyun 			 */
213*4882a593Smuzhiyun 			rx_writel(dev, OutboundDoorbellReg, OUTBOUNDDOORBELL_0);
214*4882a593Smuzhiyun 			ok = 1;
215*4882a593Smuzhiyun 			break;
216*4882a593Smuzhiyun 		}
217*4882a593Smuzhiyun 		/*
218*4882a593Smuzhiyun 		 *	Yield the processor in case we are slow
219*4882a593Smuzhiyun 		 */
220*4882a593Smuzhiyun 		msleep(1);
221*4882a593Smuzhiyun 	}
222*4882a593Smuzhiyun 	if (unlikely(ok != 1)) {
223*4882a593Smuzhiyun 		/*
224*4882a593Smuzhiyun 		 *	Restore interrupt mask even though we timed out
225*4882a593Smuzhiyun 		 */
226*4882a593Smuzhiyun 		aac_adapter_enable_int(dev);
227*4882a593Smuzhiyun 		return -ETIMEDOUT;
228*4882a593Smuzhiyun 	}
229*4882a593Smuzhiyun 	/*
230*4882a593Smuzhiyun 	 *	Pull the synch status from Mailbox 0.
231*4882a593Smuzhiyun 	 */
232*4882a593Smuzhiyun 	if (status)
233*4882a593Smuzhiyun 		*status = readl(&dev->IndexRegs->Mailbox[0]);
234*4882a593Smuzhiyun 	if (r1)
235*4882a593Smuzhiyun 		*r1 = readl(&dev->IndexRegs->Mailbox[1]);
236*4882a593Smuzhiyun 	if (r2)
237*4882a593Smuzhiyun 		*r2 = readl(&dev->IndexRegs->Mailbox[2]);
238*4882a593Smuzhiyun 	if (r3)
239*4882a593Smuzhiyun 		*r3 = readl(&dev->IndexRegs->Mailbox[3]);
240*4882a593Smuzhiyun 	if (r4)
241*4882a593Smuzhiyun 		*r4 = readl(&dev->IndexRegs->Mailbox[4]);
242*4882a593Smuzhiyun 	/*
243*4882a593Smuzhiyun 	 *	Clear the synch command doorbell.
244*4882a593Smuzhiyun 	 */
245*4882a593Smuzhiyun 	rx_writel(dev, OutboundDoorbellReg, OUTBOUNDDOORBELL_0);
246*4882a593Smuzhiyun 	/*
247*4882a593Smuzhiyun 	 *	Restore interrupt mask
248*4882a593Smuzhiyun 	 */
249*4882a593Smuzhiyun 	aac_adapter_enable_int(dev);
250*4882a593Smuzhiyun 	return 0;
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun /**
255*4882a593Smuzhiyun  *	aac_rx_interrupt_adapter	-	interrupt adapter
256*4882a593Smuzhiyun  *	@dev: Adapter
257*4882a593Smuzhiyun  *
258*4882a593Smuzhiyun  *	Send an interrupt to the i960 and breakpoint it.
259*4882a593Smuzhiyun  */
260*4882a593Smuzhiyun 
aac_rx_interrupt_adapter(struct aac_dev * dev)261*4882a593Smuzhiyun static void aac_rx_interrupt_adapter(struct aac_dev *dev)
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun 	rx_sync_cmd(dev, BREAKPOINT_REQUEST, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL);
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun /**
267*4882a593Smuzhiyun  *	aac_rx_notify_adapter		-	send an event to the adapter
268*4882a593Smuzhiyun  *	@dev: Adapter
269*4882a593Smuzhiyun  *	@event: Event to send
270*4882a593Smuzhiyun  *
271*4882a593Smuzhiyun  *	Notify the i960 that something it probably cares about has
272*4882a593Smuzhiyun  *	happened.
273*4882a593Smuzhiyun  */
274*4882a593Smuzhiyun 
aac_rx_notify_adapter(struct aac_dev * dev,u32 event)275*4882a593Smuzhiyun static void aac_rx_notify_adapter(struct aac_dev *dev, u32 event)
276*4882a593Smuzhiyun {
277*4882a593Smuzhiyun 	switch (event) {
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	case AdapNormCmdQue:
280*4882a593Smuzhiyun 		rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_1);
281*4882a593Smuzhiyun 		break;
282*4882a593Smuzhiyun 	case HostNormRespNotFull:
283*4882a593Smuzhiyun 		rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_4);
284*4882a593Smuzhiyun 		break;
285*4882a593Smuzhiyun 	case AdapNormRespQue:
286*4882a593Smuzhiyun 		rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_2);
287*4882a593Smuzhiyun 		break;
288*4882a593Smuzhiyun 	case HostNormCmdNotFull:
289*4882a593Smuzhiyun 		rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_3);
290*4882a593Smuzhiyun 		break;
291*4882a593Smuzhiyun 	case HostShutdown:
292*4882a593Smuzhiyun 		break;
293*4882a593Smuzhiyun 	case FastIo:
294*4882a593Smuzhiyun 		rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_6);
295*4882a593Smuzhiyun 		break;
296*4882a593Smuzhiyun 	case AdapPrintfDone:
297*4882a593Smuzhiyun 		rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_5);
298*4882a593Smuzhiyun 		break;
299*4882a593Smuzhiyun 	default:
300*4882a593Smuzhiyun 		BUG();
301*4882a593Smuzhiyun 		break;
302*4882a593Smuzhiyun 	}
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun /**
306*4882a593Smuzhiyun  *	aac_rx_start_adapter		-	activate adapter
307*4882a593Smuzhiyun  *	@dev:	Adapter
308*4882a593Smuzhiyun  *
309*4882a593Smuzhiyun  *	Start up processing on an i960 based AAC adapter
310*4882a593Smuzhiyun  */
311*4882a593Smuzhiyun 
aac_rx_start_adapter(struct aac_dev * dev)312*4882a593Smuzhiyun static void aac_rx_start_adapter(struct aac_dev *dev)
313*4882a593Smuzhiyun {
314*4882a593Smuzhiyun 	union aac_init *init;
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun 	init = dev->init;
317*4882a593Smuzhiyun 	init->r7.host_elapsed_seconds = cpu_to_le32(ktime_get_real_seconds());
318*4882a593Smuzhiyun 	// We can only use a 32 bit address here
319*4882a593Smuzhiyun 	rx_sync_cmd(dev, INIT_STRUCT_BASE_ADDRESS, (u32)(ulong)dev->init_pa,
320*4882a593Smuzhiyun 	  0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL);
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun /**
324*4882a593Smuzhiyun  *	aac_rx_check_health
325*4882a593Smuzhiyun  *	@dev: device to check if healthy
326*4882a593Smuzhiyun  *
327*4882a593Smuzhiyun  *	Will attempt to determine if the specified adapter is alive and
328*4882a593Smuzhiyun  *	capable of handling requests, returning 0 if alive.
329*4882a593Smuzhiyun  */
aac_rx_check_health(struct aac_dev * dev)330*4882a593Smuzhiyun static int aac_rx_check_health(struct aac_dev *dev)
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun 	u32 status = rx_readl(dev, MUnit.OMRx[0]);
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun 	/*
335*4882a593Smuzhiyun 	 *	Check to see if the board failed any self tests.
336*4882a593Smuzhiyun 	 */
337*4882a593Smuzhiyun 	if (unlikely(status & SELF_TEST_FAILED))
338*4882a593Smuzhiyun 		return -1;
339*4882a593Smuzhiyun 	/*
340*4882a593Smuzhiyun 	 *	Check to see if the board panic'd.
341*4882a593Smuzhiyun 	 */
342*4882a593Smuzhiyun 	if (unlikely(status & KERNEL_PANIC)) {
343*4882a593Smuzhiyun 		char * buffer;
344*4882a593Smuzhiyun 		struct POSTSTATUS {
345*4882a593Smuzhiyun 			__le32 Post_Command;
346*4882a593Smuzhiyun 			__le32 Post_Address;
347*4882a593Smuzhiyun 		} * post;
348*4882a593Smuzhiyun 		dma_addr_t paddr, baddr;
349*4882a593Smuzhiyun 		int ret;
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun 		if (likely((status & 0xFF000000L) == 0xBC000000L))
352*4882a593Smuzhiyun 			return (status >> 16) & 0xFF;
353*4882a593Smuzhiyun 		buffer = dma_alloc_coherent(&dev->pdev->dev, 512, &baddr,
354*4882a593Smuzhiyun 					    GFP_KERNEL);
355*4882a593Smuzhiyun 		ret = -2;
356*4882a593Smuzhiyun 		if (unlikely(buffer == NULL))
357*4882a593Smuzhiyun 			return ret;
358*4882a593Smuzhiyun 		post = dma_alloc_coherent(&dev->pdev->dev,
359*4882a593Smuzhiyun 					  sizeof(struct POSTSTATUS), &paddr,
360*4882a593Smuzhiyun 					  GFP_KERNEL);
361*4882a593Smuzhiyun 		if (unlikely(post == NULL)) {
362*4882a593Smuzhiyun 			dma_free_coherent(&dev->pdev->dev, 512, buffer, baddr);
363*4882a593Smuzhiyun 			return ret;
364*4882a593Smuzhiyun 		}
365*4882a593Smuzhiyun 		memset(buffer, 0, 512);
366*4882a593Smuzhiyun 		post->Post_Command = cpu_to_le32(COMMAND_POST_RESULTS);
367*4882a593Smuzhiyun 		post->Post_Address = cpu_to_le32(baddr);
368*4882a593Smuzhiyun 		rx_writel(dev, MUnit.IMRx[0], paddr);
369*4882a593Smuzhiyun 		rx_sync_cmd(dev, COMMAND_POST_RESULTS, baddr, 0, 0, 0, 0, 0,
370*4882a593Smuzhiyun 		  NULL, NULL, NULL, NULL, NULL);
371*4882a593Smuzhiyun 		dma_free_coherent(&dev->pdev->dev, sizeof(struct POSTSTATUS),
372*4882a593Smuzhiyun 				  post, paddr);
373*4882a593Smuzhiyun 		if (likely((buffer[0] == '0') && ((buffer[1] == 'x') || (buffer[1] == 'X')))) {
374*4882a593Smuzhiyun 			ret = (hex_to_bin(buffer[2]) << 4) +
375*4882a593Smuzhiyun 				hex_to_bin(buffer[3]);
376*4882a593Smuzhiyun 		}
377*4882a593Smuzhiyun 		dma_free_coherent(&dev->pdev->dev, 512, buffer, baddr);
378*4882a593Smuzhiyun 		return ret;
379*4882a593Smuzhiyun 	}
380*4882a593Smuzhiyun 	/*
381*4882a593Smuzhiyun 	 *	Wait for the adapter to be up and running.
382*4882a593Smuzhiyun 	 */
383*4882a593Smuzhiyun 	if (unlikely(!(status & KERNEL_UP_AND_RUNNING)))
384*4882a593Smuzhiyun 		return -3;
385*4882a593Smuzhiyun 	/*
386*4882a593Smuzhiyun 	 *	Everything is OK
387*4882a593Smuzhiyun 	 */
388*4882a593Smuzhiyun 	return 0;
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun /**
392*4882a593Smuzhiyun  *	aac_rx_deliver_producer
393*4882a593Smuzhiyun  *	@fib: fib to issue
394*4882a593Smuzhiyun  *
395*4882a593Smuzhiyun  *	Will send a fib, returning 0 if successful.
396*4882a593Smuzhiyun  */
aac_rx_deliver_producer(struct fib * fib)397*4882a593Smuzhiyun int aac_rx_deliver_producer(struct fib * fib)
398*4882a593Smuzhiyun {
399*4882a593Smuzhiyun 	struct aac_dev *dev = fib->dev;
400*4882a593Smuzhiyun 	struct aac_queue *q = &dev->queues->queue[AdapNormCmdQueue];
401*4882a593Smuzhiyun 	u32 Index;
402*4882a593Smuzhiyun 	unsigned long nointr = 0;
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	aac_queue_get( dev, &Index, AdapNormCmdQueue, fib->hw_fib_va, 1, fib, &nointr);
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 	atomic_inc(&q->numpending);
407*4882a593Smuzhiyun 	*(q->headers.producer) = cpu_to_le32(Index + 1);
408*4882a593Smuzhiyun 	if (!(nointr & aac_config.irq_mod))
409*4882a593Smuzhiyun 		aac_adapter_notify(dev, AdapNormCmdQueue);
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun 	return 0;
412*4882a593Smuzhiyun }
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun /**
415*4882a593Smuzhiyun  *	aac_rx_deliver_message
416*4882a593Smuzhiyun  *	@fib: fib to issue
417*4882a593Smuzhiyun  *
418*4882a593Smuzhiyun  *	Will send a fib, returning 0 if successful.
419*4882a593Smuzhiyun  */
aac_rx_deliver_message(struct fib * fib)420*4882a593Smuzhiyun static int aac_rx_deliver_message(struct fib * fib)
421*4882a593Smuzhiyun {
422*4882a593Smuzhiyun 	struct aac_dev *dev = fib->dev;
423*4882a593Smuzhiyun 	struct aac_queue *q = &dev->queues->queue[AdapNormCmdQueue];
424*4882a593Smuzhiyun 	u32 Index;
425*4882a593Smuzhiyun 	u64 addr;
426*4882a593Smuzhiyun 	volatile void __iomem *device;
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 	unsigned long count = 10000000L; /* 50 seconds */
429*4882a593Smuzhiyun 	atomic_inc(&q->numpending);
430*4882a593Smuzhiyun 	for(;;) {
431*4882a593Smuzhiyun 		Index = rx_readl(dev, MUnit.InboundQueue);
432*4882a593Smuzhiyun 		if (unlikely(Index == 0xFFFFFFFFL))
433*4882a593Smuzhiyun 			Index = rx_readl(dev, MUnit.InboundQueue);
434*4882a593Smuzhiyun 		if (likely(Index != 0xFFFFFFFFL))
435*4882a593Smuzhiyun 			break;
436*4882a593Smuzhiyun 		if (--count == 0) {
437*4882a593Smuzhiyun 			atomic_dec(&q->numpending);
438*4882a593Smuzhiyun 			return -ETIMEDOUT;
439*4882a593Smuzhiyun 		}
440*4882a593Smuzhiyun 		udelay(5);
441*4882a593Smuzhiyun 	}
442*4882a593Smuzhiyun 	device = dev->base + Index;
443*4882a593Smuzhiyun 	addr = fib->hw_fib_pa;
444*4882a593Smuzhiyun 	writel((u32)(addr & 0xffffffff), device);
445*4882a593Smuzhiyun 	device += sizeof(u32);
446*4882a593Smuzhiyun 	writel((u32)(addr >> 32), device);
447*4882a593Smuzhiyun 	device += sizeof(u32);
448*4882a593Smuzhiyun 	writel(le16_to_cpu(fib->hw_fib_va->header.Size), device);
449*4882a593Smuzhiyun 	rx_writel(dev, MUnit.InboundQueue, Index);
450*4882a593Smuzhiyun 	return 0;
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun /**
454*4882a593Smuzhiyun  *	aac_rx_ioremap
455*4882a593Smuzhiyun  *	@dev: adapter
456*4882a593Smuzhiyun  *	@size: mapping resize request
457*4882a593Smuzhiyun  *
458*4882a593Smuzhiyun  */
aac_rx_ioremap(struct aac_dev * dev,u32 size)459*4882a593Smuzhiyun static int aac_rx_ioremap(struct aac_dev * dev, u32 size)
460*4882a593Smuzhiyun {
461*4882a593Smuzhiyun 	if (!size) {
462*4882a593Smuzhiyun 		iounmap(dev->regs.rx);
463*4882a593Smuzhiyun 		return 0;
464*4882a593Smuzhiyun 	}
465*4882a593Smuzhiyun 	dev->base = dev->regs.rx = ioremap(dev->base_start, size);
466*4882a593Smuzhiyun 	if (dev->base == NULL)
467*4882a593Smuzhiyun 		return -1;
468*4882a593Smuzhiyun 	dev->IndexRegs = &dev->regs.rx->IndexRegs;
469*4882a593Smuzhiyun 	return 0;
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun 
aac_rx_restart_adapter(struct aac_dev * dev,int bled,u8 reset_type)472*4882a593Smuzhiyun static int aac_rx_restart_adapter(struct aac_dev *dev, int bled, u8 reset_type)
473*4882a593Smuzhiyun {
474*4882a593Smuzhiyun 	u32 var = 0;
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun 	if (!(dev->supplement_adapter_info.supported_options2 &
477*4882a593Smuzhiyun 	  AAC_OPTION_MU_RESET) || (bled >= 0) || (bled == -2)) {
478*4882a593Smuzhiyun 		if (bled)
479*4882a593Smuzhiyun 			printk(KERN_ERR "%s%d: adapter kernel panic'd %x.\n",
480*4882a593Smuzhiyun 				dev->name, dev->id, bled);
481*4882a593Smuzhiyun 		else {
482*4882a593Smuzhiyun 			bled = aac_adapter_sync_cmd(dev, IOP_RESET_ALWAYS,
483*4882a593Smuzhiyun 			  0, 0, 0, 0, 0, 0, &var, NULL, NULL, NULL, NULL);
484*4882a593Smuzhiyun 			if (!bled && (var != 0x00000001) && (var != 0x3803000F))
485*4882a593Smuzhiyun 				bled = -EINVAL;
486*4882a593Smuzhiyun 		}
487*4882a593Smuzhiyun 		if (bled && (bled != -ETIMEDOUT))
488*4882a593Smuzhiyun 			bled = aac_adapter_sync_cmd(dev, IOP_RESET,
489*4882a593Smuzhiyun 			  0, 0, 0, 0, 0, 0, &var, NULL, NULL, NULL, NULL);
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun 		if (bled && (bled != -ETIMEDOUT))
492*4882a593Smuzhiyun 			return -EINVAL;
493*4882a593Smuzhiyun 	}
494*4882a593Smuzhiyun 	if (bled && (var == 0x3803000F)) { /* USE_OTHER_METHOD */
495*4882a593Smuzhiyun 		rx_writel(dev, MUnit.reserved2, 3);
496*4882a593Smuzhiyun 		msleep(5000); /* Delay 5 seconds */
497*4882a593Smuzhiyun 		var = 0x00000001;
498*4882a593Smuzhiyun 	}
499*4882a593Smuzhiyun 	if (bled && (var != 0x00000001))
500*4882a593Smuzhiyun 		return -EINVAL;
501*4882a593Smuzhiyun 	ssleep(5);
502*4882a593Smuzhiyun 	if (rx_readl(dev, MUnit.OMRx[0]) & KERNEL_PANIC)
503*4882a593Smuzhiyun 		return -ENODEV;
504*4882a593Smuzhiyun 	if (startup_timeout < 300)
505*4882a593Smuzhiyun 		startup_timeout = 300;
506*4882a593Smuzhiyun 	return 0;
507*4882a593Smuzhiyun }
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun /**
510*4882a593Smuzhiyun  *	aac_rx_select_comm	-	Select communications method
511*4882a593Smuzhiyun  *	@dev: Adapter
512*4882a593Smuzhiyun  *	@comm: communications method
513*4882a593Smuzhiyun  */
514*4882a593Smuzhiyun 
aac_rx_select_comm(struct aac_dev * dev,int comm)515*4882a593Smuzhiyun int aac_rx_select_comm(struct aac_dev *dev, int comm)
516*4882a593Smuzhiyun {
517*4882a593Smuzhiyun 	switch (comm) {
518*4882a593Smuzhiyun 	case AAC_COMM_PRODUCER:
519*4882a593Smuzhiyun 		dev->a_ops.adapter_enable_int = aac_rx_enable_interrupt_producer;
520*4882a593Smuzhiyun 		dev->a_ops.adapter_intr = aac_rx_intr_producer;
521*4882a593Smuzhiyun 		dev->a_ops.adapter_deliver = aac_rx_deliver_producer;
522*4882a593Smuzhiyun 		break;
523*4882a593Smuzhiyun 	case AAC_COMM_MESSAGE:
524*4882a593Smuzhiyun 		dev->a_ops.adapter_enable_int = aac_rx_enable_interrupt_message;
525*4882a593Smuzhiyun 		dev->a_ops.adapter_intr = aac_rx_intr_message;
526*4882a593Smuzhiyun 		dev->a_ops.adapter_deliver = aac_rx_deliver_message;
527*4882a593Smuzhiyun 		break;
528*4882a593Smuzhiyun 	default:
529*4882a593Smuzhiyun 		return 1;
530*4882a593Smuzhiyun 	}
531*4882a593Smuzhiyun 	return 0;
532*4882a593Smuzhiyun }
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun /**
535*4882a593Smuzhiyun  *	aac_rx_init	-	initialize an i960 based AAC card
536*4882a593Smuzhiyun  *	@dev: device to configure
537*4882a593Smuzhiyun  *
538*4882a593Smuzhiyun  *	Allocate and set up resources for the i960 based AAC variants. The
539*4882a593Smuzhiyun  *	device_interface in the commregion will be allocated and linked
540*4882a593Smuzhiyun  *	to the comm region.
541*4882a593Smuzhiyun  */
542*4882a593Smuzhiyun 
_aac_rx_init(struct aac_dev * dev)543*4882a593Smuzhiyun int _aac_rx_init(struct aac_dev *dev)
544*4882a593Smuzhiyun {
545*4882a593Smuzhiyun 	unsigned long start;
546*4882a593Smuzhiyun 	unsigned long status;
547*4882a593Smuzhiyun 	int restart = 0;
548*4882a593Smuzhiyun 	int instance = dev->id;
549*4882a593Smuzhiyun 	const char * name = dev->name;
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun 	if (aac_adapter_ioremap(dev, dev->base_size)) {
552*4882a593Smuzhiyun 		printk(KERN_WARNING "%s: unable to map adapter.\n", name);
553*4882a593Smuzhiyun 		goto error_iounmap;
554*4882a593Smuzhiyun 	}
555*4882a593Smuzhiyun 
556*4882a593Smuzhiyun 	/* Failure to reset here is an option ... */
557*4882a593Smuzhiyun 	dev->a_ops.adapter_sync_cmd = rx_sync_cmd;
558*4882a593Smuzhiyun 	dev->a_ops.adapter_enable_int = aac_rx_disable_interrupt;
559*4882a593Smuzhiyun 	dev->OIMR = status = rx_readb (dev, MUnit.OIMR);
560*4882a593Smuzhiyun 
561*4882a593Smuzhiyun 	if (((status & 0x0c) != 0x0c) || dev->init_reset) {
562*4882a593Smuzhiyun 		dev->init_reset = false;
563*4882a593Smuzhiyun 		if (!aac_rx_restart_adapter(dev, 0, IOP_HWSOFT_RESET)) {
564*4882a593Smuzhiyun 			/* Make sure the Hardware FIFO is empty */
565*4882a593Smuzhiyun 			while ((++restart < 512) &&
566*4882a593Smuzhiyun 			       (rx_readl(dev, MUnit.OutboundQueue) != 0xFFFFFFFFL));
567*4882a593Smuzhiyun 		}
568*4882a593Smuzhiyun 	}
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun 	/*
571*4882a593Smuzhiyun 	 *	Check to see if the board panic'd while booting.
572*4882a593Smuzhiyun 	 */
573*4882a593Smuzhiyun 	status = rx_readl(dev, MUnit.OMRx[0]);
574*4882a593Smuzhiyun 	if (status & KERNEL_PANIC) {
575*4882a593Smuzhiyun 		if (aac_rx_restart_adapter(dev,
576*4882a593Smuzhiyun 			aac_rx_check_health(dev), IOP_HWSOFT_RESET))
577*4882a593Smuzhiyun 			goto error_iounmap;
578*4882a593Smuzhiyun 		++restart;
579*4882a593Smuzhiyun 	}
580*4882a593Smuzhiyun 	/*
581*4882a593Smuzhiyun 	 *	Check to see if the board failed any self tests.
582*4882a593Smuzhiyun 	 */
583*4882a593Smuzhiyun 	status = rx_readl(dev, MUnit.OMRx[0]);
584*4882a593Smuzhiyun 	if (status & SELF_TEST_FAILED) {
585*4882a593Smuzhiyun 		printk(KERN_ERR "%s%d: adapter self-test failed.\n", dev->name, instance);
586*4882a593Smuzhiyun 		goto error_iounmap;
587*4882a593Smuzhiyun 	}
588*4882a593Smuzhiyun 	/*
589*4882a593Smuzhiyun 	 *	Check to see if the monitor panic'd while booting.
590*4882a593Smuzhiyun 	 */
591*4882a593Smuzhiyun 	if (status & MONITOR_PANIC) {
592*4882a593Smuzhiyun 		printk(KERN_ERR "%s%d: adapter monitor panic.\n", dev->name, instance);
593*4882a593Smuzhiyun 		goto error_iounmap;
594*4882a593Smuzhiyun 	}
595*4882a593Smuzhiyun 	start = jiffies;
596*4882a593Smuzhiyun 	/*
597*4882a593Smuzhiyun 	 *	Wait for the adapter to be up and running. Wait up to 3 minutes
598*4882a593Smuzhiyun 	 */
599*4882a593Smuzhiyun 	while (!((status = rx_readl(dev, MUnit.OMRx[0])) & KERNEL_UP_AND_RUNNING))
600*4882a593Smuzhiyun 	{
601*4882a593Smuzhiyun 		if ((restart &&
602*4882a593Smuzhiyun 		  (status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC))) ||
603*4882a593Smuzhiyun 		  time_after(jiffies, start+HZ*startup_timeout)) {
604*4882a593Smuzhiyun 			printk(KERN_ERR "%s%d: adapter kernel failed to start, init status = %lx.\n",
605*4882a593Smuzhiyun 					dev->name, instance, status);
606*4882a593Smuzhiyun 			goto error_iounmap;
607*4882a593Smuzhiyun 		}
608*4882a593Smuzhiyun 		if (!restart &&
609*4882a593Smuzhiyun 		  ((status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC)) ||
610*4882a593Smuzhiyun 		  time_after(jiffies, start + HZ *
611*4882a593Smuzhiyun 		  ((startup_timeout > 60)
612*4882a593Smuzhiyun 		    ? (startup_timeout - 60)
613*4882a593Smuzhiyun 		    : (startup_timeout / 2))))) {
614*4882a593Smuzhiyun 			if (likely(!aac_rx_restart_adapter(dev,
615*4882a593Smuzhiyun 				aac_rx_check_health(dev), IOP_HWSOFT_RESET)))
616*4882a593Smuzhiyun 				start = jiffies;
617*4882a593Smuzhiyun 			++restart;
618*4882a593Smuzhiyun 		}
619*4882a593Smuzhiyun 		msleep(1);
620*4882a593Smuzhiyun 	}
621*4882a593Smuzhiyun 	if (restart && aac_commit)
622*4882a593Smuzhiyun 		aac_commit = 1;
623*4882a593Smuzhiyun 	/*
624*4882a593Smuzhiyun 	 *	Fill in the common function dispatch table.
625*4882a593Smuzhiyun 	 */
626*4882a593Smuzhiyun 	dev->a_ops.adapter_interrupt = aac_rx_interrupt_adapter;
627*4882a593Smuzhiyun 	dev->a_ops.adapter_disable_int = aac_rx_disable_interrupt;
628*4882a593Smuzhiyun 	dev->a_ops.adapter_notify = aac_rx_notify_adapter;
629*4882a593Smuzhiyun 	dev->a_ops.adapter_sync_cmd = rx_sync_cmd;
630*4882a593Smuzhiyun 	dev->a_ops.adapter_check_health = aac_rx_check_health;
631*4882a593Smuzhiyun 	dev->a_ops.adapter_restart = aac_rx_restart_adapter;
632*4882a593Smuzhiyun 	dev->a_ops.adapter_start = aac_rx_start_adapter;
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun 	/*
635*4882a593Smuzhiyun 	 *	First clear out all interrupts.  Then enable the one's that we
636*4882a593Smuzhiyun 	 *	can handle.
637*4882a593Smuzhiyun 	 */
638*4882a593Smuzhiyun 	aac_adapter_comm(dev, AAC_COMM_PRODUCER);
639*4882a593Smuzhiyun 	aac_adapter_disable_int(dev);
640*4882a593Smuzhiyun 	rx_writel(dev, MUnit.ODR, 0xffffffff);
641*4882a593Smuzhiyun 	aac_adapter_enable_int(dev);
642*4882a593Smuzhiyun 
643*4882a593Smuzhiyun 	if (aac_init_adapter(dev) == NULL)
644*4882a593Smuzhiyun 		goto error_iounmap;
645*4882a593Smuzhiyun 	aac_adapter_comm(dev, dev->comm_interface);
646*4882a593Smuzhiyun 	dev->sync_mode = 0;	/* sync. mode not supported */
647*4882a593Smuzhiyun 	dev->msi = aac_msi && !pci_enable_msi(dev->pdev);
648*4882a593Smuzhiyun 	if (request_irq(dev->pdev->irq, dev->a_ops.adapter_intr,
649*4882a593Smuzhiyun 			IRQF_SHARED, "aacraid", dev) < 0) {
650*4882a593Smuzhiyun 		if (dev->msi)
651*4882a593Smuzhiyun 			pci_disable_msi(dev->pdev);
652*4882a593Smuzhiyun 		printk(KERN_ERR "%s%d: Interrupt unavailable.\n",
653*4882a593Smuzhiyun 			name, instance);
654*4882a593Smuzhiyun 		goto error_iounmap;
655*4882a593Smuzhiyun 	}
656*4882a593Smuzhiyun 	dev->dbg_base = dev->base_start;
657*4882a593Smuzhiyun 	dev->dbg_base_mapped = dev->base;
658*4882a593Smuzhiyun 	dev->dbg_size = dev->base_size;
659*4882a593Smuzhiyun 
660*4882a593Smuzhiyun 	aac_adapter_enable_int(dev);
661*4882a593Smuzhiyun 	/*
662*4882a593Smuzhiyun 	 *	Tell the adapter that all is configured, and it can
663*4882a593Smuzhiyun 	 * start accepting requests
664*4882a593Smuzhiyun 	 */
665*4882a593Smuzhiyun 	aac_rx_start_adapter(dev);
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun 	return 0;
668*4882a593Smuzhiyun 
669*4882a593Smuzhiyun error_iounmap:
670*4882a593Smuzhiyun 
671*4882a593Smuzhiyun 	return -1;
672*4882a593Smuzhiyun }
673*4882a593Smuzhiyun 
aac_rx_init(struct aac_dev * dev)674*4882a593Smuzhiyun int aac_rx_init(struct aac_dev *dev)
675*4882a593Smuzhiyun {
676*4882a593Smuzhiyun 	/*
677*4882a593Smuzhiyun 	 *	Fill in the function dispatch table.
678*4882a593Smuzhiyun 	 */
679*4882a593Smuzhiyun 	dev->a_ops.adapter_ioremap = aac_rx_ioremap;
680*4882a593Smuzhiyun 	dev->a_ops.adapter_comm = aac_rx_select_comm;
681*4882a593Smuzhiyun 
682*4882a593Smuzhiyun 	return _aac_rx_init(dev);
683*4882a593Smuzhiyun }
684