1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /* uctrl.c: TS102 Microcontroller interface on Tadpole Sparcbook 3
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright 1999 Derrick J Brashear (shadow@dementia.org)
5*4882a593Smuzhiyun * Copyright 2008 David S. Miller (davem@davemloft.net)
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/errno.h>
10*4882a593Smuzhiyun #include <linux/delay.h>
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/slab.h>
13*4882a593Smuzhiyun #include <linux/mutex.h>
14*4882a593Smuzhiyun #include <linux/ioport.h>
15*4882a593Smuzhiyun #include <linux/miscdevice.h>
16*4882a593Smuzhiyun #include <linux/mm.h>
17*4882a593Smuzhiyun #include <linux/of.h>
18*4882a593Smuzhiyun #include <linux/of_device.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <asm/openprom.h>
21*4882a593Smuzhiyun #include <asm/oplib.h>
22*4882a593Smuzhiyun #include <asm/irq.h>
23*4882a593Smuzhiyun #include <asm/io.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define DEBUG 1
26*4882a593Smuzhiyun #ifdef DEBUG
27*4882a593Smuzhiyun #define dprintk(x) printk x
28*4882a593Smuzhiyun #else
29*4882a593Smuzhiyun #define dprintk(x)
30*4882a593Smuzhiyun #endif
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun struct uctrl_regs {
33*4882a593Smuzhiyun u32 uctrl_intr;
34*4882a593Smuzhiyun u32 uctrl_data;
35*4882a593Smuzhiyun u32 uctrl_stat;
36*4882a593Smuzhiyun u32 uctrl_xxx[5];
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun struct ts102_regs {
40*4882a593Smuzhiyun u32 card_a_intr;
41*4882a593Smuzhiyun u32 card_a_stat;
42*4882a593Smuzhiyun u32 card_a_ctrl;
43*4882a593Smuzhiyun u32 card_a_xxx;
44*4882a593Smuzhiyun u32 card_b_intr;
45*4882a593Smuzhiyun u32 card_b_stat;
46*4882a593Smuzhiyun u32 card_b_ctrl;
47*4882a593Smuzhiyun u32 card_b_xxx;
48*4882a593Smuzhiyun u32 uctrl_intr;
49*4882a593Smuzhiyun u32 uctrl_data;
50*4882a593Smuzhiyun u32 uctrl_stat;
51*4882a593Smuzhiyun u32 uctrl_xxx;
52*4882a593Smuzhiyun u32 ts102_xxx[4];
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* Bits for uctrl_intr register */
56*4882a593Smuzhiyun #define UCTRL_INTR_TXE_REQ 0x01 /* transmit FIFO empty int req */
57*4882a593Smuzhiyun #define UCTRL_INTR_TXNF_REQ 0x02 /* transmit FIFO not full int req */
58*4882a593Smuzhiyun #define UCTRL_INTR_RXNE_REQ 0x04 /* receive FIFO not empty int req */
59*4882a593Smuzhiyun #define UCTRL_INTR_RXO_REQ 0x08 /* receive FIFO overflow int req */
60*4882a593Smuzhiyun #define UCTRL_INTR_TXE_MSK 0x10 /* transmit FIFO empty mask */
61*4882a593Smuzhiyun #define UCTRL_INTR_TXNF_MSK 0x20 /* transmit FIFO not full mask */
62*4882a593Smuzhiyun #define UCTRL_INTR_RXNE_MSK 0x40 /* receive FIFO not empty mask */
63*4882a593Smuzhiyun #define UCTRL_INTR_RXO_MSK 0x80 /* receive FIFO overflow mask */
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* Bits for uctrl_stat register */
66*4882a593Smuzhiyun #define UCTRL_STAT_TXE_STA 0x01 /* transmit FIFO empty status */
67*4882a593Smuzhiyun #define UCTRL_STAT_TXNF_STA 0x02 /* transmit FIFO not full status */
68*4882a593Smuzhiyun #define UCTRL_STAT_RXNE_STA 0x04 /* receive FIFO not empty status */
69*4882a593Smuzhiyun #define UCTRL_STAT_RXO_STA 0x08 /* receive FIFO overflow status */
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun static DEFINE_MUTEX(uctrl_mutex);
72*4882a593Smuzhiyun static const char *uctrl_extstatus[16] = {
73*4882a593Smuzhiyun "main power available",
74*4882a593Smuzhiyun "internal battery attached",
75*4882a593Smuzhiyun "external battery attached",
76*4882a593Smuzhiyun "external VGA attached",
77*4882a593Smuzhiyun "external keyboard attached",
78*4882a593Smuzhiyun "external mouse attached",
79*4882a593Smuzhiyun "lid down",
80*4882a593Smuzhiyun "internal battery currently charging",
81*4882a593Smuzhiyun "external battery currently charging",
82*4882a593Smuzhiyun "internal battery currently discharging",
83*4882a593Smuzhiyun "external battery currently discharging",
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /* Everything required for one transaction with the uctrl */
87*4882a593Smuzhiyun struct uctrl_txn {
88*4882a593Smuzhiyun u8 opcode;
89*4882a593Smuzhiyun u8 inbits;
90*4882a593Smuzhiyun u8 outbits;
91*4882a593Smuzhiyun u8 *inbuf;
92*4882a593Smuzhiyun u8 *outbuf;
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun struct uctrl_status {
96*4882a593Smuzhiyun u8 current_temp; /* 0x07 */
97*4882a593Smuzhiyun u8 reset_status; /* 0x0b */
98*4882a593Smuzhiyun u16 event_status; /* 0x0c */
99*4882a593Smuzhiyun u16 error_status; /* 0x10 */
100*4882a593Smuzhiyun u16 external_status; /* 0x11, 0x1b */
101*4882a593Smuzhiyun u8 internal_charge; /* 0x18 */
102*4882a593Smuzhiyun u8 external_charge; /* 0x19 */
103*4882a593Smuzhiyun u16 control_lcd; /* 0x20 */
104*4882a593Smuzhiyun u8 control_bitport; /* 0x21 */
105*4882a593Smuzhiyun u8 speaker_volume; /* 0x23 */
106*4882a593Smuzhiyun u8 control_tft_brightness; /* 0x24 */
107*4882a593Smuzhiyun u8 control_kbd_repeat_delay; /* 0x28 */
108*4882a593Smuzhiyun u8 control_kbd_repeat_period; /* 0x29 */
109*4882a593Smuzhiyun u8 control_screen_contrast; /* 0x2F */
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun enum uctrl_opcode {
113*4882a593Smuzhiyun READ_SERIAL_NUMBER=0x1,
114*4882a593Smuzhiyun READ_ETHERNET_ADDRESS=0x2,
115*4882a593Smuzhiyun READ_HARDWARE_VERSION=0x3,
116*4882a593Smuzhiyun READ_MICROCONTROLLER_VERSION=0x4,
117*4882a593Smuzhiyun READ_MAX_TEMPERATURE=0x5,
118*4882a593Smuzhiyun READ_MIN_TEMPERATURE=0x6,
119*4882a593Smuzhiyun READ_CURRENT_TEMPERATURE=0x7,
120*4882a593Smuzhiyun READ_SYSTEM_VARIANT=0x8,
121*4882a593Smuzhiyun READ_POWERON_CYCLES=0x9,
122*4882a593Smuzhiyun READ_POWERON_SECONDS=0xA,
123*4882a593Smuzhiyun READ_RESET_STATUS=0xB,
124*4882a593Smuzhiyun READ_EVENT_STATUS=0xC,
125*4882a593Smuzhiyun READ_REAL_TIME_CLOCK=0xD,
126*4882a593Smuzhiyun READ_EXTERNAL_VGA_PORT=0xE,
127*4882a593Smuzhiyun READ_MICROCONTROLLER_ROM_CHECKSUM=0xF,
128*4882a593Smuzhiyun READ_ERROR_STATUS=0x10,
129*4882a593Smuzhiyun READ_EXTERNAL_STATUS=0x11,
130*4882a593Smuzhiyun READ_USER_CONFIGURATION_AREA=0x12,
131*4882a593Smuzhiyun READ_MICROCONTROLLER_VOLTAGE=0x13,
132*4882a593Smuzhiyun READ_INTERNAL_BATTERY_VOLTAGE=0x14,
133*4882a593Smuzhiyun READ_DCIN_VOLTAGE=0x15,
134*4882a593Smuzhiyun READ_HORIZONTAL_POINTER_VOLTAGE=0x16,
135*4882a593Smuzhiyun READ_VERTICAL_POINTER_VOLTAGE=0x17,
136*4882a593Smuzhiyun READ_INTERNAL_BATTERY_CHARGE_LEVEL=0x18,
137*4882a593Smuzhiyun READ_EXTERNAL_BATTERY_CHARGE_LEVEL=0x19,
138*4882a593Smuzhiyun READ_REAL_TIME_CLOCK_ALARM=0x1A,
139*4882a593Smuzhiyun READ_EVENT_STATUS_NO_RESET=0x1B,
140*4882a593Smuzhiyun READ_INTERNAL_KEYBOARD_LAYOUT=0x1C,
141*4882a593Smuzhiyun READ_EXTERNAL_KEYBOARD_LAYOUT=0x1D,
142*4882a593Smuzhiyun READ_EEPROM_STATUS=0x1E,
143*4882a593Smuzhiyun CONTROL_LCD=0x20,
144*4882a593Smuzhiyun CONTROL_BITPORT=0x21,
145*4882a593Smuzhiyun SPEAKER_VOLUME=0x23,
146*4882a593Smuzhiyun CONTROL_TFT_BRIGHTNESS=0x24,
147*4882a593Smuzhiyun CONTROL_WATCHDOG=0x25,
148*4882a593Smuzhiyun CONTROL_FACTORY_EEPROM_AREA=0x26,
149*4882a593Smuzhiyun CONTROL_KBD_TIME_UNTIL_REPEAT=0x28,
150*4882a593Smuzhiyun CONTROL_KBD_TIME_BETWEEN_REPEATS=0x29,
151*4882a593Smuzhiyun CONTROL_TIMEZONE=0x2A,
152*4882a593Smuzhiyun CONTROL_MARK_SPACE_RATIO=0x2B,
153*4882a593Smuzhiyun CONTROL_DIAGNOSTIC_MODE=0x2E,
154*4882a593Smuzhiyun CONTROL_SCREEN_CONTRAST=0x2F,
155*4882a593Smuzhiyun RING_BELL=0x30,
156*4882a593Smuzhiyun SET_DIAGNOSTIC_STATUS=0x32,
157*4882a593Smuzhiyun CLEAR_KEY_COMBINATION_TABLE=0x33,
158*4882a593Smuzhiyun PERFORM_SOFTWARE_RESET=0x34,
159*4882a593Smuzhiyun SET_REAL_TIME_CLOCK=0x35,
160*4882a593Smuzhiyun RECALIBRATE_POINTING_STICK=0x36,
161*4882a593Smuzhiyun SET_BELL_FREQUENCY=0x37,
162*4882a593Smuzhiyun SET_INTERNAL_BATTERY_CHARGE_RATE=0x39,
163*4882a593Smuzhiyun SET_EXTERNAL_BATTERY_CHARGE_RATE=0x3A,
164*4882a593Smuzhiyun SET_REAL_TIME_CLOCK_ALARM=0x3B,
165*4882a593Smuzhiyun READ_EEPROM=0x40,
166*4882a593Smuzhiyun WRITE_EEPROM=0x41,
167*4882a593Smuzhiyun WRITE_TO_STATUS_DISPLAY=0x42,
168*4882a593Smuzhiyun DEFINE_SPECIAL_CHARACTER=0x43,
169*4882a593Smuzhiyun DEFINE_KEY_COMBINATION_ENTRY=0x50,
170*4882a593Smuzhiyun DEFINE_STRING_TABLE_ENTRY=0x51,
171*4882a593Smuzhiyun DEFINE_STATUS_SCREEN_DISPLAY=0x52,
172*4882a593Smuzhiyun PERFORM_EMU_COMMANDS=0x64,
173*4882a593Smuzhiyun READ_EMU_REGISTER=0x65,
174*4882a593Smuzhiyun WRITE_EMU_REGISTER=0x66,
175*4882a593Smuzhiyun READ_EMU_RAM=0x67,
176*4882a593Smuzhiyun WRITE_EMU_RAM=0x68,
177*4882a593Smuzhiyun READ_BQ_REGISTER=0x69,
178*4882a593Smuzhiyun WRITE_BQ_REGISTER=0x6A,
179*4882a593Smuzhiyun SET_USER_PASSWORD=0x70,
180*4882a593Smuzhiyun VERIFY_USER_PASSWORD=0x71,
181*4882a593Smuzhiyun GET_SYSTEM_PASSWORD_KEY=0x72,
182*4882a593Smuzhiyun VERIFY_SYSTEM_PASSWORD=0x73,
183*4882a593Smuzhiyun POWER_OFF=0x82,
184*4882a593Smuzhiyun POWER_RESTART=0x83,
185*4882a593Smuzhiyun };
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun static struct uctrl_driver {
188*4882a593Smuzhiyun struct uctrl_regs __iomem *regs;
189*4882a593Smuzhiyun int irq;
190*4882a593Smuzhiyun int pending;
191*4882a593Smuzhiyun struct uctrl_status status;
192*4882a593Smuzhiyun } *global_driver;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun static void uctrl_get_event_status(struct uctrl_driver *);
195*4882a593Smuzhiyun static void uctrl_get_external_status(struct uctrl_driver *);
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun static long
uctrl_ioctl(struct file * file,unsigned int cmd,unsigned long arg)198*4882a593Smuzhiyun uctrl_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun switch (cmd) {
201*4882a593Smuzhiyun default:
202*4882a593Smuzhiyun return -EINVAL;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun return 0;
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun static int
uctrl_open(struct inode * inode,struct file * file)208*4882a593Smuzhiyun uctrl_open(struct inode *inode, struct file *file)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun mutex_lock(&uctrl_mutex);
211*4882a593Smuzhiyun uctrl_get_event_status(global_driver);
212*4882a593Smuzhiyun uctrl_get_external_status(global_driver);
213*4882a593Smuzhiyun mutex_unlock(&uctrl_mutex);
214*4882a593Smuzhiyun return 0;
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
uctrl_interrupt(int irq,void * dev_id)217*4882a593Smuzhiyun static irqreturn_t uctrl_interrupt(int irq, void *dev_id)
218*4882a593Smuzhiyun {
219*4882a593Smuzhiyun return IRQ_HANDLED;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun static const struct file_operations uctrl_fops = {
223*4882a593Smuzhiyun .owner = THIS_MODULE,
224*4882a593Smuzhiyun .llseek = no_llseek,
225*4882a593Smuzhiyun .unlocked_ioctl = uctrl_ioctl,
226*4882a593Smuzhiyun .open = uctrl_open,
227*4882a593Smuzhiyun };
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun static struct miscdevice uctrl_dev = {
230*4882a593Smuzhiyun UCTRL_MINOR,
231*4882a593Smuzhiyun "uctrl",
232*4882a593Smuzhiyun &uctrl_fops
233*4882a593Smuzhiyun };
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun /* Wait for space to write, then write to it */
236*4882a593Smuzhiyun #define WRITEUCTLDATA(value) \
237*4882a593Smuzhiyun { \
238*4882a593Smuzhiyun unsigned int i; \
239*4882a593Smuzhiyun for (i = 0; i < 10000; i++) { \
240*4882a593Smuzhiyun if (UCTRL_STAT_TXNF_STA & sbus_readl(&driver->regs->uctrl_stat)) \
241*4882a593Smuzhiyun break; \
242*4882a593Smuzhiyun } \
243*4882a593Smuzhiyun dprintk(("write data 0x%02x\n", value)); \
244*4882a593Smuzhiyun sbus_writel(value, &driver->regs->uctrl_data); \
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun /* Wait for something to read, read it, then clear the bit */
248*4882a593Smuzhiyun #define READUCTLDATA(value) \
249*4882a593Smuzhiyun { \
250*4882a593Smuzhiyun unsigned int i; \
251*4882a593Smuzhiyun value = 0; \
252*4882a593Smuzhiyun for (i = 0; i < 10000; i++) { \
253*4882a593Smuzhiyun if ((UCTRL_STAT_RXNE_STA & sbus_readl(&driver->regs->uctrl_stat)) == 0) \
254*4882a593Smuzhiyun break; \
255*4882a593Smuzhiyun udelay(1); \
256*4882a593Smuzhiyun } \
257*4882a593Smuzhiyun value = sbus_readl(&driver->regs->uctrl_data); \
258*4882a593Smuzhiyun dprintk(("read data 0x%02x\n", value)); \
259*4882a593Smuzhiyun sbus_writel(UCTRL_STAT_RXNE_STA, &driver->regs->uctrl_stat); \
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
uctrl_do_txn(struct uctrl_driver * driver,struct uctrl_txn * txn)262*4882a593Smuzhiyun static void uctrl_do_txn(struct uctrl_driver *driver, struct uctrl_txn *txn)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun int stat, incnt, outcnt, bytecnt, intr;
265*4882a593Smuzhiyun u32 byte;
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun stat = sbus_readl(&driver->regs->uctrl_stat);
268*4882a593Smuzhiyun intr = sbus_readl(&driver->regs->uctrl_intr);
269*4882a593Smuzhiyun sbus_writel(stat, &driver->regs->uctrl_stat);
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun dprintk(("interrupt stat 0x%x int 0x%x\n", stat, intr));
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun incnt = txn->inbits;
274*4882a593Smuzhiyun outcnt = txn->outbits;
275*4882a593Smuzhiyun byte = (txn->opcode << 8);
276*4882a593Smuzhiyun WRITEUCTLDATA(byte);
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun bytecnt = 0;
279*4882a593Smuzhiyun while (incnt > 0) {
280*4882a593Smuzhiyun byte = (txn->inbuf[bytecnt] << 8);
281*4882a593Smuzhiyun WRITEUCTLDATA(byte);
282*4882a593Smuzhiyun incnt--;
283*4882a593Smuzhiyun bytecnt++;
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun /* Get the ack */
287*4882a593Smuzhiyun READUCTLDATA(byte);
288*4882a593Smuzhiyun dprintk(("ack was %x\n", (byte >> 8)));
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun bytecnt = 0;
291*4882a593Smuzhiyun while (outcnt > 0) {
292*4882a593Smuzhiyun READUCTLDATA(byte);
293*4882a593Smuzhiyun txn->outbuf[bytecnt] = (byte >> 8);
294*4882a593Smuzhiyun dprintk(("set byte to %02x\n", byte));
295*4882a593Smuzhiyun outcnt--;
296*4882a593Smuzhiyun bytecnt++;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
uctrl_get_event_status(struct uctrl_driver * driver)300*4882a593Smuzhiyun static void uctrl_get_event_status(struct uctrl_driver *driver)
301*4882a593Smuzhiyun {
302*4882a593Smuzhiyun struct uctrl_txn txn;
303*4882a593Smuzhiyun u8 outbits[2];
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun txn.opcode = READ_EVENT_STATUS;
306*4882a593Smuzhiyun txn.inbits = 0;
307*4882a593Smuzhiyun txn.outbits = 2;
308*4882a593Smuzhiyun txn.inbuf = NULL;
309*4882a593Smuzhiyun txn.outbuf = outbits;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun uctrl_do_txn(driver, &txn);
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun dprintk(("bytes %x %x\n", (outbits[0] & 0xff), (outbits[1] & 0xff)));
314*4882a593Smuzhiyun driver->status.event_status =
315*4882a593Smuzhiyun ((outbits[0] & 0xff) << 8) | (outbits[1] & 0xff);
316*4882a593Smuzhiyun dprintk(("ev is %x\n", driver->status.event_status));
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun
uctrl_get_external_status(struct uctrl_driver * driver)319*4882a593Smuzhiyun static void uctrl_get_external_status(struct uctrl_driver *driver)
320*4882a593Smuzhiyun {
321*4882a593Smuzhiyun struct uctrl_txn txn;
322*4882a593Smuzhiyun u8 outbits[2];
323*4882a593Smuzhiyun int i, v;
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun txn.opcode = READ_EXTERNAL_STATUS;
326*4882a593Smuzhiyun txn.inbits = 0;
327*4882a593Smuzhiyun txn.outbits = 2;
328*4882a593Smuzhiyun txn.inbuf = NULL;
329*4882a593Smuzhiyun txn.outbuf = outbits;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun uctrl_do_txn(driver, &txn);
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun dprintk(("bytes %x %x\n", (outbits[0] & 0xff), (outbits[1] & 0xff)));
334*4882a593Smuzhiyun driver->status.external_status =
335*4882a593Smuzhiyun ((outbits[0] * 256) + (outbits[1]));
336*4882a593Smuzhiyun dprintk(("ex is %x\n", driver->status.external_status));
337*4882a593Smuzhiyun v = driver->status.external_status;
338*4882a593Smuzhiyun for (i = 0; v != 0; i++, v >>= 1) {
339*4882a593Smuzhiyun if (v & 1) {
340*4882a593Smuzhiyun dprintk(("%s%s", " ", uctrl_extstatus[i]));
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun dprintk(("\n"));
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun
uctrl_probe(struct platform_device * op)347*4882a593Smuzhiyun static int uctrl_probe(struct platform_device *op)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun struct uctrl_driver *p;
350*4882a593Smuzhiyun int err = -ENOMEM;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun p = kzalloc(sizeof(*p), GFP_KERNEL);
353*4882a593Smuzhiyun if (!p) {
354*4882a593Smuzhiyun printk(KERN_ERR "uctrl: Unable to allocate device struct.\n");
355*4882a593Smuzhiyun goto out;
356*4882a593Smuzhiyun }
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun p->regs = of_ioremap(&op->resource[0], 0,
359*4882a593Smuzhiyun resource_size(&op->resource[0]),
360*4882a593Smuzhiyun "uctrl");
361*4882a593Smuzhiyun if (!p->regs) {
362*4882a593Smuzhiyun printk(KERN_ERR "uctrl: Unable to map registers.\n");
363*4882a593Smuzhiyun goto out_free;
364*4882a593Smuzhiyun }
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun p->irq = op->archdata.irqs[0];
367*4882a593Smuzhiyun err = request_irq(p->irq, uctrl_interrupt, 0, "uctrl", p);
368*4882a593Smuzhiyun if (err) {
369*4882a593Smuzhiyun printk(KERN_ERR "uctrl: Unable to register irq.\n");
370*4882a593Smuzhiyun goto out_iounmap;
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun err = misc_register(&uctrl_dev);
374*4882a593Smuzhiyun if (err) {
375*4882a593Smuzhiyun printk(KERN_ERR "uctrl: Unable to register misc device.\n");
376*4882a593Smuzhiyun goto out_free_irq;
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun sbus_writel(UCTRL_INTR_RXNE_REQ|UCTRL_INTR_RXNE_MSK, &p->regs->uctrl_intr);
380*4882a593Smuzhiyun printk(KERN_INFO "%pOF: uctrl regs[0x%p] (irq %d)\n",
381*4882a593Smuzhiyun op->dev.of_node, p->regs, p->irq);
382*4882a593Smuzhiyun uctrl_get_event_status(p);
383*4882a593Smuzhiyun uctrl_get_external_status(p);
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun dev_set_drvdata(&op->dev, p);
386*4882a593Smuzhiyun global_driver = p;
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun out:
389*4882a593Smuzhiyun return err;
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun out_free_irq:
392*4882a593Smuzhiyun free_irq(p->irq, p);
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun out_iounmap:
395*4882a593Smuzhiyun of_iounmap(&op->resource[0], p->regs, resource_size(&op->resource[0]));
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun out_free:
398*4882a593Smuzhiyun kfree(p);
399*4882a593Smuzhiyun goto out;
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun
uctrl_remove(struct platform_device * op)402*4882a593Smuzhiyun static int uctrl_remove(struct platform_device *op)
403*4882a593Smuzhiyun {
404*4882a593Smuzhiyun struct uctrl_driver *p = dev_get_drvdata(&op->dev);
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun if (p) {
407*4882a593Smuzhiyun misc_deregister(&uctrl_dev);
408*4882a593Smuzhiyun free_irq(p->irq, p);
409*4882a593Smuzhiyun of_iounmap(&op->resource[0], p->regs, resource_size(&op->resource[0]));
410*4882a593Smuzhiyun kfree(p);
411*4882a593Smuzhiyun }
412*4882a593Smuzhiyun return 0;
413*4882a593Smuzhiyun }
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun static const struct of_device_id uctrl_match[] = {
416*4882a593Smuzhiyun {
417*4882a593Smuzhiyun .name = "uctrl",
418*4882a593Smuzhiyun },
419*4882a593Smuzhiyun {},
420*4882a593Smuzhiyun };
421*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, uctrl_match);
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun static struct platform_driver uctrl_driver = {
424*4882a593Smuzhiyun .driver = {
425*4882a593Smuzhiyun .name = "uctrl",
426*4882a593Smuzhiyun .of_match_table = uctrl_match,
427*4882a593Smuzhiyun },
428*4882a593Smuzhiyun .probe = uctrl_probe,
429*4882a593Smuzhiyun .remove = uctrl_remove,
430*4882a593Smuzhiyun };
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun module_platform_driver(uctrl_driver);
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun MODULE_LICENSE("GPL");
436