1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright IBM Corp. 2001, 2007 4*4882a593Smuzhiyun * Authors: Fritz Elfert (felfert@millenux.com) 5*4882a593Smuzhiyun * Peter Tiedemann (ptiedem@de.ibm.com) 6*4882a593Smuzhiyun * MPC additions : 7*4882a593Smuzhiyun * Belinda Thompson (belindat@us.ibm.com) 8*4882a593Smuzhiyun * Andy Richter (richtera@us.ibm.com) 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #ifndef _CTCM_FSMS_H_ 11*4882a593Smuzhiyun #define _CTCM_FSMS_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/module.h> 14*4882a593Smuzhiyun #include <linux/init.h> 15*4882a593Smuzhiyun #include <linux/kernel.h> 16*4882a593Smuzhiyun #include <linux/slab.h> 17*4882a593Smuzhiyun #include <linux/errno.h> 18*4882a593Smuzhiyun #include <linux/types.h> 19*4882a593Smuzhiyun #include <linux/interrupt.h> 20*4882a593Smuzhiyun #include <linux/timer.h> 21*4882a593Smuzhiyun #include <linux/bitops.h> 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #include <linux/signal.h> 24*4882a593Smuzhiyun #include <linux/string.h> 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #include <linux/ip.h> 27*4882a593Smuzhiyun #include <linux/if_arp.h> 28*4882a593Smuzhiyun #include <linux/tcp.h> 29*4882a593Smuzhiyun #include <linux/skbuff.h> 30*4882a593Smuzhiyun #include <linux/ctype.h> 31*4882a593Smuzhiyun #include <net/dst.h> 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #include <linux/io.h> 34*4882a593Smuzhiyun #include <asm/ccwdev.h> 35*4882a593Smuzhiyun #include <asm/ccwgroup.h> 36*4882a593Smuzhiyun #include <linux/uaccess.h> 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #include <asm/idals.h> 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #include "fsm.h" 41*4882a593Smuzhiyun #include "ctcm_main.h" 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* 44*4882a593Smuzhiyun * Definitions for the channel statemachine(s) for ctc and ctcmpc 45*4882a593Smuzhiyun * 46*4882a593Smuzhiyun * To allow better kerntyping, prefix-less definitions for channel states 47*4882a593Smuzhiyun * and channel events have been replaced : 48*4882a593Smuzhiyun * ch_event... -> ctc_ch_event... 49*4882a593Smuzhiyun * CH_EVENT... -> CTC_EVENT... 50*4882a593Smuzhiyun * ch_state... -> ctc_ch_state... 51*4882a593Smuzhiyun * CH_STATE... -> CTC_STATE... 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun /* 54*4882a593Smuzhiyun * Events of the channel statemachine(s) for ctc and ctcmpc 55*4882a593Smuzhiyun */ 56*4882a593Smuzhiyun enum ctc_ch_events { 57*4882a593Smuzhiyun /* 58*4882a593Smuzhiyun * Events, representing return code of 59*4882a593Smuzhiyun * I/O operations (ccw_device_start, ccw_device_halt et al.) 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun CTC_EVENT_IO_SUCCESS, 62*4882a593Smuzhiyun CTC_EVENT_IO_EBUSY, 63*4882a593Smuzhiyun CTC_EVENT_IO_ENODEV, 64*4882a593Smuzhiyun CTC_EVENT_IO_UNKNOWN, 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun CTC_EVENT_ATTNBUSY, 67*4882a593Smuzhiyun CTC_EVENT_ATTN, 68*4882a593Smuzhiyun CTC_EVENT_BUSY, 69*4882a593Smuzhiyun /* 70*4882a593Smuzhiyun * Events, representing unit-check 71*4882a593Smuzhiyun */ 72*4882a593Smuzhiyun CTC_EVENT_UC_RCRESET, 73*4882a593Smuzhiyun CTC_EVENT_UC_RSRESET, 74*4882a593Smuzhiyun CTC_EVENT_UC_TXTIMEOUT, 75*4882a593Smuzhiyun CTC_EVENT_UC_TXPARITY, 76*4882a593Smuzhiyun CTC_EVENT_UC_HWFAIL, 77*4882a593Smuzhiyun CTC_EVENT_UC_RXPARITY, 78*4882a593Smuzhiyun CTC_EVENT_UC_ZERO, 79*4882a593Smuzhiyun CTC_EVENT_UC_UNKNOWN, 80*4882a593Smuzhiyun /* 81*4882a593Smuzhiyun * Events, representing subchannel-check 82*4882a593Smuzhiyun */ 83*4882a593Smuzhiyun CTC_EVENT_SC_UNKNOWN, 84*4882a593Smuzhiyun /* 85*4882a593Smuzhiyun * Events, representing machine checks 86*4882a593Smuzhiyun */ 87*4882a593Smuzhiyun CTC_EVENT_MC_FAIL, 88*4882a593Smuzhiyun CTC_EVENT_MC_GOOD, 89*4882a593Smuzhiyun /* 90*4882a593Smuzhiyun * Event, representing normal IRQ 91*4882a593Smuzhiyun */ 92*4882a593Smuzhiyun CTC_EVENT_IRQ, 93*4882a593Smuzhiyun CTC_EVENT_FINSTAT, 94*4882a593Smuzhiyun /* 95*4882a593Smuzhiyun * Event, representing timer expiry. 96*4882a593Smuzhiyun */ 97*4882a593Smuzhiyun CTC_EVENT_TIMER, 98*4882a593Smuzhiyun /* 99*4882a593Smuzhiyun * Events, representing commands from upper levels. 100*4882a593Smuzhiyun */ 101*4882a593Smuzhiyun CTC_EVENT_START, 102*4882a593Smuzhiyun CTC_EVENT_STOP, 103*4882a593Smuzhiyun CTC_NR_EVENTS, 104*4882a593Smuzhiyun /* 105*4882a593Smuzhiyun * additional MPC events 106*4882a593Smuzhiyun */ 107*4882a593Smuzhiyun CTC_EVENT_SEND_XID = CTC_NR_EVENTS, 108*4882a593Smuzhiyun CTC_EVENT_RSWEEP_TIMER, 109*4882a593Smuzhiyun /* 110*4882a593Smuzhiyun * MUST be always the last element!! 111*4882a593Smuzhiyun */ 112*4882a593Smuzhiyun CTC_MPC_NR_EVENTS, 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* 116*4882a593Smuzhiyun * States of the channel statemachine(s) for ctc and ctcmpc. 117*4882a593Smuzhiyun */ 118*4882a593Smuzhiyun enum ctc_ch_states { 119*4882a593Smuzhiyun /* 120*4882a593Smuzhiyun * Channel not assigned to any device, 121*4882a593Smuzhiyun * initial state, direction invalid 122*4882a593Smuzhiyun */ 123*4882a593Smuzhiyun CTC_STATE_IDLE, 124*4882a593Smuzhiyun /* 125*4882a593Smuzhiyun * Channel assigned but not operating 126*4882a593Smuzhiyun */ 127*4882a593Smuzhiyun CTC_STATE_STOPPED, 128*4882a593Smuzhiyun CTC_STATE_STARTWAIT, 129*4882a593Smuzhiyun CTC_STATE_STARTRETRY, 130*4882a593Smuzhiyun CTC_STATE_SETUPWAIT, 131*4882a593Smuzhiyun CTC_STATE_RXINIT, 132*4882a593Smuzhiyun CTC_STATE_TXINIT, 133*4882a593Smuzhiyun CTC_STATE_RX, 134*4882a593Smuzhiyun CTC_STATE_TX, 135*4882a593Smuzhiyun CTC_STATE_RXIDLE, 136*4882a593Smuzhiyun CTC_STATE_TXIDLE, 137*4882a593Smuzhiyun CTC_STATE_RXERR, 138*4882a593Smuzhiyun CTC_STATE_TXERR, 139*4882a593Smuzhiyun CTC_STATE_TERM, 140*4882a593Smuzhiyun CTC_STATE_DTERM, 141*4882a593Smuzhiyun CTC_STATE_NOTOP, 142*4882a593Smuzhiyun CTC_NR_STATES, /* MUST be the last element of non-expanded states */ 143*4882a593Smuzhiyun /* 144*4882a593Smuzhiyun * additional MPC states 145*4882a593Smuzhiyun */ 146*4882a593Smuzhiyun CH_XID0_PENDING = CTC_NR_STATES, 147*4882a593Smuzhiyun CH_XID0_INPROGRESS, 148*4882a593Smuzhiyun CH_XID7_PENDING, 149*4882a593Smuzhiyun CH_XID7_PENDING1, 150*4882a593Smuzhiyun CH_XID7_PENDING2, 151*4882a593Smuzhiyun CH_XID7_PENDING3, 152*4882a593Smuzhiyun CH_XID7_PENDING4, 153*4882a593Smuzhiyun CTC_MPC_NR_STATES, /* MUST be the last element of expanded mpc states */ 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun extern const char *ctc_ch_event_names[]; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun extern const char *ctc_ch_state_names[]; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun void ctcm_ccw_check_rc(struct channel *ch, int rc, char *msg); 161*4882a593Smuzhiyun void ctcm_purge_skb_queue(struct sk_buff_head *q); 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun /* 164*4882a593Smuzhiyun * ----- non-static actions for ctcm channel statemachine ----- 165*4882a593Smuzhiyun * 166*4882a593Smuzhiyun */ 167*4882a593Smuzhiyun void ctcm_chx_txidle(fsm_instance *fi, int event, void *arg); 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun /* 170*4882a593Smuzhiyun * ----- FSM (state/event/action) of the ctcm channel statemachine ----- 171*4882a593Smuzhiyun */ 172*4882a593Smuzhiyun extern const fsm_node ch_fsm[]; 173*4882a593Smuzhiyun extern int ch_fsm_len; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* 177*4882a593Smuzhiyun * ----- non-static actions for ctcmpc channel statemachine ---- 178*4882a593Smuzhiyun * 179*4882a593Smuzhiyun */ 180*4882a593Smuzhiyun /* shared : 181*4882a593Smuzhiyun void ctcm_chx_txidle(fsm_instance * fi, int event, void *arg); 182*4882a593Smuzhiyun */ 183*4882a593Smuzhiyun void ctcmpc_chx_rxidle(fsm_instance *fi, int event, void *arg); 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun /* 186*4882a593Smuzhiyun * ----- FSM (state/event/action) of the ctcmpc channel statemachine ----- 187*4882a593Smuzhiyun */ 188*4882a593Smuzhiyun extern const fsm_node ctcmpc_ch_fsm[]; 189*4882a593Smuzhiyun extern int mpc_ch_fsm_len; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun /* 192*4882a593Smuzhiyun * Definitions for the device interface statemachine for ctc and mpc 193*4882a593Smuzhiyun */ 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun /* 196*4882a593Smuzhiyun * States of the device interface statemachine. 197*4882a593Smuzhiyun */ 198*4882a593Smuzhiyun enum dev_states { 199*4882a593Smuzhiyun DEV_STATE_STOPPED, 200*4882a593Smuzhiyun DEV_STATE_STARTWAIT_RXTX, 201*4882a593Smuzhiyun DEV_STATE_STARTWAIT_RX, 202*4882a593Smuzhiyun DEV_STATE_STARTWAIT_TX, 203*4882a593Smuzhiyun DEV_STATE_STOPWAIT_RXTX, 204*4882a593Smuzhiyun DEV_STATE_STOPWAIT_RX, 205*4882a593Smuzhiyun DEV_STATE_STOPWAIT_TX, 206*4882a593Smuzhiyun DEV_STATE_RUNNING, 207*4882a593Smuzhiyun /* 208*4882a593Smuzhiyun * MUST be always the last element!! 209*4882a593Smuzhiyun */ 210*4882a593Smuzhiyun CTCM_NR_DEV_STATES 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun extern const char *dev_state_names[]; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun /* 216*4882a593Smuzhiyun * Events of the device interface statemachine. 217*4882a593Smuzhiyun * ctcm and ctcmpc 218*4882a593Smuzhiyun */ 219*4882a593Smuzhiyun enum dev_events { 220*4882a593Smuzhiyun DEV_EVENT_START, 221*4882a593Smuzhiyun DEV_EVENT_STOP, 222*4882a593Smuzhiyun DEV_EVENT_RXUP, 223*4882a593Smuzhiyun DEV_EVENT_TXUP, 224*4882a593Smuzhiyun DEV_EVENT_RXDOWN, 225*4882a593Smuzhiyun DEV_EVENT_TXDOWN, 226*4882a593Smuzhiyun DEV_EVENT_RESTART, 227*4882a593Smuzhiyun /* 228*4882a593Smuzhiyun * MUST be always the last element!! 229*4882a593Smuzhiyun */ 230*4882a593Smuzhiyun CTCM_NR_DEV_EVENTS 231*4882a593Smuzhiyun }; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun extern const char *dev_event_names[]; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun /* 236*4882a593Smuzhiyun * Actions for the device interface statemachine. 237*4882a593Smuzhiyun * ctc and ctcmpc 238*4882a593Smuzhiyun */ 239*4882a593Smuzhiyun /* 240*4882a593Smuzhiyun static void dev_action_start(fsm_instance * fi, int event, void *arg); 241*4882a593Smuzhiyun static void dev_action_stop(fsm_instance * fi, int event, void *arg); 242*4882a593Smuzhiyun static void dev_action_restart(fsm_instance *fi, int event, void *arg); 243*4882a593Smuzhiyun static void dev_action_chup(fsm_instance * fi, int event, void *arg); 244*4882a593Smuzhiyun static void dev_action_chdown(fsm_instance * fi, int event, void *arg); 245*4882a593Smuzhiyun */ 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun /* 248*4882a593Smuzhiyun * The (state/event/action) fsm table of the device interface statemachine. 249*4882a593Smuzhiyun * ctcm and ctcmpc 250*4882a593Smuzhiyun */ 251*4882a593Smuzhiyun extern const fsm_node dev_fsm[]; 252*4882a593Smuzhiyun extern int dev_fsm_len; 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun /* 256*4882a593Smuzhiyun * Definitions for the MPC Group statemachine 257*4882a593Smuzhiyun */ 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun /* 260*4882a593Smuzhiyun * MPC Group Station FSM States 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun State Name When In This State 263*4882a593Smuzhiyun ====================== ======================================= 264*4882a593Smuzhiyun MPCG_STATE_RESET Initial State When Driver Loaded 265*4882a593Smuzhiyun We receive and send NOTHING 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun MPCG_STATE_INOP INOP Received. 268*4882a593Smuzhiyun Group level non-recoverable error 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun MPCG_STATE_READY XID exchanges for at least 1 write and 271*4882a593Smuzhiyun 1 read channel have completed. 272*4882a593Smuzhiyun Group is ready for data transfer. 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun States from ctc_mpc_alloc_channel 275*4882a593Smuzhiyun ============================================================== 276*4882a593Smuzhiyun MPCG_STATE_XID2INITW Awaiting XID2(0) Initiation 277*4882a593Smuzhiyun ATTN from other side will start 278*4882a593Smuzhiyun XID negotiations. 279*4882a593Smuzhiyun Y-side protocol only. 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun MPCG_STATE_XID2INITX XID2(0) negotiations are in progress. 282*4882a593Smuzhiyun At least 1, but not all, XID2(0)'s 283*4882a593Smuzhiyun have been received from partner. 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun MPCG_STATE_XID7INITW XID2(0) complete 286*4882a593Smuzhiyun No XID2(7)'s have yet been received. 287*4882a593Smuzhiyun XID2(7) negotiations pending. 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun MPCG_STATE_XID7INITX XID2(7) negotiations in progress. 290*4882a593Smuzhiyun At least 1, but not all, XID2(7)'s 291*4882a593Smuzhiyun have been received from partner. 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun MPCG_STATE_XID7INITF XID2(7) negotiations complete. 294*4882a593Smuzhiyun Transitioning to READY. 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun MPCG_STATE_READY Ready for Data Transfer. 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun States from ctc_mpc_establish_connectivity call 300*4882a593Smuzhiyun ============================================================== 301*4882a593Smuzhiyun MPCG_STATE_XID0IOWAIT Initiating XID2(0) negotiations. 302*4882a593Smuzhiyun X-side protocol only. 303*4882a593Smuzhiyun ATTN-BUSY from other side will convert 304*4882a593Smuzhiyun this to Y-side protocol and the 305*4882a593Smuzhiyun ctc_mpc_alloc_channel flow will begin. 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun MPCG_STATE_XID0IOWAIX XID2(0) negotiations are in progress. 308*4882a593Smuzhiyun At least 1, but not all, XID2(0)'s 309*4882a593Smuzhiyun have been received from partner. 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun MPCG_STATE_XID7INITI XID2(0) complete 312*4882a593Smuzhiyun No XID2(7)'s have yet been received. 313*4882a593Smuzhiyun XID2(7) negotiations pending. 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun MPCG_STATE_XID7INITZ XID2(7) negotiations in progress. 316*4882a593Smuzhiyun At least 1, but not all, XID2(7)'s 317*4882a593Smuzhiyun have been received from partner. 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun MPCG_STATE_XID7INITF XID2(7) negotiations complete. 320*4882a593Smuzhiyun Transitioning to READY. 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun MPCG_STATE_READY Ready for Data Transfer. 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun */ 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun enum mpcg_events { 327*4882a593Smuzhiyun MPCG_EVENT_INOP, 328*4882a593Smuzhiyun MPCG_EVENT_DISCONC, 329*4882a593Smuzhiyun MPCG_EVENT_XID0DO, 330*4882a593Smuzhiyun MPCG_EVENT_XID2, 331*4882a593Smuzhiyun MPCG_EVENT_XID2DONE, 332*4882a593Smuzhiyun MPCG_EVENT_XID7DONE, 333*4882a593Smuzhiyun MPCG_EVENT_TIMER, 334*4882a593Smuzhiyun MPCG_EVENT_DOIO, 335*4882a593Smuzhiyun MPCG_NR_EVENTS, 336*4882a593Smuzhiyun }; 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun enum mpcg_states { 339*4882a593Smuzhiyun MPCG_STATE_RESET, 340*4882a593Smuzhiyun MPCG_STATE_INOP, 341*4882a593Smuzhiyun MPCG_STATE_XID2INITW, 342*4882a593Smuzhiyun MPCG_STATE_XID2INITX, 343*4882a593Smuzhiyun MPCG_STATE_XID7INITW, 344*4882a593Smuzhiyun MPCG_STATE_XID7INITX, 345*4882a593Smuzhiyun MPCG_STATE_XID0IOWAIT, 346*4882a593Smuzhiyun MPCG_STATE_XID0IOWAIX, 347*4882a593Smuzhiyun MPCG_STATE_XID7INITI, 348*4882a593Smuzhiyun MPCG_STATE_XID7INITZ, 349*4882a593Smuzhiyun MPCG_STATE_XID7INITF, 350*4882a593Smuzhiyun MPCG_STATE_FLOWC, 351*4882a593Smuzhiyun MPCG_STATE_READY, 352*4882a593Smuzhiyun MPCG_NR_STATES, 353*4882a593Smuzhiyun }; 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun #endif 356*4882a593Smuzhiyun /* --- This is the END my friend --- */ 357