1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Real Time Clock driver for Wolfson Microelectronics WM831x
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2009 Wolfson Microelectronics PLC.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/time.h>
14*4882a593Smuzhiyun #include <linux/rtc.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/bcd.h>
17*4882a593Smuzhiyun #include <linux/interrupt.h>
18*4882a593Smuzhiyun #include <linux/ioctl.h>
19*4882a593Smuzhiyun #include <linux/completion.h>
20*4882a593Smuzhiyun #include <linux/mfd/wm831x/core.h>
21*4882a593Smuzhiyun #include <linux/delay.h>
22*4882a593Smuzhiyun #include <linux/platform_device.h>
23*4882a593Smuzhiyun #include <linux/random.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /*
26*4882a593Smuzhiyun * R16416 (0x4020) - RTC Write Counter
27*4882a593Smuzhiyun */
28*4882a593Smuzhiyun #define WM831X_RTC_WR_CNT_MASK 0xFFFF /* RTC_WR_CNT - [15:0] */
29*4882a593Smuzhiyun #define WM831X_RTC_WR_CNT_SHIFT 0 /* RTC_WR_CNT - [15:0] */
30*4882a593Smuzhiyun #define WM831X_RTC_WR_CNT_WIDTH 16 /* RTC_WR_CNT - [15:0] */
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /*
33*4882a593Smuzhiyun * R16417 (0x4021) - RTC Time 1
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun #define WM831X_RTC_TIME_MASK 0xFFFF /* RTC_TIME - [15:0] */
36*4882a593Smuzhiyun #define WM831X_RTC_TIME_SHIFT 0 /* RTC_TIME - [15:0] */
37*4882a593Smuzhiyun #define WM831X_RTC_TIME_WIDTH 16 /* RTC_TIME - [15:0] */
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /*
40*4882a593Smuzhiyun * R16418 (0x4022) - RTC Time 2
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun #define WM831X_RTC_TIME_MASK 0xFFFF /* RTC_TIME - [15:0] */
43*4882a593Smuzhiyun #define WM831X_RTC_TIME_SHIFT 0 /* RTC_TIME - [15:0] */
44*4882a593Smuzhiyun #define WM831X_RTC_TIME_WIDTH 16 /* RTC_TIME - [15:0] */
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /*
47*4882a593Smuzhiyun * R16419 (0x4023) - RTC Alarm 1
48*4882a593Smuzhiyun */
49*4882a593Smuzhiyun #define WM831X_RTC_ALM_MASK 0xFFFF /* RTC_ALM - [15:0] */
50*4882a593Smuzhiyun #define WM831X_RTC_ALM_SHIFT 0 /* RTC_ALM - [15:0] */
51*4882a593Smuzhiyun #define WM831X_RTC_ALM_WIDTH 16 /* RTC_ALM - [15:0] */
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /*
54*4882a593Smuzhiyun * R16420 (0x4024) - RTC Alarm 2
55*4882a593Smuzhiyun */
56*4882a593Smuzhiyun #define WM831X_RTC_ALM_MASK 0xFFFF /* RTC_ALM - [15:0] */
57*4882a593Smuzhiyun #define WM831X_RTC_ALM_SHIFT 0 /* RTC_ALM - [15:0] */
58*4882a593Smuzhiyun #define WM831X_RTC_ALM_WIDTH 16 /* RTC_ALM - [15:0] */
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /*
61*4882a593Smuzhiyun * R16421 (0x4025) - RTC Control
62*4882a593Smuzhiyun */
63*4882a593Smuzhiyun #define WM831X_RTC_VALID 0x8000 /* RTC_VALID */
64*4882a593Smuzhiyun #define WM831X_RTC_VALID_MASK 0x8000 /* RTC_VALID */
65*4882a593Smuzhiyun #define WM831X_RTC_VALID_SHIFT 15 /* RTC_VALID */
66*4882a593Smuzhiyun #define WM831X_RTC_VALID_WIDTH 1 /* RTC_VALID */
67*4882a593Smuzhiyun #define WM831X_RTC_SYNC_BUSY 0x4000 /* RTC_SYNC_BUSY */
68*4882a593Smuzhiyun #define WM831X_RTC_SYNC_BUSY_MASK 0x4000 /* RTC_SYNC_BUSY */
69*4882a593Smuzhiyun #define WM831X_RTC_SYNC_BUSY_SHIFT 14 /* RTC_SYNC_BUSY */
70*4882a593Smuzhiyun #define WM831X_RTC_SYNC_BUSY_WIDTH 1 /* RTC_SYNC_BUSY */
71*4882a593Smuzhiyun #define WM831X_RTC_ALM_ENA 0x0400 /* RTC_ALM_ENA */
72*4882a593Smuzhiyun #define WM831X_RTC_ALM_ENA_MASK 0x0400 /* RTC_ALM_ENA */
73*4882a593Smuzhiyun #define WM831X_RTC_ALM_ENA_SHIFT 10 /* RTC_ALM_ENA */
74*4882a593Smuzhiyun #define WM831X_RTC_ALM_ENA_WIDTH 1 /* RTC_ALM_ENA */
75*4882a593Smuzhiyun #define WM831X_RTC_PINT_FREQ_MASK 0x0070 /* RTC_PINT_FREQ - [6:4] */
76*4882a593Smuzhiyun #define WM831X_RTC_PINT_FREQ_SHIFT 4 /* RTC_PINT_FREQ - [6:4] */
77*4882a593Smuzhiyun #define WM831X_RTC_PINT_FREQ_WIDTH 3 /* RTC_PINT_FREQ - [6:4] */
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /*
80*4882a593Smuzhiyun * R16422 (0x4026) - RTC Trim
81*4882a593Smuzhiyun */
82*4882a593Smuzhiyun #define WM831X_RTC_TRIM_MASK 0x03FF /* RTC_TRIM - [9:0] */
83*4882a593Smuzhiyun #define WM831X_RTC_TRIM_SHIFT 0 /* RTC_TRIM - [9:0] */
84*4882a593Smuzhiyun #define WM831X_RTC_TRIM_WIDTH 10 /* RTC_TRIM - [9:0] */
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun #define WM831X_SET_TIME_RETRIES 5
87*4882a593Smuzhiyun #define WM831X_GET_TIME_RETRIES 5
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun struct wm831x_rtc {
90*4882a593Smuzhiyun struct wm831x *wm831x;
91*4882a593Smuzhiyun struct rtc_device *rtc;
92*4882a593Smuzhiyun unsigned int alarm_enabled:1;
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun
wm831x_rtc_add_randomness(struct wm831x * wm831x)95*4882a593Smuzhiyun static void wm831x_rtc_add_randomness(struct wm831x *wm831x)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun int ret;
98*4882a593Smuzhiyun u16 reg;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /*
101*4882a593Smuzhiyun * The write counter contains a pseudo-random number which is
102*4882a593Smuzhiyun * regenerated every time we set the RTC so it should be a
103*4882a593Smuzhiyun * useful per-system source of entropy.
104*4882a593Smuzhiyun */
105*4882a593Smuzhiyun ret = wm831x_reg_read(wm831x, WM831X_RTC_WRITE_COUNTER);
106*4882a593Smuzhiyun if (ret >= 0) {
107*4882a593Smuzhiyun reg = ret;
108*4882a593Smuzhiyun add_device_randomness(®, sizeof(reg));
109*4882a593Smuzhiyun } else {
110*4882a593Smuzhiyun dev_warn(wm831x->dev, "Failed to read RTC write counter: %d\n",
111*4882a593Smuzhiyun ret);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /*
116*4882a593Smuzhiyun * Read current time and date in RTC
117*4882a593Smuzhiyun */
wm831x_rtc_readtime(struct device * dev,struct rtc_time * tm)118*4882a593Smuzhiyun static int wm831x_rtc_readtime(struct device *dev, struct rtc_time *tm)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
121*4882a593Smuzhiyun struct wm831x *wm831x = wm831x_rtc->wm831x;
122*4882a593Smuzhiyun u16 time1[2], time2[2];
123*4882a593Smuzhiyun int ret;
124*4882a593Smuzhiyun int count = 0;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun /* Has the RTC been programmed? */
127*4882a593Smuzhiyun ret = wm831x_reg_read(wm831x, WM831X_RTC_CONTROL);
128*4882a593Smuzhiyun if (ret < 0) {
129*4882a593Smuzhiyun dev_err(dev, "Failed to read RTC control: %d\n", ret);
130*4882a593Smuzhiyun return ret;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun if (!(ret & WM831X_RTC_VALID)) {
133*4882a593Smuzhiyun dev_dbg(dev, "RTC not yet configured\n");
134*4882a593Smuzhiyun return -EINVAL;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun /* Read twice to make sure we don't read a corrupt, partially
138*4882a593Smuzhiyun * incremented, value.
139*4882a593Smuzhiyun */
140*4882a593Smuzhiyun do {
141*4882a593Smuzhiyun ret = wm831x_bulk_read(wm831x, WM831X_RTC_TIME_1,
142*4882a593Smuzhiyun 2, time1);
143*4882a593Smuzhiyun if (ret != 0)
144*4882a593Smuzhiyun continue;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun ret = wm831x_bulk_read(wm831x, WM831X_RTC_TIME_1,
147*4882a593Smuzhiyun 2, time2);
148*4882a593Smuzhiyun if (ret != 0)
149*4882a593Smuzhiyun continue;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun if (memcmp(time1, time2, sizeof(time1)) == 0) {
152*4882a593Smuzhiyun u32 time = (time1[0] << 16) | time1[1];
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun rtc_time64_to_tm(time, tm);
155*4882a593Smuzhiyun return 0;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun } while (++count < WM831X_GET_TIME_RETRIES);
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun dev_err(dev, "Timed out reading current time\n");
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun return -EIO;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun /*
166*4882a593Smuzhiyun * Set current time and date in RTC
167*4882a593Smuzhiyun */
wm831x_rtc_settime(struct device * dev,struct rtc_time * tm)168*4882a593Smuzhiyun static int wm831x_rtc_settime(struct device *dev, struct rtc_time *tm)
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
171*4882a593Smuzhiyun struct wm831x *wm831x = wm831x_rtc->wm831x;
172*4882a593Smuzhiyun struct rtc_time new_tm;
173*4882a593Smuzhiyun unsigned long time, new_time;
174*4882a593Smuzhiyun int ret;
175*4882a593Smuzhiyun int count = 0;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun time = rtc_tm_to_time64(tm);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun ret = wm831x_reg_write(wm831x, WM831X_RTC_TIME_1,
180*4882a593Smuzhiyun (time >> 16) & 0xffff);
181*4882a593Smuzhiyun if (ret < 0) {
182*4882a593Smuzhiyun dev_err(dev, "Failed to write TIME_1: %d\n", ret);
183*4882a593Smuzhiyun return ret;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun ret = wm831x_reg_write(wm831x, WM831X_RTC_TIME_2, time & 0xffff);
187*4882a593Smuzhiyun if (ret < 0) {
188*4882a593Smuzhiyun dev_err(dev, "Failed to write TIME_2: %d\n", ret);
189*4882a593Smuzhiyun return ret;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun /* Wait for the update to complete - should happen first time
193*4882a593Smuzhiyun * round but be conservative.
194*4882a593Smuzhiyun */
195*4882a593Smuzhiyun do {
196*4882a593Smuzhiyun msleep(1);
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun ret = wm831x_reg_read(wm831x, WM831X_RTC_CONTROL);
199*4882a593Smuzhiyun if (ret < 0)
200*4882a593Smuzhiyun ret = WM831X_RTC_SYNC_BUSY;
201*4882a593Smuzhiyun } while (!(ret & WM831X_RTC_SYNC_BUSY) &&
202*4882a593Smuzhiyun ++count < WM831X_SET_TIME_RETRIES);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun if (ret & WM831X_RTC_SYNC_BUSY) {
205*4882a593Smuzhiyun dev_err(dev, "Timed out writing RTC update\n");
206*4882a593Smuzhiyun return -EIO;
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun /* Check that the update was accepted; security features may
210*4882a593Smuzhiyun * have caused the update to be ignored.
211*4882a593Smuzhiyun */
212*4882a593Smuzhiyun ret = wm831x_rtc_readtime(dev, &new_tm);
213*4882a593Smuzhiyun if (ret < 0)
214*4882a593Smuzhiyun return ret;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun new_time = rtc_tm_to_time64(&new_tm);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun /* Allow a second of change in case of tick */
219*4882a593Smuzhiyun if (new_time - time > 1) {
220*4882a593Smuzhiyun dev_err(dev, "RTC update not permitted by hardware\n");
221*4882a593Smuzhiyun return -EPERM;
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun return 0;
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun /*
228*4882a593Smuzhiyun * Read alarm time and date in RTC
229*4882a593Smuzhiyun */
wm831x_rtc_readalarm(struct device * dev,struct rtc_wkalrm * alrm)230*4882a593Smuzhiyun static int wm831x_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
231*4882a593Smuzhiyun {
232*4882a593Smuzhiyun struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
233*4882a593Smuzhiyun int ret;
234*4882a593Smuzhiyun u16 data[2];
235*4882a593Smuzhiyun u32 time;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun ret = wm831x_bulk_read(wm831x_rtc->wm831x, WM831X_RTC_ALARM_1,
238*4882a593Smuzhiyun 2, data);
239*4882a593Smuzhiyun if (ret != 0) {
240*4882a593Smuzhiyun dev_err(dev, "Failed to read alarm time: %d\n", ret);
241*4882a593Smuzhiyun return ret;
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun time = (data[0] << 16) | data[1];
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun rtc_time64_to_tm(time, &alrm->time);
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun ret = wm831x_reg_read(wm831x_rtc->wm831x, WM831X_RTC_CONTROL);
249*4882a593Smuzhiyun if (ret < 0) {
250*4882a593Smuzhiyun dev_err(dev, "Failed to read RTC control: %d\n", ret);
251*4882a593Smuzhiyun return ret;
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun if (ret & WM831X_RTC_ALM_ENA)
255*4882a593Smuzhiyun alrm->enabled = 1;
256*4882a593Smuzhiyun else
257*4882a593Smuzhiyun alrm->enabled = 0;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun return 0;
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
wm831x_rtc_stop_alarm(struct wm831x_rtc * wm831x_rtc)262*4882a593Smuzhiyun static int wm831x_rtc_stop_alarm(struct wm831x_rtc *wm831x_rtc)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun wm831x_rtc->alarm_enabled = 0;
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun return wm831x_set_bits(wm831x_rtc->wm831x, WM831X_RTC_CONTROL,
267*4882a593Smuzhiyun WM831X_RTC_ALM_ENA, 0);
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun
wm831x_rtc_start_alarm(struct wm831x_rtc * wm831x_rtc)270*4882a593Smuzhiyun static int wm831x_rtc_start_alarm(struct wm831x_rtc *wm831x_rtc)
271*4882a593Smuzhiyun {
272*4882a593Smuzhiyun wm831x_rtc->alarm_enabled = 1;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun return wm831x_set_bits(wm831x_rtc->wm831x, WM831X_RTC_CONTROL,
275*4882a593Smuzhiyun WM831X_RTC_ALM_ENA, WM831X_RTC_ALM_ENA);
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun
wm831x_rtc_setalarm(struct device * dev,struct rtc_wkalrm * alrm)278*4882a593Smuzhiyun static int wm831x_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
279*4882a593Smuzhiyun {
280*4882a593Smuzhiyun struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
281*4882a593Smuzhiyun struct wm831x *wm831x = wm831x_rtc->wm831x;
282*4882a593Smuzhiyun int ret;
283*4882a593Smuzhiyun unsigned long time;
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun time = rtc_tm_to_time64(&alrm->time);
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun ret = wm831x_rtc_stop_alarm(wm831x_rtc);
288*4882a593Smuzhiyun if (ret < 0) {
289*4882a593Smuzhiyun dev_err(dev, "Failed to stop alarm: %d\n", ret);
290*4882a593Smuzhiyun return ret;
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun ret = wm831x_reg_write(wm831x, WM831X_RTC_ALARM_1,
294*4882a593Smuzhiyun (time >> 16) & 0xffff);
295*4882a593Smuzhiyun if (ret < 0) {
296*4882a593Smuzhiyun dev_err(dev, "Failed to write ALARM_1: %d\n", ret);
297*4882a593Smuzhiyun return ret;
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun ret = wm831x_reg_write(wm831x, WM831X_RTC_ALARM_2, time & 0xffff);
301*4882a593Smuzhiyun if (ret < 0) {
302*4882a593Smuzhiyun dev_err(dev, "Failed to write ALARM_2: %d\n", ret);
303*4882a593Smuzhiyun return ret;
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun if (alrm->enabled) {
307*4882a593Smuzhiyun ret = wm831x_rtc_start_alarm(wm831x_rtc);
308*4882a593Smuzhiyun if (ret < 0) {
309*4882a593Smuzhiyun dev_err(dev, "Failed to start alarm: %d\n", ret);
310*4882a593Smuzhiyun return ret;
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun return 0;
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun
wm831x_rtc_alarm_irq_enable(struct device * dev,unsigned int enabled)317*4882a593Smuzhiyun static int wm831x_rtc_alarm_irq_enable(struct device *dev,
318*4882a593Smuzhiyun unsigned int enabled)
319*4882a593Smuzhiyun {
320*4882a593Smuzhiyun struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun if (enabled)
323*4882a593Smuzhiyun return wm831x_rtc_start_alarm(wm831x_rtc);
324*4882a593Smuzhiyun else
325*4882a593Smuzhiyun return wm831x_rtc_stop_alarm(wm831x_rtc);
326*4882a593Smuzhiyun }
327*4882a593Smuzhiyun
wm831x_alm_irq(int irq,void * data)328*4882a593Smuzhiyun static irqreturn_t wm831x_alm_irq(int irq, void *data)
329*4882a593Smuzhiyun {
330*4882a593Smuzhiyun struct wm831x_rtc *wm831x_rtc = data;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun rtc_update_irq(wm831x_rtc->rtc, 1, RTC_IRQF | RTC_AF);
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun return IRQ_HANDLED;
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun static const struct rtc_class_ops wm831x_rtc_ops = {
338*4882a593Smuzhiyun .read_time = wm831x_rtc_readtime,
339*4882a593Smuzhiyun .set_time = wm831x_rtc_settime,
340*4882a593Smuzhiyun .read_alarm = wm831x_rtc_readalarm,
341*4882a593Smuzhiyun .set_alarm = wm831x_rtc_setalarm,
342*4882a593Smuzhiyun .alarm_irq_enable = wm831x_rtc_alarm_irq_enable,
343*4882a593Smuzhiyun };
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun #ifdef CONFIG_PM
346*4882a593Smuzhiyun /* Turn off the alarm if it should not be a wake source. */
wm831x_rtc_suspend(struct device * dev)347*4882a593Smuzhiyun static int wm831x_rtc_suspend(struct device *dev)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
350*4882a593Smuzhiyun int ret, enable;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun if (wm831x_rtc->alarm_enabled && device_may_wakeup(dev))
353*4882a593Smuzhiyun enable = WM831X_RTC_ALM_ENA;
354*4882a593Smuzhiyun else
355*4882a593Smuzhiyun enable = 0;
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun ret = wm831x_set_bits(wm831x_rtc->wm831x, WM831X_RTC_CONTROL,
358*4882a593Smuzhiyun WM831X_RTC_ALM_ENA, enable);
359*4882a593Smuzhiyun if (ret != 0)
360*4882a593Smuzhiyun dev_err(dev, "Failed to update RTC alarm: %d\n", ret);
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun return 0;
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun /* Enable the alarm if it should be enabled (in case it was disabled to
366*4882a593Smuzhiyun * prevent use as a wake source).
367*4882a593Smuzhiyun */
wm831x_rtc_resume(struct device * dev)368*4882a593Smuzhiyun static int wm831x_rtc_resume(struct device *dev)
369*4882a593Smuzhiyun {
370*4882a593Smuzhiyun struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
371*4882a593Smuzhiyun int ret;
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun if (wm831x_rtc->alarm_enabled) {
374*4882a593Smuzhiyun ret = wm831x_rtc_start_alarm(wm831x_rtc);
375*4882a593Smuzhiyun if (ret != 0)
376*4882a593Smuzhiyun dev_err(dev, "Failed to restart RTC alarm: %d\n", ret);
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun return 0;
380*4882a593Smuzhiyun }
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun /* Unconditionally disable the alarm */
wm831x_rtc_freeze(struct device * dev)383*4882a593Smuzhiyun static int wm831x_rtc_freeze(struct device *dev)
384*4882a593Smuzhiyun {
385*4882a593Smuzhiyun struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
386*4882a593Smuzhiyun int ret;
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun ret = wm831x_set_bits(wm831x_rtc->wm831x, WM831X_RTC_CONTROL,
389*4882a593Smuzhiyun WM831X_RTC_ALM_ENA, 0);
390*4882a593Smuzhiyun if (ret != 0)
391*4882a593Smuzhiyun dev_err(dev, "Failed to stop RTC alarm: %d\n", ret);
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun return 0;
394*4882a593Smuzhiyun }
395*4882a593Smuzhiyun #else
396*4882a593Smuzhiyun #define wm831x_rtc_suspend NULL
397*4882a593Smuzhiyun #define wm831x_rtc_resume NULL
398*4882a593Smuzhiyun #define wm831x_rtc_freeze NULL
399*4882a593Smuzhiyun #endif
400*4882a593Smuzhiyun
wm831x_rtc_probe(struct platform_device * pdev)401*4882a593Smuzhiyun static int wm831x_rtc_probe(struct platform_device *pdev)
402*4882a593Smuzhiyun {
403*4882a593Smuzhiyun struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
404*4882a593Smuzhiyun struct wm831x_rtc *wm831x_rtc;
405*4882a593Smuzhiyun int alm_irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "ALM"));
406*4882a593Smuzhiyun int ret = 0;
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun wm831x_rtc = devm_kzalloc(&pdev->dev, sizeof(*wm831x_rtc), GFP_KERNEL);
409*4882a593Smuzhiyun if (wm831x_rtc == NULL)
410*4882a593Smuzhiyun return -ENOMEM;
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun platform_set_drvdata(pdev, wm831x_rtc);
413*4882a593Smuzhiyun wm831x_rtc->wm831x = wm831x;
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun ret = wm831x_reg_read(wm831x, WM831X_RTC_CONTROL);
416*4882a593Smuzhiyun if (ret < 0) {
417*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to read RTC control: %d\n", ret);
418*4882a593Smuzhiyun return ret;
419*4882a593Smuzhiyun }
420*4882a593Smuzhiyun if (ret & WM831X_RTC_ALM_ENA)
421*4882a593Smuzhiyun wm831x_rtc->alarm_enabled = 1;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun device_init_wakeup(&pdev->dev, 1);
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun wm831x_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
426*4882a593Smuzhiyun if (IS_ERR(wm831x_rtc->rtc))
427*4882a593Smuzhiyun return PTR_ERR(wm831x_rtc->rtc);
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun wm831x_rtc->rtc->ops = &wm831x_rtc_ops;
430*4882a593Smuzhiyun wm831x_rtc->rtc->range_max = U32_MAX;
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun ret = rtc_register_device(wm831x_rtc->rtc);
433*4882a593Smuzhiyun if (ret)
434*4882a593Smuzhiyun return ret;
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun ret = devm_request_threaded_irq(&pdev->dev, alm_irq, NULL,
437*4882a593Smuzhiyun wm831x_alm_irq,
438*4882a593Smuzhiyun IRQF_TRIGGER_RISING | IRQF_ONESHOT,
439*4882a593Smuzhiyun "RTC alarm",
440*4882a593Smuzhiyun wm831x_rtc);
441*4882a593Smuzhiyun if (ret != 0) {
442*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to request alarm IRQ %d: %d\n",
443*4882a593Smuzhiyun alm_irq, ret);
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun wm831x_rtc_add_randomness(wm831x);
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun return 0;
449*4882a593Smuzhiyun }
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun static const struct dev_pm_ops wm831x_rtc_pm_ops = {
452*4882a593Smuzhiyun .suspend = wm831x_rtc_suspend,
453*4882a593Smuzhiyun .resume = wm831x_rtc_resume,
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun .freeze = wm831x_rtc_freeze,
456*4882a593Smuzhiyun .thaw = wm831x_rtc_resume,
457*4882a593Smuzhiyun .restore = wm831x_rtc_resume,
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun .poweroff = wm831x_rtc_suspend,
460*4882a593Smuzhiyun };
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun static struct platform_driver wm831x_rtc_driver = {
463*4882a593Smuzhiyun .probe = wm831x_rtc_probe,
464*4882a593Smuzhiyun .driver = {
465*4882a593Smuzhiyun .name = "wm831x-rtc",
466*4882a593Smuzhiyun .pm = &wm831x_rtc_pm_ops,
467*4882a593Smuzhiyun },
468*4882a593Smuzhiyun };
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun module_platform_driver(wm831x_rtc_driver);
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
473*4882a593Smuzhiyun MODULE_DESCRIPTION("RTC driver for the WM831x series PMICs");
474*4882a593Smuzhiyun MODULE_LICENSE("GPL");
475*4882a593Smuzhiyun MODULE_ALIAS("platform:wm831x-rtc");
476