1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /* drivers/rtc/rtc-v3020.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2006 8D Technologies inc.
5*4882a593Smuzhiyun * Copyright (C) 2004 Compulab Ltd.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Driver for the V3020 RTC
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Changelog:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * 10-May-2006: Raphael Assenat <raph@8d.com>
12*4882a593Smuzhiyun * - Converted to platform driver
13*4882a593Smuzhiyun * - Use the generic rtc class
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * ??-???-2004: Someone at Compulab
16*4882a593Smuzhiyun * - Initial driver creation.
17*4882a593Smuzhiyun */
18*4882a593Smuzhiyun #include <linux/platform_device.h>
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun #include <linux/init.h>
21*4882a593Smuzhiyun #include <linux/rtc.h>
22*4882a593Smuzhiyun #include <linux/types.h>
23*4882a593Smuzhiyun #include <linux/bcd.h>
24*4882a593Smuzhiyun #include <linux/platform_data/rtc-v3020.h>
25*4882a593Smuzhiyun #include <linux/delay.h>
26*4882a593Smuzhiyun #include <linux/gpio.h>
27*4882a593Smuzhiyun #include <linux/slab.h>
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #include <linux/io.h>
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #undef DEBUG
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun struct v3020;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun struct v3020_chip_ops {
36*4882a593Smuzhiyun int (*map_io)(struct v3020 *chip, struct platform_device *pdev,
37*4882a593Smuzhiyun struct v3020_platform_data *pdata);
38*4882a593Smuzhiyun void (*unmap_io)(struct v3020 *chip);
39*4882a593Smuzhiyun unsigned char (*read_bit)(struct v3020 *chip);
40*4882a593Smuzhiyun void (*write_bit)(struct v3020 *chip, unsigned char bit);
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #define V3020_CS 0
44*4882a593Smuzhiyun #define V3020_WR 1
45*4882a593Smuzhiyun #define V3020_RD 2
46*4882a593Smuzhiyun #define V3020_IO 3
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun struct v3020 {
49*4882a593Smuzhiyun /* MMIO access */
50*4882a593Smuzhiyun void __iomem *ioaddress;
51*4882a593Smuzhiyun int leftshift;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* GPIO access */
54*4882a593Smuzhiyun struct gpio *gpio;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun const struct v3020_chip_ops *ops;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun struct rtc_device *rtc;
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun
v3020_mmio_map(struct v3020 * chip,struct platform_device * pdev,struct v3020_platform_data * pdata)62*4882a593Smuzhiyun static int v3020_mmio_map(struct v3020 *chip, struct platform_device *pdev,
63*4882a593Smuzhiyun struct v3020_platform_data *pdata)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun if (pdev->num_resources != 1)
66*4882a593Smuzhiyun return -EBUSY;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun if (pdev->resource[0].flags != IORESOURCE_MEM)
69*4882a593Smuzhiyun return -EBUSY;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun chip->leftshift = pdata->leftshift;
72*4882a593Smuzhiyun chip->ioaddress = ioremap(pdev->resource[0].start, 1);
73*4882a593Smuzhiyun if (chip->ioaddress == NULL)
74*4882a593Smuzhiyun return -EBUSY;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun return 0;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
v3020_mmio_unmap(struct v3020 * chip)79*4882a593Smuzhiyun static void v3020_mmio_unmap(struct v3020 *chip)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun iounmap(chip->ioaddress);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
v3020_mmio_write_bit(struct v3020 * chip,unsigned char bit)84*4882a593Smuzhiyun static void v3020_mmio_write_bit(struct v3020 *chip, unsigned char bit)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun writel(bit << chip->leftshift, chip->ioaddress);
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
v3020_mmio_read_bit(struct v3020 * chip)89*4882a593Smuzhiyun static unsigned char v3020_mmio_read_bit(struct v3020 *chip)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun return !!(readl(chip->ioaddress) & (1 << chip->leftshift));
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun static const struct v3020_chip_ops v3020_mmio_ops = {
95*4882a593Smuzhiyun .map_io = v3020_mmio_map,
96*4882a593Smuzhiyun .unmap_io = v3020_mmio_unmap,
97*4882a593Smuzhiyun .read_bit = v3020_mmio_read_bit,
98*4882a593Smuzhiyun .write_bit = v3020_mmio_write_bit,
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun static struct gpio v3020_gpio[] = {
102*4882a593Smuzhiyun { 0, GPIOF_OUT_INIT_HIGH, "RTC CS"},
103*4882a593Smuzhiyun { 0, GPIOF_OUT_INIT_HIGH, "RTC WR"},
104*4882a593Smuzhiyun { 0, GPIOF_OUT_INIT_HIGH, "RTC RD"},
105*4882a593Smuzhiyun { 0, GPIOF_OUT_INIT_HIGH, "RTC IO"},
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
v3020_gpio_map(struct v3020 * chip,struct platform_device * pdev,struct v3020_platform_data * pdata)108*4882a593Smuzhiyun static int v3020_gpio_map(struct v3020 *chip, struct platform_device *pdev,
109*4882a593Smuzhiyun struct v3020_platform_data *pdata)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun int err;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun v3020_gpio[V3020_CS].gpio = pdata->gpio_cs;
114*4882a593Smuzhiyun v3020_gpio[V3020_WR].gpio = pdata->gpio_wr;
115*4882a593Smuzhiyun v3020_gpio[V3020_RD].gpio = pdata->gpio_rd;
116*4882a593Smuzhiyun v3020_gpio[V3020_IO].gpio = pdata->gpio_io;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun err = gpio_request_array(v3020_gpio, ARRAY_SIZE(v3020_gpio));
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun if (!err)
121*4882a593Smuzhiyun chip->gpio = v3020_gpio;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun return err;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
v3020_gpio_unmap(struct v3020 * chip)126*4882a593Smuzhiyun static void v3020_gpio_unmap(struct v3020 *chip)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun gpio_free_array(v3020_gpio, ARRAY_SIZE(v3020_gpio));
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
v3020_gpio_write_bit(struct v3020 * chip,unsigned char bit)131*4882a593Smuzhiyun static void v3020_gpio_write_bit(struct v3020 *chip, unsigned char bit)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun gpio_direction_output(chip->gpio[V3020_IO].gpio, bit);
134*4882a593Smuzhiyun gpio_set_value(chip->gpio[V3020_CS].gpio, 0);
135*4882a593Smuzhiyun gpio_set_value(chip->gpio[V3020_WR].gpio, 0);
136*4882a593Smuzhiyun udelay(1);
137*4882a593Smuzhiyun gpio_set_value(chip->gpio[V3020_WR].gpio, 1);
138*4882a593Smuzhiyun gpio_set_value(chip->gpio[V3020_CS].gpio, 1);
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
v3020_gpio_read_bit(struct v3020 * chip)141*4882a593Smuzhiyun static unsigned char v3020_gpio_read_bit(struct v3020 *chip)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun int bit;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun gpio_direction_input(chip->gpio[V3020_IO].gpio);
146*4882a593Smuzhiyun gpio_set_value(chip->gpio[V3020_CS].gpio, 0);
147*4882a593Smuzhiyun gpio_set_value(chip->gpio[V3020_RD].gpio, 0);
148*4882a593Smuzhiyun udelay(1);
149*4882a593Smuzhiyun bit = !!gpio_get_value(chip->gpio[V3020_IO].gpio);
150*4882a593Smuzhiyun udelay(1);
151*4882a593Smuzhiyun gpio_set_value(chip->gpio[V3020_RD].gpio, 1);
152*4882a593Smuzhiyun gpio_set_value(chip->gpio[V3020_CS].gpio, 1);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun return bit;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun static const struct v3020_chip_ops v3020_gpio_ops = {
158*4882a593Smuzhiyun .map_io = v3020_gpio_map,
159*4882a593Smuzhiyun .unmap_io = v3020_gpio_unmap,
160*4882a593Smuzhiyun .read_bit = v3020_gpio_read_bit,
161*4882a593Smuzhiyun .write_bit = v3020_gpio_write_bit,
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun
v3020_set_reg(struct v3020 * chip,unsigned char address,unsigned char data)164*4882a593Smuzhiyun static void v3020_set_reg(struct v3020 *chip, unsigned char address,
165*4882a593Smuzhiyun unsigned char data)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun int i;
168*4882a593Smuzhiyun unsigned char tmp;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun tmp = address;
171*4882a593Smuzhiyun for (i = 0; i < 4; i++) {
172*4882a593Smuzhiyun chip->ops->write_bit(chip, (tmp & 1));
173*4882a593Smuzhiyun tmp >>= 1;
174*4882a593Smuzhiyun udelay(1);
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun /* Commands dont have data */
178*4882a593Smuzhiyun if (!V3020_IS_COMMAND(address)) {
179*4882a593Smuzhiyun for (i = 0; i < 8; i++) {
180*4882a593Smuzhiyun chip->ops->write_bit(chip, (data & 1));
181*4882a593Smuzhiyun data >>= 1;
182*4882a593Smuzhiyun udelay(1);
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
v3020_get_reg(struct v3020 * chip,unsigned char address)187*4882a593Smuzhiyun static unsigned char v3020_get_reg(struct v3020 *chip, unsigned char address)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun unsigned int data = 0;
190*4882a593Smuzhiyun int i;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun for (i = 0; i < 4; i++) {
193*4882a593Smuzhiyun chip->ops->write_bit(chip, (address & 1));
194*4882a593Smuzhiyun address >>= 1;
195*4882a593Smuzhiyun udelay(1);
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun for (i = 0; i < 8; i++) {
199*4882a593Smuzhiyun data >>= 1;
200*4882a593Smuzhiyun if (chip->ops->read_bit(chip))
201*4882a593Smuzhiyun data |= 0x80;
202*4882a593Smuzhiyun udelay(1);
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun return data;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun
v3020_read_time(struct device * dev,struct rtc_time * dt)208*4882a593Smuzhiyun static int v3020_read_time(struct device *dev, struct rtc_time *dt)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun struct v3020 *chip = dev_get_drvdata(dev);
211*4882a593Smuzhiyun int tmp;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun /* Copy the current time to ram... */
214*4882a593Smuzhiyun v3020_set_reg(chip, V3020_CMD_CLOCK2RAM, 0);
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun /* ...and then read constant values. */
217*4882a593Smuzhiyun tmp = v3020_get_reg(chip, V3020_SECONDS);
218*4882a593Smuzhiyun dt->tm_sec = bcd2bin(tmp);
219*4882a593Smuzhiyun tmp = v3020_get_reg(chip, V3020_MINUTES);
220*4882a593Smuzhiyun dt->tm_min = bcd2bin(tmp);
221*4882a593Smuzhiyun tmp = v3020_get_reg(chip, V3020_HOURS);
222*4882a593Smuzhiyun dt->tm_hour = bcd2bin(tmp);
223*4882a593Smuzhiyun tmp = v3020_get_reg(chip, V3020_MONTH_DAY);
224*4882a593Smuzhiyun dt->tm_mday = bcd2bin(tmp);
225*4882a593Smuzhiyun tmp = v3020_get_reg(chip, V3020_MONTH);
226*4882a593Smuzhiyun dt->tm_mon = bcd2bin(tmp) - 1;
227*4882a593Smuzhiyun tmp = v3020_get_reg(chip, V3020_WEEK_DAY);
228*4882a593Smuzhiyun dt->tm_wday = bcd2bin(tmp);
229*4882a593Smuzhiyun tmp = v3020_get_reg(chip, V3020_YEAR);
230*4882a593Smuzhiyun dt->tm_year = bcd2bin(tmp)+100;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun dev_dbg(dev, "\n%s : Read RTC values\n", __func__);
233*4882a593Smuzhiyun dev_dbg(dev, "tm_hour: %i\n", dt->tm_hour);
234*4882a593Smuzhiyun dev_dbg(dev, "tm_min : %i\n", dt->tm_min);
235*4882a593Smuzhiyun dev_dbg(dev, "tm_sec : %i\n", dt->tm_sec);
236*4882a593Smuzhiyun dev_dbg(dev, "tm_year: %i\n", dt->tm_year);
237*4882a593Smuzhiyun dev_dbg(dev, "tm_mon : %i\n", dt->tm_mon);
238*4882a593Smuzhiyun dev_dbg(dev, "tm_mday: %i\n", dt->tm_mday);
239*4882a593Smuzhiyun dev_dbg(dev, "tm_wday: %i\n", dt->tm_wday);
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun return 0;
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun
v3020_set_time(struct device * dev,struct rtc_time * dt)245*4882a593Smuzhiyun static int v3020_set_time(struct device *dev, struct rtc_time *dt)
246*4882a593Smuzhiyun {
247*4882a593Smuzhiyun struct v3020 *chip = dev_get_drvdata(dev);
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun dev_dbg(dev, "\n%s : Setting RTC values\n", __func__);
250*4882a593Smuzhiyun dev_dbg(dev, "tm_sec : %i\n", dt->tm_sec);
251*4882a593Smuzhiyun dev_dbg(dev, "tm_min : %i\n", dt->tm_min);
252*4882a593Smuzhiyun dev_dbg(dev, "tm_hour: %i\n", dt->tm_hour);
253*4882a593Smuzhiyun dev_dbg(dev, "tm_mday: %i\n", dt->tm_mday);
254*4882a593Smuzhiyun dev_dbg(dev, "tm_wday: %i\n", dt->tm_wday);
255*4882a593Smuzhiyun dev_dbg(dev, "tm_year: %i\n", dt->tm_year);
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun /* Write all the values to ram... */
258*4882a593Smuzhiyun v3020_set_reg(chip, V3020_SECONDS, bin2bcd(dt->tm_sec));
259*4882a593Smuzhiyun v3020_set_reg(chip, V3020_MINUTES, bin2bcd(dt->tm_min));
260*4882a593Smuzhiyun v3020_set_reg(chip, V3020_HOURS, bin2bcd(dt->tm_hour));
261*4882a593Smuzhiyun v3020_set_reg(chip, V3020_MONTH_DAY, bin2bcd(dt->tm_mday));
262*4882a593Smuzhiyun v3020_set_reg(chip, V3020_MONTH, bin2bcd(dt->tm_mon + 1));
263*4882a593Smuzhiyun v3020_set_reg(chip, V3020_WEEK_DAY, bin2bcd(dt->tm_wday));
264*4882a593Smuzhiyun v3020_set_reg(chip, V3020_YEAR, bin2bcd(dt->tm_year % 100));
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun /* ...and set the clock. */
267*4882a593Smuzhiyun v3020_set_reg(chip, V3020_CMD_RAM2CLOCK, 0);
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun /* Compulab used this delay here. I dont know why,
270*4882a593Smuzhiyun * the datasheet does not specify a delay. */
271*4882a593Smuzhiyun /*mdelay(5);*/
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun return 0;
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun static const struct rtc_class_ops v3020_rtc_ops = {
277*4882a593Smuzhiyun .read_time = v3020_read_time,
278*4882a593Smuzhiyun .set_time = v3020_set_time,
279*4882a593Smuzhiyun };
280*4882a593Smuzhiyun
rtc_probe(struct platform_device * pdev)281*4882a593Smuzhiyun static int rtc_probe(struct platform_device *pdev)
282*4882a593Smuzhiyun {
283*4882a593Smuzhiyun struct v3020_platform_data *pdata = dev_get_platdata(&pdev->dev);
284*4882a593Smuzhiyun struct v3020 *chip;
285*4882a593Smuzhiyun int retval = -EBUSY;
286*4882a593Smuzhiyun int i;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
289*4882a593Smuzhiyun if (!chip)
290*4882a593Smuzhiyun return -ENOMEM;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun if (pdata->use_gpio)
293*4882a593Smuzhiyun chip->ops = &v3020_gpio_ops;
294*4882a593Smuzhiyun else
295*4882a593Smuzhiyun chip->ops = &v3020_mmio_ops;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun retval = chip->ops->map_io(chip, pdev, pdata);
298*4882a593Smuzhiyun if (retval)
299*4882a593Smuzhiyun return retval;
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun /* Make sure the v3020 expects a communication cycle
302*4882a593Smuzhiyun * by reading 8 times */
303*4882a593Smuzhiyun for (i = 0; i < 8; i++)
304*4882a593Smuzhiyun chip->ops->read_bit(chip);
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun /* Test chip by doing a write/read sequence
307*4882a593Smuzhiyun * to the chip ram */
308*4882a593Smuzhiyun v3020_set_reg(chip, V3020_SECONDS, 0x33);
309*4882a593Smuzhiyun if (v3020_get_reg(chip, V3020_SECONDS) != 0x33) {
310*4882a593Smuzhiyun retval = -ENODEV;
311*4882a593Smuzhiyun goto err_io;
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun /* Make sure frequency measurement mode, test modes, and lock
315*4882a593Smuzhiyun * are all disabled */
316*4882a593Smuzhiyun v3020_set_reg(chip, V3020_STATUS_0, 0x0);
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun if (pdata->use_gpio)
319*4882a593Smuzhiyun dev_info(&pdev->dev, "Chip available at GPIOs "
320*4882a593Smuzhiyun "%d, %d, %d, %d\n",
321*4882a593Smuzhiyun chip->gpio[V3020_CS].gpio, chip->gpio[V3020_WR].gpio,
322*4882a593Smuzhiyun chip->gpio[V3020_RD].gpio, chip->gpio[V3020_IO].gpio);
323*4882a593Smuzhiyun else
324*4882a593Smuzhiyun dev_info(&pdev->dev, "Chip available at "
325*4882a593Smuzhiyun "physical address 0x%llx,"
326*4882a593Smuzhiyun "data connected to D%d\n",
327*4882a593Smuzhiyun (unsigned long long)pdev->resource[0].start,
328*4882a593Smuzhiyun chip->leftshift);
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun platform_set_drvdata(pdev, chip);
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun chip->rtc = devm_rtc_device_register(&pdev->dev, "v3020",
333*4882a593Smuzhiyun &v3020_rtc_ops, THIS_MODULE);
334*4882a593Smuzhiyun if (IS_ERR(chip->rtc)) {
335*4882a593Smuzhiyun retval = PTR_ERR(chip->rtc);
336*4882a593Smuzhiyun goto err_io;
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun return 0;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun err_io:
342*4882a593Smuzhiyun chip->ops->unmap_io(chip);
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun return retval;
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun
rtc_remove(struct platform_device * dev)347*4882a593Smuzhiyun static int rtc_remove(struct platform_device *dev)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun struct v3020 *chip = platform_get_drvdata(dev);
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun chip->ops->unmap_io(chip);
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun return 0;
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun static struct platform_driver rtc_device_driver = {
357*4882a593Smuzhiyun .probe = rtc_probe,
358*4882a593Smuzhiyun .remove = rtc_remove,
359*4882a593Smuzhiyun .driver = {
360*4882a593Smuzhiyun .name = "v3020",
361*4882a593Smuzhiyun },
362*4882a593Smuzhiyun };
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun module_platform_driver(rtc_device_driver);
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun MODULE_DESCRIPTION("V3020 RTC");
367*4882a593Smuzhiyun MODULE_AUTHOR("Raphael Assenat");
368*4882a593Smuzhiyun MODULE_LICENSE("GPL");
369*4882a593Smuzhiyun MODULE_ALIAS("platform:v3020");
370