1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * rtc-tps80031.c -- TI TPS80031/TPS80032 RTC driver
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * RTC driver for TI TPS80031/TPS80032 Fully Integrated
5*4882a593Smuzhiyun * Power Management with Power Path and Battery Charger
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (c) 2012, NVIDIA Corporation.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Author: Laxman Dewangan <ldewangan@nvidia.com>
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
12*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as
13*4882a593Smuzhiyun * published by the Free Software Foundation version 2.
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
16*4882a593Smuzhiyun * whether express or implied; without even the implied warranty of
17*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18*4882a593Smuzhiyun * General Public License for more details.
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License
21*4882a593Smuzhiyun * along with this program; if not, write to the Free Software
22*4882a593Smuzhiyun * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
23*4882a593Smuzhiyun * 02111-1307, USA
24*4882a593Smuzhiyun */
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include <linux/bcd.h>
27*4882a593Smuzhiyun #include <linux/device.h>
28*4882a593Smuzhiyun #include <linux/err.h>
29*4882a593Smuzhiyun #include <linux/init.h>
30*4882a593Smuzhiyun #include <linux/kernel.h>
31*4882a593Smuzhiyun #include <linux/module.h>
32*4882a593Smuzhiyun #include <linux/mfd/tps80031.h>
33*4882a593Smuzhiyun #include <linux/platform_device.h>
34*4882a593Smuzhiyun #include <linux/pm.h>
35*4882a593Smuzhiyun #include <linux/rtc.h>
36*4882a593Smuzhiyun #include <linux/slab.h>
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define ENABLE_ALARM_INT 0x08
39*4882a593Smuzhiyun #define ALARM_INT_STATUS 0x40
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /**
42*4882a593Smuzhiyun * Setting bit to 1 in STOP_RTC will run the RTC and
43*4882a593Smuzhiyun * setting this bit to 0 will freeze RTC.
44*4882a593Smuzhiyun */
45*4882a593Smuzhiyun #define STOP_RTC 0x1
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* Power on reset Values of RTC registers */
48*4882a593Smuzhiyun #define TPS80031_RTC_POR_YEAR 0
49*4882a593Smuzhiyun #define TPS80031_RTC_POR_MONTH 1
50*4882a593Smuzhiyun #define TPS80031_RTC_POR_DAY 1
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* Numbers of registers for time and alarms */
53*4882a593Smuzhiyun #define TPS80031_RTC_TIME_NUM_REGS 7
54*4882a593Smuzhiyun #define TPS80031_RTC_ALARM_NUM_REGS 6
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /**
57*4882a593Smuzhiyun * PMU RTC have only 2 nibbles to store year information, so using an
58*4882a593Smuzhiyun * offset of 100 to set the base year as 2000 for our driver.
59*4882a593Smuzhiyun */
60*4882a593Smuzhiyun #define RTC_YEAR_OFFSET 100
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun struct tps80031_rtc {
63*4882a593Smuzhiyun struct rtc_device *rtc;
64*4882a593Smuzhiyun int irq;
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
tps80031_rtc_read_time(struct device * dev,struct rtc_time * tm)67*4882a593Smuzhiyun static int tps80031_rtc_read_time(struct device *dev, struct rtc_time *tm)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun u8 buff[TPS80031_RTC_TIME_NUM_REGS];
70*4882a593Smuzhiyun int ret;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun ret = tps80031_reads(dev->parent, TPS80031_SLAVE_ID1,
73*4882a593Smuzhiyun TPS80031_SECONDS_REG, TPS80031_RTC_TIME_NUM_REGS, buff);
74*4882a593Smuzhiyun if (ret < 0) {
75*4882a593Smuzhiyun dev_err(dev, "reading RTC_SECONDS_REG failed, err = %d\n", ret);
76*4882a593Smuzhiyun return ret;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun tm->tm_sec = bcd2bin(buff[0]);
80*4882a593Smuzhiyun tm->tm_min = bcd2bin(buff[1]);
81*4882a593Smuzhiyun tm->tm_hour = bcd2bin(buff[2]);
82*4882a593Smuzhiyun tm->tm_mday = bcd2bin(buff[3]);
83*4882a593Smuzhiyun tm->tm_mon = bcd2bin(buff[4]) - 1;
84*4882a593Smuzhiyun tm->tm_year = bcd2bin(buff[5]) + RTC_YEAR_OFFSET;
85*4882a593Smuzhiyun tm->tm_wday = bcd2bin(buff[6]);
86*4882a593Smuzhiyun return 0;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
tps80031_rtc_set_time(struct device * dev,struct rtc_time * tm)89*4882a593Smuzhiyun static int tps80031_rtc_set_time(struct device *dev, struct rtc_time *tm)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun u8 buff[7];
92*4882a593Smuzhiyun int ret;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun buff[0] = bin2bcd(tm->tm_sec);
95*4882a593Smuzhiyun buff[1] = bin2bcd(tm->tm_min);
96*4882a593Smuzhiyun buff[2] = bin2bcd(tm->tm_hour);
97*4882a593Smuzhiyun buff[3] = bin2bcd(tm->tm_mday);
98*4882a593Smuzhiyun buff[4] = bin2bcd(tm->tm_mon + 1);
99*4882a593Smuzhiyun buff[5] = bin2bcd(tm->tm_year % RTC_YEAR_OFFSET);
100*4882a593Smuzhiyun buff[6] = bin2bcd(tm->tm_wday);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* Stop RTC while updating the RTC time registers */
103*4882a593Smuzhiyun ret = tps80031_clr_bits(dev->parent, TPS80031_SLAVE_ID1,
104*4882a593Smuzhiyun TPS80031_RTC_CTRL_REG, STOP_RTC);
105*4882a593Smuzhiyun if (ret < 0) {
106*4882a593Smuzhiyun dev_err(dev->parent, "Stop RTC failed, err = %d\n", ret);
107*4882a593Smuzhiyun return ret;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun ret = tps80031_writes(dev->parent, TPS80031_SLAVE_ID1,
111*4882a593Smuzhiyun TPS80031_SECONDS_REG,
112*4882a593Smuzhiyun TPS80031_RTC_TIME_NUM_REGS, buff);
113*4882a593Smuzhiyun if (ret < 0) {
114*4882a593Smuzhiyun dev_err(dev, "writing RTC_SECONDS_REG failed, err %d\n", ret);
115*4882a593Smuzhiyun return ret;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun ret = tps80031_set_bits(dev->parent, TPS80031_SLAVE_ID1,
119*4882a593Smuzhiyun TPS80031_RTC_CTRL_REG, STOP_RTC);
120*4882a593Smuzhiyun if (ret < 0)
121*4882a593Smuzhiyun dev_err(dev->parent, "Start RTC failed, err = %d\n", ret);
122*4882a593Smuzhiyun return ret;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
tps80031_rtc_alarm_irq_enable(struct device * dev,unsigned int enable)125*4882a593Smuzhiyun static int tps80031_rtc_alarm_irq_enable(struct device *dev,
126*4882a593Smuzhiyun unsigned int enable)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun int ret;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun if (enable)
131*4882a593Smuzhiyun ret = tps80031_set_bits(dev->parent, TPS80031_SLAVE_ID1,
132*4882a593Smuzhiyun TPS80031_RTC_INTERRUPTS_REG, ENABLE_ALARM_INT);
133*4882a593Smuzhiyun else
134*4882a593Smuzhiyun ret = tps80031_clr_bits(dev->parent, TPS80031_SLAVE_ID1,
135*4882a593Smuzhiyun TPS80031_RTC_INTERRUPTS_REG, ENABLE_ALARM_INT);
136*4882a593Smuzhiyun if (ret < 0) {
137*4882a593Smuzhiyun dev_err(dev, "Update on RTC_INT failed, err = %d\n", ret);
138*4882a593Smuzhiyun return ret;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun return 0;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
tps80031_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)143*4882a593Smuzhiyun static int tps80031_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun u8 buff[TPS80031_RTC_ALARM_NUM_REGS];
146*4882a593Smuzhiyun int ret;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun buff[0] = bin2bcd(alrm->time.tm_sec);
149*4882a593Smuzhiyun buff[1] = bin2bcd(alrm->time.tm_min);
150*4882a593Smuzhiyun buff[2] = bin2bcd(alrm->time.tm_hour);
151*4882a593Smuzhiyun buff[3] = bin2bcd(alrm->time.tm_mday);
152*4882a593Smuzhiyun buff[4] = bin2bcd(alrm->time.tm_mon + 1);
153*4882a593Smuzhiyun buff[5] = bin2bcd(alrm->time.tm_year % RTC_YEAR_OFFSET);
154*4882a593Smuzhiyun ret = tps80031_writes(dev->parent, TPS80031_SLAVE_ID1,
155*4882a593Smuzhiyun TPS80031_ALARM_SECONDS_REG,
156*4882a593Smuzhiyun TPS80031_RTC_ALARM_NUM_REGS, buff);
157*4882a593Smuzhiyun if (ret < 0) {
158*4882a593Smuzhiyun dev_err(dev, "Writing RTC_ALARM failed, err %d\n", ret);
159*4882a593Smuzhiyun return ret;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun return tps80031_rtc_alarm_irq_enable(dev, alrm->enabled);
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun
tps80031_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alrm)164*4882a593Smuzhiyun static int tps80031_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun u8 buff[6];
167*4882a593Smuzhiyun int ret;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun ret = tps80031_reads(dev->parent, TPS80031_SLAVE_ID1,
170*4882a593Smuzhiyun TPS80031_ALARM_SECONDS_REG,
171*4882a593Smuzhiyun TPS80031_RTC_ALARM_NUM_REGS, buff);
172*4882a593Smuzhiyun if (ret < 0) {
173*4882a593Smuzhiyun dev_err(dev->parent,
174*4882a593Smuzhiyun "reading RTC_ALARM failed, err = %d\n", ret);
175*4882a593Smuzhiyun return ret;
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun alrm->time.tm_sec = bcd2bin(buff[0]);
179*4882a593Smuzhiyun alrm->time.tm_min = bcd2bin(buff[1]);
180*4882a593Smuzhiyun alrm->time.tm_hour = bcd2bin(buff[2]);
181*4882a593Smuzhiyun alrm->time.tm_mday = bcd2bin(buff[3]);
182*4882a593Smuzhiyun alrm->time.tm_mon = bcd2bin(buff[4]) - 1;
183*4882a593Smuzhiyun alrm->time.tm_year = bcd2bin(buff[5]) + RTC_YEAR_OFFSET;
184*4882a593Smuzhiyun return 0;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
clear_alarm_int_status(struct device * dev,struct tps80031_rtc * rtc)187*4882a593Smuzhiyun static int clear_alarm_int_status(struct device *dev, struct tps80031_rtc *rtc)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun int ret;
190*4882a593Smuzhiyun u8 buf;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun /**
193*4882a593Smuzhiyun * As per datasheet, A dummy read of this RTC_STATUS_REG register
194*4882a593Smuzhiyun * is necessary before each I2C read in order to update the status
195*4882a593Smuzhiyun * register value.
196*4882a593Smuzhiyun */
197*4882a593Smuzhiyun ret = tps80031_read(dev->parent, TPS80031_SLAVE_ID1,
198*4882a593Smuzhiyun TPS80031_RTC_STATUS_REG, &buf);
199*4882a593Smuzhiyun if (ret < 0) {
200*4882a593Smuzhiyun dev_err(dev, "reading RTC_STATUS failed. err = %d\n", ret);
201*4882a593Smuzhiyun return ret;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun /* clear Alarm status bits.*/
205*4882a593Smuzhiyun ret = tps80031_set_bits(dev->parent, TPS80031_SLAVE_ID1,
206*4882a593Smuzhiyun TPS80031_RTC_STATUS_REG, ALARM_INT_STATUS);
207*4882a593Smuzhiyun if (ret < 0) {
208*4882a593Smuzhiyun dev_err(dev, "clear Alarm INT failed, err = %d\n", ret);
209*4882a593Smuzhiyun return ret;
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun return 0;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
tps80031_rtc_irq(int irq,void * data)214*4882a593Smuzhiyun static irqreturn_t tps80031_rtc_irq(int irq, void *data)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun struct device *dev = data;
217*4882a593Smuzhiyun struct tps80031_rtc *rtc = dev_get_drvdata(dev);
218*4882a593Smuzhiyun int ret;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun ret = clear_alarm_int_status(dev, rtc);
221*4882a593Smuzhiyun if (ret < 0)
222*4882a593Smuzhiyun return ret;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_AF);
225*4882a593Smuzhiyun return IRQ_HANDLED;
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun static const struct rtc_class_ops tps80031_rtc_ops = {
229*4882a593Smuzhiyun .read_time = tps80031_rtc_read_time,
230*4882a593Smuzhiyun .set_time = tps80031_rtc_set_time,
231*4882a593Smuzhiyun .set_alarm = tps80031_rtc_set_alarm,
232*4882a593Smuzhiyun .read_alarm = tps80031_rtc_read_alarm,
233*4882a593Smuzhiyun .alarm_irq_enable = tps80031_rtc_alarm_irq_enable,
234*4882a593Smuzhiyun };
235*4882a593Smuzhiyun
tps80031_rtc_probe(struct platform_device * pdev)236*4882a593Smuzhiyun static int tps80031_rtc_probe(struct platform_device *pdev)
237*4882a593Smuzhiyun {
238*4882a593Smuzhiyun struct tps80031_rtc *rtc;
239*4882a593Smuzhiyun struct rtc_time tm;
240*4882a593Smuzhiyun int ret;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
243*4882a593Smuzhiyun if (!rtc)
244*4882a593Smuzhiyun return -ENOMEM;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun rtc->irq = platform_get_irq(pdev, 0);
247*4882a593Smuzhiyun platform_set_drvdata(pdev, rtc);
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun /* Start RTC */
250*4882a593Smuzhiyun ret = tps80031_set_bits(pdev->dev.parent, TPS80031_SLAVE_ID1,
251*4882a593Smuzhiyun TPS80031_RTC_CTRL_REG, STOP_RTC);
252*4882a593Smuzhiyun if (ret < 0) {
253*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to start RTC. err = %d\n", ret);
254*4882a593Smuzhiyun return ret;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun /* If RTC have POR values, set time 01:01:2000 */
258*4882a593Smuzhiyun tps80031_rtc_read_time(&pdev->dev, &tm);
259*4882a593Smuzhiyun if ((tm.tm_year == RTC_YEAR_OFFSET + TPS80031_RTC_POR_YEAR) &&
260*4882a593Smuzhiyun (tm.tm_mon == (TPS80031_RTC_POR_MONTH - 1)) &&
261*4882a593Smuzhiyun (tm.tm_mday == TPS80031_RTC_POR_DAY)) {
262*4882a593Smuzhiyun tm.tm_year = 2000;
263*4882a593Smuzhiyun tm.tm_mday = 1;
264*4882a593Smuzhiyun tm.tm_mon = 1;
265*4882a593Smuzhiyun ret = tps80031_rtc_set_time(&pdev->dev, &tm);
266*4882a593Smuzhiyun if (ret < 0) {
267*4882a593Smuzhiyun dev_err(&pdev->dev,
268*4882a593Smuzhiyun "RTC set time failed, err = %d\n", ret);
269*4882a593Smuzhiyun return ret;
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun /* Clear alarm intretupt status if it is there */
274*4882a593Smuzhiyun ret = clear_alarm_int_status(&pdev->dev, rtc);
275*4882a593Smuzhiyun if (ret < 0) {
276*4882a593Smuzhiyun dev_err(&pdev->dev, "Clear alarm int failed, err = %d\n", ret);
277*4882a593Smuzhiyun return ret;
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
281*4882a593Smuzhiyun &tps80031_rtc_ops, THIS_MODULE);
282*4882a593Smuzhiyun if (IS_ERR(rtc->rtc)) {
283*4882a593Smuzhiyun ret = PTR_ERR(rtc->rtc);
284*4882a593Smuzhiyun dev_err(&pdev->dev, "RTC registration failed, err %d\n", ret);
285*4882a593Smuzhiyun return ret;
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun ret = devm_request_threaded_irq(&pdev->dev, rtc->irq, NULL,
289*4882a593Smuzhiyun tps80031_rtc_irq,
290*4882a593Smuzhiyun IRQF_ONESHOT,
291*4882a593Smuzhiyun dev_name(&pdev->dev), rtc);
292*4882a593Smuzhiyun if (ret < 0) {
293*4882a593Smuzhiyun dev_err(&pdev->dev, "request IRQ:%d failed, err = %d\n",
294*4882a593Smuzhiyun rtc->irq, ret);
295*4882a593Smuzhiyun return ret;
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun device_set_wakeup_capable(&pdev->dev, 1);
298*4882a593Smuzhiyun return 0;
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
tps80031_rtc_suspend(struct device * dev)302*4882a593Smuzhiyun static int tps80031_rtc_suspend(struct device *dev)
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun struct tps80031_rtc *rtc = dev_get_drvdata(dev);
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun if (device_may_wakeup(dev))
307*4882a593Smuzhiyun enable_irq_wake(rtc->irq);
308*4882a593Smuzhiyun return 0;
309*4882a593Smuzhiyun }
310*4882a593Smuzhiyun
tps80031_rtc_resume(struct device * dev)311*4882a593Smuzhiyun static int tps80031_rtc_resume(struct device *dev)
312*4882a593Smuzhiyun {
313*4882a593Smuzhiyun struct tps80031_rtc *rtc = dev_get_drvdata(dev);
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun if (device_may_wakeup(dev))
316*4882a593Smuzhiyun disable_irq_wake(rtc->irq);
317*4882a593Smuzhiyun return 0;
318*4882a593Smuzhiyun };
319*4882a593Smuzhiyun #endif
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(tps80031_pm_ops, tps80031_rtc_suspend,
322*4882a593Smuzhiyun tps80031_rtc_resume);
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun static struct platform_driver tps80031_rtc_driver = {
325*4882a593Smuzhiyun .driver = {
326*4882a593Smuzhiyun .name = "tps80031-rtc",
327*4882a593Smuzhiyun .pm = &tps80031_pm_ops,
328*4882a593Smuzhiyun },
329*4882a593Smuzhiyun .probe = tps80031_rtc_probe,
330*4882a593Smuzhiyun };
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun module_platform_driver(tps80031_rtc_driver);
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun MODULE_ALIAS("platform:tps80031-rtc");
335*4882a593Smuzhiyun MODULE_DESCRIPTION("TI TPS80031/TPS80032 RTC driver");
336*4882a593Smuzhiyun MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
337*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
338