xref: /OK3568_Linux_fs/kernel/drivers/rtc/rtc-sunxi.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * An RTC driver for Allwinner A10/A20
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/delay.h>
9*4882a593Smuzhiyun #include <linux/err.h>
10*4882a593Smuzhiyun #include <linux/fs.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/interrupt.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/kernel.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/of.h>
17*4882a593Smuzhiyun #include <linux/of_address.h>
18*4882a593Smuzhiyun #include <linux/of_device.h>
19*4882a593Smuzhiyun #include <linux/platform_device.h>
20*4882a593Smuzhiyun #include <linux/rtc.h>
21*4882a593Smuzhiyun #include <linux/types.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define SUNXI_LOSC_CTRL				0x0000
24*4882a593Smuzhiyun #define SUNXI_LOSC_CTRL_RTC_HMS_ACC		BIT(8)
25*4882a593Smuzhiyun #define SUNXI_LOSC_CTRL_RTC_YMD_ACC		BIT(7)
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define SUNXI_RTC_YMD				0x0004
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #define SUNXI_RTC_HMS				0x0008
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #define SUNXI_ALRM_DHMS				0x000c
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define SUNXI_ALRM_EN				0x0014
34*4882a593Smuzhiyun #define SUNXI_ALRM_EN_CNT_EN			BIT(8)
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define SUNXI_ALRM_IRQ_EN			0x0018
37*4882a593Smuzhiyun #define SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN		BIT(0)
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define SUNXI_ALRM_IRQ_STA			0x001c
40*4882a593Smuzhiyun #define SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND		BIT(0)
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun #define SUNXI_MASK_DH				0x0000001f
43*4882a593Smuzhiyun #define SUNXI_MASK_SM				0x0000003f
44*4882a593Smuzhiyun #define SUNXI_MASK_M				0x0000000f
45*4882a593Smuzhiyun #define SUNXI_MASK_LY				0x00000001
46*4882a593Smuzhiyun #define SUNXI_MASK_D				0x00000ffe
47*4882a593Smuzhiyun #define SUNXI_MASK_M				0x0000000f
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun #define SUNXI_GET(x, mask, shift)		(((x) & ((mask) << (shift))) \
50*4882a593Smuzhiyun 							>> (shift))
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #define SUNXI_SET(x, mask, shift)		(((x) & (mask)) << (shift))
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun  * Get date values
56*4882a593Smuzhiyun  */
57*4882a593Smuzhiyun #define SUNXI_DATE_GET_DAY_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_DH, 0)
58*4882a593Smuzhiyun #define SUNXI_DATE_GET_MON_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_M, 8)
59*4882a593Smuzhiyun #define SUNXI_DATE_GET_YEAR_VALUE(x, mask)	SUNXI_GET(x, mask, 16)
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun /*
62*4882a593Smuzhiyun  * Get time values
63*4882a593Smuzhiyun  */
64*4882a593Smuzhiyun #define SUNXI_TIME_GET_SEC_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_SM, 0)
65*4882a593Smuzhiyun #define SUNXI_TIME_GET_MIN_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_SM, 8)
66*4882a593Smuzhiyun #define SUNXI_TIME_GET_HOUR_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_DH, 16)
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun /*
69*4882a593Smuzhiyun  * Get alarm values
70*4882a593Smuzhiyun  */
71*4882a593Smuzhiyun #define SUNXI_ALRM_GET_SEC_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_SM, 0)
72*4882a593Smuzhiyun #define SUNXI_ALRM_GET_MIN_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_SM, 8)
73*4882a593Smuzhiyun #define SUNXI_ALRM_GET_HOUR_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_DH, 16)
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun /*
76*4882a593Smuzhiyun  * Set date values
77*4882a593Smuzhiyun  */
78*4882a593Smuzhiyun #define SUNXI_DATE_SET_DAY_VALUE(x)		SUNXI_DATE_GET_DAY_VALUE(x)
79*4882a593Smuzhiyun #define SUNXI_DATE_SET_MON_VALUE(x)		SUNXI_SET(x, SUNXI_MASK_M, 8)
80*4882a593Smuzhiyun #define SUNXI_DATE_SET_YEAR_VALUE(x, mask)	SUNXI_SET(x, mask, 16)
81*4882a593Smuzhiyun #define SUNXI_LEAP_SET_VALUE(x, shift)		SUNXI_SET(x, SUNXI_MASK_LY, shift)
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun /*
84*4882a593Smuzhiyun  * Set time values
85*4882a593Smuzhiyun  */
86*4882a593Smuzhiyun #define SUNXI_TIME_SET_SEC_VALUE(x)		SUNXI_TIME_GET_SEC_VALUE(x)
87*4882a593Smuzhiyun #define SUNXI_TIME_SET_MIN_VALUE(x)		SUNXI_SET(x, SUNXI_MASK_SM, 8)
88*4882a593Smuzhiyun #define SUNXI_TIME_SET_HOUR_VALUE(x)		SUNXI_SET(x, SUNXI_MASK_DH, 16)
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun /*
91*4882a593Smuzhiyun  * Set alarm values
92*4882a593Smuzhiyun  */
93*4882a593Smuzhiyun #define SUNXI_ALRM_SET_SEC_VALUE(x)		SUNXI_ALRM_GET_SEC_VALUE(x)
94*4882a593Smuzhiyun #define SUNXI_ALRM_SET_MIN_VALUE(x)		SUNXI_SET(x, SUNXI_MASK_SM, 8)
95*4882a593Smuzhiyun #define SUNXI_ALRM_SET_HOUR_VALUE(x)		SUNXI_SET(x, SUNXI_MASK_DH, 16)
96*4882a593Smuzhiyun #define SUNXI_ALRM_SET_DAY_VALUE(x)		SUNXI_SET(x, SUNXI_MASK_D, 21)
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun /*
99*4882a593Smuzhiyun  * Time unit conversions
100*4882a593Smuzhiyun  */
101*4882a593Smuzhiyun #define SEC_IN_MIN				60
102*4882a593Smuzhiyun #define SEC_IN_HOUR				(60 * SEC_IN_MIN)
103*4882a593Smuzhiyun #define SEC_IN_DAY				(24 * SEC_IN_HOUR)
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun /*
106*4882a593Smuzhiyun  * The year parameter passed to the driver is usually an offset relative to
107*4882a593Smuzhiyun  * the year 1900. This macro is used to convert this offset to another one
108*4882a593Smuzhiyun  * relative to the minimum year allowed by the hardware.
109*4882a593Smuzhiyun  */
110*4882a593Smuzhiyun #define SUNXI_YEAR_OFF(x)			((x)->min - 1900)
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun /*
113*4882a593Smuzhiyun  * min and max year are arbitrary set considering the limited range of the
114*4882a593Smuzhiyun  * hardware register field
115*4882a593Smuzhiyun  */
116*4882a593Smuzhiyun struct sunxi_rtc_data_year {
117*4882a593Smuzhiyun 	unsigned int min;		/* min year allowed */
118*4882a593Smuzhiyun 	unsigned int max;		/* max year allowed */
119*4882a593Smuzhiyun 	unsigned int mask;		/* mask for the year field */
120*4882a593Smuzhiyun 	unsigned char leap_shift;	/* bit shift to get the leap year */
121*4882a593Smuzhiyun };
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun static const struct sunxi_rtc_data_year data_year_param[] = {
124*4882a593Smuzhiyun 	[0] = {
125*4882a593Smuzhiyun 		.min		= 2010,
126*4882a593Smuzhiyun 		.max		= 2073,
127*4882a593Smuzhiyun 		.mask		= 0x3f,
128*4882a593Smuzhiyun 		.leap_shift	= 22,
129*4882a593Smuzhiyun 	},
130*4882a593Smuzhiyun 	[1] = {
131*4882a593Smuzhiyun 		.min		= 1970,
132*4882a593Smuzhiyun 		.max		= 2225,
133*4882a593Smuzhiyun 		.mask		= 0xff,
134*4882a593Smuzhiyun 		.leap_shift	= 24,
135*4882a593Smuzhiyun 	},
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun struct sunxi_rtc_dev {
139*4882a593Smuzhiyun 	struct rtc_device *rtc;
140*4882a593Smuzhiyun 	struct device *dev;
141*4882a593Smuzhiyun 	const struct sunxi_rtc_data_year *data_year;
142*4882a593Smuzhiyun 	void __iomem *base;
143*4882a593Smuzhiyun 	int irq;
144*4882a593Smuzhiyun };
145*4882a593Smuzhiyun 
sunxi_rtc_alarmirq(int irq,void * id)146*4882a593Smuzhiyun static irqreturn_t sunxi_rtc_alarmirq(int irq, void *id)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun 	struct sunxi_rtc_dev *chip = (struct sunxi_rtc_dev *) id;
149*4882a593Smuzhiyun 	u32 val;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	val = readl(chip->base + SUNXI_ALRM_IRQ_STA);
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	if (val & SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND) {
154*4882a593Smuzhiyun 		val |= SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND;
155*4882a593Smuzhiyun 		writel(val, chip->base + SUNXI_ALRM_IRQ_STA);
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 		rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 		return IRQ_HANDLED;
160*4882a593Smuzhiyun 	}
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	return IRQ_NONE;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun 
sunxi_rtc_setaie(unsigned int to,struct sunxi_rtc_dev * chip)165*4882a593Smuzhiyun static void sunxi_rtc_setaie(unsigned int to, struct sunxi_rtc_dev *chip)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun 	u32 alrm_val = 0;
168*4882a593Smuzhiyun 	u32 alrm_irq_val = 0;
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	if (to) {
171*4882a593Smuzhiyun 		alrm_val = readl(chip->base + SUNXI_ALRM_EN);
172*4882a593Smuzhiyun 		alrm_val |= SUNXI_ALRM_EN_CNT_EN;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 		alrm_irq_val = readl(chip->base + SUNXI_ALRM_IRQ_EN);
175*4882a593Smuzhiyun 		alrm_irq_val |= SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN;
176*4882a593Smuzhiyun 	} else {
177*4882a593Smuzhiyun 		writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND,
178*4882a593Smuzhiyun 				chip->base + SUNXI_ALRM_IRQ_STA);
179*4882a593Smuzhiyun 	}
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	writel(alrm_val, chip->base + SUNXI_ALRM_EN);
182*4882a593Smuzhiyun 	writel(alrm_irq_val, chip->base + SUNXI_ALRM_IRQ_EN);
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun 
sunxi_rtc_getalarm(struct device * dev,struct rtc_wkalrm * wkalrm)185*4882a593Smuzhiyun static int sunxi_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun 	struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
188*4882a593Smuzhiyun 	struct rtc_time *alrm_tm = &wkalrm->time;
189*4882a593Smuzhiyun 	u32 alrm;
190*4882a593Smuzhiyun 	u32 alrm_en;
191*4882a593Smuzhiyun 	u32 date;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	alrm = readl(chip->base + SUNXI_ALRM_DHMS);
194*4882a593Smuzhiyun 	date = readl(chip->base + SUNXI_RTC_YMD);
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	alrm_tm->tm_sec = SUNXI_ALRM_GET_SEC_VALUE(alrm);
197*4882a593Smuzhiyun 	alrm_tm->tm_min = SUNXI_ALRM_GET_MIN_VALUE(alrm);
198*4882a593Smuzhiyun 	alrm_tm->tm_hour = SUNXI_ALRM_GET_HOUR_VALUE(alrm);
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	alrm_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date);
201*4882a593Smuzhiyun 	alrm_tm->tm_mon = SUNXI_DATE_GET_MON_VALUE(date);
202*4882a593Smuzhiyun 	alrm_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date,
203*4882a593Smuzhiyun 			chip->data_year->mask);
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	alrm_tm->tm_mon -= 1;
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	/*
208*4882a593Smuzhiyun 	 * switch from (data_year->min)-relative offset to
209*4882a593Smuzhiyun 	 * a (1900)-relative one
210*4882a593Smuzhiyun 	 */
211*4882a593Smuzhiyun 	alrm_tm->tm_year += SUNXI_YEAR_OFF(chip->data_year);
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	alrm_en = readl(chip->base + SUNXI_ALRM_IRQ_EN);
214*4882a593Smuzhiyun 	if (alrm_en & SUNXI_ALRM_EN_CNT_EN)
215*4882a593Smuzhiyun 		wkalrm->enabled = 1;
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	return 0;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun 
sunxi_rtc_gettime(struct device * dev,struct rtc_time * rtc_tm)220*4882a593Smuzhiyun static int sunxi_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun 	struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
223*4882a593Smuzhiyun 	u32 date, time;
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	/*
226*4882a593Smuzhiyun 	 * read again in case it changes
227*4882a593Smuzhiyun 	 */
228*4882a593Smuzhiyun 	do {
229*4882a593Smuzhiyun 		date = readl(chip->base + SUNXI_RTC_YMD);
230*4882a593Smuzhiyun 		time = readl(chip->base + SUNXI_RTC_HMS);
231*4882a593Smuzhiyun 	} while ((date != readl(chip->base + SUNXI_RTC_YMD)) ||
232*4882a593Smuzhiyun 		 (time != readl(chip->base + SUNXI_RTC_HMS)));
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	rtc_tm->tm_sec  = SUNXI_TIME_GET_SEC_VALUE(time);
235*4882a593Smuzhiyun 	rtc_tm->tm_min  = SUNXI_TIME_GET_MIN_VALUE(time);
236*4882a593Smuzhiyun 	rtc_tm->tm_hour = SUNXI_TIME_GET_HOUR_VALUE(time);
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	rtc_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date);
239*4882a593Smuzhiyun 	rtc_tm->tm_mon  = SUNXI_DATE_GET_MON_VALUE(date);
240*4882a593Smuzhiyun 	rtc_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date,
241*4882a593Smuzhiyun 					chip->data_year->mask);
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	rtc_tm->tm_mon  -= 1;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	/*
246*4882a593Smuzhiyun 	 * switch from (data_year->min)-relative offset to
247*4882a593Smuzhiyun 	 * a (1900)-relative one
248*4882a593Smuzhiyun 	 */
249*4882a593Smuzhiyun 	rtc_tm->tm_year += SUNXI_YEAR_OFF(chip->data_year);
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	return 0;
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun 
sunxi_rtc_setalarm(struct device * dev,struct rtc_wkalrm * wkalrm)254*4882a593Smuzhiyun static int sunxi_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
255*4882a593Smuzhiyun {
256*4882a593Smuzhiyun 	struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
257*4882a593Smuzhiyun 	struct rtc_time *alrm_tm = &wkalrm->time;
258*4882a593Smuzhiyun 	struct rtc_time tm_now;
259*4882a593Smuzhiyun 	u32 alrm;
260*4882a593Smuzhiyun 	time64_t diff;
261*4882a593Smuzhiyun 	unsigned long time_gap;
262*4882a593Smuzhiyun 	unsigned long time_gap_day;
263*4882a593Smuzhiyun 	unsigned long time_gap_hour;
264*4882a593Smuzhiyun 	unsigned long time_gap_min;
265*4882a593Smuzhiyun 	int ret;
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 	ret = sunxi_rtc_gettime(dev, &tm_now);
268*4882a593Smuzhiyun 	if (ret < 0) {
269*4882a593Smuzhiyun 		dev_err(dev, "Error in getting time\n");
270*4882a593Smuzhiyun 		return -EINVAL;
271*4882a593Smuzhiyun 	}
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	diff = rtc_tm_sub(alrm_tm, &tm_now);
274*4882a593Smuzhiyun 	if (diff <= 0) {
275*4882a593Smuzhiyun 		dev_err(dev, "Date to set in the past\n");
276*4882a593Smuzhiyun 		return -EINVAL;
277*4882a593Smuzhiyun 	}
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	if (diff > 255 * SEC_IN_DAY) {
280*4882a593Smuzhiyun 		dev_err(dev, "Day must be in the range 0 - 255\n");
281*4882a593Smuzhiyun 		return -EINVAL;
282*4882a593Smuzhiyun 	}
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 	time_gap = diff;
285*4882a593Smuzhiyun 	time_gap_day = time_gap / SEC_IN_DAY;
286*4882a593Smuzhiyun 	time_gap -= time_gap_day * SEC_IN_DAY;
287*4882a593Smuzhiyun 	time_gap_hour = time_gap / SEC_IN_HOUR;
288*4882a593Smuzhiyun 	time_gap -= time_gap_hour * SEC_IN_HOUR;
289*4882a593Smuzhiyun 	time_gap_min = time_gap / SEC_IN_MIN;
290*4882a593Smuzhiyun 	time_gap -= time_gap_min * SEC_IN_MIN;
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	sunxi_rtc_setaie(0, chip);
293*4882a593Smuzhiyun 	writel(0, chip->base + SUNXI_ALRM_DHMS);
294*4882a593Smuzhiyun 	usleep_range(100, 300);
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	alrm = SUNXI_ALRM_SET_SEC_VALUE(time_gap) |
297*4882a593Smuzhiyun 		SUNXI_ALRM_SET_MIN_VALUE(time_gap_min) |
298*4882a593Smuzhiyun 		SUNXI_ALRM_SET_HOUR_VALUE(time_gap_hour) |
299*4882a593Smuzhiyun 		SUNXI_ALRM_SET_DAY_VALUE(time_gap_day);
300*4882a593Smuzhiyun 	writel(alrm, chip->base + SUNXI_ALRM_DHMS);
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 	writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
303*4882a593Smuzhiyun 	writel(SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN, chip->base + SUNXI_ALRM_IRQ_EN);
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 	sunxi_rtc_setaie(wkalrm->enabled, chip);
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	return 0;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun 
sunxi_rtc_wait(struct sunxi_rtc_dev * chip,int offset,unsigned int mask,unsigned int ms_timeout)310*4882a593Smuzhiyun static int sunxi_rtc_wait(struct sunxi_rtc_dev *chip, int offset,
311*4882a593Smuzhiyun 			  unsigned int mask, unsigned int ms_timeout)
312*4882a593Smuzhiyun {
313*4882a593Smuzhiyun 	const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
314*4882a593Smuzhiyun 	u32 reg;
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun 	do {
317*4882a593Smuzhiyun 		reg = readl(chip->base + offset);
318*4882a593Smuzhiyun 		reg &= mask;
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun 		if (reg == mask)
321*4882a593Smuzhiyun 			return 0;
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun 	} while (time_before(jiffies, timeout));
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	return -ETIMEDOUT;
326*4882a593Smuzhiyun }
327*4882a593Smuzhiyun 
sunxi_rtc_settime(struct device * dev,struct rtc_time * rtc_tm)328*4882a593Smuzhiyun static int sunxi_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
329*4882a593Smuzhiyun {
330*4882a593Smuzhiyun 	struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
331*4882a593Smuzhiyun 	u32 date = 0;
332*4882a593Smuzhiyun 	u32 time = 0;
333*4882a593Smuzhiyun 	unsigned int year;
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 	/*
336*4882a593Smuzhiyun 	 * the input rtc_tm->tm_year is the offset relative to 1900. We use
337*4882a593Smuzhiyun 	 * the SUNXI_YEAR_OFF macro to rebase it with respect to the min year
338*4882a593Smuzhiyun 	 * allowed by the hardware
339*4882a593Smuzhiyun 	 */
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun 	year = rtc_tm->tm_year + 1900;
342*4882a593Smuzhiyun 	if (year < chip->data_year->min || year > chip->data_year->max) {
343*4882a593Smuzhiyun 		dev_err(dev, "rtc only supports year in range %u - %u\n",
344*4882a593Smuzhiyun 			chip->data_year->min, chip->data_year->max);
345*4882a593Smuzhiyun 		return -EINVAL;
346*4882a593Smuzhiyun 	}
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	rtc_tm->tm_year -= SUNXI_YEAR_OFF(chip->data_year);
349*4882a593Smuzhiyun 	rtc_tm->tm_mon += 1;
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun 	date = SUNXI_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
352*4882a593Smuzhiyun 		SUNXI_DATE_SET_MON_VALUE(rtc_tm->tm_mon)  |
353*4882a593Smuzhiyun 		SUNXI_DATE_SET_YEAR_VALUE(rtc_tm->tm_year,
354*4882a593Smuzhiyun 				chip->data_year->mask);
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 	if (is_leap_year(year))
357*4882a593Smuzhiyun 		date |= SUNXI_LEAP_SET_VALUE(1, chip->data_year->leap_shift);
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun 	time = SUNXI_TIME_SET_SEC_VALUE(rtc_tm->tm_sec)  |
360*4882a593Smuzhiyun 		SUNXI_TIME_SET_MIN_VALUE(rtc_tm->tm_min)  |
361*4882a593Smuzhiyun 		SUNXI_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	writel(0, chip->base + SUNXI_RTC_HMS);
364*4882a593Smuzhiyun 	writel(0, chip->base + SUNXI_RTC_YMD);
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun 	writel(time, chip->base + SUNXI_RTC_HMS);
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	/*
369*4882a593Smuzhiyun 	 * After writing the RTC HH-MM-SS register, the
370*4882a593Smuzhiyun 	 * SUNXI_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
371*4882a593Smuzhiyun 	 * be cleared until the real writing operation is finished
372*4882a593Smuzhiyun 	 */
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 	if (sunxi_rtc_wait(chip, SUNXI_LOSC_CTRL,
375*4882a593Smuzhiyun 				SUNXI_LOSC_CTRL_RTC_HMS_ACC, 50)) {
376*4882a593Smuzhiyun 		dev_err(dev, "Failed to set rtc time.\n");
377*4882a593Smuzhiyun 		return -1;
378*4882a593Smuzhiyun 	}
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun 	writel(date, chip->base + SUNXI_RTC_YMD);
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	/*
383*4882a593Smuzhiyun 	 * After writing the RTC YY-MM-DD register, the
384*4882a593Smuzhiyun 	 * SUNXI_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
385*4882a593Smuzhiyun 	 * be cleared until the real writing operation is finished
386*4882a593Smuzhiyun 	 */
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 	if (sunxi_rtc_wait(chip, SUNXI_LOSC_CTRL,
389*4882a593Smuzhiyun 				SUNXI_LOSC_CTRL_RTC_YMD_ACC, 50)) {
390*4882a593Smuzhiyun 		dev_err(dev, "Failed to set rtc time.\n");
391*4882a593Smuzhiyun 		return -1;
392*4882a593Smuzhiyun 	}
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun 	return 0;
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun 
sunxi_rtc_alarm_irq_enable(struct device * dev,unsigned int enabled)397*4882a593Smuzhiyun static int sunxi_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
398*4882a593Smuzhiyun {
399*4882a593Smuzhiyun 	struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun 	if (!enabled)
402*4882a593Smuzhiyun 		sunxi_rtc_setaie(enabled, chip);
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	return 0;
405*4882a593Smuzhiyun }
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun static const struct rtc_class_ops sunxi_rtc_ops = {
408*4882a593Smuzhiyun 	.read_time		= sunxi_rtc_gettime,
409*4882a593Smuzhiyun 	.set_time		= sunxi_rtc_settime,
410*4882a593Smuzhiyun 	.read_alarm		= sunxi_rtc_getalarm,
411*4882a593Smuzhiyun 	.set_alarm		= sunxi_rtc_setalarm,
412*4882a593Smuzhiyun 	.alarm_irq_enable	= sunxi_rtc_alarm_irq_enable
413*4882a593Smuzhiyun };
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun static const struct of_device_id sunxi_rtc_dt_ids[] = {
416*4882a593Smuzhiyun 	{ .compatible = "allwinner,sun4i-a10-rtc", .data = &data_year_param[0] },
417*4882a593Smuzhiyun 	{ .compatible = "allwinner,sun7i-a20-rtc", .data = &data_year_param[1] },
418*4882a593Smuzhiyun 	{ /* sentinel */ },
419*4882a593Smuzhiyun };
420*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, sunxi_rtc_dt_ids);
421*4882a593Smuzhiyun 
sunxi_rtc_probe(struct platform_device * pdev)422*4882a593Smuzhiyun static int sunxi_rtc_probe(struct platform_device *pdev)
423*4882a593Smuzhiyun {
424*4882a593Smuzhiyun 	struct sunxi_rtc_dev *chip;
425*4882a593Smuzhiyun 	int ret;
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun 	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
428*4882a593Smuzhiyun 	if (!chip)
429*4882a593Smuzhiyun 		return -ENOMEM;
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun 	platform_set_drvdata(pdev, chip);
432*4882a593Smuzhiyun 	chip->dev = &pdev->dev;
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	chip->rtc = devm_rtc_allocate_device(&pdev->dev);
435*4882a593Smuzhiyun 	if (IS_ERR(chip->rtc))
436*4882a593Smuzhiyun 		return PTR_ERR(chip->rtc);
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun 	chip->base = devm_platform_ioremap_resource(pdev, 0);
439*4882a593Smuzhiyun 	if (IS_ERR(chip->base))
440*4882a593Smuzhiyun 		return PTR_ERR(chip->base);
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun 	chip->irq = platform_get_irq(pdev, 0);
443*4882a593Smuzhiyun 	if (chip->irq < 0)
444*4882a593Smuzhiyun 		return chip->irq;
445*4882a593Smuzhiyun 	ret = devm_request_irq(&pdev->dev, chip->irq, sunxi_rtc_alarmirq,
446*4882a593Smuzhiyun 			0, dev_name(&pdev->dev), chip);
447*4882a593Smuzhiyun 	if (ret) {
448*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Could not request IRQ\n");
449*4882a593Smuzhiyun 		return ret;
450*4882a593Smuzhiyun 	}
451*4882a593Smuzhiyun 
452*4882a593Smuzhiyun 	chip->data_year = of_device_get_match_data(&pdev->dev);
453*4882a593Smuzhiyun 	if (!chip->data_year) {
454*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Unable to setup RTC data\n");
455*4882a593Smuzhiyun 		return -ENODEV;
456*4882a593Smuzhiyun 	}
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun 	/* clear the alarm count value */
459*4882a593Smuzhiyun 	writel(0, chip->base + SUNXI_ALRM_DHMS);
460*4882a593Smuzhiyun 
461*4882a593Smuzhiyun 	/* disable alarm, not generate irq pending */
462*4882a593Smuzhiyun 	writel(0, chip->base + SUNXI_ALRM_EN);
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun 	/* disable alarm week/cnt irq, unset to cpu */
465*4882a593Smuzhiyun 	writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun 	/* clear alarm week/cnt irq pending */
468*4882a593Smuzhiyun 	writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND, chip->base +
469*4882a593Smuzhiyun 			SUNXI_ALRM_IRQ_STA);
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun 	chip->rtc->ops = &sunxi_rtc_ops;
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun 	return rtc_register_device(chip->rtc);
474*4882a593Smuzhiyun }
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun static struct platform_driver sunxi_rtc_driver = {
477*4882a593Smuzhiyun 	.probe		= sunxi_rtc_probe,
478*4882a593Smuzhiyun 	.driver		= {
479*4882a593Smuzhiyun 		.name		= "sunxi-rtc",
480*4882a593Smuzhiyun 		.of_match_table = sunxi_rtc_dt_ids,
481*4882a593Smuzhiyun 	},
482*4882a593Smuzhiyun };
483*4882a593Smuzhiyun 
484*4882a593Smuzhiyun module_platform_driver(sunxi_rtc_driver);
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun MODULE_DESCRIPTION("sunxi RTC driver");
487*4882a593Smuzhiyun MODULE_AUTHOR("Carlo Caione <carlo.caione@gmail.com>");
488*4882a593Smuzhiyun MODULE_LICENSE("GPL");
489