1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> 4*4882a593Smuzhiyun * http://www.simtec.co.uk/products/SWLINUX/ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * S3C2410 Internal RTC register definition 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASM_ARCH_REGS_RTC_H 10*4882a593Smuzhiyun #define __ASM_ARCH_REGS_RTC_H __FILE__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define S3C2410_RTCREG(x) (x) 13*4882a593Smuzhiyun #define S3C2410_INTP S3C2410_RTCREG(0x30) 14*4882a593Smuzhiyun #define S3C2410_INTP_ALM (1 << 1) 15*4882a593Smuzhiyun #define S3C2410_INTP_TIC (1 << 0) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define S3C2410_RTCCON S3C2410_RTCREG(0x40) 18*4882a593Smuzhiyun #define S3C2410_RTCCON_RTCEN (1 << 0) 19*4882a593Smuzhiyun #define S3C2410_RTCCON_CNTSEL (1 << 2) 20*4882a593Smuzhiyun #define S3C2410_RTCCON_CLKRST (1 << 3) 21*4882a593Smuzhiyun #define S3C2443_RTCCON_TICSEL (1 << 4) 22*4882a593Smuzhiyun #define S3C64XX_RTCCON_TICEN (1 << 8) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define S3C2410_TICNT S3C2410_RTCREG(0x44) 25*4882a593Smuzhiyun #define S3C2410_TICNT_ENABLE (1 << 7) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* S3C2443: tick count is 15 bit wide 28*4882a593Smuzhiyun * TICNT[6:0] contains upper 7 bits 29*4882a593Smuzhiyun * TICNT1[7:0] contains lower 8 bits 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun #define S3C2443_TICNT_PART(x) ((x & 0x7f00) >> 8) 32*4882a593Smuzhiyun #define S3C2443_TICNT1 S3C2410_RTCREG(0x4C) 33*4882a593Smuzhiyun #define S3C2443_TICNT1_PART(x) (x & 0xff) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* S3C2416: tick count is 32 bit wide 36*4882a593Smuzhiyun * TICNT[6:0] contains bits [14:8] 37*4882a593Smuzhiyun * TICNT1[7:0] contains lower 8 bits 38*4882a593Smuzhiyun * TICNT2[16:0] contains upper 17 bits 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun #define S3C2416_TICNT2 S3C2410_RTCREG(0x48) 41*4882a593Smuzhiyun #define S3C2416_TICNT2_PART(x) ((x & 0xffff8000) >> 15) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define S3C2410_RTCALM S3C2410_RTCREG(0x50) 44*4882a593Smuzhiyun #define S3C2410_RTCALM_ALMEN (1 << 6) 45*4882a593Smuzhiyun #define S3C2410_RTCALM_YEAREN (1 << 5) 46*4882a593Smuzhiyun #define S3C2410_RTCALM_MONEN (1 << 4) 47*4882a593Smuzhiyun #define S3C2410_RTCALM_DAYEN (1 << 3) 48*4882a593Smuzhiyun #define S3C2410_RTCALM_HOUREN (1 << 2) 49*4882a593Smuzhiyun #define S3C2410_RTCALM_MINEN (1 << 1) 50*4882a593Smuzhiyun #define S3C2410_RTCALM_SECEN (1 << 0) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define S3C2410_ALMSEC S3C2410_RTCREG(0x54) 53*4882a593Smuzhiyun #define S3C2410_ALMMIN S3C2410_RTCREG(0x58) 54*4882a593Smuzhiyun #define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define S3C2410_ALMDATE S3C2410_RTCREG(0x60) 57*4882a593Smuzhiyun #define S3C2410_ALMMON S3C2410_RTCREG(0x64) 58*4882a593Smuzhiyun #define S3C2410_ALMYEAR S3C2410_RTCREG(0x68) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define S3C2410_RTCSEC S3C2410_RTCREG(0x70) 61*4882a593Smuzhiyun #define S3C2410_RTCMIN S3C2410_RTCREG(0x74) 62*4882a593Smuzhiyun #define S3C2410_RTCHOUR S3C2410_RTCREG(0x78) 63*4882a593Smuzhiyun #define S3C2410_RTCDATE S3C2410_RTCREG(0x7c) 64*4882a593Smuzhiyun #define S3C2410_RTCMON S3C2410_RTCREG(0x84) 65*4882a593Smuzhiyun #define S3C2410_RTCYEAR S3C2410_RTCREG(0x88) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif /* __ASM_ARCH_REGS_RTC_H */ 68