1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Seiko Instruments S-35390A RTC Driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2007 Byron Bradley
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/rtc.h>
10*4882a593Smuzhiyun #include <linux/i2c.h>
11*4882a593Smuzhiyun #include <linux/bitrev.h>
12*4882a593Smuzhiyun #include <linux/bcd.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define S35390A_CMD_STATUS1 0
17*4882a593Smuzhiyun #define S35390A_CMD_STATUS2 1
18*4882a593Smuzhiyun #define S35390A_CMD_TIME1 2
19*4882a593Smuzhiyun #define S35390A_CMD_TIME2 3
20*4882a593Smuzhiyun #define S35390A_CMD_INT2_REG1 5
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define S35390A_BYTE_YEAR 0
23*4882a593Smuzhiyun #define S35390A_BYTE_MONTH 1
24*4882a593Smuzhiyun #define S35390A_BYTE_DAY 2
25*4882a593Smuzhiyun #define S35390A_BYTE_WDAY 3
26*4882a593Smuzhiyun #define S35390A_BYTE_HOURS 4
27*4882a593Smuzhiyun #define S35390A_BYTE_MINS 5
28*4882a593Smuzhiyun #define S35390A_BYTE_SECS 6
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define S35390A_ALRM_BYTE_WDAY 0
31*4882a593Smuzhiyun #define S35390A_ALRM_BYTE_HOURS 1
32*4882a593Smuzhiyun #define S35390A_ALRM_BYTE_MINS 2
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* flags for STATUS1 */
35*4882a593Smuzhiyun #define S35390A_FLAG_POC BIT(0)
36*4882a593Smuzhiyun #define S35390A_FLAG_BLD BIT(1)
37*4882a593Smuzhiyun #define S35390A_FLAG_INT2 BIT(2)
38*4882a593Smuzhiyun #define S35390A_FLAG_24H BIT(6)
39*4882a593Smuzhiyun #define S35390A_FLAG_RESET BIT(7)
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* flag for STATUS2 */
42*4882a593Smuzhiyun #define S35390A_FLAG_TEST BIT(0)
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* INT2 pin output mode */
45*4882a593Smuzhiyun #define S35390A_INT2_MODE_MASK 0x0E
46*4882a593Smuzhiyun #define S35390A_INT2_MODE_NOINTR 0x00
47*4882a593Smuzhiyun #define S35390A_INT2_MODE_ALARM BIT(1) /* INT2AE */
48*4882a593Smuzhiyun #define S35390A_INT2_MODE_PMIN_EDG BIT(2) /* INT2ME */
49*4882a593Smuzhiyun #define S35390A_INT2_MODE_FREQ BIT(3) /* INT2FE */
50*4882a593Smuzhiyun #define S35390A_INT2_MODE_PMIN (BIT(3) | BIT(2)) /* INT2FE | INT2ME */
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun static const struct i2c_device_id s35390a_id[] = {
53*4882a593Smuzhiyun { "s35390a", 0 },
54*4882a593Smuzhiyun { }
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, s35390a_id);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun static const struct of_device_id s35390a_of_match[] = {
59*4882a593Smuzhiyun { .compatible = "s35390a" },
60*4882a593Smuzhiyun { .compatible = "sii,s35390a" },
61*4882a593Smuzhiyun { }
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, s35390a_of_match);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun struct s35390a {
66*4882a593Smuzhiyun struct i2c_client *client[8];
67*4882a593Smuzhiyun struct rtc_device *rtc;
68*4882a593Smuzhiyun int twentyfourhour;
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
s35390a_set_reg(struct s35390a * s35390a,int reg,char * buf,int len)71*4882a593Smuzhiyun static int s35390a_set_reg(struct s35390a *s35390a, int reg, char *buf, int len)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun struct i2c_client *client = s35390a->client[reg];
74*4882a593Smuzhiyun struct i2c_msg msg[] = {
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun .addr = client->addr,
77*4882a593Smuzhiyun .len = len,
78*4882a593Smuzhiyun .buf = buf
79*4882a593Smuzhiyun },
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun if ((i2c_transfer(client->adapter, msg, 1)) != 1)
83*4882a593Smuzhiyun return -EIO;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun return 0;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
s35390a_get_reg(struct s35390a * s35390a,int reg,char * buf,int len)88*4882a593Smuzhiyun static int s35390a_get_reg(struct s35390a *s35390a, int reg, char *buf, int len)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun struct i2c_client *client = s35390a->client[reg];
91*4882a593Smuzhiyun struct i2c_msg msg[] = {
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun .addr = client->addr,
94*4882a593Smuzhiyun .flags = I2C_M_RD,
95*4882a593Smuzhiyun .len = len,
96*4882a593Smuzhiyun .buf = buf
97*4882a593Smuzhiyun },
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun if ((i2c_transfer(client->adapter, msg, 1)) != 1)
101*4882a593Smuzhiyun return -EIO;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun return 0;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
s35390a_init(struct s35390a * s35390a)106*4882a593Smuzhiyun static int s35390a_init(struct s35390a *s35390a)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun u8 buf;
109*4882a593Smuzhiyun int ret;
110*4882a593Smuzhiyun unsigned initcount = 0;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /*
113*4882a593Smuzhiyun * At least one of POC and BLD are set, so reinitialise chip. Keeping
114*4882a593Smuzhiyun * this information in the hardware to know later that the time isn't
115*4882a593Smuzhiyun * valid is unfortunately not possible because POC and BLD are cleared
116*4882a593Smuzhiyun * on read. So the reset is best done now.
117*4882a593Smuzhiyun *
118*4882a593Smuzhiyun * The 24H bit is kept over reset, so set it already here.
119*4882a593Smuzhiyun */
120*4882a593Smuzhiyun initialize:
121*4882a593Smuzhiyun buf = S35390A_FLAG_RESET | S35390A_FLAG_24H;
122*4882a593Smuzhiyun ret = s35390a_set_reg(s35390a, S35390A_CMD_STATUS1, &buf, 1);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun if (ret < 0)
125*4882a593Smuzhiyun return ret;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun ret = s35390a_get_reg(s35390a, S35390A_CMD_STATUS1, &buf, 1);
128*4882a593Smuzhiyun if (ret < 0)
129*4882a593Smuzhiyun return ret;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun if (buf & (S35390A_FLAG_POC | S35390A_FLAG_BLD)) {
132*4882a593Smuzhiyun /* Try up to five times to reset the chip */
133*4882a593Smuzhiyun if (initcount < 5) {
134*4882a593Smuzhiyun ++initcount;
135*4882a593Smuzhiyun goto initialize;
136*4882a593Smuzhiyun } else
137*4882a593Smuzhiyun return -EIO;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun return 1;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /*
144*4882a593Smuzhiyun * Returns <0 on error, 0 if rtc is setup fine and 1 if the chip was reset.
145*4882a593Smuzhiyun * To keep the information if an irq is pending, pass the value read from
146*4882a593Smuzhiyun * STATUS1 to the caller.
147*4882a593Smuzhiyun */
s35390a_read_status(struct s35390a * s35390a,char * status1)148*4882a593Smuzhiyun static int s35390a_read_status(struct s35390a *s35390a, char *status1)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun int ret;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun ret = s35390a_get_reg(s35390a, S35390A_CMD_STATUS1, status1, 1);
153*4882a593Smuzhiyun if (ret < 0)
154*4882a593Smuzhiyun return ret;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun if (*status1 & S35390A_FLAG_POC) {
157*4882a593Smuzhiyun /*
158*4882a593Smuzhiyun * Do not communicate for 0.5 seconds since the power-on
159*4882a593Smuzhiyun * detection circuit is in operation.
160*4882a593Smuzhiyun */
161*4882a593Smuzhiyun msleep(500);
162*4882a593Smuzhiyun return 1;
163*4882a593Smuzhiyun } else if (*status1 & S35390A_FLAG_BLD)
164*4882a593Smuzhiyun return 1;
165*4882a593Smuzhiyun /*
166*4882a593Smuzhiyun * If both POC and BLD are unset everything is fine.
167*4882a593Smuzhiyun */
168*4882a593Smuzhiyun return 0;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
s35390a_disable_test_mode(struct s35390a * s35390a)171*4882a593Smuzhiyun static int s35390a_disable_test_mode(struct s35390a *s35390a)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun char buf[1];
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun if (s35390a_get_reg(s35390a, S35390A_CMD_STATUS2, buf, sizeof(buf)) < 0)
176*4882a593Smuzhiyun return -EIO;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun if (!(buf[0] & S35390A_FLAG_TEST))
179*4882a593Smuzhiyun return 0;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun buf[0] &= ~S35390A_FLAG_TEST;
182*4882a593Smuzhiyun return s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, buf, sizeof(buf));
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun
s35390a_hr2reg(struct s35390a * s35390a,int hour)185*4882a593Smuzhiyun static char s35390a_hr2reg(struct s35390a *s35390a, int hour)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun if (s35390a->twentyfourhour)
188*4882a593Smuzhiyun return bin2bcd(hour);
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun if (hour < 12)
191*4882a593Smuzhiyun return bin2bcd(hour);
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun return 0x40 | bin2bcd(hour - 12);
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
s35390a_reg2hr(struct s35390a * s35390a,char reg)196*4882a593Smuzhiyun static int s35390a_reg2hr(struct s35390a *s35390a, char reg)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun unsigned hour;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun if (s35390a->twentyfourhour)
201*4882a593Smuzhiyun return bcd2bin(reg & 0x3f);
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun hour = bcd2bin(reg & 0x3f);
204*4882a593Smuzhiyun if (reg & 0x40)
205*4882a593Smuzhiyun hour += 12;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun return hour;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
s35390a_rtc_set_time(struct device * dev,struct rtc_time * tm)210*4882a593Smuzhiyun static int s35390a_rtc_set_time(struct device *dev, struct rtc_time *tm)
211*4882a593Smuzhiyun {
212*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
213*4882a593Smuzhiyun struct s35390a *s35390a = i2c_get_clientdata(client);
214*4882a593Smuzhiyun int i, err;
215*4882a593Smuzhiyun char buf[7], status;
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d mday=%d, "
218*4882a593Smuzhiyun "mon=%d, year=%d, wday=%d\n", __func__, tm->tm_sec,
219*4882a593Smuzhiyun tm->tm_min, tm->tm_hour, tm->tm_mday, tm->tm_mon, tm->tm_year,
220*4882a593Smuzhiyun tm->tm_wday);
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun if (s35390a_read_status(s35390a, &status) == 1)
223*4882a593Smuzhiyun s35390a_init(s35390a);
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun buf[S35390A_BYTE_YEAR] = bin2bcd(tm->tm_year - 100);
226*4882a593Smuzhiyun buf[S35390A_BYTE_MONTH] = bin2bcd(tm->tm_mon + 1);
227*4882a593Smuzhiyun buf[S35390A_BYTE_DAY] = bin2bcd(tm->tm_mday);
228*4882a593Smuzhiyun buf[S35390A_BYTE_WDAY] = bin2bcd(tm->tm_wday);
229*4882a593Smuzhiyun buf[S35390A_BYTE_HOURS] = s35390a_hr2reg(s35390a, tm->tm_hour);
230*4882a593Smuzhiyun buf[S35390A_BYTE_MINS] = bin2bcd(tm->tm_min);
231*4882a593Smuzhiyun buf[S35390A_BYTE_SECS] = bin2bcd(tm->tm_sec);
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun /* This chip expects the bits of each byte to be in reverse order */
234*4882a593Smuzhiyun for (i = 0; i < 7; ++i)
235*4882a593Smuzhiyun buf[i] = bitrev8(buf[i]);
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun err = s35390a_set_reg(s35390a, S35390A_CMD_TIME1, buf, sizeof(buf));
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun return err;
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun
s35390a_rtc_read_time(struct device * dev,struct rtc_time * tm)242*4882a593Smuzhiyun static int s35390a_rtc_read_time(struct device *dev, struct rtc_time *tm)
243*4882a593Smuzhiyun {
244*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
245*4882a593Smuzhiyun struct s35390a *s35390a = i2c_get_clientdata(client);
246*4882a593Smuzhiyun char buf[7], status;
247*4882a593Smuzhiyun int i, err;
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun if (s35390a_read_status(s35390a, &status) == 1)
250*4882a593Smuzhiyun return -EINVAL;
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun err = s35390a_get_reg(s35390a, S35390A_CMD_TIME1, buf, sizeof(buf));
253*4882a593Smuzhiyun if (err < 0)
254*4882a593Smuzhiyun return err;
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun /* This chip returns the bits of each byte in reverse order */
257*4882a593Smuzhiyun for (i = 0; i < 7; ++i)
258*4882a593Smuzhiyun buf[i] = bitrev8(buf[i]);
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun tm->tm_sec = bcd2bin(buf[S35390A_BYTE_SECS]);
261*4882a593Smuzhiyun tm->tm_min = bcd2bin(buf[S35390A_BYTE_MINS]);
262*4882a593Smuzhiyun tm->tm_hour = s35390a_reg2hr(s35390a, buf[S35390A_BYTE_HOURS]);
263*4882a593Smuzhiyun tm->tm_wday = bcd2bin(buf[S35390A_BYTE_WDAY]);
264*4882a593Smuzhiyun tm->tm_mday = bcd2bin(buf[S35390A_BYTE_DAY]);
265*4882a593Smuzhiyun tm->tm_mon = bcd2bin(buf[S35390A_BYTE_MONTH]) - 1;
266*4882a593Smuzhiyun tm->tm_year = bcd2bin(buf[S35390A_BYTE_YEAR]) + 100;
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, mday=%d, "
269*4882a593Smuzhiyun "mon=%d, year=%d, wday=%d\n", __func__, tm->tm_sec,
270*4882a593Smuzhiyun tm->tm_min, tm->tm_hour, tm->tm_mday, tm->tm_mon, tm->tm_year,
271*4882a593Smuzhiyun tm->tm_wday);
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun return 0;
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun
s35390a_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alm)276*4882a593Smuzhiyun static int s35390a_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
277*4882a593Smuzhiyun {
278*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
279*4882a593Smuzhiyun struct s35390a *s35390a = i2c_get_clientdata(client);
280*4882a593Smuzhiyun char buf[3], sts = 0;
281*4882a593Smuzhiyun int err, i;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun dev_dbg(&client->dev, "%s: alm is secs=%d, mins=%d, hours=%d mday=%d, "\
284*4882a593Smuzhiyun "mon=%d, year=%d, wday=%d\n", __func__, alm->time.tm_sec,
285*4882a593Smuzhiyun alm->time.tm_min, alm->time.tm_hour, alm->time.tm_mday,
286*4882a593Smuzhiyun alm->time.tm_mon, alm->time.tm_year, alm->time.tm_wday);
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun if (alm->time.tm_sec != 0)
289*4882a593Smuzhiyun dev_warn(&client->dev, "Alarms are only supported on a per minute basis!\n");
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun /* disable interrupt (which deasserts the irq line) */
292*4882a593Smuzhiyun err = s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, &sts, sizeof(sts));
293*4882a593Smuzhiyun if (err < 0)
294*4882a593Smuzhiyun return err;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun /* clear pending interrupt (in STATUS1 only), if any */
297*4882a593Smuzhiyun err = s35390a_get_reg(s35390a, S35390A_CMD_STATUS1, &sts, sizeof(sts));
298*4882a593Smuzhiyun if (err < 0)
299*4882a593Smuzhiyun return err;
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun if (alm->enabled)
302*4882a593Smuzhiyun sts = S35390A_INT2_MODE_ALARM;
303*4882a593Smuzhiyun else
304*4882a593Smuzhiyun sts = S35390A_INT2_MODE_NOINTR;
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun /* set interupt mode*/
307*4882a593Smuzhiyun err = s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, &sts, sizeof(sts));
308*4882a593Smuzhiyun if (err < 0)
309*4882a593Smuzhiyun return err;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun if (alm->time.tm_wday != -1)
312*4882a593Smuzhiyun buf[S35390A_ALRM_BYTE_WDAY] = bin2bcd(alm->time.tm_wday) | 0x80;
313*4882a593Smuzhiyun else
314*4882a593Smuzhiyun buf[S35390A_ALRM_BYTE_WDAY] = 0;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun buf[S35390A_ALRM_BYTE_HOURS] = s35390a_hr2reg(s35390a,
317*4882a593Smuzhiyun alm->time.tm_hour) | 0x80;
318*4882a593Smuzhiyun buf[S35390A_ALRM_BYTE_MINS] = bin2bcd(alm->time.tm_min) | 0x80;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun if (alm->time.tm_hour >= 12)
321*4882a593Smuzhiyun buf[S35390A_ALRM_BYTE_HOURS] |= 0x40;
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun for (i = 0; i < 3; ++i)
324*4882a593Smuzhiyun buf[i] = bitrev8(buf[i]);
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun err = s35390a_set_reg(s35390a, S35390A_CMD_INT2_REG1, buf,
327*4882a593Smuzhiyun sizeof(buf));
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun return err;
330*4882a593Smuzhiyun }
331*4882a593Smuzhiyun
s35390a_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alm)332*4882a593Smuzhiyun static int s35390a_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
333*4882a593Smuzhiyun {
334*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
335*4882a593Smuzhiyun struct s35390a *s35390a = i2c_get_clientdata(client);
336*4882a593Smuzhiyun char buf[3], sts;
337*4882a593Smuzhiyun int i, err;
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun err = s35390a_get_reg(s35390a, S35390A_CMD_STATUS2, &sts, sizeof(sts));
340*4882a593Smuzhiyun if (err < 0)
341*4882a593Smuzhiyun return err;
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun if ((sts & S35390A_INT2_MODE_MASK) != S35390A_INT2_MODE_ALARM) {
344*4882a593Smuzhiyun /*
345*4882a593Smuzhiyun * When the alarm isn't enabled, the register to configure
346*4882a593Smuzhiyun * the alarm time isn't accessible.
347*4882a593Smuzhiyun */
348*4882a593Smuzhiyun alm->enabled = 0;
349*4882a593Smuzhiyun return 0;
350*4882a593Smuzhiyun } else {
351*4882a593Smuzhiyun alm->enabled = 1;
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun err = s35390a_get_reg(s35390a, S35390A_CMD_INT2_REG1, buf, sizeof(buf));
355*4882a593Smuzhiyun if (err < 0)
356*4882a593Smuzhiyun return err;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun /* This chip returns the bits of each byte in reverse order */
359*4882a593Smuzhiyun for (i = 0; i < 3; ++i)
360*4882a593Smuzhiyun buf[i] = bitrev8(buf[i]);
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun /*
363*4882a593Smuzhiyun * B0 of the three matching registers is an enable flag. Iff it is set
364*4882a593Smuzhiyun * the configured value is used for matching.
365*4882a593Smuzhiyun */
366*4882a593Smuzhiyun if (buf[S35390A_ALRM_BYTE_WDAY] & 0x80)
367*4882a593Smuzhiyun alm->time.tm_wday =
368*4882a593Smuzhiyun bcd2bin(buf[S35390A_ALRM_BYTE_WDAY] & ~0x80);
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun if (buf[S35390A_ALRM_BYTE_HOURS] & 0x80)
371*4882a593Smuzhiyun alm->time.tm_hour =
372*4882a593Smuzhiyun s35390a_reg2hr(s35390a,
373*4882a593Smuzhiyun buf[S35390A_ALRM_BYTE_HOURS] & ~0x80);
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun if (buf[S35390A_ALRM_BYTE_MINS] & 0x80)
376*4882a593Smuzhiyun alm->time.tm_min = bcd2bin(buf[S35390A_ALRM_BYTE_MINS] & ~0x80);
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun /* alarm triggers always at s=0 */
379*4882a593Smuzhiyun alm->time.tm_sec = 0;
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun dev_dbg(&client->dev, "%s: alm is mins=%d, hours=%d, wday=%d\n",
382*4882a593Smuzhiyun __func__, alm->time.tm_min, alm->time.tm_hour,
383*4882a593Smuzhiyun alm->time.tm_wday);
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun return 0;
386*4882a593Smuzhiyun }
387*4882a593Smuzhiyun
s35390a_rtc_ioctl(struct device * dev,unsigned int cmd,unsigned long arg)388*4882a593Smuzhiyun static int s35390a_rtc_ioctl(struct device *dev, unsigned int cmd,
389*4882a593Smuzhiyun unsigned long arg)
390*4882a593Smuzhiyun {
391*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
392*4882a593Smuzhiyun struct s35390a *s35390a = i2c_get_clientdata(client);
393*4882a593Smuzhiyun char sts;
394*4882a593Smuzhiyun int err;
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun switch (cmd) {
397*4882a593Smuzhiyun case RTC_VL_READ:
398*4882a593Smuzhiyun /* s35390a_reset set lowvoltage flag and init RTC if needed */
399*4882a593Smuzhiyun err = s35390a_read_status(s35390a, &sts);
400*4882a593Smuzhiyun if (err < 0)
401*4882a593Smuzhiyun return err;
402*4882a593Smuzhiyun if (copy_to_user((void __user *)arg, &err, sizeof(int)))
403*4882a593Smuzhiyun return -EFAULT;
404*4882a593Smuzhiyun break;
405*4882a593Smuzhiyun case RTC_VL_CLR:
406*4882a593Smuzhiyun /* update flag and clear register */
407*4882a593Smuzhiyun err = s35390a_init(s35390a);
408*4882a593Smuzhiyun if (err < 0)
409*4882a593Smuzhiyun return err;
410*4882a593Smuzhiyun break;
411*4882a593Smuzhiyun default:
412*4882a593Smuzhiyun return -ENOIOCTLCMD;
413*4882a593Smuzhiyun }
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun return 0;
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun static const struct rtc_class_ops s35390a_rtc_ops = {
419*4882a593Smuzhiyun .read_time = s35390a_rtc_read_time,
420*4882a593Smuzhiyun .set_time = s35390a_rtc_set_time,
421*4882a593Smuzhiyun .set_alarm = s35390a_rtc_set_alarm,
422*4882a593Smuzhiyun .read_alarm = s35390a_rtc_read_alarm,
423*4882a593Smuzhiyun .ioctl = s35390a_rtc_ioctl,
424*4882a593Smuzhiyun };
425*4882a593Smuzhiyun
s35390a_probe(struct i2c_client * client,const struct i2c_device_id * id)426*4882a593Smuzhiyun static int s35390a_probe(struct i2c_client *client,
427*4882a593Smuzhiyun const struct i2c_device_id *id)
428*4882a593Smuzhiyun {
429*4882a593Smuzhiyun int err, err_read;
430*4882a593Smuzhiyun unsigned int i;
431*4882a593Smuzhiyun struct s35390a *s35390a;
432*4882a593Smuzhiyun char buf, status1;
433*4882a593Smuzhiyun struct device *dev = &client->dev;
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
436*4882a593Smuzhiyun return -ENODEV;
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun s35390a = devm_kzalloc(dev, sizeof(struct s35390a), GFP_KERNEL);
439*4882a593Smuzhiyun if (!s35390a)
440*4882a593Smuzhiyun return -ENOMEM;
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun s35390a->client[0] = client;
443*4882a593Smuzhiyun i2c_set_clientdata(client, s35390a);
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun /* This chip uses multiple addresses, use dummy devices for them */
446*4882a593Smuzhiyun for (i = 1; i < 8; ++i) {
447*4882a593Smuzhiyun s35390a->client[i] = devm_i2c_new_dummy_device(dev,
448*4882a593Smuzhiyun client->adapter,
449*4882a593Smuzhiyun client->addr + i);
450*4882a593Smuzhiyun if (IS_ERR(s35390a->client[i])) {
451*4882a593Smuzhiyun dev_err(dev, "Address %02x unavailable\n",
452*4882a593Smuzhiyun client->addr + i);
453*4882a593Smuzhiyun return PTR_ERR(s35390a->client[i]);
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun }
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun s35390a->rtc = devm_rtc_allocate_device(dev);
458*4882a593Smuzhiyun if (IS_ERR(s35390a->rtc))
459*4882a593Smuzhiyun return PTR_ERR(s35390a->rtc);
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun err_read = s35390a_read_status(s35390a, &status1);
462*4882a593Smuzhiyun if (err_read < 0) {
463*4882a593Smuzhiyun dev_err(dev, "error resetting chip\n");
464*4882a593Smuzhiyun return err_read;
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun if (status1 & S35390A_FLAG_24H)
468*4882a593Smuzhiyun s35390a->twentyfourhour = 1;
469*4882a593Smuzhiyun else
470*4882a593Smuzhiyun s35390a->twentyfourhour = 0;
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun if (status1 & S35390A_FLAG_INT2) {
473*4882a593Smuzhiyun /* disable alarm (and maybe test mode) */
474*4882a593Smuzhiyun buf = 0;
475*4882a593Smuzhiyun err = s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, &buf, 1);
476*4882a593Smuzhiyun if (err < 0) {
477*4882a593Smuzhiyun dev_err(dev, "error disabling alarm");
478*4882a593Smuzhiyun return err;
479*4882a593Smuzhiyun }
480*4882a593Smuzhiyun } else {
481*4882a593Smuzhiyun err = s35390a_disable_test_mode(s35390a);
482*4882a593Smuzhiyun if (err < 0) {
483*4882a593Smuzhiyun dev_err(dev, "error disabling test mode\n");
484*4882a593Smuzhiyun return err;
485*4882a593Smuzhiyun }
486*4882a593Smuzhiyun }
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun device_set_wakeup_capable(dev, 1);
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun s35390a->rtc->ops = &s35390a_rtc_ops;
491*4882a593Smuzhiyun s35390a->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
492*4882a593Smuzhiyun s35390a->rtc->range_max = RTC_TIMESTAMP_END_2099;
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun /* supports per-minute alarms only, therefore set uie_unsupported */
495*4882a593Smuzhiyun s35390a->rtc->uie_unsupported = 1;
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun if (status1 & S35390A_FLAG_INT2)
498*4882a593Smuzhiyun rtc_update_irq(s35390a->rtc, 1, RTC_AF);
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun return rtc_register_device(s35390a->rtc);
501*4882a593Smuzhiyun }
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun static struct i2c_driver s35390a_driver = {
504*4882a593Smuzhiyun .driver = {
505*4882a593Smuzhiyun .name = "rtc-s35390a",
506*4882a593Smuzhiyun .of_match_table = of_match_ptr(s35390a_of_match),
507*4882a593Smuzhiyun },
508*4882a593Smuzhiyun .probe = s35390a_probe,
509*4882a593Smuzhiyun .id_table = s35390a_id,
510*4882a593Smuzhiyun };
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun module_i2c_driver(s35390a_driver);
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun MODULE_AUTHOR("Byron Bradley <byron.bbradley@gmail.com>");
515*4882a593Smuzhiyun MODULE_DESCRIPTION("S35390A RTC driver");
516*4882a593Smuzhiyun MODULE_LICENSE("GPL");
517