1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for the Epson RTC module RX-6110 SA
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright(C) 2015 Pengutronix, Steffen Trumtrar <kernel@pengutronix.de>
6*4882a593Smuzhiyun * Copyright(C) SEIKO EPSON CORPORATION 2013. All rights reserved.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/bcd.h>
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/of_gpio.h>
14*4882a593Smuzhiyun #include <linux/regmap.h>
15*4882a593Smuzhiyun #include <linux/rtc.h>
16*4882a593Smuzhiyun #include <linux/of.h>
17*4882a593Smuzhiyun #include <linux/of_device.h>
18*4882a593Smuzhiyun #include <linux/spi/spi.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /* RX-6110 Register definitions */
21*4882a593Smuzhiyun #define RX6110_REG_SEC 0x10
22*4882a593Smuzhiyun #define RX6110_REG_MIN 0x11
23*4882a593Smuzhiyun #define RX6110_REG_HOUR 0x12
24*4882a593Smuzhiyun #define RX6110_REG_WDAY 0x13
25*4882a593Smuzhiyun #define RX6110_REG_MDAY 0x14
26*4882a593Smuzhiyun #define RX6110_REG_MONTH 0x15
27*4882a593Smuzhiyun #define RX6110_REG_YEAR 0x16
28*4882a593Smuzhiyun #define RX6110_REG_RES1 0x17
29*4882a593Smuzhiyun #define RX6110_REG_ALMIN 0x18
30*4882a593Smuzhiyun #define RX6110_REG_ALHOUR 0x19
31*4882a593Smuzhiyun #define RX6110_REG_ALWDAY 0x1A
32*4882a593Smuzhiyun #define RX6110_REG_TCOUNT0 0x1B
33*4882a593Smuzhiyun #define RX6110_REG_TCOUNT1 0x1C
34*4882a593Smuzhiyun #define RX6110_REG_EXT 0x1D
35*4882a593Smuzhiyun #define RX6110_REG_FLAG 0x1E
36*4882a593Smuzhiyun #define RX6110_REG_CTRL 0x1F
37*4882a593Smuzhiyun #define RX6110_REG_USER0 0x20
38*4882a593Smuzhiyun #define RX6110_REG_USER1 0x21
39*4882a593Smuzhiyun #define RX6110_REG_USER2 0x22
40*4882a593Smuzhiyun #define RX6110_REG_USER3 0x23
41*4882a593Smuzhiyun #define RX6110_REG_USER4 0x24
42*4882a593Smuzhiyun #define RX6110_REG_USER5 0x25
43*4882a593Smuzhiyun #define RX6110_REG_USER6 0x26
44*4882a593Smuzhiyun #define RX6110_REG_USER7 0x27
45*4882a593Smuzhiyun #define RX6110_REG_USER8 0x28
46*4882a593Smuzhiyun #define RX6110_REG_USER9 0x29
47*4882a593Smuzhiyun #define RX6110_REG_USERA 0x2A
48*4882a593Smuzhiyun #define RX6110_REG_USERB 0x2B
49*4882a593Smuzhiyun #define RX6110_REG_USERC 0x2C
50*4882a593Smuzhiyun #define RX6110_REG_USERD 0x2D
51*4882a593Smuzhiyun #define RX6110_REG_USERE 0x2E
52*4882a593Smuzhiyun #define RX6110_REG_USERF 0x2F
53*4882a593Smuzhiyun #define RX6110_REG_RES2 0x30
54*4882a593Smuzhiyun #define RX6110_REG_RES3 0x31
55*4882a593Smuzhiyun #define RX6110_REG_IRQ 0x32
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #define RX6110_BIT_ALARM_EN BIT(7)
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* Extension Register (1Dh) bit positions */
60*4882a593Smuzhiyun #define RX6110_BIT_EXT_TSEL0 BIT(0)
61*4882a593Smuzhiyun #define RX6110_BIT_EXT_TSEL1 BIT(1)
62*4882a593Smuzhiyun #define RX6110_BIT_EXT_TSEL2 BIT(2)
63*4882a593Smuzhiyun #define RX6110_BIT_EXT_WADA BIT(3)
64*4882a593Smuzhiyun #define RX6110_BIT_EXT_TE BIT(4)
65*4882a593Smuzhiyun #define RX6110_BIT_EXT_USEL BIT(5)
66*4882a593Smuzhiyun #define RX6110_BIT_EXT_FSEL0 BIT(6)
67*4882a593Smuzhiyun #define RX6110_BIT_EXT_FSEL1 BIT(7)
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* Flag Register (1Eh) bit positions */
70*4882a593Smuzhiyun #define RX6110_BIT_FLAG_VLF BIT(1)
71*4882a593Smuzhiyun #define RX6110_BIT_FLAG_AF BIT(3)
72*4882a593Smuzhiyun #define RX6110_BIT_FLAG_TF BIT(4)
73*4882a593Smuzhiyun #define RX6110_BIT_FLAG_UF BIT(5)
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Control Register (1Fh) bit positions */
76*4882a593Smuzhiyun #define RX6110_BIT_CTRL_TBKE BIT(0)
77*4882a593Smuzhiyun #define RX6110_BIT_CTRL_TBKON BIT(1)
78*4882a593Smuzhiyun #define RX6110_BIT_CTRL_TSTP BIT(2)
79*4882a593Smuzhiyun #define RX6110_BIT_CTRL_AIE BIT(3)
80*4882a593Smuzhiyun #define RX6110_BIT_CTRL_TIE BIT(4)
81*4882a593Smuzhiyun #define RX6110_BIT_CTRL_UIE BIT(5)
82*4882a593Smuzhiyun #define RX6110_BIT_CTRL_STOP BIT(6)
83*4882a593Smuzhiyun #define RX6110_BIT_CTRL_TEST BIT(7)
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun enum {
86*4882a593Smuzhiyun RTC_SEC = 0,
87*4882a593Smuzhiyun RTC_MIN,
88*4882a593Smuzhiyun RTC_HOUR,
89*4882a593Smuzhiyun RTC_WDAY,
90*4882a593Smuzhiyun RTC_MDAY,
91*4882a593Smuzhiyun RTC_MONTH,
92*4882a593Smuzhiyun RTC_YEAR,
93*4882a593Smuzhiyun RTC_NR_TIME
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun #define RX6110_DRIVER_NAME "rx6110"
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun struct rx6110_data {
99*4882a593Smuzhiyun struct rtc_device *rtc;
100*4882a593Smuzhiyun struct regmap *regmap;
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /**
104*4882a593Smuzhiyun * rx6110_rtc_tm_to_data - convert rtc_time to native time encoding
105*4882a593Smuzhiyun *
106*4882a593Smuzhiyun * @tm: holds date and time
107*4882a593Smuzhiyun * @data: holds the encoding in rx6110 native form
108*4882a593Smuzhiyun */
rx6110_rtc_tm_to_data(struct rtc_time * tm,u8 * data)109*4882a593Smuzhiyun static int rx6110_rtc_tm_to_data(struct rtc_time *tm, u8 *data)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun pr_debug("%s: date %ptRr\n", __func__, tm);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /*
114*4882a593Smuzhiyun * The year in the RTC is a value between 0 and 99.
115*4882a593Smuzhiyun * Assume that this represents the current century
116*4882a593Smuzhiyun * and disregard all other values.
117*4882a593Smuzhiyun */
118*4882a593Smuzhiyun if (tm->tm_year < 100 || tm->tm_year >= 200)
119*4882a593Smuzhiyun return -EINVAL;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun data[RTC_SEC] = bin2bcd(tm->tm_sec);
122*4882a593Smuzhiyun data[RTC_MIN] = bin2bcd(tm->tm_min);
123*4882a593Smuzhiyun data[RTC_HOUR] = bin2bcd(tm->tm_hour);
124*4882a593Smuzhiyun data[RTC_WDAY] = BIT(bin2bcd(tm->tm_wday));
125*4882a593Smuzhiyun data[RTC_MDAY] = bin2bcd(tm->tm_mday);
126*4882a593Smuzhiyun data[RTC_MONTH] = bin2bcd(tm->tm_mon + 1);
127*4882a593Smuzhiyun data[RTC_YEAR] = bin2bcd(tm->tm_year % 100);
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun return 0;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun /**
133*4882a593Smuzhiyun * rx6110_data_to_rtc_tm - convert native time encoding to rtc_time
134*4882a593Smuzhiyun *
135*4882a593Smuzhiyun * @data: holds the encoding in rx6110 native form
136*4882a593Smuzhiyun * @tm: holds date and time
137*4882a593Smuzhiyun */
rx6110_data_to_rtc_tm(u8 * data,struct rtc_time * tm)138*4882a593Smuzhiyun static int rx6110_data_to_rtc_tm(u8 *data, struct rtc_time *tm)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun tm->tm_sec = bcd2bin(data[RTC_SEC] & 0x7f);
141*4882a593Smuzhiyun tm->tm_min = bcd2bin(data[RTC_MIN] & 0x7f);
142*4882a593Smuzhiyun /* only 24-hour clock */
143*4882a593Smuzhiyun tm->tm_hour = bcd2bin(data[RTC_HOUR] & 0x3f);
144*4882a593Smuzhiyun tm->tm_wday = ffs(data[RTC_WDAY] & 0x7f);
145*4882a593Smuzhiyun tm->tm_mday = bcd2bin(data[RTC_MDAY] & 0x3f);
146*4882a593Smuzhiyun tm->tm_mon = bcd2bin(data[RTC_MONTH] & 0x1f) - 1;
147*4882a593Smuzhiyun tm->tm_year = bcd2bin(data[RTC_YEAR]) + 100;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun pr_debug("%s: date %ptRr\n", __func__, tm);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun /*
152*4882a593Smuzhiyun * The year in the RTC is a value between 0 and 99.
153*4882a593Smuzhiyun * Assume that this represents the current century
154*4882a593Smuzhiyun * and disregard all other values.
155*4882a593Smuzhiyun */
156*4882a593Smuzhiyun if (tm->tm_year < 100 || tm->tm_year >= 200)
157*4882a593Smuzhiyun return -EINVAL;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun return 0;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun /**
163*4882a593Smuzhiyun * rx6110_set_time - set the current time in the rx6110 registers
164*4882a593Smuzhiyun *
165*4882a593Smuzhiyun * @dev: the rtc device in use
166*4882a593Smuzhiyun * @tm: holds date and time
167*4882a593Smuzhiyun *
168*4882a593Smuzhiyun * BUG: The HW assumes every year that is a multiple of 4 to be a leap
169*4882a593Smuzhiyun * year. Next time this is wrong is 2100, which will not be a leap year
170*4882a593Smuzhiyun *
171*4882a593Smuzhiyun * Note: If STOP is not set/cleared, the clock will start when the seconds
172*4882a593Smuzhiyun * register is written
173*4882a593Smuzhiyun *
174*4882a593Smuzhiyun */
rx6110_set_time(struct device * dev,struct rtc_time * tm)175*4882a593Smuzhiyun static int rx6110_set_time(struct device *dev, struct rtc_time *tm)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun struct rx6110_data *rx6110 = dev_get_drvdata(dev);
178*4882a593Smuzhiyun u8 data[RTC_NR_TIME];
179*4882a593Smuzhiyun int ret;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun ret = rx6110_rtc_tm_to_data(tm, data);
182*4882a593Smuzhiyun if (ret < 0)
183*4882a593Smuzhiyun return ret;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun /* set STOP bit before changing clock/calendar */
186*4882a593Smuzhiyun ret = regmap_update_bits(rx6110->regmap, RX6110_REG_CTRL,
187*4882a593Smuzhiyun RX6110_BIT_CTRL_STOP, RX6110_BIT_CTRL_STOP);
188*4882a593Smuzhiyun if (ret)
189*4882a593Smuzhiyun return ret;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun ret = regmap_bulk_write(rx6110->regmap, RX6110_REG_SEC, data,
192*4882a593Smuzhiyun RTC_NR_TIME);
193*4882a593Smuzhiyun if (ret)
194*4882a593Smuzhiyun return ret;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun /* The time in the RTC is valid. Be sure to have VLF cleared. */
197*4882a593Smuzhiyun ret = regmap_update_bits(rx6110->regmap, RX6110_REG_FLAG,
198*4882a593Smuzhiyun RX6110_BIT_FLAG_VLF, 0);
199*4882a593Smuzhiyun if (ret)
200*4882a593Smuzhiyun return ret;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun /* clear STOP bit after changing clock/calendar */
203*4882a593Smuzhiyun ret = regmap_update_bits(rx6110->regmap, RX6110_REG_CTRL,
204*4882a593Smuzhiyun RX6110_BIT_CTRL_STOP, 0);
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun return ret;
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun /**
210*4882a593Smuzhiyun * rx6110_get_time - get the current time from the rx6110 registers
211*4882a593Smuzhiyun * @dev: the rtc device in use
212*4882a593Smuzhiyun * @tm: holds date and time
213*4882a593Smuzhiyun */
rx6110_get_time(struct device * dev,struct rtc_time * tm)214*4882a593Smuzhiyun static int rx6110_get_time(struct device *dev, struct rtc_time *tm)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun struct rx6110_data *rx6110 = dev_get_drvdata(dev);
217*4882a593Smuzhiyun u8 data[RTC_NR_TIME];
218*4882a593Smuzhiyun int flags;
219*4882a593Smuzhiyun int ret;
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun ret = regmap_read(rx6110->regmap, RX6110_REG_FLAG, &flags);
222*4882a593Smuzhiyun if (ret)
223*4882a593Smuzhiyun return -EINVAL;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun /* check for VLF Flag (set at power-on) */
226*4882a593Smuzhiyun if ((flags & RX6110_BIT_FLAG_VLF)) {
227*4882a593Smuzhiyun dev_warn(dev, "Voltage low, data is invalid.\n");
228*4882a593Smuzhiyun return -EINVAL;
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun /* read registers to date */
232*4882a593Smuzhiyun ret = regmap_bulk_read(rx6110->regmap, RX6110_REG_SEC, data,
233*4882a593Smuzhiyun RTC_NR_TIME);
234*4882a593Smuzhiyun if (ret)
235*4882a593Smuzhiyun return ret;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun ret = rx6110_data_to_rtc_tm(data, tm);
238*4882a593Smuzhiyun if (ret)
239*4882a593Smuzhiyun return ret;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun dev_dbg(dev, "%s: date %ptRr\n", __func__, tm);
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun return 0;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun static const struct reg_sequence rx6110_default_regs[] = {
247*4882a593Smuzhiyun { RX6110_REG_RES1, 0xB8 },
248*4882a593Smuzhiyun { RX6110_REG_RES2, 0x00 },
249*4882a593Smuzhiyun { RX6110_REG_RES3, 0x10 },
250*4882a593Smuzhiyun { RX6110_REG_IRQ, 0x00 },
251*4882a593Smuzhiyun { RX6110_REG_ALMIN, 0x00 },
252*4882a593Smuzhiyun { RX6110_REG_ALHOUR, 0x00 },
253*4882a593Smuzhiyun { RX6110_REG_ALWDAY, 0x00 },
254*4882a593Smuzhiyun };
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun /**
257*4882a593Smuzhiyun * rx6110_init - initialize the rx6110 registers
258*4882a593Smuzhiyun *
259*4882a593Smuzhiyun * @rx6110: pointer to the rx6110 struct in use
260*4882a593Smuzhiyun *
261*4882a593Smuzhiyun */
rx6110_init(struct rx6110_data * rx6110)262*4882a593Smuzhiyun static int rx6110_init(struct rx6110_data *rx6110)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun struct rtc_device *rtc = rx6110->rtc;
265*4882a593Smuzhiyun int flags;
266*4882a593Smuzhiyun int ret;
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun ret = regmap_update_bits(rx6110->regmap, RX6110_REG_EXT,
269*4882a593Smuzhiyun RX6110_BIT_EXT_TE, 0);
270*4882a593Smuzhiyun if (ret)
271*4882a593Smuzhiyun return ret;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun ret = regmap_register_patch(rx6110->regmap, rx6110_default_regs,
274*4882a593Smuzhiyun ARRAY_SIZE(rx6110_default_regs));
275*4882a593Smuzhiyun if (ret)
276*4882a593Smuzhiyun return ret;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun ret = regmap_read(rx6110->regmap, RX6110_REG_FLAG, &flags);
279*4882a593Smuzhiyun if (ret)
280*4882a593Smuzhiyun return ret;
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun /* check for VLF Flag (set at power-on) */
283*4882a593Smuzhiyun if ((flags & RX6110_BIT_FLAG_VLF))
284*4882a593Smuzhiyun dev_warn(&rtc->dev, "Voltage low, data loss detected.\n");
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun /* check for Alarm Flag */
287*4882a593Smuzhiyun if (flags & RX6110_BIT_FLAG_AF)
288*4882a593Smuzhiyun dev_warn(&rtc->dev, "An alarm may have been missed.\n");
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun /* check for Periodic Timer Flag */
291*4882a593Smuzhiyun if (flags & RX6110_BIT_FLAG_TF)
292*4882a593Smuzhiyun dev_warn(&rtc->dev, "Periodic timer was detected\n");
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun /* check for Update Timer Flag */
295*4882a593Smuzhiyun if (flags & RX6110_BIT_FLAG_UF)
296*4882a593Smuzhiyun dev_warn(&rtc->dev, "Update timer was detected\n");
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun /* clear all flags BUT VLF */
299*4882a593Smuzhiyun ret = regmap_update_bits(rx6110->regmap, RX6110_REG_FLAG,
300*4882a593Smuzhiyun RX6110_BIT_FLAG_AF |
301*4882a593Smuzhiyun RX6110_BIT_FLAG_UF |
302*4882a593Smuzhiyun RX6110_BIT_FLAG_TF,
303*4882a593Smuzhiyun 0);
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun return ret;
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun static const struct rtc_class_ops rx6110_rtc_ops = {
309*4882a593Smuzhiyun .read_time = rx6110_get_time,
310*4882a593Smuzhiyun .set_time = rx6110_set_time,
311*4882a593Smuzhiyun };
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun static struct regmap_config regmap_spi_config = {
314*4882a593Smuzhiyun .reg_bits = 8,
315*4882a593Smuzhiyun .val_bits = 8,
316*4882a593Smuzhiyun .max_register = RX6110_REG_IRQ,
317*4882a593Smuzhiyun .read_flag_mask = 0x80,
318*4882a593Smuzhiyun };
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun /**
321*4882a593Smuzhiyun * rx6110_probe - initialize rtc driver
322*4882a593Smuzhiyun * @spi: pointer to spi device
323*4882a593Smuzhiyun */
rx6110_probe(struct spi_device * spi)324*4882a593Smuzhiyun static int rx6110_probe(struct spi_device *spi)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun struct rx6110_data *rx6110;
327*4882a593Smuzhiyun int err;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun if ((spi->bits_per_word && spi->bits_per_word != 8) ||
330*4882a593Smuzhiyun (spi->max_speed_hz > 2000000) ||
331*4882a593Smuzhiyun (spi->mode != (SPI_CS_HIGH | SPI_CPOL | SPI_CPHA))) {
332*4882a593Smuzhiyun dev_warn(&spi->dev, "SPI settings: bits_per_word: %d, max_speed_hz: %d, mode: %xh\n",
333*4882a593Smuzhiyun spi->bits_per_word, spi->max_speed_hz, spi->mode);
334*4882a593Smuzhiyun dev_warn(&spi->dev, "driving device in an unsupported mode");
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun rx6110 = devm_kzalloc(&spi->dev, sizeof(*rx6110), GFP_KERNEL);
338*4882a593Smuzhiyun if (!rx6110)
339*4882a593Smuzhiyun return -ENOMEM;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun rx6110->regmap = devm_regmap_init_spi(spi, ®map_spi_config);
342*4882a593Smuzhiyun if (IS_ERR(rx6110->regmap)) {
343*4882a593Smuzhiyun dev_err(&spi->dev, "regmap init failed for rtc rx6110\n");
344*4882a593Smuzhiyun return PTR_ERR(rx6110->regmap);
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun spi_set_drvdata(spi, rx6110);
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun rx6110->rtc = devm_rtc_device_register(&spi->dev,
350*4882a593Smuzhiyun RX6110_DRIVER_NAME,
351*4882a593Smuzhiyun &rx6110_rtc_ops, THIS_MODULE);
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun if (IS_ERR(rx6110->rtc))
354*4882a593Smuzhiyun return PTR_ERR(rx6110->rtc);
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun err = rx6110_init(rx6110);
357*4882a593Smuzhiyun if (err)
358*4882a593Smuzhiyun return err;
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun rx6110->rtc->max_user_freq = 1;
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun return 0;
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun static const struct spi_device_id rx6110_id[] = {
366*4882a593Smuzhiyun { "rx6110", 0 },
367*4882a593Smuzhiyun { }
368*4882a593Smuzhiyun };
369*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, rx6110_id);
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun static const struct of_device_id rx6110_spi_of_match[] = {
372*4882a593Smuzhiyun { .compatible = "epson,rx6110" },
373*4882a593Smuzhiyun { },
374*4882a593Smuzhiyun };
375*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rx6110_spi_of_match);
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun static struct spi_driver rx6110_driver = {
378*4882a593Smuzhiyun .driver = {
379*4882a593Smuzhiyun .name = RX6110_DRIVER_NAME,
380*4882a593Smuzhiyun .of_match_table = of_match_ptr(rx6110_spi_of_match),
381*4882a593Smuzhiyun },
382*4882a593Smuzhiyun .probe = rx6110_probe,
383*4882a593Smuzhiyun .id_table = rx6110_id,
384*4882a593Smuzhiyun };
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun module_spi_driver(rx6110_driver);
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun MODULE_AUTHOR("Val Krutov <val.krutov@erd.epson.com>");
389*4882a593Smuzhiyun MODULE_DESCRIPTION("RX-6110 SA RTC driver");
390*4882a593Smuzhiyun MODULE_LICENSE("GPL");
391