xref: /OK3568_Linux_fs/kernel/drivers/rtc/rtc-rv3028.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * RTC driver for the Micro Crystal RV3028
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2019 Micro Crystal SA
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Alexandre Belloni <alexandre.belloni@bootlin.com>
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/clk-provider.h>
12*4882a593Smuzhiyun #include <linux/bcd.h>
13*4882a593Smuzhiyun #include <linux/bitops.h>
14*4882a593Smuzhiyun #include <linux/i2c.h>
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/kernel.h>
17*4882a593Smuzhiyun #include <linux/log2.h>
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <linux/of_device.h>
20*4882a593Smuzhiyun #include <linux/regmap.h>
21*4882a593Smuzhiyun #include <linux/rtc.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define RV3028_SEC			0x00
24*4882a593Smuzhiyun #define RV3028_MIN			0x01
25*4882a593Smuzhiyun #define RV3028_HOUR			0x02
26*4882a593Smuzhiyun #define RV3028_WDAY			0x03
27*4882a593Smuzhiyun #define RV3028_DAY			0x04
28*4882a593Smuzhiyun #define RV3028_MONTH			0x05
29*4882a593Smuzhiyun #define RV3028_YEAR			0x06
30*4882a593Smuzhiyun #define RV3028_ALARM_MIN		0x07
31*4882a593Smuzhiyun #define RV3028_ALARM_HOUR		0x08
32*4882a593Smuzhiyun #define RV3028_ALARM_DAY		0x09
33*4882a593Smuzhiyun #define RV3028_STATUS			0x0E
34*4882a593Smuzhiyun #define RV3028_CTRL1			0x0F
35*4882a593Smuzhiyun #define RV3028_CTRL2			0x10
36*4882a593Smuzhiyun #define RV3028_EVT_CTRL			0x13
37*4882a593Smuzhiyun #define RV3028_TS_COUNT			0x14
38*4882a593Smuzhiyun #define RV3028_TS_SEC			0x15
39*4882a593Smuzhiyun #define RV3028_RAM1			0x1F
40*4882a593Smuzhiyun #define RV3028_EEPROM_ADDR		0x25
41*4882a593Smuzhiyun #define RV3028_EEPROM_DATA		0x26
42*4882a593Smuzhiyun #define RV3028_EEPROM_CMD		0x27
43*4882a593Smuzhiyun #define RV3028_CLKOUT			0x35
44*4882a593Smuzhiyun #define RV3028_OFFSET			0x36
45*4882a593Smuzhiyun #define RV3028_BACKUP			0x37
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun #define RV3028_STATUS_PORF		BIT(0)
48*4882a593Smuzhiyun #define RV3028_STATUS_EVF		BIT(1)
49*4882a593Smuzhiyun #define RV3028_STATUS_AF		BIT(2)
50*4882a593Smuzhiyun #define RV3028_STATUS_TF		BIT(3)
51*4882a593Smuzhiyun #define RV3028_STATUS_UF		BIT(4)
52*4882a593Smuzhiyun #define RV3028_STATUS_BSF		BIT(5)
53*4882a593Smuzhiyun #define RV3028_STATUS_CLKF		BIT(6)
54*4882a593Smuzhiyun #define RV3028_STATUS_EEBUSY		BIT(7)
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun #define RV3028_CLKOUT_FD_MASK		GENMASK(2, 0)
57*4882a593Smuzhiyun #define RV3028_CLKOUT_PORIE		BIT(3)
58*4882a593Smuzhiyun #define RV3028_CLKOUT_CLKSY		BIT(6)
59*4882a593Smuzhiyun #define RV3028_CLKOUT_CLKOE		BIT(7)
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun #define RV3028_CTRL1_EERD		BIT(3)
62*4882a593Smuzhiyun #define RV3028_CTRL1_WADA		BIT(5)
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun #define RV3028_CTRL2_RESET		BIT(0)
65*4882a593Smuzhiyun #define RV3028_CTRL2_12_24		BIT(1)
66*4882a593Smuzhiyun #define RV3028_CTRL2_EIE		BIT(2)
67*4882a593Smuzhiyun #define RV3028_CTRL2_AIE		BIT(3)
68*4882a593Smuzhiyun #define RV3028_CTRL2_TIE		BIT(4)
69*4882a593Smuzhiyun #define RV3028_CTRL2_UIE		BIT(5)
70*4882a593Smuzhiyun #define RV3028_CTRL2_TSE		BIT(7)
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun #define RV3028_EVT_CTRL_TSR		BIT(2)
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun #define RV3028_EEPROM_CMD_UPDATE	0x11
75*4882a593Smuzhiyun #define RV3028_EEPROM_CMD_WRITE		0x21
76*4882a593Smuzhiyun #define RV3028_EEPROM_CMD_READ		0x22
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun #define RV3028_EEBUSY_POLL		10000
79*4882a593Smuzhiyun #define RV3028_EEBUSY_TIMEOUT		100000
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun #define RV3028_BACKUP_TCE		BIT(5)
82*4882a593Smuzhiyun #define RV3028_BACKUP_TCR_MASK		GENMASK(1,0)
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun #define OFFSET_STEP_PPT			953674
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun enum rv3028_type {
87*4882a593Smuzhiyun 	rv_3028,
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun struct rv3028_data {
91*4882a593Smuzhiyun 	struct regmap *regmap;
92*4882a593Smuzhiyun 	struct rtc_device *rtc;
93*4882a593Smuzhiyun 	enum rv3028_type type;
94*4882a593Smuzhiyun #ifdef CONFIG_COMMON_CLK
95*4882a593Smuzhiyun 	struct clk_hw clkout_hw;
96*4882a593Smuzhiyun #endif
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun static u16 rv3028_trickle_resistors[] = {3000, 5000, 9000, 15000};
100*4882a593Smuzhiyun 
timestamp0_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)101*4882a593Smuzhiyun static ssize_t timestamp0_store(struct device *dev,
102*4882a593Smuzhiyun 				struct device_attribute *attr,
103*4882a593Smuzhiyun 				const char *buf, size_t count)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun 	struct rv3028_data *rv3028 = dev_get_drvdata(dev->parent);
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	regmap_update_bits(rv3028->regmap, RV3028_EVT_CTRL, RV3028_EVT_CTRL_TSR,
108*4882a593Smuzhiyun 			   RV3028_EVT_CTRL_TSR);
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	return count;
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun 
timestamp0_show(struct device * dev,struct device_attribute * attr,char * buf)113*4882a593Smuzhiyun static ssize_t timestamp0_show(struct device *dev,
114*4882a593Smuzhiyun 			       struct device_attribute *attr, char *buf)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun 	struct rv3028_data *rv3028 = dev_get_drvdata(dev->parent);
117*4882a593Smuzhiyun 	struct rtc_time tm;
118*4882a593Smuzhiyun 	int ret, count;
119*4882a593Smuzhiyun 	u8 date[6];
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	ret = regmap_read(rv3028->regmap, RV3028_TS_COUNT, &count);
122*4882a593Smuzhiyun 	if (ret)
123*4882a593Smuzhiyun 		return ret;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	if (!count)
126*4882a593Smuzhiyun 		return 0;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	ret = regmap_bulk_read(rv3028->regmap, RV3028_TS_SEC, date,
129*4882a593Smuzhiyun 			       sizeof(date));
130*4882a593Smuzhiyun 	if (ret)
131*4882a593Smuzhiyun 		return ret;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	tm.tm_sec = bcd2bin(date[0]);
134*4882a593Smuzhiyun 	tm.tm_min = bcd2bin(date[1]);
135*4882a593Smuzhiyun 	tm.tm_hour = bcd2bin(date[2]);
136*4882a593Smuzhiyun 	tm.tm_mday = bcd2bin(date[3]);
137*4882a593Smuzhiyun 	tm.tm_mon = bcd2bin(date[4]) - 1;
138*4882a593Smuzhiyun 	tm.tm_year = bcd2bin(date[5]) + 100;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	ret = rtc_valid_tm(&tm);
141*4882a593Smuzhiyun 	if (ret)
142*4882a593Smuzhiyun 		return ret;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	return sprintf(buf, "%llu\n",
145*4882a593Smuzhiyun 		       (unsigned long long)rtc_tm_to_time64(&tm));
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun static DEVICE_ATTR_RW(timestamp0);
149*4882a593Smuzhiyun 
timestamp0_count_show(struct device * dev,struct device_attribute * attr,char * buf)150*4882a593Smuzhiyun static ssize_t timestamp0_count_show(struct device *dev,
151*4882a593Smuzhiyun 				     struct device_attribute *attr, char *buf)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun 	struct rv3028_data *rv3028 = dev_get_drvdata(dev->parent);
154*4882a593Smuzhiyun 	int ret, count;
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	ret = regmap_read(rv3028->regmap, RV3028_TS_COUNT, &count);
157*4882a593Smuzhiyun 	if (ret)
158*4882a593Smuzhiyun 		return ret;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	return sprintf(buf, "%u\n", count);
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun static DEVICE_ATTR_RO(timestamp0_count);
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun static struct attribute *rv3028_attrs[] = {
166*4882a593Smuzhiyun 	&dev_attr_timestamp0.attr,
167*4882a593Smuzhiyun 	&dev_attr_timestamp0_count.attr,
168*4882a593Smuzhiyun 	NULL
169*4882a593Smuzhiyun };
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun static const struct attribute_group rv3028_attr_group = {
172*4882a593Smuzhiyun 	.attrs	= rv3028_attrs,
173*4882a593Smuzhiyun };
174*4882a593Smuzhiyun 
rv3028_exit_eerd(struct rv3028_data * rv3028,u32 eerd)175*4882a593Smuzhiyun static int rv3028_exit_eerd(struct rv3028_data *rv3028, u32 eerd)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun 	if (eerd)
178*4882a593Smuzhiyun 		return 0;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	return regmap_update_bits(rv3028->regmap, RV3028_CTRL1, RV3028_CTRL1_EERD, 0);
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun 
rv3028_enter_eerd(struct rv3028_data * rv3028,u32 * eerd)183*4882a593Smuzhiyun static int rv3028_enter_eerd(struct rv3028_data *rv3028, u32 *eerd)
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun 	u32 ctrl1, status;
186*4882a593Smuzhiyun 	int ret;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	ret = regmap_read(rv3028->regmap, RV3028_CTRL1, &ctrl1);
189*4882a593Smuzhiyun 	if (ret)
190*4882a593Smuzhiyun 		return ret;
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	*eerd = ctrl1 & RV3028_CTRL1_EERD;
193*4882a593Smuzhiyun 	if (*eerd)
194*4882a593Smuzhiyun 		return 0;
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL1,
197*4882a593Smuzhiyun 				 RV3028_CTRL1_EERD, RV3028_CTRL1_EERD);
198*4882a593Smuzhiyun 	if (ret)
199*4882a593Smuzhiyun 		return ret;
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	ret = regmap_read_poll_timeout(rv3028->regmap, RV3028_STATUS, status,
202*4882a593Smuzhiyun 				       !(status & RV3028_STATUS_EEBUSY),
203*4882a593Smuzhiyun 				       RV3028_EEBUSY_POLL, RV3028_EEBUSY_TIMEOUT);
204*4882a593Smuzhiyun 	if (ret) {
205*4882a593Smuzhiyun 		rv3028_exit_eerd(rv3028, *eerd);
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 		return ret;
208*4882a593Smuzhiyun 	}
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	return 0;
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun 
rv3028_update_eeprom(struct rv3028_data * rv3028,u32 eerd)213*4882a593Smuzhiyun static int rv3028_update_eeprom(struct rv3028_data *rv3028, u32 eerd)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun 	u32 status;
216*4882a593Smuzhiyun 	int ret;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	ret = regmap_write(rv3028->regmap, RV3028_EEPROM_CMD, 0x0);
219*4882a593Smuzhiyun 	if (ret)
220*4882a593Smuzhiyun 		goto exit_eerd;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	ret = regmap_write(rv3028->regmap, RV3028_EEPROM_CMD, RV3028_EEPROM_CMD_UPDATE);
223*4882a593Smuzhiyun 	if (ret)
224*4882a593Smuzhiyun 		goto exit_eerd;
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	usleep_range(63000, RV3028_EEBUSY_TIMEOUT);
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 	ret = regmap_read_poll_timeout(rv3028->regmap, RV3028_STATUS, status,
229*4882a593Smuzhiyun 				       !(status & RV3028_STATUS_EEBUSY),
230*4882a593Smuzhiyun 				       RV3028_EEBUSY_POLL, RV3028_EEBUSY_TIMEOUT);
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun exit_eerd:
233*4882a593Smuzhiyun 	rv3028_exit_eerd(rv3028, eerd);
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 	return ret;
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun 
rv3028_update_cfg(struct rv3028_data * rv3028,unsigned int reg,unsigned int mask,unsigned int val)238*4882a593Smuzhiyun static int rv3028_update_cfg(struct rv3028_data *rv3028, unsigned int reg,
239*4882a593Smuzhiyun 			     unsigned int mask, unsigned int val)
240*4882a593Smuzhiyun {
241*4882a593Smuzhiyun 	u32 eerd;
242*4882a593Smuzhiyun 	int ret;
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	ret = rv3028_enter_eerd(rv3028, &eerd);
245*4882a593Smuzhiyun 	if (ret)
246*4882a593Smuzhiyun 		return ret;
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	ret = regmap_update_bits(rv3028->regmap, reg, mask, val);
249*4882a593Smuzhiyun 	if (ret) {
250*4882a593Smuzhiyun 		rv3028_exit_eerd(rv3028, eerd);
251*4882a593Smuzhiyun 		return ret;
252*4882a593Smuzhiyun 	}
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	return rv3028_update_eeprom(rv3028, eerd);
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun 
rv3028_handle_irq(int irq,void * dev_id)257*4882a593Smuzhiyun static irqreturn_t rv3028_handle_irq(int irq, void *dev_id)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun 	struct rv3028_data *rv3028 = dev_id;
260*4882a593Smuzhiyun 	unsigned long events = 0;
261*4882a593Smuzhiyun 	u32 status = 0, ctrl = 0;
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	if (regmap_read(rv3028->regmap, RV3028_STATUS, &status) < 0 ||
264*4882a593Smuzhiyun 	   status == 0) {
265*4882a593Smuzhiyun 		return IRQ_NONE;
266*4882a593Smuzhiyun 	}
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	if (status & RV3028_STATUS_PORF)
269*4882a593Smuzhiyun 		dev_warn(&rv3028->rtc->dev, "Voltage low, data loss detected.\n");
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	if (status & RV3028_STATUS_TF) {
272*4882a593Smuzhiyun 		status |= RV3028_STATUS_TF;
273*4882a593Smuzhiyun 		ctrl |= RV3028_CTRL2_TIE;
274*4882a593Smuzhiyun 		events |= RTC_PF;
275*4882a593Smuzhiyun 	}
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	if (status & RV3028_STATUS_AF) {
278*4882a593Smuzhiyun 		status |= RV3028_STATUS_AF;
279*4882a593Smuzhiyun 		ctrl |= RV3028_CTRL2_AIE;
280*4882a593Smuzhiyun 		events |= RTC_AF;
281*4882a593Smuzhiyun 	}
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun 	if (status & RV3028_STATUS_UF) {
284*4882a593Smuzhiyun 		status |= RV3028_STATUS_UF;
285*4882a593Smuzhiyun 		ctrl |= RV3028_CTRL2_UIE;
286*4882a593Smuzhiyun 		events |= RTC_UF;
287*4882a593Smuzhiyun 	}
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	if (events) {
290*4882a593Smuzhiyun 		rtc_update_irq(rv3028->rtc, 1, events);
291*4882a593Smuzhiyun 		regmap_update_bits(rv3028->regmap, RV3028_STATUS, status, 0);
292*4882a593Smuzhiyun 		regmap_update_bits(rv3028->regmap, RV3028_CTRL2, ctrl, 0);
293*4882a593Smuzhiyun 	}
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun 	if (status & RV3028_STATUS_EVF) {
296*4882a593Smuzhiyun 		sysfs_notify(&rv3028->rtc->dev.kobj, NULL,
297*4882a593Smuzhiyun 			     dev_attr_timestamp0.attr.name);
298*4882a593Smuzhiyun 		dev_warn(&rv3028->rtc->dev, "event detected");
299*4882a593Smuzhiyun 	}
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	return IRQ_HANDLED;
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun 
rv3028_get_time(struct device * dev,struct rtc_time * tm)304*4882a593Smuzhiyun static int rv3028_get_time(struct device *dev, struct rtc_time *tm)
305*4882a593Smuzhiyun {
306*4882a593Smuzhiyun 	struct rv3028_data *rv3028 = dev_get_drvdata(dev);
307*4882a593Smuzhiyun 	u8 date[7];
308*4882a593Smuzhiyun 	int ret, status;
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 	ret = regmap_read(rv3028->regmap, RV3028_STATUS, &status);
311*4882a593Smuzhiyun 	if (ret < 0)
312*4882a593Smuzhiyun 		return ret;
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 	if (status & RV3028_STATUS_PORF) {
315*4882a593Smuzhiyun 		dev_warn(dev, "Voltage low, data is invalid.\n");
316*4882a593Smuzhiyun 		return -EINVAL;
317*4882a593Smuzhiyun 	}
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	ret = regmap_bulk_read(rv3028->regmap, RV3028_SEC, date, sizeof(date));
320*4882a593Smuzhiyun 	if (ret)
321*4882a593Smuzhiyun 		return ret;
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun 	tm->tm_sec  = bcd2bin(date[RV3028_SEC] & 0x7f);
324*4882a593Smuzhiyun 	tm->tm_min  = bcd2bin(date[RV3028_MIN] & 0x7f);
325*4882a593Smuzhiyun 	tm->tm_hour = bcd2bin(date[RV3028_HOUR] & 0x3f);
326*4882a593Smuzhiyun 	tm->tm_wday = ilog2(date[RV3028_WDAY] & 0x7f);
327*4882a593Smuzhiyun 	tm->tm_mday = bcd2bin(date[RV3028_DAY] & 0x3f);
328*4882a593Smuzhiyun 	tm->tm_mon  = bcd2bin(date[RV3028_MONTH] & 0x1f) - 1;
329*4882a593Smuzhiyun 	tm->tm_year = bcd2bin(date[RV3028_YEAR]) + 100;
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun 	return 0;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun 
rv3028_set_time(struct device * dev,struct rtc_time * tm)334*4882a593Smuzhiyun static int rv3028_set_time(struct device *dev, struct rtc_time *tm)
335*4882a593Smuzhiyun {
336*4882a593Smuzhiyun 	struct rv3028_data *rv3028 = dev_get_drvdata(dev);
337*4882a593Smuzhiyun 	u8 date[7];
338*4882a593Smuzhiyun 	int ret;
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	date[RV3028_SEC]   = bin2bcd(tm->tm_sec);
341*4882a593Smuzhiyun 	date[RV3028_MIN]   = bin2bcd(tm->tm_min);
342*4882a593Smuzhiyun 	date[RV3028_HOUR]  = bin2bcd(tm->tm_hour);
343*4882a593Smuzhiyun 	date[RV3028_WDAY]  = 1 << (tm->tm_wday);
344*4882a593Smuzhiyun 	date[RV3028_DAY]   = bin2bcd(tm->tm_mday);
345*4882a593Smuzhiyun 	date[RV3028_MONTH] = bin2bcd(tm->tm_mon + 1);
346*4882a593Smuzhiyun 	date[RV3028_YEAR]  = bin2bcd(tm->tm_year - 100);
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	/*
349*4882a593Smuzhiyun 	 * Writing to the Seconds register has the same effect as setting RESET
350*4882a593Smuzhiyun 	 * bit to 1
351*4882a593Smuzhiyun 	 */
352*4882a593Smuzhiyun 	ret = regmap_bulk_write(rv3028->regmap, RV3028_SEC, date,
353*4882a593Smuzhiyun 				sizeof(date));
354*4882a593Smuzhiyun 	if (ret)
355*4882a593Smuzhiyun 		return ret;
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun 	ret = regmap_update_bits(rv3028->regmap, RV3028_STATUS,
358*4882a593Smuzhiyun 				 RV3028_STATUS_PORF, 0);
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 	return ret;
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun 
rv3028_get_alarm(struct device * dev,struct rtc_wkalrm * alrm)363*4882a593Smuzhiyun static int rv3028_get_alarm(struct device *dev, struct rtc_wkalrm *alrm)
364*4882a593Smuzhiyun {
365*4882a593Smuzhiyun 	struct rv3028_data *rv3028 = dev_get_drvdata(dev);
366*4882a593Smuzhiyun 	u8 alarmvals[3];
367*4882a593Smuzhiyun 	int status, ctrl, ret;
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun 	ret = regmap_bulk_read(rv3028->regmap, RV3028_ALARM_MIN, alarmvals,
370*4882a593Smuzhiyun 			       sizeof(alarmvals));
371*4882a593Smuzhiyun 	if (ret)
372*4882a593Smuzhiyun 		return ret;
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 	ret = regmap_read(rv3028->regmap, RV3028_STATUS, &status);
375*4882a593Smuzhiyun 	if (ret < 0)
376*4882a593Smuzhiyun 		return ret;
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	ret = regmap_read(rv3028->regmap, RV3028_CTRL2, &ctrl);
379*4882a593Smuzhiyun 	if (ret < 0)
380*4882a593Smuzhiyun 		return ret;
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	alrm->time.tm_sec  = 0;
383*4882a593Smuzhiyun 	alrm->time.tm_min  = bcd2bin(alarmvals[0] & 0x7f);
384*4882a593Smuzhiyun 	alrm->time.tm_hour = bcd2bin(alarmvals[1] & 0x3f);
385*4882a593Smuzhiyun 	alrm->time.tm_mday = bcd2bin(alarmvals[2] & 0x3f);
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun 	alrm->enabled = !!(ctrl & RV3028_CTRL2_AIE);
388*4882a593Smuzhiyun 	alrm->pending = (status & RV3028_STATUS_AF) && alrm->enabled;
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	return 0;
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun 
rv3028_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)393*4882a593Smuzhiyun static int rv3028_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
394*4882a593Smuzhiyun {
395*4882a593Smuzhiyun 	struct rv3028_data *rv3028 = dev_get_drvdata(dev);
396*4882a593Smuzhiyun 	u8 alarmvals[3];
397*4882a593Smuzhiyun 	u8 ctrl = 0;
398*4882a593Smuzhiyun 	int ret;
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	/* The alarm has no seconds, round up to nearest minute */
401*4882a593Smuzhiyun 	if (alrm->time.tm_sec) {
402*4882a593Smuzhiyun 		time64_t alarm_time = rtc_tm_to_time64(&alrm->time);
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 		alarm_time += 60 - alrm->time.tm_sec;
405*4882a593Smuzhiyun 		rtc_time64_to_tm(alarm_time, &alrm->time);
406*4882a593Smuzhiyun 	}
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 	ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL2,
409*4882a593Smuzhiyun 				 RV3028_CTRL2_AIE | RV3028_CTRL2_UIE, 0);
410*4882a593Smuzhiyun 	if (ret)
411*4882a593Smuzhiyun 		return ret;
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun 	alarmvals[0] = bin2bcd(alrm->time.tm_min);
414*4882a593Smuzhiyun 	alarmvals[1] = bin2bcd(alrm->time.tm_hour);
415*4882a593Smuzhiyun 	alarmvals[2] = bin2bcd(alrm->time.tm_mday);
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 	ret = regmap_update_bits(rv3028->regmap, RV3028_STATUS,
418*4882a593Smuzhiyun 				 RV3028_STATUS_AF, 0);
419*4882a593Smuzhiyun 	if (ret)
420*4882a593Smuzhiyun 		return ret;
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun 	ret = regmap_bulk_write(rv3028->regmap, RV3028_ALARM_MIN, alarmvals,
423*4882a593Smuzhiyun 				sizeof(alarmvals));
424*4882a593Smuzhiyun 	if (ret)
425*4882a593Smuzhiyun 		return ret;
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun 	if (alrm->enabled) {
428*4882a593Smuzhiyun 		if (rv3028->rtc->uie_rtctimer.enabled)
429*4882a593Smuzhiyun 			ctrl |= RV3028_CTRL2_UIE;
430*4882a593Smuzhiyun 		if (rv3028->rtc->aie_timer.enabled)
431*4882a593Smuzhiyun 			ctrl |= RV3028_CTRL2_AIE;
432*4882a593Smuzhiyun 	}
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL2,
435*4882a593Smuzhiyun 				 RV3028_CTRL2_UIE | RV3028_CTRL2_AIE, ctrl);
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 	return ret;
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun 
rv3028_alarm_irq_enable(struct device * dev,unsigned int enabled)440*4882a593Smuzhiyun static int rv3028_alarm_irq_enable(struct device *dev, unsigned int enabled)
441*4882a593Smuzhiyun {
442*4882a593Smuzhiyun 	struct rv3028_data *rv3028 = dev_get_drvdata(dev);
443*4882a593Smuzhiyun 	int ctrl = 0, ret;
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun 	if (enabled) {
446*4882a593Smuzhiyun 		if (rv3028->rtc->uie_rtctimer.enabled)
447*4882a593Smuzhiyun 			ctrl |= RV3028_CTRL2_UIE;
448*4882a593Smuzhiyun 		if (rv3028->rtc->aie_timer.enabled)
449*4882a593Smuzhiyun 			ctrl |= RV3028_CTRL2_AIE;
450*4882a593Smuzhiyun 	}
451*4882a593Smuzhiyun 
452*4882a593Smuzhiyun 	ret = regmap_update_bits(rv3028->regmap, RV3028_STATUS,
453*4882a593Smuzhiyun 				 RV3028_STATUS_AF | RV3028_STATUS_UF, 0);
454*4882a593Smuzhiyun 	if (ret)
455*4882a593Smuzhiyun 		return ret;
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun 	ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL2,
458*4882a593Smuzhiyun 				 RV3028_CTRL2_UIE | RV3028_CTRL2_AIE, ctrl);
459*4882a593Smuzhiyun 	if (ret)
460*4882a593Smuzhiyun 		return ret;
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 	return 0;
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun 
rv3028_read_offset(struct device * dev,long * offset)465*4882a593Smuzhiyun static int rv3028_read_offset(struct device *dev, long *offset)
466*4882a593Smuzhiyun {
467*4882a593Smuzhiyun 	struct rv3028_data *rv3028 = dev_get_drvdata(dev);
468*4882a593Smuzhiyun 	int ret, value, steps;
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun 	ret = regmap_read(rv3028->regmap, RV3028_OFFSET, &value);
471*4882a593Smuzhiyun 	if (ret < 0)
472*4882a593Smuzhiyun 		return ret;
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun 	steps = sign_extend32(value << 1, 8);
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun 	ret = regmap_read(rv3028->regmap, RV3028_BACKUP, &value);
477*4882a593Smuzhiyun 	if (ret < 0)
478*4882a593Smuzhiyun 		return ret;
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 	steps += value >> 7;
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun 	*offset = DIV_ROUND_CLOSEST(steps * OFFSET_STEP_PPT, 1000);
483*4882a593Smuzhiyun 
484*4882a593Smuzhiyun 	return 0;
485*4882a593Smuzhiyun }
486*4882a593Smuzhiyun 
rv3028_set_offset(struct device * dev,long offset)487*4882a593Smuzhiyun static int rv3028_set_offset(struct device *dev, long offset)
488*4882a593Smuzhiyun {
489*4882a593Smuzhiyun 	struct rv3028_data *rv3028 = dev_get_drvdata(dev);
490*4882a593Smuzhiyun 	u32 eerd;
491*4882a593Smuzhiyun 	int ret;
492*4882a593Smuzhiyun 
493*4882a593Smuzhiyun 	offset = clamp(offset, -244141L, 243187L) * 1000;
494*4882a593Smuzhiyun 	offset = DIV_ROUND_CLOSEST(offset, OFFSET_STEP_PPT);
495*4882a593Smuzhiyun 
496*4882a593Smuzhiyun 	ret = rv3028_enter_eerd(rv3028, &eerd);
497*4882a593Smuzhiyun 	if (ret)
498*4882a593Smuzhiyun 		return ret;
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun 	ret = regmap_write(rv3028->regmap, RV3028_OFFSET, offset >> 1);
501*4882a593Smuzhiyun 	if (ret < 0)
502*4882a593Smuzhiyun 		goto exit_eerd;
503*4882a593Smuzhiyun 
504*4882a593Smuzhiyun 	ret = regmap_update_bits(rv3028->regmap, RV3028_BACKUP, BIT(7),
505*4882a593Smuzhiyun 				 offset << 7);
506*4882a593Smuzhiyun 	if (ret < 0)
507*4882a593Smuzhiyun 		goto exit_eerd;
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun 	return rv3028_update_eeprom(rv3028, eerd);
510*4882a593Smuzhiyun 
511*4882a593Smuzhiyun exit_eerd:
512*4882a593Smuzhiyun 	rv3028_exit_eerd(rv3028, eerd);
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun 	return ret;
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun }
517*4882a593Smuzhiyun 
rv3028_ioctl(struct device * dev,unsigned int cmd,unsigned long arg)518*4882a593Smuzhiyun static int rv3028_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
519*4882a593Smuzhiyun {
520*4882a593Smuzhiyun 	struct rv3028_data *rv3028 = dev_get_drvdata(dev);
521*4882a593Smuzhiyun 	int status, ret = 0;
522*4882a593Smuzhiyun 
523*4882a593Smuzhiyun 	switch (cmd) {
524*4882a593Smuzhiyun 	case RTC_VL_READ:
525*4882a593Smuzhiyun 		ret = regmap_read(rv3028->regmap, RV3028_STATUS, &status);
526*4882a593Smuzhiyun 		if (ret < 0)
527*4882a593Smuzhiyun 			return ret;
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun 		status = status & RV3028_STATUS_PORF ? RTC_VL_DATA_INVALID : 0;
530*4882a593Smuzhiyun 		return put_user(status, (unsigned int __user *)arg);
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun 	default:
533*4882a593Smuzhiyun 		return -ENOIOCTLCMD;
534*4882a593Smuzhiyun 	}
535*4882a593Smuzhiyun }
536*4882a593Smuzhiyun 
rv3028_nvram_write(void * priv,unsigned int offset,void * val,size_t bytes)537*4882a593Smuzhiyun static int rv3028_nvram_write(void *priv, unsigned int offset, void *val,
538*4882a593Smuzhiyun 			      size_t bytes)
539*4882a593Smuzhiyun {
540*4882a593Smuzhiyun 	return regmap_bulk_write(priv, RV3028_RAM1 + offset, val, bytes);
541*4882a593Smuzhiyun }
542*4882a593Smuzhiyun 
rv3028_nvram_read(void * priv,unsigned int offset,void * val,size_t bytes)543*4882a593Smuzhiyun static int rv3028_nvram_read(void *priv, unsigned int offset, void *val,
544*4882a593Smuzhiyun 			     size_t bytes)
545*4882a593Smuzhiyun {
546*4882a593Smuzhiyun 	return regmap_bulk_read(priv, RV3028_RAM1 + offset, val, bytes);
547*4882a593Smuzhiyun }
548*4882a593Smuzhiyun 
rv3028_eeprom_write(void * priv,unsigned int offset,void * val,size_t bytes)549*4882a593Smuzhiyun static int rv3028_eeprom_write(void *priv, unsigned int offset, void *val,
550*4882a593Smuzhiyun 			       size_t bytes)
551*4882a593Smuzhiyun {
552*4882a593Smuzhiyun 	struct rv3028_data *rv3028 = priv;
553*4882a593Smuzhiyun 	u32 status, eerd;
554*4882a593Smuzhiyun 	int i, ret;
555*4882a593Smuzhiyun 	u8 *buf = val;
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun 	ret = rv3028_enter_eerd(rv3028, &eerd);
558*4882a593Smuzhiyun 	if (ret)
559*4882a593Smuzhiyun 		return ret;
560*4882a593Smuzhiyun 
561*4882a593Smuzhiyun 	for (i = 0; i < bytes; i++) {
562*4882a593Smuzhiyun 		ret = regmap_write(rv3028->regmap, RV3028_EEPROM_ADDR, offset + i);
563*4882a593Smuzhiyun 		if (ret)
564*4882a593Smuzhiyun 			goto restore_eerd;
565*4882a593Smuzhiyun 
566*4882a593Smuzhiyun 		ret = regmap_write(rv3028->regmap, RV3028_EEPROM_DATA, buf[i]);
567*4882a593Smuzhiyun 		if (ret)
568*4882a593Smuzhiyun 			goto restore_eerd;
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun 		ret = regmap_write(rv3028->regmap, RV3028_EEPROM_CMD, 0x0);
571*4882a593Smuzhiyun 		if (ret)
572*4882a593Smuzhiyun 			goto restore_eerd;
573*4882a593Smuzhiyun 
574*4882a593Smuzhiyun 		ret = regmap_write(rv3028->regmap, RV3028_EEPROM_CMD,
575*4882a593Smuzhiyun 				   RV3028_EEPROM_CMD_WRITE);
576*4882a593Smuzhiyun 		if (ret)
577*4882a593Smuzhiyun 			goto restore_eerd;
578*4882a593Smuzhiyun 
579*4882a593Smuzhiyun 		usleep_range(RV3028_EEBUSY_POLL, RV3028_EEBUSY_TIMEOUT);
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun 		ret = regmap_read_poll_timeout(rv3028->regmap, RV3028_STATUS, status,
582*4882a593Smuzhiyun 					       !(status & RV3028_STATUS_EEBUSY),
583*4882a593Smuzhiyun 					       RV3028_EEBUSY_POLL,
584*4882a593Smuzhiyun 					       RV3028_EEBUSY_TIMEOUT);
585*4882a593Smuzhiyun 		if (ret)
586*4882a593Smuzhiyun 			goto restore_eerd;
587*4882a593Smuzhiyun 	}
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun restore_eerd:
590*4882a593Smuzhiyun 	rv3028_exit_eerd(rv3028, eerd);
591*4882a593Smuzhiyun 
592*4882a593Smuzhiyun 	return ret;
593*4882a593Smuzhiyun }
594*4882a593Smuzhiyun 
rv3028_eeprom_read(void * priv,unsigned int offset,void * val,size_t bytes)595*4882a593Smuzhiyun static int rv3028_eeprom_read(void *priv, unsigned int offset, void *val,
596*4882a593Smuzhiyun 			      size_t bytes)
597*4882a593Smuzhiyun {
598*4882a593Smuzhiyun 	struct rv3028_data *rv3028 = priv;
599*4882a593Smuzhiyun 	u32 status, eerd, data;
600*4882a593Smuzhiyun 	int i, ret;
601*4882a593Smuzhiyun 	u8 *buf = val;
602*4882a593Smuzhiyun 
603*4882a593Smuzhiyun 	ret = rv3028_enter_eerd(rv3028, &eerd);
604*4882a593Smuzhiyun 	if (ret)
605*4882a593Smuzhiyun 		return ret;
606*4882a593Smuzhiyun 
607*4882a593Smuzhiyun 	for (i = 0; i < bytes; i++) {
608*4882a593Smuzhiyun 		ret = regmap_write(rv3028->regmap, RV3028_EEPROM_ADDR, offset + i);
609*4882a593Smuzhiyun 		if (ret)
610*4882a593Smuzhiyun 			goto restore_eerd;
611*4882a593Smuzhiyun 
612*4882a593Smuzhiyun 		ret = regmap_write(rv3028->regmap, RV3028_EEPROM_CMD, 0x0);
613*4882a593Smuzhiyun 		if (ret)
614*4882a593Smuzhiyun 			goto restore_eerd;
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun 		ret = regmap_write(rv3028->regmap, RV3028_EEPROM_CMD,
617*4882a593Smuzhiyun 				   RV3028_EEPROM_CMD_READ);
618*4882a593Smuzhiyun 		if (ret)
619*4882a593Smuzhiyun 			goto restore_eerd;
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun 		ret = regmap_read_poll_timeout(rv3028->regmap, RV3028_STATUS, status,
622*4882a593Smuzhiyun 					       !(status & RV3028_STATUS_EEBUSY),
623*4882a593Smuzhiyun 					       RV3028_EEBUSY_POLL,
624*4882a593Smuzhiyun 					       RV3028_EEBUSY_TIMEOUT);
625*4882a593Smuzhiyun 		if (ret)
626*4882a593Smuzhiyun 			goto restore_eerd;
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun 		ret = regmap_read(rv3028->regmap, RV3028_EEPROM_DATA, &data);
629*4882a593Smuzhiyun 		if (ret)
630*4882a593Smuzhiyun 			goto restore_eerd;
631*4882a593Smuzhiyun 		buf[i] = data;
632*4882a593Smuzhiyun 	}
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun restore_eerd:
635*4882a593Smuzhiyun 	rv3028_exit_eerd(rv3028, eerd);
636*4882a593Smuzhiyun 
637*4882a593Smuzhiyun 	return ret;
638*4882a593Smuzhiyun }
639*4882a593Smuzhiyun 
640*4882a593Smuzhiyun #ifdef CONFIG_COMMON_CLK
641*4882a593Smuzhiyun #define clkout_hw_to_rv3028(hw) container_of(hw, struct rv3028_data, clkout_hw)
642*4882a593Smuzhiyun 
643*4882a593Smuzhiyun static int clkout_rates[] = {
644*4882a593Smuzhiyun 	32768,
645*4882a593Smuzhiyun 	8192,
646*4882a593Smuzhiyun 	1024,
647*4882a593Smuzhiyun 	64,
648*4882a593Smuzhiyun 	32,
649*4882a593Smuzhiyun 	1,
650*4882a593Smuzhiyun };
651*4882a593Smuzhiyun 
rv3028_clkout_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)652*4882a593Smuzhiyun static unsigned long rv3028_clkout_recalc_rate(struct clk_hw *hw,
653*4882a593Smuzhiyun 					       unsigned long parent_rate)
654*4882a593Smuzhiyun {
655*4882a593Smuzhiyun 	int clkout, ret;
656*4882a593Smuzhiyun 	struct rv3028_data *rv3028 = clkout_hw_to_rv3028(hw);
657*4882a593Smuzhiyun 
658*4882a593Smuzhiyun 	ret = regmap_read(rv3028->regmap, RV3028_CLKOUT, &clkout);
659*4882a593Smuzhiyun 	if (ret < 0)
660*4882a593Smuzhiyun 		return 0;
661*4882a593Smuzhiyun 
662*4882a593Smuzhiyun 	clkout &= RV3028_CLKOUT_FD_MASK;
663*4882a593Smuzhiyun 	return clkout_rates[clkout];
664*4882a593Smuzhiyun }
665*4882a593Smuzhiyun 
rv3028_clkout_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)666*4882a593Smuzhiyun static long rv3028_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
667*4882a593Smuzhiyun 				     unsigned long *prate)
668*4882a593Smuzhiyun {
669*4882a593Smuzhiyun 	int i;
670*4882a593Smuzhiyun 
671*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
672*4882a593Smuzhiyun 		if (clkout_rates[i] <= rate)
673*4882a593Smuzhiyun 			return clkout_rates[i];
674*4882a593Smuzhiyun 
675*4882a593Smuzhiyun 	return 0;
676*4882a593Smuzhiyun }
677*4882a593Smuzhiyun 
rv3028_clkout_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)678*4882a593Smuzhiyun static int rv3028_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
679*4882a593Smuzhiyun 				  unsigned long parent_rate)
680*4882a593Smuzhiyun {
681*4882a593Smuzhiyun 	int i, ret;
682*4882a593Smuzhiyun 	u32 enabled;
683*4882a593Smuzhiyun 	struct rv3028_data *rv3028 = clkout_hw_to_rv3028(hw);
684*4882a593Smuzhiyun 
685*4882a593Smuzhiyun 	ret = regmap_read(rv3028->regmap, RV3028_CLKOUT, &enabled);
686*4882a593Smuzhiyun 	if (ret < 0)
687*4882a593Smuzhiyun 		return ret;
688*4882a593Smuzhiyun 
689*4882a593Smuzhiyun 	ret = regmap_write(rv3028->regmap, RV3028_CLKOUT, 0x0);
690*4882a593Smuzhiyun 	if (ret < 0)
691*4882a593Smuzhiyun 		return ret;
692*4882a593Smuzhiyun 
693*4882a593Smuzhiyun 	enabled &= RV3028_CLKOUT_CLKOE;
694*4882a593Smuzhiyun 
695*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
696*4882a593Smuzhiyun 		if (clkout_rates[i] == rate)
697*4882a593Smuzhiyun 			return rv3028_update_cfg(rv3028, RV3028_CLKOUT, 0xff,
698*4882a593Smuzhiyun 						 RV3028_CLKOUT_CLKSY | enabled | i);
699*4882a593Smuzhiyun 
700*4882a593Smuzhiyun 	return -EINVAL;
701*4882a593Smuzhiyun }
702*4882a593Smuzhiyun 
rv3028_clkout_prepare(struct clk_hw * hw)703*4882a593Smuzhiyun static int rv3028_clkout_prepare(struct clk_hw *hw)
704*4882a593Smuzhiyun {
705*4882a593Smuzhiyun 	struct rv3028_data *rv3028 = clkout_hw_to_rv3028(hw);
706*4882a593Smuzhiyun 
707*4882a593Smuzhiyun 	return regmap_write(rv3028->regmap, RV3028_CLKOUT,
708*4882a593Smuzhiyun 			    RV3028_CLKOUT_CLKSY | RV3028_CLKOUT_CLKOE);
709*4882a593Smuzhiyun }
710*4882a593Smuzhiyun 
rv3028_clkout_unprepare(struct clk_hw * hw)711*4882a593Smuzhiyun static void rv3028_clkout_unprepare(struct clk_hw *hw)
712*4882a593Smuzhiyun {
713*4882a593Smuzhiyun 	struct rv3028_data *rv3028 = clkout_hw_to_rv3028(hw);
714*4882a593Smuzhiyun 
715*4882a593Smuzhiyun 	regmap_write(rv3028->regmap, RV3028_CLKOUT, 0x0);
716*4882a593Smuzhiyun 	regmap_update_bits(rv3028->regmap, RV3028_STATUS,
717*4882a593Smuzhiyun 			   RV3028_STATUS_CLKF, 0);
718*4882a593Smuzhiyun }
719*4882a593Smuzhiyun 
rv3028_clkout_is_prepared(struct clk_hw * hw)720*4882a593Smuzhiyun static int rv3028_clkout_is_prepared(struct clk_hw *hw)
721*4882a593Smuzhiyun {
722*4882a593Smuzhiyun 	int clkout, ret;
723*4882a593Smuzhiyun 	struct rv3028_data *rv3028 = clkout_hw_to_rv3028(hw);
724*4882a593Smuzhiyun 
725*4882a593Smuzhiyun 	ret = regmap_read(rv3028->regmap, RV3028_CLKOUT, &clkout);
726*4882a593Smuzhiyun 	if (ret < 0)
727*4882a593Smuzhiyun 		return ret;
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun 	return !!(clkout & RV3028_CLKOUT_CLKOE);
730*4882a593Smuzhiyun }
731*4882a593Smuzhiyun 
732*4882a593Smuzhiyun static const struct clk_ops rv3028_clkout_ops = {
733*4882a593Smuzhiyun 	.prepare = rv3028_clkout_prepare,
734*4882a593Smuzhiyun 	.unprepare = rv3028_clkout_unprepare,
735*4882a593Smuzhiyun 	.is_prepared = rv3028_clkout_is_prepared,
736*4882a593Smuzhiyun 	.recalc_rate = rv3028_clkout_recalc_rate,
737*4882a593Smuzhiyun 	.round_rate = rv3028_clkout_round_rate,
738*4882a593Smuzhiyun 	.set_rate = rv3028_clkout_set_rate,
739*4882a593Smuzhiyun };
740*4882a593Smuzhiyun 
rv3028_clkout_register_clk(struct rv3028_data * rv3028,struct i2c_client * client)741*4882a593Smuzhiyun static int rv3028_clkout_register_clk(struct rv3028_data *rv3028,
742*4882a593Smuzhiyun 				      struct i2c_client *client)
743*4882a593Smuzhiyun {
744*4882a593Smuzhiyun 	int ret;
745*4882a593Smuzhiyun 	struct clk *clk;
746*4882a593Smuzhiyun 	struct clk_init_data init;
747*4882a593Smuzhiyun 	struct device_node *node = client->dev.of_node;
748*4882a593Smuzhiyun 
749*4882a593Smuzhiyun 	ret = regmap_update_bits(rv3028->regmap, RV3028_STATUS,
750*4882a593Smuzhiyun 				 RV3028_STATUS_CLKF, 0);
751*4882a593Smuzhiyun 	if (ret < 0)
752*4882a593Smuzhiyun 		return ret;
753*4882a593Smuzhiyun 
754*4882a593Smuzhiyun 	init.name = "rv3028-clkout";
755*4882a593Smuzhiyun 	init.ops = &rv3028_clkout_ops;
756*4882a593Smuzhiyun 	init.flags = 0;
757*4882a593Smuzhiyun 	init.parent_names = NULL;
758*4882a593Smuzhiyun 	init.num_parents = 0;
759*4882a593Smuzhiyun 	rv3028->clkout_hw.init = &init;
760*4882a593Smuzhiyun 
761*4882a593Smuzhiyun 	/* optional override of the clockname */
762*4882a593Smuzhiyun 	of_property_read_string(node, "clock-output-names", &init.name);
763*4882a593Smuzhiyun 
764*4882a593Smuzhiyun 	/* register the clock */
765*4882a593Smuzhiyun 	clk = devm_clk_register(&client->dev, &rv3028->clkout_hw);
766*4882a593Smuzhiyun 	if (!IS_ERR(clk))
767*4882a593Smuzhiyun 		of_clk_add_provider(node, of_clk_src_simple_get, clk);
768*4882a593Smuzhiyun 
769*4882a593Smuzhiyun 	return 0;
770*4882a593Smuzhiyun }
771*4882a593Smuzhiyun #endif
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun static struct rtc_class_ops rv3028_rtc_ops = {
774*4882a593Smuzhiyun 	.read_time = rv3028_get_time,
775*4882a593Smuzhiyun 	.set_time = rv3028_set_time,
776*4882a593Smuzhiyun 	.read_offset = rv3028_read_offset,
777*4882a593Smuzhiyun 	.set_offset = rv3028_set_offset,
778*4882a593Smuzhiyun 	.ioctl = rv3028_ioctl,
779*4882a593Smuzhiyun };
780*4882a593Smuzhiyun 
781*4882a593Smuzhiyun static const struct regmap_config regmap_config = {
782*4882a593Smuzhiyun         .reg_bits = 8,
783*4882a593Smuzhiyun         .val_bits = 8,
784*4882a593Smuzhiyun         .max_register = 0x37,
785*4882a593Smuzhiyun };
786*4882a593Smuzhiyun 
rv3028_probe(struct i2c_client * client)787*4882a593Smuzhiyun static int rv3028_probe(struct i2c_client *client)
788*4882a593Smuzhiyun {
789*4882a593Smuzhiyun 	struct rv3028_data *rv3028;
790*4882a593Smuzhiyun 	int ret, status;
791*4882a593Smuzhiyun 	u32 ohms;
792*4882a593Smuzhiyun 	struct nvmem_config nvmem_cfg = {
793*4882a593Smuzhiyun 		.name = "rv3028_nvram",
794*4882a593Smuzhiyun 		.word_size = 1,
795*4882a593Smuzhiyun 		.stride = 1,
796*4882a593Smuzhiyun 		.size = 2,
797*4882a593Smuzhiyun 		.type = NVMEM_TYPE_BATTERY_BACKED,
798*4882a593Smuzhiyun 		.reg_read = rv3028_nvram_read,
799*4882a593Smuzhiyun 		.reg_write = rv3028_nvram_write,
800*4882a593Smuzhiyun 	};
801*4882a593Smuzhiyun 	struct nvmem_config eeprom_cfg = {
802*4882a593Smuzhiyun 		.name = "rv3028_eeprom",
803*4882a593Smuzhiyun 		.word_size = 1,
804*4882a593Smuzhiyun 		.stride = 1,
805*4882a593Smuzhiyun 		.size = 43,
806*4882a593Smuzhiyun 		.type = NVMEM_TYPE_EEPROM,
807*4882a593Smuzhiyun 		.reg_read = rv3028_eeprom_read,
808*4882a593Smuzhiyun 		.reg_write = rv3028_eeprom_write,
809*4882a593Smuzhiyun 	};
810*4882a593Smuzhiyun 
811*4882a593Smuzhiyun 	rv3028 = devm_kzalloc(&client->dev, sizeof(struct rv3028_data),
812*4882a593Smuzhiyun 			      GFP_KERNEL);
813*4882a593Smuzhiyun 	if (!rv3028)
814*4882a593Smuzhiyun 		return -ENOMEM;
815*4882a593Smuzhiyun 
816*4882a593Smuzhiyun 	rv3028->regmap = devm_regmap_init_i2c(client, &regmap_config);
817*4882a593Smuzhiyun 	if (IS_ERR(rv3028->regmap))
818*4882a593Smuzhiyun 		return PTR_ERR(rv3028->regmap);
819*4882a593Smuzhiyun 
820*4882a593Smuzhiyun 	i2c_set_clientdata(client, rv3028);
821*4882a593Smuzhiyun 
822*4882a593Smuzhiyun 	ret = regmap_read(rv3028->regmap, RV3028_STATUS, &status);
823*4882a593Smuzhiyun 	if (ret < 0)
824*4882a593Smuzhiyun 		return ret;
825*4882a593Smuzhiyun 
826*4882a593Smuzhiyun 	if (status & RV3028_STATUS_PORF)
827*4882a593Smuzhiyun 		dev_warn(&client->dev, "Voltage low, data loss detected.\n");
828*4882a593Smuzhiyun 
829*4882a593Smuzhiyun 	if (status & RV3028_STATUS_AF)
830*4882a593Smuzhiyun 		dev_warn(&client->dev, "An alarm may have been missed.\n");
831*4882a593Smuzhiyun 
832*4882a593Smuzhiyun 	rv3028->rtc = devm_rtc_allocate_device(&client->dev);
833*4882a593Smuzhiyun 	if (IS_ERR(rv3028->rtc))
834*4882a593Smuzhiyun 		return PTR_ERR(rv3028->rtc);
835*4882a593Smuzhiyun 
836*4882a593Smuzhiyun 	if (client->irq > 0) {
837*4882a593Smuzhiyun 		ret = devm_request_threaded_irq(&client->dev, client->irq,
838*4882a593Smuzhiyun 						NULL, rv3028_handle_irq,
839*4882a593Smuzhiyun 						IRQF_TRIGGER_LOW | IRQF_ONESHOT,
840*4882a593Smuzhiyun 						"rv3028", rv3028);
841*4882a593Smuzhiyun 		if (ret) {
842*4882a593Smuzhiyun 			dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n");
843*4882a593Smuzhiyun 			client->irq = 0;
844*4882a593Smuzhiyun 		} else {
845*4882a593Smuzhiyun 			rv3028_rtc_ops.read_alarm = rv3028_get_alarm;
846*4882a593Smuzhiyun 			rv3028_rtc_ops.set_alarm = rv3028_set_alarm;
847*4882a593Smuzhiyun 			rv3028_rtc_ops.alarm_irq_enable = rv3028_alarm_irq_enable;
848*4882a593Smuzhiyun 		}
849*4882a593Smuzhiyun 	}
850*4882a593Smuzhiyun 
851*4882a593Smuzhiyun 	ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL1,
852*4882a593Smuzhiyun 				 RV3028_CTRL1_WADA, RV3028_CTRL1_WADA);
853*4882a593Smuzhiyun 	if (ret)
854*4882a593Smuzhiyun 		return ret;
855*4882a593Smuzhiyun 
856*4882a593Smuzhiyun 	/* setup timestamping */
857*4882a593Smuzhiyun 	ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL2,
858*4882a593Smuzhiyun 				 RV3028_CTRL2_EIE | RV3028_CTRL2_TSE,
859*4882a593Smuzhiyun 				 RV3028_CTRL2_EIE | RV3028_CTRL2_TSE);
860*4882a593Smuzhiyun 	if (ret)
861*4882a593Smuzhiyun 		return ret;
862*4882a593Smuzhiyun 
863*4882a593Smuzhiyun 	/* setup trickle charger */
864*4882a593Smuzhiyun 	if (!device_property_read_u32(&client->dev, "trickle-resistor-ohms",
865*4882a593Smuzhiyun 				      &ohms)) {
866*4882a593Smuzhiyun 		int i;
867*4882a593Smuzhiyun 
868*4882a593Smuzhiyun 		for (i = 0; i < ARRAY_SIZE(rv3028_trickle_resistors); i++)
869*4882a593Smuzhiyun 			if (ohms == rv3028_trickle_resistors[i])
870*4882a593Smuzhiyun 				break;
871*4882a593Smuzhiyun 
872*4882a593Smuzhiyun 		if (i < ARRAY_SIZE(rv3028_trickle_resistors)) {
873*4882a593Smuzhiyun 			ret = rv3028_update_cfg(rv3028, RV3028_BACKUP, RV3028_BACKUP_TCE |
874*4882a593Smuzhiyun 						 RV3028_BACKUP_TCR_MASK, RV3028_BACKUP_TCE | i);
875*4882a593Smuzhiyun 			if (ret)
876*4882a593Smuzhiyun 				return ret;
877*4882a593Smuzhiyun 		} else {
878*4882a593Smuzhiyun 			dev_warn(&client->dev, "invalid trickle resistor value\n");
879*4882a593Smuzhiyun 		}
880*4882a593Smuzhiyun 	}
881*4882a593Smuzhiyun 
882*4882a593Smuzhiyun 	ret = rtc_add_group(rv3028->rtc, &rv3028_attr_group);
883*4882a593Smuzhiyun 	if (ret)
884*4882a593Smuzhiyun 		return ret;
885*4882a593Smuzhiyun 
886*4882a593Smuzhiyun 	rv3028->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
887*4882a593Smuzhiyun 	rv3028->rtc->range_max = RTC_TIMESTAMP_END_2099;
888*4882a593Smuzhiyun 	rv3028->rtc->ops = &rv3028_rtc_ops;
889*4882a593Smuzhiyun 	ret = rtc_register_device(rv3028->rtc);
890*4882a593Smuzhiyun 	if (ret)
891*4882a593Smuzhiyun 		return ret;
892*4882a593Smuzhiyun 
893*4882a593Smuzhiyun 	nvmem_cfg.priv = rv3028->regmap;
894*4882a593Smuzhiyun 	rtc_nvmem_register(rv3028->rtc, &nvmem_cfg);
895*4882a593Smuzhiyun 	eeprom_cfg.priv = rv3028;
896*4882a593Smuzhiyun 	rtc_nvmem_register(rv3028->rtc, &eeprom_cfg);
897*4882a593Smuzhiyun 
898*4882a593Smuzhiyun 	rv3028->rtc->max_user_freq = 1;
899*4882a593Smuzhiyun 
900*4882a593Smuzhiyun #ifdef CONFIG_COMMON_CLK
901*4882a593Smuzhiyun 	rv3028_clkout_register_clk(rv3028, client);
902*4882a593Smuzhiyun #endif
903*4882a593Smuzhiyun 	return 0;
904*4882a593Smuzhiyun }
905*4882a593Smuzhiyun 
906*4882a593Smuzhiyun static const struct of_device_id rv3028_of_match[] = {
907*4882a593Smuzhiyun 	{ .compatible = "microcrystal,rv3028", },
908*4882a593Smuzhiyun 	{ }
909*4882a593Smuzhiyun };
910*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rv3028_of_match);
911*4882a593Smuzhiyun 
912*4882a593Smuzhiyun static struct i2c_driver rv3028_driver = {
913*4882a593Smuzhiyun 	.driver = {
914*4882a593Smuzhiyun 		.name = "rtc-rv3028",
915*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(rv3028_of_match),
916*4882a593Smuzhiyun 	},
917*4882a593Smuzhiyun 	.probe_new	= rv3028_probe,
918*4882a593Smuzhiyun };
919*4882a593Smuzhiyun module_i2c_driver(rv3028_driver);
920*4882a593Smuzhiyun 
921*4882a593Smuzhiyun MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
922*4882a593Smuzhiyun MODULE_DESCRIPTION("Micro Crystal RV3028 RTC driver");
923*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
924