1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd
4 */
5 #include <linux/bcd.h>
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/mfd/syscon.h>
10 #include <linux/clk.h>
11 #include <linux/of.h>
12 #include <linux/regmap.h>
13 #include <linux/rtc.h>
14
15 /* RTC_CTRL_REG bitfields */
16
17 #define RTC_REG(x) ((x))
18 #define RTC_SET_SECONDS RTC_REG(0x0)
19 #define RTC_SET_MINUTES RTC_REG(0x4)
20 #define RTC_SET_HOURS RTC_REG(0x8)
21 #define RTC_SET_DAYS RTC_REG(0xc)
22 #define RTC_SET_MONTHS RTC_REG(0x10)
23 #define RTC_SET_YEARL RTC_REG(0x14)
24 #define RTC_SET_YEARH RTC_REG(0x18)
25 #define RTC_SET_WEEKS RTC_REG(0x1c)
26 #define RTC_ALARM_SECONDS RTC_REG(0x20)
27 #define RTC_ALARM_MINUTES RTC_REG(0x24)
28 #define RTC_ALARM_HOURS RTC_REG(0x28)
29 #define RTC_ALARM_DAYS RTC_REG(0x2c)
30 #define RTC_ALARM_MONTHS RTC_REG(0x30)
31 #define RTC_ALARM_YEARL RTC_REG(0x34)
32 #define RTC_ALARM_YEARH RTC_REG(0x38)
33 #define RTC_CTRL RTC_REG(0x3C)
34 #define RTC_STATUS0 RTC_REG(0x40)
35 #define RTC_STATUS1 RTC_REG(0x44)
36 #define RTC_INT0_EN RTC_REG(0x48)
37 #define RTC_INT1_EN RTC_REG(0x4c)
38 #define RTC_MSEC_CTRL RTC_REG(0x50)
39 #define RTC_MSEC_CNT RTC_REG(0x54)
40 #define RTC_COMP_H RTC_REG(0x58)
41 #define RTC_COMP_D RTC_REG(0x5c)
42 #define RTC_COMP_M RTC_REG(0x60)
43 #define RTC_ANALOG_CTRL RTC_REG(0x64)
44 #define RTC_ANALOG_TEST RTC_REG(0x68)
45 #define RTC_LDO_CTRL RTC_REG(0x6c)
46 #define RTC_XO_TRIM0 RTC_REG(0x70)
47 #define RTC_XO_TRIM1 RTC_REG(0x74)
48 #define RTC_VPTAT_TRIM RTC_REG(0x78)
49 #define RTC_ANALOG_EN RTC_REG(0x7c)
50 #define RTC_CLK32K_TEST RTC_REG(0x80)
51 #define RTC_TEST_ST RTC_REG(0x84)
52 #define RTC_TEST_LEN RTC_REG(0x88)
53 #define RTC_CNT_0 RTC_REG(0x8c)
54 #define RTC_CNT_1 RTC_REG(0x90)
55 #define RTC_CNT_2 RTC_REG(0x94)
56 #define RTC_CNT_3 RTC_REG(0x98)
57 #define RTC_MAX_REGISTER RTC_CNT_3
58
59 #define VI_GRF_VI_MISC_CON0 0x50000
60 #define RTC_CLAMP_EN BIT(6)
61
62 /* RTC_CTRL_REG bitfields */
63 #define RTC_CTRL_REG_START_RTC BIT(0)
64 #define RTC_TIMEOUT (3000 * 1000)
65
66 /* RK630 has a shadowed register for saving a "frozen" RTC time.
67 * When user setting "GET_TIME" to 1, the time will save in this shadowed
68 * register. If set "READSEL" to 1, user read rtc time register, actually
69 * get the time of that moment. If we need the real time, clr this bit.
70 */
71 #define RTC_CTRL_REG_RTC_GET_TIME BIT(6)
72 #define RTC_CTRL_REG_RTC_READSEL_M BIT(7)
73 #define RTC_INT_REG_ALARM_EN BIT(7)
74 #define RTC_D2A_XO_EN BIT(0)
75 #define RTC_D2A_CLK_OUT_EN BIT(5)
76
77 #define RTC_STATUS_MASK 0xFF
78
79 #define SECONDS_REG_MSK 0x7F
80 #define MINUTES_REG_MAK 0x7F
81 #define HOURS_REG_MSK 0x3F
82 #define DAYS_REG_MSK 0x3F
83 #define MONTHS_REG_MSK 0x1F
84 #define YEARS_REG_MSK 0xFF
85 #define WEEKS_REG_MSK 0x7
86
87 #define RTC_VREF_INIT 0x40
88
89 #define D2A_POR_REG_SEL1 BIT(4)
90 #define D2A_POR_REG_SEL0 BIT(1)
91
92 #define NUM_TIME_REGS 8
93 #define NUM_ALARM_REGS 7
94
95 #define DISABLE_ALARM_INT 0x3F
96 #define ENABLE_ALARM_INT 0xFF
97 #define ALARM_INT_STATUS BIT(4)
98
99 #define CLK32K_TEST_EN BIT(0)
100 #define CLK32K_TEST_START BIT(0)
101 #define CLK32K_TEST_STATUS BIT(1)
102 #define CLK32K_TEST_DONE BIT(2)
103 #define CLK32K_TEST_LEN 1
104
105 #define CLK32K_COMP_DIR_ADD BIT(7)
106 #define CLK32K_COMP_EN BIT(2)
107 #define CLK32K_NO_COMP 0x1
108
109 #define CLK32K_TEST_REF_CLK 24000000
110
111 #define RTC_WRITE_MASK 0xc4522900
112
113 enum {
114 ROCKCHIP_RV1106_RTC = 1,
115 };
116
117 struct rockchip_rtc {
118 struct regmap *regmap;
119 struct rtc_device *rtc;
120 struct regmap *grf;
121 struct clk_bulk_data *clks;
122 int num_clks;
123 int irq;
124 unsigned int flag;
125 unsigned int mode;
126 struct delayed_work trim_work;
127 };
128
rockchip_rtc_write(struct regmap * map,u32 offset,u32 val)129 static unsigned int rockchip_rtc_write(struct regmap *map,
130 u32 offset, u32 val)
131 {
132 return regmap_write(map, offset, val | RTC_WRITE_MASK);
133 }
134
rockchip_rtc_update_bits(struct regmap * map,u32 offset,u32 mask,u32 set)135 static unsigned int rockchip_rtc_update_bits(struct regmap *map,
136 u32 offset, u32 mask,
137 u32 set)
138 {
139 unsigned int val;
140
141 regmap_read(map, offset, &val);
142 return regmap_write(map, offset, (val & ~mask) | set | RTC_WRITE_MASK);
143 }
144
145 /* Read current time and date in RTC */
rockchip_rtc_read_time(struct device * dev,struct rtc_time * tm)146 static int rockchip_rtc_read_time(struct device *dev, struct rtc_time *tm)
147 {
148 struct rockchip_rtc *rtc = dev_get_drvdata(dev);
149 u32 rtc_data[NUM_TIME_REGS];
150 int ret;
151 int yearl, yearh;
152
153 /* No shadowed registers, need read time three time to update time */
154 ret = regmap_bulk_read(rtc->regmap, RTC_SET_SECONDS,
155 rtc_data, NUM_TIME_REGS);
156 if (ret) {
157 dev_err(dev, "Failed to bulk read rtc_data: %d\n", ret);
158 return ret;
159 }
160 ret = regmap_bulk_read(rtc->regmap, RTC_SET_SECONDS,
161 rtc_data, NUM_TIME_REGS);
162 if (ret) {
163 dev_err(dev, "Failed to bulk read rtc_data: %d\n", ret);
164 return ret;
165 }
166 ret = regmap_bulk_read(rtc->regmap, RTC_SET_SECONDS,
167 rtc_data, NUM_TIME_REGS);
168 if (ret) {
169 dev_err(dev, "Failed to bulk read rtc_data: %d\n", ret);
170 return ret;
171 }
172
173 tm->tm_sec = bcd2bin(rtc_data[0] & SECONDS_REG_MSK);
174 tm->tm_min = bcd2bin(rtc_data[1] & MINUTES_REG_MAK);
175 tm->tm_hour = bcd2bin(rtc_data[2] & HOURS_REG_MSK);
176 tm->tm_mday = bcd2bin(rtc_data[3] & DAYS_REG_MSK);
177 tm->tm_mon = (bcd2bin(rtc_data[4] & MONTHS_REG_MSK)) - 1;
178 yearl = (bcd2bin(rtc_data[5] & YEARS_REG_MSK));
179 yearh = (bcd2bin(rtc_data[6] & YEARS_REG_MSK));
180 tm->tm_year = yearh * 100 + yearl + 100;
181 tm->tm_wday = bcd2bin(rtc_data[7] & WEEKS_REG_MSK);
182
183 dev_dbg(dev, "RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
184 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
185 tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec);
186
187 return ret;
188 }
189
190 /* Set current time and date in RTC */
rockchip_rtc_set_time(struct device * dev,struct rtc_time * tm)191 static int rockchip_rtc_set_time(struct device *dev, struct rtc_time *tm)
192 {
193 struct rockchip_rtc *rtc = dev_get_drvdata(dev);
194 u32 rtc_data[NUM_TIME_REGS];
195 int ret, status = 0;
196 int yearl, yearh;
197
198 dev_dbg(dev, "set RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
199 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
200 tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec);
201
202 rtc_data[0] = bin2bcd(tm->tm_sec) | RTC_WRITE_MASK;
203 rtc_data[1] = bin2bcd(tm->tm_min) | RTC_WRITE_MASK;
204 rtc_data[2] = bin2bcd(tm->tm_hour) | RTC_WRITE_MASK;
205 rtc_data[3] = bin2bcd(tm->tm_mday) | RTC_WRITE_MASK;
206 rtc_data[4] = bin2bcd(tm->tm_mon + 1) | RTC_WRITE_MASK;
207 if (tm->tm_year > 199) {
208 yearh = (tm->tm_year - 100) / 100;
209 yearl = tm->tm_year - 100 - yearh * 100;
210 } else {
211 yearh = 0;
212 yearl = tm->tm_year - 100 - yearh * 100;
213 }
214 rtc_data[5] = bin2bcd(yearl) | RTC_WRITE_MASK;
215 rtc_data[6] = bin2bcd(yearh) | RTC_WRITE_MASK;
216 rtc_data[7] = bin2bcd(tm->tm_wday) | RTC_WRITE_MASK;
217
218 /* Stop RTC while updating the RTC registers */
219 ret = rockchip_rtc_update_bits(rtc->regmap, RTC_CTRL,
220 RTC_CTRL_REG_START_RTC, 0);
221 if (ret) {
222 dev_err(dev, "Failed to update RTC control: %d\n", ret);
223 return ret;
224 }
225
226 ret = regmap_read_poll_timeout(rtc->regmap, RTC_STATUS1, status,
227 !(status & RTC_CTRL_REG_START_RTC),
228 0, RTC_TIMEOUT);
229 if (ret)
230 dev_err(dev,
231 "%s:timeout Update RTC_STATUS1 : %d\n",
232 __func__, ret);
233
234 ret = regmap_bulk_write(rtc->regmap, RTC_SET_SECONDS,
235 rtc_data, NUM_TIME_REGS);
236 if (ret) {
237 dev_err(dev, "Failed to bull write rtc_data: %d\n", ret);
238 return ret;
239 }
240
241 /* Start RTC again */
242 ret = rockchip_rtc_update_bits(rtc->regmap, RTC_CTRL,
243 RTC_CTRL_REG_RTC_READSEL_M |
244 RTC_CTRL_REG_START_RTC,
245 RTC_CTRL_REG_RTC_READSEL_M |
246 RTC_CTRL_REG_START_RTC);
247 if (ret) {
248 dev_err(dev, "Failed to update RTC control: %d\n", ret);
249 return ret;
250 }
251
252 ret = regmap_read_poll_timeout(rtc->regmap, RTC_STATUS1, status,
253 (status & RTC_CTRL_REG_START_RTC),
254 0, RTC_TIMEOUT);
255 if (ret)
256 dev_err(dev,
257 "%s:timeout Update RTC_STATUS1 : %d\n",
258 __func__, ret);
259
260 return 0;
261 }
262
263 /* Read alarm time and date in RTC */
rockchip_rtc_readalarm(struct device * dev,struct rtc_wkalrm * alrm)264 static int rockchip_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
265 {
266 struct rockchip_rtc *rtc = dev_get_drvdata(dev);
267 u32 alrm_data[NUM_ALARM_REGS];
268 u32 int_reg;
269 int yearl, yearh;
270 int ret;
271
272 ret = regmap_bulk_read(rtc->regmap,
273 RTC_ALARM_SECONDS,
274 alrm_data, NUM_ALARM_REGS);
275 if (ret) {
276 dev_err(dev, "Failed to read RTC alarm date REG: %d\n", ret);
277 return ret;
278 }
279
280 alrm->time.tm_sec = bcd2bin(alrm_data[0] & SECONDS_REG_MSK);
281 alrm->time.tm_min = bcd2bin(alrm_data[1] & MINUTES_REG_MAK);
282 alrm->time.tm_hour = bcd2bin(alrm_data[2] & HOURS_REG_MSK);
283 alrm->time.tm_mday = bcd2bin(alrm_data[3] & DAYS_REG_MSK);
284 alrm->time.tm_mon = (bcd2bin(alrm_data[4] & MONTHS_REG_MSK)) - 1;
285 yearl = (bcd2bin(alrm_data[5] & YEARS_REG_MSK));
286 yearh = (bcd2bin(alrm_data[6] & YEARS_REG_MSK));
287 alrm->time.tm_year = yearh * 100 + yearl + 100;
288
289 ret = regmap_read(rtc->regmap, RTC_INT0_EN, &int_reg);
290 if (ret) {
291 dev_err(dev, "Failed to read RTC INT REG: %d\n", ret);
292 return ret;
293 }
294
295 dev_dbg(dev,
296 "alrm read RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
297 1900 + alrm->time.tm_year, alrm->time.tm_mon + 1,
298 alrm->time.tm_mday, alrm->time.tm_wday, alrm->time.tm_hour,
299 alrm->time.tm_min, alrm->time.tm_sec);
300
301 alrm->enabled = (int_reg & RTC_INT_REG_ALARM_EN) ? 1 : 0;
302
303 return 0;
304 }
305
rockchip_rtc_stop_alarm(struct rockchip_rtc * rtc)306 static int rockchip_rtc_stop_alarm(struct rockchip_rtc *rtc)
307 {
308 int ret;
309
310 ret = rockchip_rtc_write(rtc->regmap, RTC_INT0_EN, 0);
311
312 return ret;
313 }
314
rockchip_rtc_start_alarm(struct rockchip_rtc * rtc)315 static int rockchip_rtc_start_alarm(struct rockchip_rtc *rtc)
316 {
317 int ret;
318
319 ret = rockchip_rtc_write(rtc->regmap, RTC_STATUS0, RTC_STATUS_MASK);
320 ret = rockchip_rtc_write(rtc->regmap, RTC_STATUS0, 0);
321 ret = rockchip_rtc_write(rtc->regmap, RTC_INT0_EN, ENABLE_ALARM_INT);
322
323 return ret;
324 }
325
rockchip_rtc_setalarm(struct device * dev,struct rtc_wkalrm * alrm)326 static int rockchip_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
327 {
328 struct rockchip_rtc *rtc = dev_get_drvdata(dev);
329 u32 alrm_data[NUM_ALARM_REGS];
330 int yearl, yearh;
331 int ret;
332
333 ret = rockchip_rtc_stop_alarm(rtc);
334 if (ret) {
335 dev_err(dev, "Failed to stop alarm: %d\n", ret);
336 return ret;
337 }
338 dev_dbg(dev,
339 "alrm set RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
340 1900 + alrm->time.tm_year, alrm->time.tm_mon + 1,
341 alrm->time.tm_mday, alrm->time.tm_wday, alrm->time.tm_hour,
342 alrm->time.tm_min, alrm->time.tm_sec);
343
344 alrm_data[0] = bin2bcd(alrm->time.tm_sec) | RTC_WRITE_MASK;
345 alrm_data[1] = bin2bcd(alrm->time.tm_min) | RTC_WRITE_MASK;
346 alrm_data[2] = bin2bcd(alrm->time.tm_hour) | RTC_WRITE_MASK;
347 alrm_data[3] = bin2bcd(alrm->time.tm_mday) | RTC_WRITE_MASK;
348 alrm_data[4] = bin2bcd(alrm->time.tm_mon + 1) | RTC_WRITE_MASK;
349 if (alrm->time.tm_year > 199) {
350 yearh = (alrm->time.tm_year - 100) / 100;
351 yearl = alrm->time.tm_year - 100 - yearh * 100;
352 } else {
353 yearh = 0;
354 yearl = alrm->time.tm_year - 100 - yearh * 100;
355 }
356 alrm_data[5] = bin2bcd(yearl) | RTC_WRITE_MASK;
357 alrm_data[6] = bin2bcd(yearh) | RTC_WRITE_MASK;
358
359 ret = regmap_bulk_write(rtc->regmap,
360 RTC_ALARM_SECONDS,
361 alrm_data, NUM_ALARM_REGS);
362 if (ret) {
363 dev_err(dev, "Failed to bulk write: %d\n", ret);
364 return ret;
365 }
366 if (alrm->enabled) {
367 ret = rockchip_rtc_start_alarm(rtc);
368 if (ret) {
369 dev_err(dev, "Failed to start alarm: %d\n", ret);
370 return ret;
371 }
372 }
373 return 0;
374 }
375
rockchip_rtc_alarm_irq_enable(struct device * dev,unsigned int enabled)376 static int rockchip_rtc_alarm_irq_enable(struct device *dev,
377 unsigned int enabled)
378 {
379 struct rockchip_rtc *rtc = dev_get_drvdata(dev);
380
381 if (enabled)
382 return rockchip_rtc_start_alarm(rtc);
383
384 return rockchip_rtc_stop_alarm(rtc);
385 }
386
387 /*
388 * We will just handle setting the frequency and make use the framework for
389 * reading the periodic interrupts.
390 *
391 */
rockchip_rtc_alarm_irq(int irq,void * data)392 static irqreturn_t rockchip_rtc_alarm_irq(int irq, void *data)
393 {
394 struct rockchip_rtc *rtc = data;
395 int ret, status;
396
397 ret = regmap_read(rtc->regmap, RTC_STATUS0, &status);
398 if (ret) {
399 pr_err("Failed to read RTC INT REG: %d\n", ret);
400 return ret;
401 }
402
403 ret = rockchip_rtc_write(rtc->regmap, RTC_STATUS0, status);
404 if (ret) {
405 pr_err("%s:Failed to update RTC status: %d\n", __func__, ret);
406 return ret;
407 }
408 if (status & ALARM_INT_STATUS) {
409 pr_info("Alarm by: %s\n", __func__);
410 rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_AF);
411 }
412
413 return IRQ_HANDLED;
414 }
415
416 static const struct rtc_class_ops rockchip_rtc_ops = {
417 .read_time = rockchip_rtc_read_time,
418 .set_time = rockchip_rtc_set_time,
419 .read_alarm = rockchip_rtc_readalarm,
420 .set_alarm = rockchip_rtc_setalarm,
421 .alarm_irq_enable = rockchip_rtc_alarm_irq_enable,
422 };
423
424 /*
425 * Due to the analog generator 32k clock affected by
426 * temperature, voltage, clock precision need test
427 * with the environment change. In rtc test,
428 * use 24M clock as reference clock to measure the 32k clock.
429 * Before start test 32k clock, we should enable clk32k test(0x80),
430 * and configure test length, when rtc test done(0x84[2]),
431 * latch the 24M clock domain counter,
432 * and read out the counter from rtc_test
433 * registers(0x8c~0x98) via apb bus.
434 * In RTC digital design, we set three level compensation,
435 * the compensation value due to the
436 * RTC 32k clock test result, and if we need compensation,
437 * we need configure the compensation enable bit.
438 * Comp every hour, compensation at last minute every hour,
439 * and support add time and sub time by the MSB bit.
440 * Comp every day, compensation at last minute in last hour every day,
441 * and support add time and sub time by the MSB bit.
442 * Comp every month, compensation at last minute
443 * in last hour in last day every month,
444 * and support add time and sub time by the MSB bit.
445 */
rockchip_rtc_compensation_delay_work(struct work_struct * work)446 static void rockchip_rtc_compensation_delay_work(struct work_struct *work)
447 {
448 struct rockchip_rtc *rtc = container_of(work, struct rockchip_rtc, trim_work.work);
449 u64 camp;
450 u32 count[4], counts, g_ref, tcamp;
451 int ret, done = 0, trim_dir, c_hour,
452 c_day, c_det_day, c_mon, c_det_mon;
453
454 ret = rockchip_rtc_update_bits(rtc->regmap, RTC_CLK32K_TEST,
455 CLK32K_TEST_EN, CLK32K_TEST_EN);
456 if (ret) {
457 pr_err("%s:Failed to update RTC CLK32K TEST: %d\n",
458 __func__, ret);
459 return;
460 }
461
462 ret = rockchip_rtc_write(rtc->regmap, RTC_TEST_LEN,
463 CLK32K_TEST_LEN);
464 if (ret) {
465 pr_err("%s:Failed to update RTC CLK32K TEST LEN: %d\n",
466 __func__, ret);
467 return;
468 }
469
470 ret = rockchip_rtc_update_bits(rtc->regmap, RTC_TEST_ST,
471 CLK32K_TEST_START,
472 CLK32K_TEST_START);
473 if (ret) {
474 pr_err("%s:Failed to update RTC CLK32K TEST STATUS : %d\n",
475 __func__, ret);
476 return;
477 }
478 ret = regmap_read_poll_timeout(rtc->regmap, RTC_TEST_ST, done,
479 (done & CLK32K_TEST_DONE), 20000, RTC_TIMEOUT);
480 if (ret)
481 pr_err("%s:timeout waiting for RTC TEST STATUS : %d\n",
482 __func__, ret);
483
484 ret = regmap_bulk_read(rtc->regmap,
485 RTC_CNT_0,
486 count, 4);
487 if (ret) {
488 pr_err("Failed to read RTC count REG: %d\n", ret);
489 return;
490 }
491
492 counts = count[0] | (count[1] << 8) |
493 (count[2] << 16) | (count[3] << 24);
494 g_ref = CLK32K_TEST_REF_CLK * (CLK32K_TEST_LEN + 1);
495
496 if (counts > g_ref) {
497 trim_dir = 0;
498 camp = 36ULL * (32768 * (counts - g_ref));
499 do_div(camp, (g_ref / 100));
500 } else {
501 trim_dir = CLK32K_COMP_DIR_ADD;
502 camp = 36ULL * (32768 * (g_ref - counts));
503 do_div(camp, (g_ref / 100));
504 }
505 tcamp = (u32)camp;
506 c_hour = DIV_ROUND_CLOSEST(tcamp, 32768);
507 c_day = DIV_ROUND_CLOSEST(24 * tcamp, 32768);
508 c_mon = DIV_ROUND_CLOSEST(30 * 24 * tcamp, 32768);
509
510 if (c_hour > 1)
511 rockchip_rtc_write(rtc->regmap, RTC_COMP_H, (c_hour - 1) | trim_dir);
512 else
513 rockchip_rtc_write(rtc->regmap, RTC_COMP_H, CLK32K_NO_COMP);
514
515 if (c_day > c_hour * 23) {
516 c_det_day = c_day - c_hour * 23;
517 trim_dir = CLK32K_COMP_DIR_ADD;
518 } else {
519 c_det_day = c_hour * 24 - c_day;
520 trim_dir = 0;
521 }
522
523 if (c_det_day > 1)
524 rockchip_rtc_write(rtc->regmap, RTC_COMP_D,
525 (c_det_day - 1) | trim_dir);
526 else
527 rockchip_rtc_write(rtc->regmap, RTC_COMP_D, CLK32K_NO_COMP);
528
529 if (c_mon > (29 * c_day + 23 * c_hour)) {
530 c_det_mon = c_mon - 29 * c_day - 23 * c_hour;
531 trim_dir = CLK32K_COMP_DIR_ADD;
532 } else {
533 c_det_mon = 29 * c_day + 23 * c_hour - c_mon;
534 trim_dir = 0;
535 }
536
537 if (c_det_mon)
538 rockchip_rtc_write(rtc->regmap, RTC_COMP_M,
539 (c_det_mon - 1) | trim_dir);
540 else
541 rockchip_rtc_write(rtc->regmap, RTC_COMP_M, CLK32K_NO_COMP);
542
543 ret = regmap_read(rtc->regmap, RTC_CTRL, &done);
544 if (ret) {
545 pr_err("Failed to read RTC_CTRL: %d\n", ret);
546 return;
547 }
548
549 ret = rockchip_rtc_update_bits(rtc->regmap, RTC_CTRL,
550 CLK32K_COMP_EN, CLK32K_COMP_EN);
551 if (ret) {
552 pr_err("%s:Failed to update RTC CTRL : %d\n", __func__, ret);
553 return;
554 }
555 return;
556 }
557
558 /* Enable the alarm if it should be enabled (in case it was disabled to
559 * prevent use as a wake source).
560 */
561 #ifdef CONFIG_PM_SLEEP
562 /* Turn off the alarm if it should not be a wake source. */
rockchip_rtc_suspend(struct device * dev)563 static int rockchip_rtc_suspend(struct device *dev)
564 {
565 struct platform_device *pdev = to_platform_device(dev);
566 struct rockchip_rtc *rtc = dev_get_drvdata(&pdev->dev);
567
568 if (device_may_wakeup(dev))
569 enable_irq_wake(rtc->irq);
570
571 if (rtc->grf) {
572 switch (rtc->mode) {
573 case ROCKCHIP_RV1106_RTC:
574 regmap_write(rtc->grf, VI_GRF_VI_MISC_CON0,
575 (RTC_CLAMP_EN << 16));
576 break;
577 default:
578 return -EINVAL;
579 }
580 }
581 clk_bulk_disable_unprepare(rtc->num_clks, rtc->clks);
582
583 return 0;
584 }
585
586 /* Enable the alarm if it should be enabled (in case it was disabled to
587 * prevent use as a wake source).
588 */
rockchip_rtc_resume(struct device * dev)589 static int rockchip_rtc_resume(struct device *dev)
590 {
591 struct platform_device *pdev = to_platform_device(dev);
592 struct rockchip_rtc *rtc = dev_get_drvdata(&pdev->dev);
593 int ret;
594
595 if (device_may_wakeup(dev))
596 disable_irq_wake(rtc->irq);
597
598 if (rtc->grf) {
599 switch (rtc->mode) {
600 case ROCKCHIP_RV1106_RTC:
601 regmap_write(rtc->grf, VI_GRF_VI_MISC_CON0,
602 (RTC_CLAMP_EN << 16) | RTC_CLAMP_EN);
603 break;
604 default:
605 return -EINVAL;
606 }
607 }
608 ret = clk_bulk_prepare_enable(rtc->num_clks, rtc->clks);
609 if (ret) {
610 dev_err(dev, "Cannot enable clock.\n");
611 return ret;
612 }
613
614 return 0;
615 }
616 #endif
617
618 static SIMPLE_DEV_PM_OPS(rockchip_rtc_pm_ops,
619 rockchip_rtc_suspend, rockchip_rtc_resume);
620
621 static const struct of_device_id rockchip_rtc_of_match[] = {
622 {
623 .compatible = "rockchip,rv1106-rtc",
624 .data = (void *)ROCKCHIP_RV1106_RTC
625 },
626 {},
627 };
628 MODULE_DEVICE_TABLE(of, rockchip_rtc_of_match);
629
rockchip_rtc_clk_disable(void * data)630 static void rockchip_rtc_clk_disable(void *data)
631 {
632 struct rockchip_rtc *rtc = data;
633
634 clk_bulk_disable_unprepare(rtc->num_clks, rtc->clks);
635 }
636
rockchip_rtc_probe(struct platform_device * pdev)637 static int rockchip_rtc_probe(struct platform_device *pdev)
638 {
639 struct device *dev = &pdev->dev;
640 struct device_node *np = dev->of_node;
641 struct rockchip_rtc *rtc;
642 int ret;
643 struct rtc_time tm_read, tm = {
644 .tm_wday = 0,
645 .tm_year = 121,
646 .tm_mon = 0,
647 .tm_mday = 1,
648 .tm_hour = 12,
649 .tm_min = 0,
650 .tm_sec = 0,
651 };
652
653 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
654 if (!rtc)
655 return -ENOMEM;
656
657 rtc->regmap = device_node_to_regmap(np);
658 if (IS_ERR(rtc->regmap))
659 return dev_err_probe(dev, PTR_ERR(rtc->regmap),
660 "no regmap available\n");
661
662 rtc->mode = (uintptr_t)device_get_match_data(dev);
663 rtc->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
664 if (IS_ERR(rtc->grf)) {
665 dev_warn(dev, "Missing rockchip,grf property\n");
666 rtc->grf = NULL;
667 } else {
668 switch (rtc->mode) {
669 case ROCKCHIP_RV1106_RTC:
670 regmap_write(rtc->grf, VI_GRF_VI_MISC_CON0,
671 (RTC_CLAMP_EN << 16) | RTC_CLAMP_EN);
672 break;
673 default:
674 return -EINVAL;
675 }
676 }
677
678 platform_set_drvdata(pdev, rtc);
679
680 rtc->num_clks = devm_clk_bulk_get_all(&pdev->dev, &rtc->clks);
681 if (rtc->num_clks < 1)
682 return -ENODEV;
683 ret = clk_bulk_prepare_enable(rtc->num_clks, rtc->clks);
684 if (ret)
685 return dev_err_probe(dev, ret, "Cannot enable clock.\n");
686 ret = devm_add_action_or_reset(dev, rockchip_rtc_clk_disable, rtc);
687 if (ret)
688 return dev_err_probe(dev, ret,
689 "Failed to add clk disable action.");
690
691 ret = rockchip_rtc_update_bits(rtc->regmap, RTC_VPTAT_TRIM,
692 D2A_POR_REG_SEL1,
693 D2A_POR_REG_SEL1);
694 if (ret)
695 return dev_err_probe(&pdev->dev, ret,
696 "Failed to write RTC_VPTAT_TRIM\n");
697 ret = rockchip_rtc_update_bits(rtc->regmap, RTC_ANALOG_EN,
698 D2A_POR_REG_SEL0,
699 0x00);
700 if (ret)
701 return dev_err_probe(&pdev->dev, ret,
702 "Failed to write RTC_ANALOG_EN\n");
703
704 ret = rockchip_rtc_update_bits(rtc->regmap, RTC_LDO_CTRL,
705 RTC_D2A_XO_EN,
706 RTC_D2A_XO_EN);
707 if (ret)
708 return dev_err_probe(&pdev->dev, ret,
709 "Failed to update RTC_LDO_CTRL\n");
710
711 ret = rockchip_rtc_update_bits(rtc->regmap, RTC_ANALOG_EN,
712 RTC_D2A_CLK_OUT_EN,
713 RTC_D2A_CLK_OUT_EN);
714 if (ret)
715 return dev_err_probe(&pdev->dev, ret,
716 "Failed to update RTC_ANALOG_EN\n");
717
718 /* start rtc running by default, and use shadowed timer. */
719 ret = rockchip_rtc_update_bits(rtc->regmap, RTC_CTRL,
720 RTC_CTRL_REG_START_RTC |
721 RTC_CTRL_REG_RTC_READSEL_M,
722 RTC_CTRL_REG_RTC_READSEL_M |
723 RTC_CTRL_REG_START_RTC);
724 if (ret)
725 return dev_err_probe(&pdev->dev, ret,
726 "Failed to update RTC control\n");
727
728 ret = rockchip_rtc_write(rtc->regmap, RTC_STATUS0, RTC_STATUS_MASK);
729 if (ret)
730 return dev_err_probe(&pdev->dev, ret,
731 "Failed to write RTC status0\n");
732
733 ret = rockchip_rtc_write(rtc->regmap, RTC_STATUS0, 0);
734 if (ret)
735 return dev_err_probe(&pdev->dev, ret,
736 "Failed to write RTC status0\n");
737
738 device_init_wakeup(&pdev->dev, 1);
739
740 rockchip_rtc_read_time(&pdev->dev, &tm_read);
741 if (rtc_valid_tm(&tm_read) != 0)
742 rockchip_rtc_set_time(&pdev->dev, &tm);
743
744 rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
745 if (IS_ERR(rtc->rtc))
746 return PTR_ERR(rtc->rtc);
747
748 rtc->rtc->ops = &rockchip_rtc_ops;
749
750 rtc->irq = platform_get_irq(pdev, 0);
751 if (rtc->irq < 0)
752 return dev_err_probe(&pdev->dev, rtc->irq, "No IRQ resource\n");
753
754 /* request alarm irq of rtc */
755 ret = devm_request_threaded_irq(&pdev->dev, rtc->irq, NULL,
756 &rockchip_rtc_alarm_irq, IRQF_ONESHOT,
757 "RTC alarm", rtc);
758 if (ret)
759 return dev_err_probe(&pdev->dev, ret,
760 "Failed to request alarm IRQ %d\n",
761 rtc->irq);
762
763 INIT_DELAYED_WORK(&rtc->trim_work, rockchip_rtc_compensation_delay_work);
764 queue_delayed_work(system_long_wq, &rtc->trim_work, 3000);
765
766 return rtc_register_device(rtc->rtc);
767 }
768
769 static struct platform_driver rockchip_rtc_driver = {
770 .probe = rockchip_rtc_probe,
771 .driver = {
772 .name = "rockchip-rtc",
773 .pm = &rockchip_rtc_pm_ops,
774 .of_match_table = rockchip_rtc_of_match,
775 },
776 };
777
778 module_platform_driver(rockchip_rtc_driver);
779
780 MODULE_DESCRIPTION("RTC driver for the rockchip");
781 MODULE_AUTHOR("Zhang Qing <zhangqing@rock-chips.com>");
782 MODULE_LICENSE("GPL");
783