1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * drivers/rtc/rtc-pl031.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Real Time Clock interface for ARM AMBA PrimeCell 031 RTC
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Deepak Saxena <dsaxena@plexity.net>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Copyright 2006 (c) MontaVista Software, Inc.
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
12*4882a593Smuzhiyun * Copyright 2010 (c) ST-Ericsson AB
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/rtc.h>
16*4882a593Smuzhiyun #include <linux/init.h>
17*4882a593Smuzhiyun #include <linux/interrupt.h>
18*4882a593Smuzhiyun #include <linux/amba/bus.h>
19*4882a593Smuzhiyun #include <linux/io.h>
20*4882a593Smuzhiyun #include <linux/bcd.h>
21*4882a593Smuzhiyun #include <linux/delay.h>
22*4882a593Smuzhiyun #include <linux/pm_wakeirq.h>
23*4882a593Smuzhiyun #include <linux/slab.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /*
26*4882a593Smuzhiyun * Register definitions
27*4882a593Smuzhiyun */
28*4882a593Smuzhiyun #define RTC_DR 0x00 /* Data read register */
29*4882a593Smuzhiyun #define RTC_MR 0x04 /* Match register */
30*4882a593Smuzhiyun #define RTC_LR 0x08 /* Data load register */
31*4882a593Smuzhiyun #define RTC_CR 0x0c /* Control register */
32*4882a593Smuzhiyun #define RTC_IMSC 0x10 /* Interrupt mask and set register */
33*4882a593Smuzhiyun #define RTC_RIS 0x14 /* Raw interrupt status register */
34*4882a593Smuzhiyun #define RTC_MIS 0x18 /* Masked interrupt status register */
35*4882a593Smuzhiyun #define RTC_ICR 0x1c /* Interrupt clear register */
36*4882a593Smuzhiyun /* ST variants have additional timer functionality */
37*4882a593Smuzhiyun #define RTC_TDR 0x20 /* Timer data read register */
38*4882a593Smuzhiyun #define RTC_TLR 0x24 /* Timer data load register */
39*4882a593Smuzhiyun #define RTC_TCR 0x28 /* Timer control register */
40*4882a593Smuzhiyun #define RTC_YDR 0x30 /* Year data read register */
41*4882a593Smuzhiyun #define RTC_YMR 0x34 /* Year match register */
42*4882a593Smuzhiyun #define RTC_YLR 0x38 /* Year data load register */
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define RTC_CR_EN (1 << 0) /* counter enable bit */
45*4882a593Smuzhiyun #define RTC_CR_CWEN (1 << 26) /* Clockwatch enable bit */
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define RTC_TCR_EN (1 << 1) /* Periodic timer enable bit */
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* Common bit definitions for Interrupt status and control registers */
50*4882a593Smuzhiyun #define RTC_BIT_AI (1 << 0) /* Alarm interrupt bit */
51*4882a593Smuzhiyun #define RTC_BIT_PI (1 << 1) /* Periodic interrupt bit. ST variants only. */
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* Common bit definations for ST v2 for reading/writing time */
54*4882a593Smuzhiyun #define RTC_SEC_SHIFT 0
55*4882a593Smuzhiyun #define RTC_SEC_MASK (0x3F << RTC_SEC_SHIFT) /* Second [0-59] */
56*4882a593Smuzhiyun #define RTC_MIN_SHIFT 6
57*4882a593Smuzhiyun #define RTC_MIN_MASK (0x3F << RTC_MIN_SHIFT) /* Minute [0-59] */
58*4882a593Smuzhiyun #define RTC_HOUR_SHIFT 12
59*4882a593Smuzhiyun #define RTC_HOUR_MASK (0x1F << RTC_HOUR_SHIFT) /* Hour [0-23] */
60*4882a593Smuzhiyun #define RTC_WDAY_SHIFT 17
61*4882a593Smuzhiyun #define RTC_WDAY_MASK (0x7 << RTC_WDAY_SHIFT) /* Day of Week [1-7] 1=Sunday */
62*4882a593Smuzhiyun #define RTC_MDAY_SHIFT 20
63*4882a593Smuzhiyun #define RTC_MDAY_MASK (0x1F << RTC_MDAY_SHIFT) /* Day of Month [1-31] */
64*4882a593Smuzhiyun #define RTC_MON_SHIFT 25
65*4882a593Smuzhiyun #define RTC_MON_MASK (0xF << RTC_MON_SHIFT) /* Month [1-12] 1=January */
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #define RTC_TIMER_FREQ 32768
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /**
70*4882a593Smuzhiyun * struct pl031_vendor_data - per-vendor variations
71*4882a593Smuzhiyun * @ops: the vendor-specific operations used on this silicon version
72*4882a593Smuzhiyun * @clockwatch: if this is an ST Microelectronics silicon version with a
73*4882a593Smuzhiyun * clockwatch function
74*4882a593Smuzhiyun * @st_weekday: if this is an ST Microelectronics silicon version that need
75*4882a593Smuzhiyun * the weekday fix
76*4882a593Smuzhiyun * @irqflags: special IRQ flags per variant
77*4882a593Smuzhiyun */
78*4882a593Smuzhiyun struct pl031_vendor_data {
79*4882a593Smuzhiyun struct rtc_class_ops ops;
80*4882a593Smuzhiyun bool clockwatch;
81*4882a593Smuzhiyun bool st_weekday;
82*4882a593Smuzhiyun unsigned long irqflags;
83*4882a593Smuzhiyun time64_t range_min;
84*4882a593Smuzhiyun timeu64_t range_max;
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun struct pl031_local {
88*4882a593Smuzhiyun struct pl031_vendor_data *vendor;
89*4882a593Smuzhiyun struct rtc_device *rtc;
90*4882a593Smuzhiyun void __iomem *base;
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun
pl031_alarm_irq_enable(struct device * dev,unsigned int enabled)93*4882a593Smuzhiyun static int pl031_alarm_irq_enable(struct device *dev,
94*4882a593Smuzhiyun unsigned int enabled)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun struct pl031_local *ldata = dev_get_drvdata(dev);
97*4882a593Smuzhiyun unsigned long imsc;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /* Clear any pending alarm interrupts. */
100*4882a593Smuzhiyun writel(RTC_BIT_AI, ldata->base + RTC_ICR);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun imsc = readl(ldata->base + RTC_IMSC);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun if (enabled == 1)
105*4882a593Smuzhiyun writel(imsc | RTC_BIT_AI, ldata->base + RTC_IMSC);
106*4882a593Smuzhiyun else
107*4882a593Smuzhiyun writel(imsc & ~RTC_BIT_AI, ldata->base + RTC_IMSC);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun return 0;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /*
113*4882a593Smuzhiyun * Convert Gregorian date to ST v2 RTC format.
114*4882a593Smuzhiyun */
pl031_stv2_tm_to_time(struct device * dev,struct rtc_time * tm,unsigned long * st_time,unsigned long * bcd_year)115*4882a593Smuzhiyun static int pl031_stv2_tm_to_time(struct device *dev,
116*4882a593Smuzhiyun struct rtc_time *tm, unsigned long *st_time,
117*4882a593Smuzhiyun unsigned long *bcd_year)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun int year = tm->tm_year + 1900;
120*4882a593Smuzhiyun int wday = tm->tm_wday;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun /* wday masking is not working in hardware so wday must be valid */
123*4882a593Smuzhiyun if (wday < -1 || wday > 6) {
124*4882a593Smuzhiyun dev_err(dev, "invalid wday value %d\n", tm->tm_wday);
125*4882a593Smuzhiyun return -EINVAL;
126*4882a593Smuzhiyun } else if (wday == -1) {
127*4882a593Smuzhiyun /* wday is not provided, calculate it here */
128*4882a593Smuzhiyun struct rtc_time calc_tm;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun rtc_time64_to_tm(rtc_tm_to_time64(tm), &calc_tm);
131*4882a593Smuzhiyun wday = calc_tm.tm_wday;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun *bcd_year = (bin2bcd(year % 100) | bin2bcd(year / 100) << 8);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun *st_time = ((tm->tm_mon + 1) << RTC_MON_SHIFT)
137*4882a593Smuzhiyun | (tm->tm_mday << RTC_MDAY_SHIFT)
138*4882a593Smuzhiyun | ((wday + 1) << RTC_WDAY_SHIFT)
139*4882a593Smuzhiyun | (tm->tm_hour << RTC_HOUR_SHIFT)
140*4882a593Smuzhiyun | (tm->tm_min << RTC_MIN_SHIFT)
141*4882a593Smuzhiyun | (tm->tm_sec << RTC_SEC_SHIFT);
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun return 0;
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun /*
147*4882a593Smuzhiyun * Convert ST v2 RTC format to Gregorian date.
148*4882a593Smuzhiyun */
pl031_stv2_time_to_tm(unsigned long st_time,unsigned long bcd_year,struct rtc_time * tm)149*4882a593Smuzhiyun static int pl031_stv2_time_to_tm(unsigned long st_time, unsigned long bcd_year,
150*4882a593Smuzhiyun struct rtc_time *tm)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun tm->tm_year = bcd2bin(bcd_year) + (bcd2bin(bcd_year >> 8) * 100);
153*4882a593Smuzhiyun tm->tm_mon = ((st_time & RTC_MON_MASK) >> RTC_MON_SHIFT) - 1;
154*4882a593Smuzhiyun tm->tm_mday = ((st_time & RTC_MDAY_MASK) >> RTC_MDAY_SHIFT);
155*4882a593Smuzhiyun tm->tm_wday = ((st_time & RTC_WDAY_MASK) >> RTC_WDAY_SHIFT) - 1;
156*4882a593Smuzhiyun tm->tm_hour = ((st_time & RTC_HOUR_MASK) >> RTC_HOUR_SHIFT);
157*4882a593Smuzhiyun tm->tm_min = ((st_time & RTC_MIN_MASK) >> RTC_MIN_SHIFT);
158*4882a593Smuzhiyun tm->tm_sec = ((st_time & RTC_SEC_MASK) >> RTC_SEC_SHIFT);
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
161*4882a593Smuzhiyun tm->tm_year -= 1900;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun return 0;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun
pl031_stv2_read_time(struct device * dev,struct rtc_time * tm)166*4882a593Smuzhiyun static int pl031_stv2_read_time(struct device *dev, struct rtc_time *tm)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun struct pl031_local *ldata = dev_get_drvdata(dev);
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun pl031_stv2_time_to_tm(readl(ldata->base + RTC_DR),
171*4882a593Smuzhiyun readl(ldata->base + RTC_YDR), tm);
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun return 0;
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
pl031_stv2_set_time(struct device * dev,struct rtc_time * tm)176*4882a593Smuzhiyun static int pl031_stv2_set_time(struct device *dev, struct rtc_time *tm)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun unsigned long time;
179*4882a593Smuzhiyun unsigned long bcd_year;
180*4882a593Smuzhiyun struct pl031_local *ldata = dev_get_drvdata(dev);
181*4882a593Smuzhiyun int ret;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun ret = pl031_stv2_tm_to_time(dev, tm, &time, &bcd_year);
184*4882a593Smuzhiyun if (ret == 0) {
185*4882a593Smuzhiyun writel(bcd_year, ldata->base + RTC_YLR);
186*4882a593Smuzhiyun writel(time, ldata->base + RTC_LR);
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun return ret;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
pl031_stv2_read_alarm(struct device * dev,struct rtc_wkalrm * alarm)192*4882a593Smuzhiyun static int pl031_stv2_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun struct pl031_local *ldata = dev_get_drvdata(dev);
195*4882a593Smuzhiyun int ret;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun ret = pl031_stv2_time_to_tm(readl(ldata->base + RTC_MR),
198*4882a593Smuzhiyun readl(ldata->base + RTC_YMR), &alarm->time);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun alarm->pending = readl(ldata->base + RTC_RIS) & RTC_BIT_AI;
201*4882a593Smuzhiyun alarm->enabled = readl(ldata->base + RTC_IMSC) & RTC_BIT_AI;
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun return ret;
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun
pl031_stv2_set_alarm(struct device * dev,struct rtc_wkalrm * alarm)206*4882a593Smuzhiyun static int pl031_stv2_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
207*4882a593Smuzhiyun {
208*4882a593Smuzhiyun struct pl031_local *ldata = dev_get_drvdata(dev);
209*4882a593Smuzhiyun unsigned long time;
210*4882a593Smuzhiyun unsigned long bcd_year;
211*4882a593Smuzhiyun int ret;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun ret = pl031_stv2_tm_to_time(dev, &alarm->time,
214*4882a593Smuzhiyun &time, &bcd_year);
215*4882a593Smuzhiyun if (ret == 0) {
216*4882a593Smuzhiyun writel(bcd_year, ldata->base + RTC_YMR);
217*4882a593Smuzhiyun writel(time, ldata->base + RTC_MR);
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun pl031_alarm_irq_enable(dev, alarm->enabled);
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun return ret;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
pl031_interrupt(int irq,void * dev_id)225*4882a593Smuzhiyun static irqreturn_t pl031_interrupt(int irq, void *dev_id)
226*4882a593Smuzhiyun {
227*4882a593Smuzhiyun struct pl031_local *ldata = dev_id;
228*4882a593Smuzhiyun unsigned long rtcmis;
229*4882a593Smuzhiyun unsigned long events = 0;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun rtcmis = readl(ldata->base + RTC_MIS);
232*4882a593Smuzhiyun if (rtcmis & RTC_BIT_AI) {
233*4882a593Smuzhiyun writel(RTC_BIT_AI, ldata->base + RTC_ICR);
234*4882a593Smuzhiyun events |= (RTC_AF | RTC_IRQF);
235*4882a593Smuzhiyun rtc_update_irq(ldata->rtc, 1, events);
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun return IRQ_HANDLED;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun return IRQ_NONE;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun
pl031_read_time(struct device * dev,struct rtc_time * tm)243*4882a593Smuzhiyun static int pl031_read_time(struct device *dev, struct rtc_time *tm)
244*4882a593Smuzhiyun {
245*4882a593Smuzhiyun struct pl031_local *ldata = dev_get_drvdata(dev);
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun rtc_time64_to_tm(readl(ldata->base + RTC_DR), tm);
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun return 0;
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun
pl031_set_time(struct device * dev,struct rtc_time * tm)252*4882a593Smuzhiyun static int pl031_set_time(struct device *dev, struct rtc_time *tm)
253*4882a593Smuzhiyun {
254*4882a593Smuzhiyun struct pl031_local *ldata = dev_get_drvdata(dev);
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun writel(rtc_tm_to_time64(tm), ldata->base + RTC_LR);
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun return 0;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
pl031_read_alarm(struct device * dev,struct rtc_wkalrm * alarm)261*4882a593Smuzhiyun static int pl031_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun struct pl031_local *ldata = dev_get_drvdata(dev);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun rtc_time64_to_tm(readl(ldata->base + RTC_MR), &alarm->time);
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun alarm->pending = readl(ldata->base + RTC_RIS) & RTC_BIT_AI;
268*4882a593Smuzhiyun alarm->enabled = readl(ldata->base + RTC_IMSC) & RTC_BIT_AI;
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun return 0;
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
pl031_set_alarm(struct device * dev,struct rtc_wkalrm * alarm)273*4882a593Smuzhiyun static int pl031_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun struct pl031_local *ldata = dev_get_drvdata(dev);
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun writel(rtc_tm_to_time64(&alarm->time), ldata->base + RTC_MR);
278*4882a593Smuzhiyun pl031_alarm_irq_enable(dev, alarm->enabled);
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun return 0;
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun
pl031_remove(struct amba_device * adev)283*4882a593Smuzhiyun static void pl031_remove(struct amba_device *adev)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun struct pl031_local *ldata = dev_get_drvdata(&adev->dev);
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun dev_pm_clear_wake_irq(&adev->dev);
288*4882a593Smuzhiyun device_init_wakeup(&adev->dev, false);
289*4882a593Smuzhiyun if (adev->irq[0])
290*4882a593Smuzhiyun free_irq(adev->irq[0], ldata);
291*4882a593Smuzhiyun amba_release_regions(adev);
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun
pl031_probe(struct amba_device * adev,const struct amba_id * id)294*4882a593Smuzhiyun static int pl031_probe(struct amba_device *adev, const struct amba_id *id)
295*4882a593Smuzhiyun {
296*4882a593Smuzhiyun int ret;
297*4882a593Smuzhiyun struct pl031_local *ldata;
298*4882a593Smuzhiyun struct pl031_vendor_data *vendor = id->data;
299*4882a593Smuzhiyun struct rtc_class_ops *ops;
300*4882a593Smuzhiyun unsigned long time, data;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun ret = amba_request_regions(adev, NULL);
303*4882a593Smuzhiyun if (ret)
304*4882a593Smuzhiyun goto err_req;
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun ldata = devm_kzalloc(&adev->dev, sizeof(struct pl031_local),
307*4882a593Smuzhiyun GFP_KERNEL);
308*4882a593Smuzhiyun ops = devm_kmemdup(&adev->dev, &vendor->ops, sizeof(vendor->ops),
309*4882a593Smuzhiyun GFP_KERNEL);
310*4882a593Smuzhiyun if (!ldata || !ops) {
311*4882a593Smuzhiyun ret = -ENOMEM;
312*4882a593Smuzhiyun goto out;
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun ldata->vendor = vendor;
316*4882a593Smuzhiyun ldata->base = devm_ioremap(&adev->dev, adev->res.start,
317*4882a593Smuzhiyun resource_size(&adev->res));
318*4882a593Smuzhiyun if (!ldata->base) {
319*4882a593Smuzhiyun ret = -ENOMEM;
320*4882a593Smuzhiyun goto out;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun amba_set_drvdata(adev, ldata);
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun dev_dbg(&adev->dev, "designer ID = 0x%02x\n", amba_manf(adev));
326*4882a593Smuzhiyun dev_dbg(&adev->dev, "revision = 0x%01x\n", amba_rev(adev));
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun data = readl(ldata->base + RTC_CR);
329*4882a593Smuzhiyun /* Enable the clockwatch on ST Variants */
330*4882a593Smuzhiyun if (vendor->clockwatch)
331*4882a593Smuzhiyun data |= RTC_CR_CWEN;
332*4882a593Smuzhiyun else
333*4882a593Smuzhiyun data |= RTC_CR_EN;
334*4882a593Smuzhiyun writel(data, ldata->base + RTC_CR);
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun /*
337*4882a593Smuzhiyun * On ST PL031 variants, the RTC reset value does not provide correct
338*4882a593Smuzhiyun * weekday for 2000-01-01. Correct the erroneous sunday to saturday.
339*4882a593Smuzhiyun */
340*4882a593Smuzhiyun if (vendor->st_weekday) {
341*4882a593Smuzhiyun if (readl(ldata->base + RTC_YDR) == 0x2000) {
342*4882a593Smuzhiyun time = readl(ldata->base + RTC_DR);
343*4882a593Smuzhiyun if ((time &
344*4882a593Smuzhiyun (RTC_MON_MASK | RTC_MDAY_MASK | RTC_WDAY_MASK))
345*4882a593Smuzhiyun == 0x02120000) {
346*4882a593Smuzhiyun time = time | (0x7 << RTC_WDAY_SHIFT);
347*4882a593Smuzhiyun writel(0x2000, ldata->base + RTC_YLR);
348*4882a593Smuzhiyun writel(time, ldata->base + RTC_LR);
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun }
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun if (!adev->irq[0]) {
354*4882a593Smuzhiyun /* When there's no interrupt, no point in exposing the alarm */
355*4882a593Smuzhiyun ops->read_alarm = NULL;
356*4882a593Smuzhiyun ops->set_alarm = NULL;
357*4882a593Smuzhiyun ops->alarm_irq_enable = NULL;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun device_init_wakeup(&adev->dev, true);
361*4882a593Smuzhiyun ldata->rtc = devm_rtc_allocate_device(&adev->dev);
362*4882a593Smuzhiyun if (IS_ERR(ldata->rtc)) {
363*4882a593Smuzhiyun ret = PTR_ERR(ldata->rtc);
364*4882a593Smuzhiyun goto out;
365*4882a593Smuzhiyun }
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun ldata->rtc->ops = ops;
368*4882a593Smuzhiyun ldata->rtc->range_min = vendor->range_min;
369*4882a593Smuzhiyun ldata->rtc->range_max = vendor->range_max;
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun ret = rtc_register_device(ldata->rtc);
372*4882a593Smuzhiyun if (ret)
373*4882a593Smuzhiyun goto out;
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun if (adev->irq[0]) {
376*4882a593Smuzhiyun ret = request_irq(adev->irq[0], pl031_interrupt,
377*4882a593Smuzhiyun vendor->irqflags, "rtc-pl031", ldata);
378*4882a593Smuzhiyun if (ret)
379*4882a593Smuzhiyun goto out;
380*4882a593Smuzhiyun dev_pm_set_wake_irq(&adev->dev, adev->irq[0]);
381*4882a593Smuzhiyun }
382*4882a593Smuzhiyun return 0;
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun out:
385*4882a593Smuzhiyun amba_release_regions(adev);
386*4882a593Smuzhiyun err_req:
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun return ret;
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun /* Operations for the original ARM version */
392*4882a593Smuzhiyun static struct pl031_vendor_data arm_pl031 = {
393*4882a593Smuzhiyun .ops = {
394*4882a593Smuzhiyun .read_time = pl031_read_time,
395*4882a593Smuzhiyun .set_time = pl031_set_time,
396*4882a593Smuzhiyun .read_alarm = pl031_read_alarm,
397*4882a593Smuzhiyun .set_alarm = pl031_set_alarm,
398*4882a593Smuzhiyun .alarm_irq_enable = pl031_alarm_irq_enable,
399*4882a593Smuzhiyun },
400*4882a593Smuzhiyun .range_max = U32_MAX,
401*4882a593Smuzhiyun };
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun /* The First ST derivative */
404*4882a593Smuzhiyun static struct pl031_vendor_data stv1_pl031 = {
405*4882a593Smuzhiyun .ops = {
406*4882a593Smuzhiyun .read_time = pl031_read_time,
407*4882a593Smuzhiyun .set_time = pl031_set_time,
408*4882a593Smuzhiyun .read_alarm = pl031_read_alarm,
409*4882a593Smuzhiyun .set_alarm = pl031_set_alarm,
410*4882a593Smuzhiyun .alarm_irq_enable = pl031_alarm_irq_enable,
411*4882a593Smuzhiyun },
412*4882a593Smuzhiyun .clockwatch = true,
413*4882a593Smuzhiyun .st_weekday = true,
414*4882a593Smuzhiyun .range_max = U32_MAX,
415*4882a593Smuzhiyun };
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun /* And the second ST derivative */
418*4882a593Smuzhiyun static struct pl031_vendor_data stv2_pl031 = {
419*4882a593Smuzhiyun .ops = {
420*4882a593Smuzhiyun .read_time = pl031_stv2_read_time,
421*4882a593Smuzhiyun .set_time = pl031_stv2_set_time,
422*4882a593Smuzhiyun .read_alarm = pl031_stv2_read_alarm,
423*4882a593Smuzhiyun .set_alarm = pl031_stv2_set_alarm,
424*4882a593Smuzhiyun .alarm_irq_enable = pl031_alarm_irq_enable,
425*4882a593Smuzhiyun },
426*4882a593Smuzhiyun .clockwatch = true,
427*4882a593Smuzhiyun .st_weekday = true,
428*4882a593Smuzhiyun /*
429*4882a593Smuzhiyun * This variant shares the IRQ with another block and must not
430*4882a593Smuzhiyun * suspend that IRQ line.
431*4882a593Smuzhiyun * TODO check if it shares with IRQF_NO_SUSPEND user, else we can
432*4882a593Smuzhiyun * remove IRQF_COND_SUSPEND
433*4882a593Smuzhiyun */
434*4882a593Smuzhiyun .irqflags = IRQF_SHARED | IRQF_COND_SUSPEND,
435*4882a593Smuzhiyun .range_min = RTC_TIMESTAMP_BEGIN_0000,
436*4882a593Smuzhiyun .range_max = RTC_TIMESTAMP_END_9999,
437*4882a593Smuzhiyun };
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun static const struct amba_id pl031_ids[] = {
440*4882a593Smuzhiyun {
441*4882a593Smuzhiyun .id = 0x00041031,
442*4882a593Smuzhiyun .mask = 0x000fffff,
443*4882a593Smuzhiyun .data = &arm_pl031,
444*4882a593Smuzhiyun },
445*4882a593Smuzhiyun /* ST Micro variants */
446*4882a593Smuzhiyun {
447*4882a593Smuzhiyun .id = 0x00180031,
448*4882a593Smuzhiyun .mask = 0x00ffffff,
449*4882a593Smuzhiyun .data = &stv1_pl031,
450*4882a593Smuzhiyun },
451*4882a593Smuzhiyun {
452*4882a593Smuzhiyun .id = 0x00280031,
453*4882a593Smuzhiyun .mask = 0x00ffffff,
454*4882a593Smuzhiyun .data = &stv2_pl031,
455*4882a593Smuzhiyun },
456*4882a593Smuzhiyun {0, 0},
457*4882a593Smuzhiyun };
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun MODULE_DEVICE_TABLE(amba, pl031_ids);
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun static struct amba_driver pl031_driver = {
462*4882a593Smuzhiyun .drv = {
463*4882a593Smuzhiyun .name = "rtc-pl031",
464*4882a593Smuzhiyun },
465*4882a593Smuzhiyun .id_table = pl031_ids,
466*4882a593Smuzhiyun .probe = pl031_probe,
467*4882a593Smuzhiyun .remove = pl031_remove,
468*4882a593Smuzhiyun };
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun module_amba_driver(pl031_driver);
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun MODULE_AUTHOR("Deepak Saxena <dsaxena@plexity.net>");
473*4882a593Smuzhiyun MODULE_DESCRIPTION("ARM AMBA PL031 RTC Driver");
474*4882a593Smuzhiyun MODULE_LICENSE("GPL");
475