xref: /OK3568_Linux_fs/kernel/drivers/rtc/rtc-mt7622.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Driver for MediaTek SoC based RTC
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/clk.h>
9*4882a593Smuzhiyun #include <linux/interrupt.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/of_address.h>
12*4882a593Smuzhiyun #include <linux/of_device.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/rtc.h>
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #define MTK_RTC_DEV KBUILD_MODNAME
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define MTK_RTC_PWRCHK1		0x4
19*4882a593Smuzhiyun #define	RTC_PWRCHK1_MAGIC	0xc6
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define MTK_RTC_PWRCHK2		0x8
22*4882a593Smuzhiyun #define	RTC_PWRCHK2_MAGIC	0x9a
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #define MTK_RTC_KEY		0xc
25*4882a593Smuzhiyun #define	RTC_KEY_MAGIC		0x59
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define MTK_RTC_PROT1		0x10
28*4882a593Smuzhiyun #define	RTC_PROT1_MAGIC		0xa3
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define MTK_RTC_PROT2		0x14
31*4882a593Smuzhiyun #define	RTC_PROT2_MAGIC		0x57
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define MTK_RTC_PROT3		0x18
34*4882a593Smuzhiyun #define	RTC_PROT3_MAGIC		0x67
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define MTK_RTC_PROT4		0x1c
37*4882a593Smuzhiyun #define	RTC_PROT4_MAGIC		0xd2
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define MTK_RTC_CTL		0x20
40*4882a593Smuzhiyun #define	RTC_RC_STOP		BIT(0)
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun #define MTK_RTC_DEBNCE		0x2c
43*4882a593Smuzhiyun #define	RTC_DEBNCE_MASK		GENMASK(2, 0)
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #define MTK_RTC_INT		0x30
46*4882a593Smuzhiyun #define RTC_INT_AL_STA		BIT(4)
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun /*
49*4882a593Smuzhiyun  * Ranges from 0x40 to 0x78 provide RTC time setup for year, month,
50*4882a593Smuzhiyun  * day of month, day of week, hour, minute and second.
51*4882a593Smuzhiyun  */
52*4882a593Smuzhiyun #define MTK_RTC_TREG(_t, _f)	(0x40 + (0x4 * (_f)) + ((_t) * 0x20))
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #define MTK_RTC_AL_CTL		0x7c
55*4882a593Smuzhiyun #define	RTC_AL_EN		BIT(0)
56*4882a593Smuzhiyun #define	RTC_AL_ALL		GENMASK(7, 0)
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun /*
59*4882a593Smuzhiyun  * The offset is used in the translation for the year between in struct
60*4882a593Smuzhiyun  * rtc_time and in hardware register MTK_RTC_TREG(x,MTK_YEA)
61*4882a593Smuzhiyun  */
62*4882a593Smuzhiyun #define MTK_RTC_TM_YR_OFFSET	100
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun /*
65*4882a593Smuzhiyun  * The lowest value for the valid tm_year. RTC hardware would take incorrectly
66*4882a593Smuzhiyun  * tm_year 100 as not a leap year and thus it is also required being excluded
67*4882a593Smuzhiyun  * from the valid options.
68*4882a593Smuzhiyun  */
69*4882a593Smuzhiyun #define MTK_RTC_TM_YR_L		(MTK_RTC_TM_YR_OFFSET + 1)
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun /*
72*4882a593Smuzhiyun  * The most year the RTC can hold is 99 and the next to 99 in year register
73*4882a593Smuzhiyun  * would be wraparound to 0, for MT7622.
74*4882a593Smuzhiyun  */
75*4882a593Smuzhiyun #define MTK_RTC_HW_YR_LIMIT	99
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun /* The highest value for the valid tm_year */
78*4882a593Smuzhiyun #define MTK_RTC_TM_YR_H		(MTK_RTC_TM_YR_OFFSET + MTK_RTC_HW_YR_LIMIT)
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun /* Simple macro helps to check whether the hardware supports the tm_year */
81*4882a593Smuzhiyun #define MTK_RTC_TM_YR_VALID(_y)	((_y) >= MTK_RTC_TM_YR_L && \
82*4882a593Smuzhiyun 				 (_y) <= MTK_RTC_TM_YR_H)
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun /* Types of the function the RTC provides are time counter and alarm. */
85*4882a593Smuzhiyun enum {
86*4882a593Smuzhiyun 	MTK_TC,
87*4882a593Smuzhiyun 	MTK_AL,
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun /* Indexes are used for the pointer to relevant registers in MTK_RTC_TREG */
91*4882a593Smuzhiyun enum {
92*4882a593Smuzhiyun 	MTK_YEA,
93*4882a593Smuzhiyun 	MTK_MON,
94*4882a593Smuzhiyun 	MTK_DOM,
95*4882a593Smuzhiyun 	MTK_DOW,
96*4882a593Smuzhiyun 	MTK_HOU,
97*4882a593Smuzhiyun 	MTK_MIN,
98*4882a593Smuzhiyun 	MTK_SEC
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun struct mtk_rtc {
102*4882a593Smuzhiyun 	struct rtc_device *rtc;
103*4882a593Smuzhiyun 	void __iomem *base;
104*4882a593Smuzhiyun 	int irq;
105*4882a593Smuzhiyun 	struct clk *clk;
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun 
mtk_w32(struct mtk_rtc * rtc,u32 reg,u32 val)108*4882a593Smuzhiyun static void mtk_w32(struct mtk_rtc *rtc, u32 reg, u32 val)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun 	writel_relaxed(val, rtc->base + reg);
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun 
mtk_r32(struct mtk_rtc * rtc,u32 reg)113*4882a593Smuzhiyun static u32 mtk_r32(struct mtk_rtc *rtc, u32 reg)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun 	return readl_relaxed(rtc->base + reg);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun 
mtk_rmw(struct mtk_rtc * rtc,u32 reg,u32 mask,u32 set)118*4882a593Smuzhiyun static void mtk_rmw(struct mtk_rtc *rtc, u32 reg, u32 mask, u32 set)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun 	u32 val;
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	val = mtk_r32(rtc, reg);
123*4882a593Smuzhiyun 	val &= ~mask;
124*4882a593Smuzhiyun 	val |= set;
125*4882a593Smuzhiyun 	mtk_w32(rtc, reg, val);
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun 
mtk_set(struct mtk_rtc * rtc,u32 reg,u32 val)128*4882a593Smuzhiyun static void mtk_set(struct mtk_rtc *rtc, u32 reg, u32 val)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun 	mtk_rmw(rtc, reg, 0, val);
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
mtk_clr(struct mtk_rtc * rtc,u32 reg,u32 val)133*4882a593Smuzhiyun static void mtk_clr(struct mtk_rtc *rtc, u32 reg, u32 val)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun 	mtk_rmw(rtc, reg, val, 0);
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun 
mtk_rtc_hw_init(struct mtk_rtc * hw)138*4882a593Smuzhiyun static void mtk_rtc_hw_init(struct mtk_rtc *hw)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun 	/* The setup of the init sequence is for allowing RTC got to work */
141*4882a593Smuzhiyun 	mtk_w32(hw, MTK_RTC_PWRCHK1, RTC_PWRCHK1_MAGIC);
142*4882a593Smuzhiyun 	mtk_w32(hw, MTK_RTC_PWRCHK2, RTC_PWRCHK2_MAGIC);
143*4882a593Smuzhiyun 	mtk_w32(hw, MTK_RTC_KEY, RTC_KEY_MAGIC);
144*4882a593Smuzhiyun 	mtk_w32(hw, MTK_RTC_PROT1, RTC_PROT1_MAGIC);
145*4882a593Smuzhiyun 	mtk_w32(hw, MTK_RTC_PROT2, RTC_PROT2_MAGIC);
146*4882a593Smuzhiyun 	mtk_w32(hw, MTK_RTC_PROT3, RTC_PROT3_MAGIC);
147*4882a593Smuzhiyun 	mtk_w32(hw, MTK_RTC_PROT4, RTC_PROT4_MAGIC);
148*4882a593Smuzhiyun 	mtk_rmw(hw, MTK_RTC_DEBNCE, RTC_DEBNCE_MASK, 0);
149*4882a593Smuzhiyun 	mtk_clr(hw, MTK_RTC_CTL, RTC_RC_STOP);
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun 
mtk_rtc_get_alarm_or_time(struct mtk_rtc * hw,struct rtc_time * tm,int time_alarm)152*4882a593Smuzhiyun static void mtk_rtc_get_alarm_or_time(struct mtk_rtc *hw, struct rtc_time *tm,
153*4882a593Smuzhiyun 				      int time_alarm)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun 	u32 year, mon, mday, wday, hour, min, sec;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	/*
158*4882a593Smuzhiyun 	 * Read again until the field of the second is not changed which
159*4882a593Smuzhiyun 	 * ensures all fields in the consistent state. Note that MTK_SEC must
160*4882a593Smuzhiyun 	 * be read first. In this way, it guarantees the others remain not
161*4882a593Smuzhiyun 	 * changed when the results for two MTK_SEC consecutive reads are same.
162*4882a593Smuzhiyun 	 */
163*4882a593Smuzhiyun 	do {
164*4882a593Smuzhiyun 		sec = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC));
165*4882a593Smuzhiyun 		min = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN));
166*4882a593Smuzhiyun 		hour = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU));
167*4882a593Smuzhiyun 		wday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW));
168*4882a593Smuzhiyun 		mday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM));
169*4882a593Smuzhiyun 		mon = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MON));
170*4882a593Smuzhiyun 		year = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA));
171*4882a593Smuzhiyun 	} while (sec != mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC)));
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	tm->tm_sec  = sec;
174*4882a593Smuzhiyun 	tm->tm_min  = min;
175*4882a593Smuzhiyun 	tm->tm_hour = hour;
176*4882a593Smuzhiyun 	tm->tm_wday = wday;
177*4882a593Smuzhiyun 	tm->tm_mday = mday;
178*4882a593Smuzhiyun 	tm->tm_mon  = mon - 1;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	/* Rebase to the absolute year which userspace queries */
181*4882a593Smuzhiyun 	tm->tm_year = year + MTK_RTC_TM_YR_OFFSET;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun 
mtk_rtc_set_alarm_or_time(struct mtk_rtc * hw,struct rtc_time * tm,int time_alarm)184*4882a593Smuzhiyun static void mtk_rtc_set_alarm_or_time(struct mtk_rtc *hw, struct rtc_time *tm,
185*4882a593Smuzhiyun 				      int time_alarm)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun 	u32 year;
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	/* Rebase to the relative year which RTC hardware requires */
190*4882a593Smuzhiyun 	year = tm->tm_year - MTK_RTC_TM_YR_OFFSET;
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA), year);
193*4882a593Smuzhiyun 	mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MON), tm->tm_mon + 1);
194*4882a593Smuzhiyun 	mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW), tm->tm_wday);
195*4882a593Smuzhiyun 	mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM), tm->tm_mday);
196*4882a593Smuzhiyun 	mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU), tm->tm_hour);
197*4882a593Smuzhiyun 	mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN), tm->tm_min);
198*4882a593Smuzhiyun 	mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC), tm->tm_sec);
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun 
mtk_rtc_alarmirq(int irq,void * id)201*4882a593Smuzhiyun static irqreturn_t mtk_rtc_alarmirq(int irq, void *id)
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun 	struct mtk_rtc *hw = (struct mtk_rtc *)id;
204*4882a593Smuzhiyun 	u32 irq_sta;
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	irq_sta = mtk_r32(hw, MTK_RTC_INT);
207*4882a593Smuzhiyun 	if (irq_sta & RTC_INT_AL_STA) {
208*4882a593Smuzhiyun 		/* Stop alarm also implicitly disables the alarm interrupt */
209*4882a593Smuzhiyun 		mtk_w32(hw, MTK_RTC_AL_CTL, 0);
210*4882a593Smuzhiyun 		rtc_update_irq(hw->rtc, 1, RTC_IRQF | RTC_AF);
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 		/* Ack alarm interrupt status */
213*4882a593Smuzhiyun 		mtk_w32(hw, MTK_RTC_INT, RTC_INT_AL_STA);
214*4882a593Smuzhiyun 		return IRQ_HANDLED;
215*4882a593Smuzhiyun 	}
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	return IRQ_NONE;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun 
mtk_rtc_gettime(struct device * dev,struct rtc_time * tm)220*4882a593Smuzhiyun static int mtk_rtc_gettime(struct device *dev, struct rtc_time *tm)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun 	struct mtk_rtc *hw = dev_get_drvdata(dev);
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	mtk_rtc_get_alarm_or_time(hw, tm, MTK_TC);
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	return 0;
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun 
mtk_rtc_settime(struct device * dev,struct rtc_time * tm)229*4882a593Smuzhiyun static int mtk_rtc_settime(struct device *dev, struct rtc_time *tm)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun 	struct mtk_rtc *hw = dev_get_drvdata(dev);
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	if (!MTK_RTC_TM_YR_VALID(tm->tm_year))
234*4882a593Smuzhiyun 		return -EINVAL;
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	/* Stop time counter before setting a new one*/
237*4882a593Smuzhiyun 	mtk_set(hw, MTK_RTC_CTL, RTC_RC_STOP);
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	mtk_rtc_set_alarm_or_time(hw, tm, MTK_TC);
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	/* Restart the time counter */
242*4882a593Smuzhiyun 	mtk_clr(hw, MTK_RTC_CTL, RTC_RC_STOP);
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	return 0;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun 
mtk_rtc_getalarm(struct device * dev,struct rtc_wkalrm * wkalrm)247*4882a593Smuzhiyun static int mtk_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun 	struct mtk_rtc *hw = dev_get_drvdata(dev);
250*4882a593Smuzhiyun 	struct rtc_time *alrm_tm = &wkalrm->time;
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	mtk_rtc_get_alarm_or_time(hw, alrm_tm, MTK_AL);
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	wkalrm->enabled = !!(mtk_r32(hw, MTK_RTC_AL_CTL) & RTC_AL_EN);
255*4882a593Smuzhiyun 	wkalrm->pending = !!(mtk_r32(hw, MTK_RTC_INT) & RTC_INT_AL_STA);
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	return 0;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun 
mtk_rtc_setalarm(struct device * dev,struct rtc_wkalrm * wkalrm)260*4882a593Smuzhiyun static int mtk_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun 	struct mtk_rtc *hw = dev_get_drvdata(dev);
263*4882a593Smuzhiyun 	struct rtc_time *alrm_tm = &wkalrm->time;
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	if (!MTK_RTC_TM_YR_VALID(alrm_tm->tm_year))
266*4882a593Smuzhiyun 		return -EINVAL;
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	/*
269*4882a593Smuzhiyun 	 * Stop the alarm also implicitly including disables interrupt before
270*4882a593Smuzhiyun 	 * setting a new one.
271*4882a593Smuzhiyun 	 */
272*4882a593Smuzhiyun 	mtk_clr(hw, MTK_RTC_AL_CTL, RTC_AL_EN);
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	/*
275*4882a593Smuzhiyun 	 * Avoid contention between mtk_rtc_setalarm and IRQ handler so that
276*4882a593Smuzhiyun 	 * disabling the interrupt and awaiting for pending IRQ handler to
277*4882a593Smuzhiyun 	 * complete.
278*4882a593Smuzhiyun 	 */
279*4882a593Smuzhiyun 	synchronize_irq(hw->irq);
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 	mtk_rtc_set_alarm_or_time(hw, alrm_tm, MTK_AL);
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun 	/* Restart the alarm with the new setup */
284*4882a593Smuzhiyun 	mtk_w32(hw, MTK_RTC_AL_CTL, RTC_AL_ALL);
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 	return 0;
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun static const struct rtc_class_ops mtk_rtc_ops = {
290*4882a593Smuzhiyun 	.read_time		= mtk_rtc_gettime,
291*4882a593Smuzhiyun 	.set_time		= mtk_rtc_settime,
292*4882a593Smuzhiyun 	.read_alarm		= mtk_rtc_getalarm,
293*4882a593Smuzhiyun 	.set_alarm		= mtk_rtc_setalarm,
294*4882a593Smuzhiyun };
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun static const struct of_device_id mtk_rtc_match[] = {
297*4882a593Smuzhiyun 	{ .compatible = "mediatek,mt7622-rtc" },
298*4882a593Smuzhiyun 	{ .compatible = "mediatek,soc-rtc" },
299*4882a593Smuzhiyun 	{},
300*4882a593Smuzhiyun };
301*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, mtk_rtc_match);
302*4882a593Smuzhiyun 
mtk_rtc_probe(struct platform_device * pdev)303*4882a593Smuzhiyun static int mtk_rtc_probe(struct platform_device *pdev)
304*4882a593Smuzhiyun {
305*4882a593Smuzhiyun 	struct mtk_rtc *hw;
306*4882a593Smuzhiyun 	int ret;
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun 	hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
309*4882a593Smuzhiyun 	if (!hw)
310*4882a593Smuzhiyun 		return -ENOMEM;
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	platform_set_drvdata(pdev, hw);
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 	hw->base = devm_platform_ioremap_resource(pdev, 0);
315*4882a593Smuzhiyun 	if (IS_ERR(hw->base))
316*4882a593Smuzhiyun 		return PTR_ERR(hw->base);
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	hw->clk = devm_clk_get(&pdev->dev, "rtc");
319*4882a593Smuzhiyun 	if (IS_ERR(hw->clk)) {
320*4882a593Smuzhiyun 		dev_err(&pdev->dev, "No clock\n");
321*4882a593Smuzhiyun 		return PTR_ERR(hw->clk);
322*4882a593Smuzhiyun 	}
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 	ret = clk_prepare_enable(hw->clk);
325*4882a593Smuzhiyun 	if (ret)
326*4882a593Smuzhiyun 		return ret;
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 	hw->irq = platform_get_irq(pdev, 0);
329*4882a593Smuzhiyun 	if (hw->irq < 0) {
330*4882a593Smuzhiyun 		ret = hw->irq;
331*4882a593Smuzhiyun 		goto err;
332*4882a593Smuzhiyun 	}
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun 	ret = devm_request_irq(&pdev->dev, hw->irq, mtk_rtc_alarmirq,
335*4882a593Smuzhiyun 			       0, dev_name(&pdev->dev), hw);
336*4882a593Smuzhiyun 	if (ret) {
337*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Can't request IRQ\n");
338*4882a593Smuzhiyun 		goto err;
339*4882a593Smuzhiyun 	}
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun 	mtk_rtc_hw_init(hw);
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	device_init_wakeup(&pdev->dev, true);
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 	hw->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
346*4882a593Smuzhiyun 					   &mtk_rtc_ops, THIS_MODULE);
347*4882a593Smuzhiyun 	if (IS_ERR(hw->rtc)) {
348*4882a593Smuzhiyun 		ret = PTR_ERR(hw->rtc);
349*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Unable to register device\n");
350*4882a593Smuzhiyun 		goto err;
351*4882a593Smuzhiyun 	}
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 	return 0;
354*4882a593Smuzhiyun err:
355*4882a593Smuzhiyun 	clk_disable_unprepare(hw->clk);
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun 	return ret;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun 
mtk_rtc_remove(struct platform_device * pdev)360*4882a593Smuzhiyun static int mtk_rtc_remove(struct platform_device *pdev)
361*4882a593Smuzhiyun {
362*4882a593Smuzhiyun 	struct mtk_rtc *hw = platform_get_drvdata(pdev);
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun 	clk_disable_unprepare(hw->clk);
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun 	return 0;
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
mtk_rtc_suspend(struct device * dev)370*4882a593Smuzhiyun static int mtk_rtc_suspend(struct device *dev)
371*4882a593Smuzhiyun {
372*4882a593Smuzhiyun 	struct mtk_rtc *hw = dev_get_drvdata(dev);
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 	if (device_may_wakeup(dev))
375*4882a593Smuzhiyun 		enable_irq_wake(hw->irq);
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 	return 0;
378*4882a593Smuzhiyun }
379*4882a593Smuzhiyun 
mtk_rtc_resume(struct device * dev)380*4882a593Smuzhiyun static int mtk_rtc_resume(struct device *dev)
381*4882a593Smuzhiyun {
382*4882a593Smuzhiyun 	struct mtk_rtc *hw = dev_get_drvdata(dev);
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	if (device_may_wakeup(dev))
385*4882a593Smuzhiyun 		disable_irq_wake(hw->irq);
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun 	return 0;
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(mtk_rtc_pm_ops, mtk_rtc_suspend, mtk_rtc_resume);
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun #define MTK_RTC_PM_OPS (&mtk_rtc_pm_ops)
393*4882a593Smuzhiyun #else	/* CONFIG_PM */
394*4882a593Smuzhiyun #define MTK_RTC_PM_OPS NULL
395*4882a593Smuzhiyun #endif	/* CONFIG_PM */
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun static struct platform_driver mtk_rtc_driver = {
398*4882a593Smuzhiyun 	.probe	= mtk_rtc_probe,
399*4882a593Smuzhiyun 	.remove	= mtk_rtc_remove,
400*4882a593Smuzhiyun 	.driver = {
401*4882a593Smuzhiyun 		.name = MTK_RTC_DEV,
402*4882a593Smuzhiyun 		.of_match_table = mtk_rtc_match,
403*4882a593Smuzhiyun 		.pm = MTK_RTC_PM_OPS,
404*4882a593Smuzhiyun 	},
405*4882a593Smuzhiyun };
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun module_platform_driver(mtk_rtc_driver);
408*4882a593Smuzhiyun 
409*4882a593Smuzhiyun MODULE_DESCRIPTION("MediaTek SoC based RTC Driver");
410*4882a593Smuzhiyun MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
411*4882a593Smuzhiyun MODULE_LICENSE("GPL");
412