1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Oki MSM6242 RTC Driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2009 Geert Uytterhoeven
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Based on the A2000 TOD code in arch/m68k/amiga/config.c
8*4882a593Smuzhiyun * Copyright (C) 1993 Hamish Macdonald
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/io.h>
15*4882a593Smuzhiyun #include <linux/kernel.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/platform_device.h>
18*4882a593Smuzhiyun #include <linux/rtc.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun enum {
23*4882a593Smuzhiyun MSM6242_SECOND1 = 0x0, /* 1-second digit register */
24*4882a593Smuzhiyun MSM6242_SECOND10 = 0x1, /* 10-second digit register */
25*4882a593Smuzhiyun MSM6242_MINUTE1 = 0x2, /* 1-minute digit register */
26*4882a593Smuzhiyun MSM6242_MINUTE10 = 0x3, /* 10-minute digit register */
27*4882a593Smuzhiyun MSM6242_HOUR1 = 0x4, /* 1-hour digit register */
28*4882a593Smuzhiyun MSM6242_HOUR10 = 0x5, /* PM/AM, 10-hour digit register */
29*4882a593Smuzhiyun MSM6242_DAY1 = 0x6, /* 1-day digit register */
30*4882a593Smuzhiyun MSM6242_DAY10 = 0x7, /* 10-day digit register */
31*4882a593Smuzhiyun MSM6242_MONTH1 = 0x8, /* 1-month digit register */
32*4882a593Smuzhiyun MSM6242_MONTH10 = 0x9, /* 10-month digit register */
33*4882a593Smuzhiyun MSM6242_YEAR1 = 0xa, /* 1-year digit register */
34*4882a593Smuzhiyun MSM6242_YEAR10 = 0xb, /* 10-year digit register */
35*4882a593Smuzhiyun MSM6242_WEEK = 0xc, /* Week register */
36*4882a593Smuzhiyun MSM6242_CD = 0xd, /* Control Register D */
37*4882a593Smuzhiyun MSM6242_CE = 0xe, /* Control Register E */
38*4882a593Smuzhiyun MSM6242_CF = 0xf, /* Control Register F */
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define MSM6242_HOUR10_AM (0 << 2)
42*4882a593Smuzhiyun #define MSM6242_HOUR10_PM (1 << 2)
43*4882a593Smuzhiyun #define MSM6242_HOUR10_HR_MASK (3 << 0)
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #define MSM6242_WEEK_SUNDAY 0
46*4882a593Smuzhiyun #define MSM6242_WEEK_MONDAY 1
47*4882a593Smuzhiyun #define MSM6242_WEEK_TUESDAY 2
48*4882a593Smuzhiyun #define MSM6242_WEEK_WEDNESDAY 3
49*4882a593Smuzhiyun #define MSM6242_WEEK_THURSDAY 4
50*4882a593Smuzhiyun #define MSM6242_WEEK_FRIDAY 5
51*4882a593Smuzhiyun #define MSM6242_WEEK_SATURDAY 6
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #define MSM6242_CD_30_S_ADJ (1 << 3) /* 30-second adjustment */
54*4882a593Smuzhiyun #define MSM6242_CD_IRQ_FLAG (1 << 2)
55*4882a593Smuzhiyun #define MSM6242_CD_BUSY (1 << 1)
56*4882a593Smuzhiyun #define MSM6242_CD_HOLD (1 << 0)
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define MSM6242_CE_T_MASK (3 << 2)
59*4882a593Smuzhiyun #define MSM6242_CE_T_64HZ (0 << 2) /* period 1/64 second */
60*4882a593Smuzhiyun #define MSM6242_CE_T_1HZ (1 << 2) /* period 1 second */
61*4882a593Smuzhiyun #define MSM6242_CE_T_1MINUTE (2 << 2) /* period 1 minute */
62*4882a593Smuzhiyun #define MSM6242_CE_T_1HOUR (3 << 2) /* period 1 hour */
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #define MSM6242_CE_ITRPT_STND (1 << 1)
65*4882a593Smuzhiyun #define MSM6242_CE_MASK (1 << 0) /* STD.P output control */
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #define MSM6242_CF_TEST (1 << 3)
68*4882a593Smuzhiyun #define MSM6242_CF_12H (0 << 2)
69*4882a593Smuzhiyun #define MSM6242_CF_24H (1 << 2)
70*4882a593Smuzhiyun #define MSM6242_CF_STOP (1 << 1)
71*4882a593Smuzhiyun #define MSM6242_CF_REST (1 << 0) /* reset */
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun struct msm6242_priv {
75*4882a593Smuzhiyun u32 __iomem *regs;
76*4882a593Smuzhiyun struct rtc_device *rtc;
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun
msm6242_read(struct msm6242_priv * priv,unsigned int reg)79*4882a593Smuzhiyun static inline unsigned int msm6242_read(struct msm6242_priv *priv,
80*4882a593Smuzhiyun unsigned int reg)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun return __raw_readl(&priv->regs[reg]) & 0xf;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
msm6242_write(struct msm6242_priv * priv,unsigned int val,unsigned int reg)85*4882a593Smuzhiyun static inline void msm6242_write(struct msm6242_priv *priv, unsigned int val,
86*4882a593Smuzhiyun unsigned int reg)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun __raw_writel(val, &priv->regs[reg]);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
msm6242_lock(struct msm6242_priv * priv)91*4882a593Smuzhiyun static void msm6242_lock(struct msm6242_priv *priv)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun int cnt = 5;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun msm6242_write(priv, MSM6242_CD_HOLD|MSM6242_CD_IRQ_FLAG, MSM6242_CD);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun while ((msm6242_read(priv, MSM6242_CD) & MSM6242_CD_BUSY) && cnt) {
98*4882a593Smuzhiyun msm6242_write(priv, MSM6242_CD_IRQ_FLAG, MSM6242_CD);
99*4882a593Smuzhiyun udelay(70);
100*4882a593Smuzhiyun msm6242_write(priv, MSM6242_CD_HOLD|MSM6242_CD_IRQ_FLAG, MSM6242_CD);
101*4882a593Smuzhiyun cnt--;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun if (!cnt)
105*4882a593Smuzhiyun pr_warn("timed out waiting for RTC (0x%x)\n",
106*4882a593Smuzhiyun msm6242_read(priv, MSM6242_CD));
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
msm6242_unlock(struct msm6242_priv * priv)109*4882a593Smuzhiyun static void msm6242_unlock(struct msm6242_priv *priv)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun msm6242_write(priv, MSM6242_CD_IRQ_FLAG, MSM6242_CD);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
msm6242_read_time(struct device * dev,struct rtc_time * tm)114*4882a593Smuzhiyun static int msm6242_read_time(struct device *dev, struct rtc_time *tm)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun struct msm6242_priv *priv = dev_get_drvdata(dev);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun msm6242_lock(priv);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun tm->tm_sec = msm6242_read(priv, MSM6242_SECOND10) * 10 +
121*4882a593Smuzhiyun msm6242_read(priv, MSM6242_SECOND1);
122*4882a593Smuzhiyun tm->tm_min = msm6242_read(priv, MSM6242_MINUTE10) * 10 +
123*4882a593Smuzhiyun msm6242_read(priv, MSM6242_MINUTE1);
124*4882a593Smuzhiyun tm->tm_hour = (msm6242_read(priv, MSM6242_HOUR10) &
125*4882a593Smuzhiyun MSM6242_HOUR10_HR_MASK) * 10 +
126*4882a593Smuzhiyun msm6242_read(priv, MSM6242_HOUR1);
127*4882a593Smuzhiyun tm->tm_mday = msm6242_read(priv, MSM6242_DAY10) * 10 +
128*4882a593Smuzhiyun msm6242_read(priv, MSM6242_DAY1);
129*4882a593Smuzhiyun tm->tm_wday = msm6242_read(priv, MSM6242_WEEK);
130*4882a593Smuzhiyun tm->tm_mon = msm6242_read(priv, MSM6242_MONTH10) * 10 +
131*4882a593Smuzhiyun msm6242_read(priv, MSM6242_MONTH1) - 1;
132*4882a593Smuzhiyun tm->tm_year = msm6242_read(priv, MSM6242_YEAR10) * 10 +
133*4882a593Smuzhiyun msm6242_read(priv, MSM6242_YEAR1);
134*4882a593Smuzhiyun if (tm->tm_year <= 69)
135*4882a593Smuzhiyun tm->tm_year += 100;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun if (!(msm6242_read(priv, MSM6242_CF) & MSM6242_CF_24H)) {
138*4882a593Smuzhiyun unsigned int pm = msm6242_read(priv, MSM6242_HOUR10) &
139*4882a593Smuzhiyun MSM6242_HOUR10_PM;
140*4882a593Smuzhiyun if (!pm && tm->tm_hour == 12)
141*4882a593Smuzhiyun tm->tm_hour = 0;
142*4882a593Smuzhiyun else if (pm && tm->tm_hour != 12)
143*4882a593Smuzhiyun tm->tm_hour += 12;
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun msm6242_unlock(priv);
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun return 0;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
msm6242_set_time(struct device * dev,struct rtc_time * tm)151*4882a593Smuzhiyun static int msm6242_set_time(struct device *dev, struct rtc_time *tm)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun struct msm6242_priv *priv = dev_get_drvdata(dev);
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun msm6242_lock(priv);
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun msm6242_write(priv, tm->tm_sec / 10, MSM6242_SECOND10);
158*4882a593Smuzhiyun msm6242_write(priv, tm->tm_sec % 10, MSM6242_SECOND1);
159*4882a593Smuzhiyun msm6242_write(priv, tm->tm_min / 10, MSM6242_MINUTE10);
160*4882a593Smuzhiyun msm6242_write(priv, tm->tm_min % 10, MSM6242_MINUTE1);
161*4882a593Smuzhiyun if (msm6242_read(priv, MSM6242_CF) & MSM6242_CF_24H)
162*4882a593Smuzhiyun msm6242_write(priv, tm->tm_hour / 10, MSM6242_HOUR10);
163*4882a593Smuzhiyun else if (tm->tm_hour >= 12)
164*4882a593Smuzhiyun msm6242_write(priv, MSM6242_HOUR10_PM + (tm->tm_hour - 12) / 10,
165*4882a593Smuzhiyun MSM6242_HOUR10);
166*4882a593Smuzhiyun else
167*4882a593Smuzhiyun msm6242_write(priv, tm->tm_hour / 10, MSM6242_HOUR10);
168*4882a593Smuzhiyun msm6242_write(priv, tm->tm_hour % 10, MSM6242_HOUR1);
169*4882a593Smuzhiyun msm6242_write(priv, tm->tm_mday / 10, MSM6242_DAY10);
170*4882a593Smuzhiyun msm6242_write(priv, tm->tm_mday % 10, MSM6242_DAY1);
171*4882a593Smuzhiyun if (tm->tm_wday != -1)
172*4882a593Smuzhiyun msm6242_write(priv, tm->tm_wday, MSM6242_WEEK);
173*4882a593Smuzhiyun msm6242_write(priv, (tm->tm_mon + 1) / 10, MSM6242_MONTH10);
174*4882a593Smuzhiyun msm6242_write(priv, (tm->tm_mon + 1) % 10, MSM6242_MONTH1);
175*4882a593Smuzhiyun if (tm->tm_year >= 100)
176*4882a593Smuzhiyun tm->tm_year -= 100;
177*4882a593Smuzhiyun msm6242_write(priv, tm->tm_year / 10, MSM6242_YEAR10);
178*4882a593Smuzhiyun msm6242_write(priv, tm->tm_year % 10, MSM6242_YEAR1);
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun msm6242_unlock(priv);
181*4882a593Smuzhiyun return 0;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun static const struct rtc_class_ops msm6242_rtc_ops = {
185*4882a593Smuzhiyun .read_time = msm6242_read_time,
186*4882a593Smuzhiyun .set_time = msm6242_set_time,
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun
msm6242_rtc_probe(struct platform_device * pdev)189*4882a593Smuzhiyun static int __init msm6242_rtc_probe(struct platform_device *pdev)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun struct resource *res;
192*4882a593Smuzhiyun struct msm6242_priv *priv;
193*4882a593Smuzhiyun struct rtc_device *rtc;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
196*4882a593Smuzhiyun if (!res)
197*4882a593Smuzhiyun return -ENODEV;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
200*4882a593Smuzhiyun if (!priv)
201*4882a593Smuzhiyun return -ENOMEM;
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun priv->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
204*4882a593Smuzhiyun if (!priv->regs)
205*4882a593Smuzhiyun return -ENOMEM;
206*4882a593Smuzhiyun platform_set_drvdata(pdev, priv);
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun rtc = devm_rtc_device_register(&pdev->dev, "rtc-msm6242",
209*4882a593Smuzhiyun &msm6242_rtc_ops, THIS_MODULE);
210*4882a593Smuzhiyun if (IS_ERR(rtc))
211*4882a593Smuzhiyun return PTR_ERR(rtc);
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun priv->rtc = rtc;
214*4882a593Smuzhiyun return 0;
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun static struct platform_driver msm6242_rtc_driver = {
218*4882a593Smuzhiyun .driver = {
219*4882a593Smuzhiyun .name = "rtc-msm6242",
220*4882a593Smuzhiyun },
221*4882a593Smuzhiyun };
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun module_platform_driver_probe(msm6242_rtc_driver, msm6242_rtc_probe);
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun MODULE_AUTHOR("Geert Uytterhoeven <geert@linux-m68k.org>");
226*4882a593Smuzhiyun MODULE_LICENSE("GPL");
227*4882a593Smuzhiyun MODULE_DESCRIPTION("Oki MSM6242 RTC driver");
228*4882a593Smuzhiyun MODULE_ALIAS("platform:rtc-msm6242");
229