1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // RTC driver for Maxim MAX8997
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (C) 2013 Samsung Electronics Co.Ltd
6*4882a593Smuzhiyun //
7*4882a593Smuzhiyun // based on rtc-max8998.c
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/slab.h>
12*4882a593Smuzhiyun #include <linux/rtc.h>
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/mutex.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/mfd/max8997-private.h>
18*4882a593Smuzhiyun #include <linux/irqdomain.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /* Module parameter for WTSR function control */
21*4882a593Smuzhiyun static int wtsr_en = 1;
22*4882a593Smuzhiyun module_param(wtsr_en, int, 0444);
23*4882a593Smuzhiyun MODULE_PARM_DESC(wtsr_en, "Watchdog Timeout & Software Reset (default=on)");
24*4882a593Smuzhiyun /* Module parameter for SMPL function control */
25*4882a593Smuzhiyun static int smpl_en = 1;
26*4882a593Smuzhiyun module_param(smpl_en, int, 0444);
27*4882a593Smuzhiyun MODULE_PARM_DESC(smpl_en, "Sudden Momentary Power Loss (default=on)");
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* RTC Control Register */
30*4882a593Smuzhiyun #define BCD_EN_SHIFT 0
31*4882a593Smuzhiyun #define BCD_EN_MASK (1 << BCD_EN_SHIFT)
32*4882a593Smuzhiyun #define MODEL24_SHIFT 1
33*4882a593Smuzhiyun #define MODEL24_MASK (1 << MODEL24_SHIFT)
34*4882a593Smuzhiyun /* RTC Update Register1 */
35*4882a593Smuzhiyun #define RTC_UDR_SHIFT 0
36*4882a593Smuzhiyun #define RTC_UDR_MASK (1 << RTC_UDR_SHIFT)
37*4882a593Smuzhiyun /* WTSR and SMPL Register */
38*4882a593Smuzhiyun #define WTSRT_SHIFT 0
39*4882a593Smuzhiyun #define SMPLT_SHIFT 2
40*4882a593Smuzhiyun #define WTSR_EN_SHIFT 6
41*4882a593Smuzhiyun #define SMPL_EN_SHIFT 7
42*4882a593Smuzhiyun #define WTSRT_MASK (3 << WTSRT_SHIFT)
43*4882a593Smuzhiyun #define SMPLT_MASK (3 << SMPLT_SHIFT)
44*4882a593Smuzhiyun #define WTSR_EN_MASK (1 << WTSR_EN_SHIFT)
45*4882a593Smuzhiyun #define SMPL_EN_MASK (1 << SMPL_EN_SHIFT)
46*4882a593Smuzhiyun /* RTC Hour register */
47*4882a593Smuzhiyun #define HOUR_PM_SHIFT 6
48*4882a593Smuzhiyun #define HOUR_PM_MASK (1 << HOUR_PM_SHIFT)
49*4882a593Smuzhiyun /* RTC Alarm Enable */
50*4882a593Smuzhiyun #define ALARM_ENABLE_SHIFT 7
51*4882a593Smuzhiyun #define ALARM_ENABLE_MASK (1 << ALARM_ENABLE_SHIFT)
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun enum {
54*4882a593Smuzhiyun RTC_SEC = 0,
55*4882a593Smuzhiyun RTC_MIN,
56*4882a593Smuzhiyun RTC_HOUR,
57*4882a593Smuzhiyun RTC_WEEKDAY,
58*4882a593Smuzhiyun RTC_MONTH,
59*4882a593Smuzhiyun RTC_YEAR,
60*4882a593Smuzhiyun RTC_DATE,
61*4882a593Smuzhiyun RTC_NR_TIME
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun struct max8997_rtc_info {
65*4882a593Smuzhiyun struct device *dev;
66*4882a593Smuzhiyun struct max8997_dev *max8997;
67*4882a593Smuzhiyun struct i2c_client *rtc;
68*4882a593Smuzhiyun struct rtc_device *rtc_dev;
69*4882a593Smuzhiyun struct mutex lock;
70*4882a593Smuzhiyun int virq;
71*4882a593Smuzhiyun int rtc_24hr_mode;
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun
max8997_rtc_data_to_tm(u8 * data,struct rtc_time * tm,int rtc_24hr_mode)74*4882a593Smuzhiyun static void max8997_rtc_data_to_tm(u8 *data, struct rtc_time *tm,
75*4882a593Smuzhiyun int rtc_24hr_mode)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun tm->tm_sec = data[RTC_SEC] & 0x7f;
78*4882a593Smuzhiyun tm->tm_min = data[RTC_MIN] & 0x7f;
79*4882a593Smuzhiyun if (rtc_24hr_mode)
80*4882a593Smuzhiyun tm->tm_hour = data[RTC_HOUR] & 0x1f;
81*4882a593Smuzhiyun else {
82*4882a593Smuzhiyun tm->tm_hour = data[RTC_HOUR] & 0x0f;
83*4882a593Smuzhiyun if (data[RTC_HOUR] & HOUR_PM_MASK)
84*4882a593Smuzhiyun tm->tm_hour += 12;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun tm->tm_wday = fls(data[RTC_WEEKDAY] & 0x7f) - 1;
88*4882a593Smuzhiyun tm->tm_mday = data[RTC_DATE] & 0x1f;
89*4882a593Smuzhiyun tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1;
90*4882a593Smuzhiyun tm->tm_year = (data[RTC_YEAR] & 0x7f) + 100;
91*4882a593Smuzhiyun tm->tm_yday = 0;
92*4882a593Smuzhiyun tm->tm_isdst = 0;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
max8997_rtc_tm_to_data(struct rtc_time * tm,u8 * data)95*4882a593Smuzhiyun static int max8997_rtc_tm_to_data(struct rtc_time *tm, u8 *data)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun data[RTC_SEC] = tm->tm_sec;
98*4882a593Smuzhiyun data[RTC_MIN] = tm->tm_min;
99*4882a593Smuzhiyun data[RTC_HOUR] = tm->tm_hour;
100*4882a593Smuzhiyun data[RTC_WEEKDAY] = 1 << tm->tm_wday;
101*4882a593Smuzhiyun data[RTC_DATE] = tm->tm_mday;
102*4882a593Smuzhiyun data[RTC_MONTH] = tm->tm_mon + 1;
103*4882a593Smuzhiyun data[RTC_YEAR] = tm->tm_year > 100 ? (tm->tm_year - 100) : 0;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun if (tm->tm_year < 100) {
106*4882a593Smuzhiyun pr_warn("RTC cannot handle the year %d. Assume it's 2000.\n",
107*4882a593Smuzhiyun 1900 + tm->tm_year);
108*4882a593Smuzhiyun return -EINVAL;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun return 0;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
max8997_rtc_set_update_reg(struct max8997_rtc_info * info)113*4882a593Smuzhiyun static inline int max8997_rtc_set_update_reg(struct max8997_rtc_info *info)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun int ret;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun ret = max8997_write_reg(info->rtc, MAX8997_RTC_UPDATE1,
118*4882a593Smuzhiyun RTC_UDR_MASK);
119*4882a593Smuzhiyun if (ret < 0)
120*4882a593Smuzhiyun dev_err(info->dev, "%s: fail to write update reg(%d)\n",
121*4882a593Smuzhiyun __func__, ret);
122*4882a593Smuzhiyun else {
123*4882a593Smuzhiyun /* Minimum 16ms delay required before RTC update.
124*4882a593Smuzhiyun * Otherwise, we may read and update based on out-of-date
125*4882a593Smuzhiyun * value */
126*4882a593Smuzhiyun msleep(20);
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun return ret;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
max8997_rtc_read_time(struct device * dev,struct rtc_time * tm)132*4882a593Smuzhiyun static int max8997_rtc_read_time(struct device *dev, struct rtc_time *tm)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun struct max8997_rtc_info *info = dev_get_drvdata(dev);
135*4882a593Smuzhiyun u8 data[RTC_NR_TIME];
136*4882a593Smuzhiyun int ret;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun mutex_lock(&info->lock);
139*4882a593Smuzhiyun ret = max8997_bulk_read(info->rtc, MAX8997_RTC_SEC, RTC_NR_TIME, data);
140*4882a593Smuzhiyun mutex_unlock(&info->lock);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun if (ret < 0) {
143*4882a593Smuzhiyun dev_err(info->dev, "%s: fail to read time reg(%d)\n", __func__,
144*4882a593Smuzhiyun ret);
145*4882a593Smuzhiyun return ret;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun max8997_rtc_data_to_tm(data, tm, info->rtc_24hr_mode);
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun return 0;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
max8997_rtc_set_time(struct device * dev,struct rtc_time * tm)153*4882a593Smuzhiyun static int max8997_rtc_set_time(struct device *dev, struct rtc_time *tm)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun struct max8997_rtc_info *info = dev_get_drvdata(dev);
156*4882a593Smuzhiyun u8 data[RTC_NR_TIME];
157*4882a593Smuzhiyun int ret;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun ret = max8997_rtc_tm_to_data(tm, data);
160*4882a593Smuzhiyun if (ret < 0)
161*4882a593Smuzhiyun return ret;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun mutex_lock(&info->lock);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun ret = max8997_bulk_write(info->rtc, MAX8997_RTC_SEC, RTC_NR_TIME, data);
166*4882a593Smuzhiyun if (ret < 0) {
167*4882a593Smuzhiyun dev_err(info->dev, "%s: fail to write time reg(%d)\n", __func__,
168*4882a593Smuzhiyun ret);
169*4882a593Smuzhiyun goto out;
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun ret = max8997_rtc_set_update_reg(info);
173*4882a593Smuzhiyun out:
174*4882a593Smuzhiyun mutex_unlock(&info->lock);
175*4882a593Smuzhiyun return ret;
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
max8997_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alrm)178*4882a593Smuzhiyun static int max8997_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun struct max8997_rtc_info *info = dev_get_drvdata(dev);
181*4882a593Smuzhiyun u8 data[RTC_NR_TIME];
182*4882a593Smuzhiyun u8 val;
183*4882a593Smuzhiyun int i, ret;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun mutex_lock(&info->lock);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun ret = max8997_bulk_read(info->rtc, MAX8997_RTC_ALARM1_SEC, RTC_NR_TIME,
188*4882a593Smuzhiyun data);
189*4882a593Smuzhiyun if (ret < 0) {
190*4882a593Smuzhiyun dev_err(info->dev, "%s:%d fail to read alarm reg(%d)\n",
191*4882a593Smuzhiyun __func__, __LINE__, ret);
192*4882a593Smuzhiyun goto out;
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun max8997_rtc_data_to_tm(data, &alrm->time, info->rtc_24hr_mode);
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun alrm->enabled = 0;
198*4882a593Smuzhiyun for (i = 0; i < RTC_NR_TIME; i++) {
199*4882a593Smuzhiyun if (data[i] & ALARM_ENABLE_MASK) {
200*4882a593Smuzhiyun alrm->enabled = 1;
201*4882a593Smuzhiyun break;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun alrm->pending = 0;
206*4882a593Smuzhiyun ret = max8997_read_reg(info->max8997->i2c, MAX8997_REG_STATUS1, &val);
207*4882a593Smuzhiyun if (ret < 0) {
208*4882a593Smuzhiyun dev_err(info->dev, "%s:%d fail to read status1 reg(%d)\n",
209*4882a593Smuzhiyun __func__, __LINE__, ret);
210*4882a593Smuzhiyun goto out;
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun if (val & (1 << 4)) /* RTCA1 */
214*4882a593Smuzhiyun alrm->pending = 1;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun out:
217*4882a593Smuzhiyun mutex_unlock(&info->lock);
218*4882a593Smuzhiyun return ret;
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun
max8997_rtc_stop_alarm(struct max8997_rtc_info * info)221*4882a593Smuzhiyun static int max8997_rtc_stop_alarm(struct max8997_rtc_info *info)
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun u8 data[RTC_NR_TIME];
224*4882a593Smuzhiyun int ret, i;
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun if (!mutex_is_locked(&info->lock))
227*4882a593Smuzhiyun dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun ret = max8997_bulk_read(info->rtc, MAX8997_RTC_ALARM1_SEC, RTC_NR_TIME,
230*4882a593Smuzhiyun data);
231*4882a593Smuzhiyun if (ret < 0) {
232*4882a593Smuzhiyun dev_err(info->dev, "%s: fail to read alarm reg(%d)\n",
233*4882a593Smuzhiyun __func__, ret);
234*4882a593Smuzhiyun goto out;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun for (i = 0; i < RTC_NR_TIME; i++)
238*4882a593Smuzhiyun data[i] &= ~ALARM_ENABLE_MASK;
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun ret = max8997_bulk_write(info->rtc, MAX8997_RTC_ALARM1_SEC, RTC_NR_TIME,
241*4882a593Smuzhiyun data);
242*4882a593Smuzhiyun if (ret < 0) {
243*4882a593Smuzhiyun dev_err(info->dev, "%s: fail to write alarm reg(%d)\n",
244*4882a593Smuzhiyun __func__, ret);
245*4882a593Smuzhiyun goto out;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun ret = max8997_rtc_set_update_reg(info);
249*4882a593Smuzhiyun out:
250*4882a593Smuzhiyun return ret;
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun
max8997_rtc_start_alarm(struct max8997_rtc_info * info)253*4882a593Smuzhiyun static int max8997_rtc_start_alarm(struct max8997_rtc_info *info)
254*4882a593Smuzhiyun {
255*4882a593Smuzhiyun u8 data[RTC_NR_TIME];
256*4882a593Smuzhiyun int ret;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun if (!mutex_is_locked(&info->lock))
259*4882a593Smuzhiyun dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun ret = max8997_bulk_read(info->rtc, MAX8997_RTC_ALARM1_SEC, RTC_NR_TIME,
262*4882a593Smuzhiyun data);
263*4882a593Smuzhiyun if (ret < 0) {
264*4882a593Smuzhiyun dev_err(info->dev, "%s: fail to read alarm reg(%d)\n",
265*4882a593Smuzhiyun __func__, ret);
266*4882a593Smuzhiyun goto out;
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun data[RTC_SEC] |= (1 << ALARM_ENABLE_SHIFT);
270*4882a593Smuzhiyun data[RTC_MIN] |= (1 << ALARM_ENABLE_SHIFT);
271*4882a593Smuzhiyun data[RTC_HOUR] |= (1 << ALARM_ENABLE_SHIFT);
272*4882a593Smuzhiyun data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK;
273*4882a593Smuzhiyun if (data[RTC_MONTH] & 0xf)
274*4882a593Smuzhiyun data[RTC_MONTH] |= (1 << ALARM_ENABLE_SHIFT);
275*4882a593Smuzhiyun if (data[RTC_YEAR] & 0x7f)
276*4882a593Smuzhiyun data[RTC_YEAR] |= (1 << ALARM_ENABLE_SHIFT);
277*4882a593Smuzhiyun if (data[RTC_DATE] & 0x1f)
278*4882a593Smuzhiyun data[RTC_DATE] |= (1 << ALARM_ENABLE_SHIFT);
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun ret = max8997_bulk_write(info->rtc, MAX8997_RTC_ALARM1_SEC, RTC_NR_TIME,
281*4882a593Smuzhiyun data);
282*4882a593Smuzhiyun if (ret < 0) {
283*4882a593Smuzhiyun dev_err(info->dev, "%s: fail to write alarm reg(%d)\n",
284*4882a593Smuzhiyun __func__, ret);
285*4882a593Smuzhiyun goto out;
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun ret = max8997_rtc_set_update_reg(info);
289*4882a593Smuzhiyun out:
290*4882a593Smuzhiyun return ret;
291*4882a593Smuzhiyun }
max8997_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)292*4882a593Smuzhiyun static int max8997_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
293*4882a593Smuzhiyun {
294*4882a593Smuzhiyun struct max8997_rtc_info *info = dev_get_drvdata(dev);
295*4882a593Smuzhiyun u8 data[RTC_NR_TIME];
296*4882a593Smuzhiyun int ret;
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun ret = max8997_rtc_tm_to_data(&alrm->time, data);
299*4882a593Smuzhiyun if (ret < 0)
300*4882a593Smuzhiyun return ret;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun dev_info(info->dev, "%s: %d-%02d-%02d %02d:%02d:%02d\n", __func__,
303*4882a593Smuzhiyun data[RTC_YEAR] + 2000, data[RTC_MONTH], data[RTC_DATE],
304*4882a593Smuzhiyun data[RTC_HOUR], data[RTC_MIN], data[RTC_SEC]);
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun mutex_lock(&info->lock);
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun ret = max8997_rtc_stop_alarm(info);
309*4882a593Smuzhiyun if (ret < 0)
310*4882a593Smuzhiyun goto out;
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun ret = max8997_bulk_write(info->rtc, MAX8997_RTC_ALARM1_SEC, RTC_NR_TIME,
313*4882a593Smuzhiyun data);
314*4882a593Smuzhiyun if (ret < 0) {
315*4882a593Smuzhiyun dev_err(info->dev, "%s: fail to write alarm reg(%d)\n",
316*4882a593Smuzhiyun __func__, ret);
317*4882a593Smuzhiyun goto out;
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun ret = max8997_rtc_set_update_reg(info);
321*4882a593Smuzhiyun if (ret < 0)
322*4882a593Smuzhiyun goto out;
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun if (alrm->enabled)
325*4882a593Smuzhiyun ret = max8997_rtc_start_alarm(info);
326*4882a593Smuzhiyun out:
327*4882a593Smuzhiyun mutex_unlock(&info->lock);
328*4882a593Smuzhiyun return ret;
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun
max8997_rtc_alarm_irq_enable(struct device * dev,unsigned int enabled)331*4882a593Smuzhiyun static int max8997_rtc_alarm_irq_enable(struct device *dev,
332*4882a593Smuzhiyun unsigned int enabled)
333*4882a593Smuzhiyun {
334*4882a593Smuzhiyun struct max8997_rtc_info *info = dev_get_drvdata(dev);
335*4882a593Smuzhiyun int ret;
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun mutex_lock(&info->lock);
338*4882a593Smuzhiyun if (enabled)
339*4882a593Smuzhiyun ret = max8997_rtc_start_alarm(info);
340*4882a593Smuzhiyun else
341*4882a593Smuzhiyun ret = max8997_rtc_stop_alarm(info);
342*4882a593Smuzhiyun mutex_unlock(&info->lock);
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun return ret;
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun
max8997_rtc_alarm_irq(int irq,void * data)347*4882a593Smuzhiyun static irqreturn_t max8997_rtc_alarm_irq(int irq, void *data)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun struct max8997_rtc_info *info = data;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun dev_info(info->dev, "%s:irq(%d)\n", __func__, irq);
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF);
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun return IRQ_HANDLED;
356*4882a593Smuzhiyun }
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun static const struct rtc_class_ops max8997_rtc_ops = {
359*4882a593Smuzhiyun .read_time = max8997_rtc_read_time,
360*4882a593Smuzhiyun .set_time = max8997_rtc_set_time,
361*4882a593Smuzhiyun .read_alarm = max8997_rtc_read_alarm,
362*4882a593Smuzhiyun .set_alarm = max8997_rtc_set_alarm,
363*4882a593Smuzhiyun .alarm_irq_enable = max8997_rtc_alarm_irq_enable,
364*4882a593Smuzhiyun };
365*4882a593Smuzhiyun
max8997_rtc_enable_wtsr(struct max8997_rtc_info * info,bool enable)366*4882a593Smuzhiyun static void max8997_rtc_enable_wtsr(struct max8997_rtc_info *info, bool enable)
367*4882a593Smuzhiyun {
368*4882a593Smuzhiyun int ret;
369*4882a593Smuzhiyun u8 val, mask;
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun if (!wtsr_en)
372*4882a593Smuzhiyun return;
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun if (enable)
375*4882a593Smuzhiyun val = (1 << WTSR_EN_SHIFT) | (3 << WTSRT_SHIFT);
376*4882a593Smuzhiyun else
377*4882a593Smuzhiyun val = 0;
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun mask = WTSR_EN_MASK | WTSRT_MASK;
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun dev_info(info->dev, "%s: %s WTSR\n", __func__,
382*4882a593Smuzhiyun enable ? "enable" : "disable");
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun ret = max8997_update_reg(info->rtc, MAX8997_RTC_WTSR_SMPL, val, mask);
385*4882a593Smuzhiyun if (ret < 0) {
386*4882a593Smuzhiyun dev_err(info->dev, "%s: fail to update WTSR reg(%d)\n",
387*4882a593Smuzhiyun __func__, ret);
388*4882a593Smuzhiyun return;
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun max8997_rtc_set_update_reg(info);
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun
max8997_rtc_enable_smpl(struct max8997_rtc_info * info,bool enable)394*4882a593Smuzhiyun static void max8997_rtc_enable_smpl(struct max8997_rtc_info *info, bool enable)
395*4882a593Smuzhiyun {
396*4882a593Smuzhiyun int ret;
397*4882a593Smuzhiyun u8 val, mask;
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun if (!smpl_en)
400*4882a593Smuzhiyun return;
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun if (enable)
403*4882a593Smuzhiyun val = (1 << SMPL_EN_SHIFT) | (0 << SMPLT_SHIFT);
404*4882a593Smuzhiyun else
405*4882a593Smuzhiyun val = 0;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun mask = SMPL_EN_MASK | SMPLT_MASK;
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun dev_info(info->dev, "%s: %s SMPL\n", __func__,
410*4882a593Smuzhiyun enable ? "enable" : "disable");
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun ret = max8997_update_reg(info->rtc, MAX8997_RTC_WTSR_SMPL, val, mask);
413*4882a593Smuzhiyun if (ret < 0) {
414*4882a593Smuzhiyun dev_err(info->dev, "%s: fail to update SMPL reg(%d)\n",
415*4882a593Smuzhiyun __func__, ret);
416*4882a593Smuzhiyun return;
417*4882a593Smuzhiyun }
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun max8997_rtc_set_update_reg(info);
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun val = 0;
422*4882a593Smuzhiyun max8997_read_reg(info->rtc, MAX8997_RTC_WTSR_SMPL, &val);
423*4882a593Smuzhiyun pr_info("WTSR_SMPL(0x%02x)\n", val);
424*4882a593Smuzhiyun }
425*4882a593Smuzhiyun
max8997_rtc_init_reg(struct max8997_rtc_info * info)426*4882a593Smuzhiyun static int max8997_rtc_init_reg(struct max8997_rtc_info *info)
427*4882a593Smuzhiyun {
428*4882a593Smuzhiyun u8 data[2];
429*4882a593Smuzhiyun int ret;
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun /* Set RTC control register : Binary mode, 24hour mdoe */
432*4882a593Smuzhiyun data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
433*4882a593Smuzhiyun data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun info->rtc_24hr_mode = 1;
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun ret = max8997_bulk_write(info->rtc, MAX8997_RTC_CTRLMASK, 2, data);
438*4882a593Smuzhiyun if (ret < 0) {
439*4882a593Smuzhiyun dev_err(info->dev, "%s: fail to write controlm reg(%d)\n",
440*4882a593Smuzhiyun __func__, ret);
441*4882a593Smuzhiyun return ret;
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun ret = max8997_rtc_set_update_reg(info);
445*4882a593Smuzhiyun return ret;
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun
max8997_rtc_probe(struct platform_device * pdev)448*4882a593Smuzhiyun static int max8997_rtc_probe(struct platform_device *pdev)
449*4882a593Smuzhiyun {
450*4882a593Smuzhiyun struct max8997_dev *max8997 = dev_get_drvdata(pdev->dev.parent);
451*4882a593Smuzhiyun struct max8997_rtc_info *info;
452*4882a593Smuzhiyun int ret, virq;
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun info = devm_kzalloc(&pdev->dev, sizeof(struct max8997_rtc_info),
455*4882a593Smuzhiyun GFP_KERNEL);
456*4882a593Smuzhiyun if (!info)
457*4882a593Smuzhiyun return -ENOMEM;
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun mutex_init(&info->lock);
460*4882a593Smuzhiyun info->dev = &pdev->dev;
461*4882a593Smuzhiyun info->max8997 = max8997;
462*4882a593Smuzhiyun info->rtc = max8997->rtc;
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun platform_set_drvdata(pdev, info);
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun ret = max8997_rtc_init_reg(info);
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun if (ret < 0) {
469*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to initialize RTC reg:%d\n", ret);
470*4882a593Smuzhiyun return ret;
471*4882a593Smuzhiyun }
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun max8997_rtc_enable_wtsr(info, true);
474*4882a593Smuzhiyun max8997_rtc_enable_smpl(info, true);
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun device_init_wakeup(&pdev->dev, 1);
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun info->rtc_dev = devm_rtc_device_register(&pdev->dev, "max8997-rtc",
479*4882a593Smuzhiyun &max8997_rtc_ops, THIS_MODULE);
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun if (IS_ERR(info->rtc_dev)) {
482*4882a593Smuzhiyun ret = PTR_ERR(info->rtc_dev);
483*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
484*4882a593Smuzhiyun return ret;
485*4882a593Smuzhiyun }
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun virq = irq_create_mapping(max8997->irq_domain, MAX8997_PMICIRQ_RTCA1);
488*4882a593Smuzhiyun if (!virq) {
489*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to create mapping alarm IRQ\n");
490*4882a593Smuzhiyun ret = -ENXIO;
491*4882a593Smuzhiyun goto err_out;
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun info->virq = virq;
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun ret = devm_request_threaded_irq(&pdev->dev, virq, NULL,
496*4882a593Smuzhiyun max8997_rtc_alarm_irq, 0,
497*4882a593Smuzhiyun "rtc-alarm0", info);
498*4882a593Smuzhiyun if (ret < 0)
499*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
500*4882a593Smuzhiyun info->virq, ret);
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun err_out:
503*4882a593Smuzhiyun return ret;
504*4882a593Smuzhiyun }
505*4882a593Smuzhiyun
max8997_rtc_shutdown(struct platform_device * pdev)506*4882a593Smuzhiyun static void max8997_rtc_shutdown(struct platform_device *pdev)
507*4882a593Smuzhiyun {
508*4882a593Smuzhiyun struct max8997_rtc_info *info = platform_get_drvdata(pdev);
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun max8997_rtc_enable_wtsr(info, false);
511*4882a593Smuzhiyun max8997_rtc_enable_smpl(info, false);
512*4882a593Smuzhiyun }
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun static const struct platform_device_id rtc_id[] = {
515*4882a593Smuzhiyun { "max8997-rtc", 0 },
516*4882a593Smuzhiyun {},
517*4882a593Smuzhiyun };
518*4882a593Smuzhiyun MODULE_DEVICE_TABLE(platform, rtc_id);
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun static struct platform_driver max8997_rtc_driver = {
521*4882a593Smuzhiyun .driver = {
522*4882a593Smuzhiyun .name = "max8997-rtc",
523*4882a593Smuzhiyun },
524*4882a593Smuzhiyun .probe = max8997_rtc_probe,
525*4882a593Smuzhiyun .shutdown = max8997_rtc_shutdown,
526*4882a593Smuzhiyun .id_table = rtc_id,
527*4882a593Smuzhiyun };
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun module_platform_driver(max8997_rtc_driver);
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun MODULE_DESCRIPTION("Maxim MAX8997 RTC driver");
532*4882a593Smuzhiyun MODULE_AUTHOR("<ms925.kim@samsung.com>");
533*4882a593Smuzhiyun MODULE_LICENSE("GPL");
534